JP2017537392A - デュアルプロセッサシステムによるメモリアクセス - Google Patents

デュアルプロセッサシステムによるメモリアクセス Download PDF

Info

Publication number
JP2017537392A
JP2017537392A JP2017525968A JP2017525968A JP2017537392A JP 2017537392 A JP2017537392 A JP 2017537392A JP 2017525968 A JP2017525968 A JP 2017525968A JP 2017525968 A JP2017525968 A JP 2017525968A JP 2017537392 A JP2017537392 A JP 2017537392A
Authority
JP
Japan
Prior art keywords
processor
data
threshold
determining
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2017525968A
Other languages
English (en)
Japanese (ja)
Other versions
JP2017537392A5 (enExample
Inventor
アブヒジート・シン
Original Assignee
クアルコム テクノロジーズ インターナショナル，リミテッド
クアルコム テクノロジーズ インターナショナル，リミテッド
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by クアルコム テクノロジーズ インターナショナル，リミテッド, クアルコム テクノロジーズ インターナショナル，リミテッド filed Critical クアルコム テクノロジーズ インターナショナル，リミテッド
Publication of JP2017537392A publication Critical patent/JP2017537392A/ja
Publication of JP2017537392A5 publication Critical patent/JP2017537392A5/ja
Pending legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
    • G06F13/1663—Access to shared memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
    • G06F9/526—Mutual exclusion algorithms
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
    • G06F11/3024—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is a central processing unit [CPU]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/3055—Monitoring arrangements for monitoring the status of the computing system or of the computing system component, e.g. monitoring if the computing system is on, off, available, not available
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Computing Systems (AREA)
  • Quality & Reliability (AREA)
  • Mathematical Physics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Multi Processors (AREA)
JP2017525968A 2014-12-02 2015-11-20 デュアルプロセッサシステムによるメモリアクセス Pending JP2017537392A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/558,147 US9720861B2 (en) 2014-12-02 2014-12-02 Memory access by dual processor systems
US14/558,147 2014-12-02
PCT/US2015/061942 WO2016089628A1 (en) 2014-12-02 2015-11-20 Memory access by dual processor systems

Publications (2)

Publication Number Publication Date
JP2017537392A true JP2017537392A (ja) 2017-12-14
JP2017537392A5 JP2017537392A5 (enExample) 2018-12-20

Family

ID=53785083

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2017525968A Pending JP2017537392A (ja) 2014-12-02 2015-11-20 デュアルプロセッサシステムによるメモリアクセス

Country Status (10)

Country Link
US (1) US9720861B2 (enExample)
EP (1) EP3227782B1 (enExample)
JP (1) JP2017537392A (enExample)
KR (1) KR20170129674A (enExample)
CN (1) CN107111577B (enExample)
BR (1) BR112017011658A2 (enExample)
CA (1) CA2965826A1 (enExample)
DE (1) DE102015111270A1 (enExample)
GB (1) GB2535249A (enExample)
WO (1) WO2016089628A1 (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6360387B2 (ja) 2014-08-19 2018-07-18 ルネサスエレクトロニクス株式会社 プロセッサシステム、エンジン制御システム及び制御方法
CN114253729B (zh) * 2021-12-23 2025-05-09 上海商米科技集团股份有限公司 适用于pos机双处理器间的通信系统、方法和装置
CN118915955A (zh) * 2023-05-08 2024-11-08 芯翼信息科技(上海)有限公司 Flash存储器的控制方法、装置、设备及存储介质

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH052529A (ja) * 1991-06-24 1993-01-08 Iwaki Electron Corp Ltd フラツシユ・メモリのアクセス方法及びその回路
JP2001216284A (ja) * 1999-11-25 2001-08-10 Denso Corp 電子制御装置
JP2005215924A (ja) * 2004-01-29 2005-08-11 Dainichi Co Ltd 制御装置の通信方法および制御装置
JP2006323617A (ja) * 2005-05-19 2006-11-30 Fujitsu Ten Ltd メモリ管理方法及びメモリ管理装置
CN101114271A (zh) * 2006-07-28 2008-01-30 三星电子株式会社 在处理器之间具有主接口的可多路径访问的半导体存储器
US20080256348A1 (en) * 2007-03-21 2008-10-16 Prabhudesai Shantanu Prasad Method for configuration of a processing unit
US20090228895A1 (en) * 2008-03-04 2009-09-10 Jianzu Ding Method and system for polling network controllers

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4591975A (en) 1983-07-18 1986-05-27 Data General Corporation Data processing system having dual processors
US6161162A (en) * 1993-12-08 2000-12-12 Nec Corporation Multiprocessor system for enabling shared access to a memory
US5845130A (en) 1996-09-11 1998-12-01 Vlsi Technology, Inc. Mailbox traffic controller
US5918248A (en) * 1996-12-30 1999-06-29 Northern Telecom Limited Shared memory control algorithm for mutual exclusion and rollback
US6012121A (en) 1997-04-08 2000-01-04 International Business Machines Corporation Apparatus for flexible control of interrupts in multiprocessor systems
US5875342A (en) 1997-06-03 1999-02-23 International Business Machines Corporation User programmable interrupt mask with timeout
US6393590B1 (en) * 1998-12-22 2002-05-21 Nortel Networks Limited Method and apparatus for ensuring proper functionality of a shared memory, multiprocessor system
US7130951B1 (en) 2002-04-18 2006-10-31 Advanced Micro Devices, Inc. Method for selectively disabling interrupts on a secure execution mode-capable processor
US7290080B2 (en) 2002-06-27 2007-10-30 Nazomi Communications Inc. Application processors and memory architecture for wireless applications
US7685354B1 (en) * 2004-06-30 2010-03-23 Sun Microsystems, Inc. Multiple-core processor with flexible mapping of processor cores to cache banks
US7873776B2 (en) * 2004-06-30 2011-01-18 Oracle America, Inc. Multiple-core processor with support for multiple virtual processors
US7617403B2 (en) * 2006-07-26 2009-11-10 International Business Machines Corporation Method and apparatus for controlling heat generation in a multi-core processor
US7808428B2 (en) 2007-10-08 2010-10-05 Hemisphere Gps Llc GNSS receiver and external storage device system and GNSS data processing method
GB2458499A (en) * 2008-03-20 2009-09-23 Cambridge Silicon Radio Ltd Sharing access to a data store by a host processor and a signal processor in a mobile phone
US20110179311A1 (en) * 2009-12-31 2011-07-21 Nachimuthu Murugasamy K Injecting error and/or migrating memory in a computing system
US8510492B2 (en) 2010-09-08 2013-08-13 Integrated Device Technology Inc. System and method for communication handshaking between a master processors and a slave processor
US8392635B2 (en) 2010-12-22 2013-03-05 Western Digital Technologies, Inc. Selectively enabling a host transfer interrupt
US9009702B2 (en) 2011-11-30 2015-04-14 Red Hat Israel, Ltd. Application-driven shared device queue polling in a virtualized computing environment
US20150006962A1 (en) * 2013-06-27 2015-01-01 Robert C. Swanson Memory dump without error containment loss

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH052529A (ja) * 1991-06-24 1993-01-08 Iwaki Electron Corp Ltd フラツシユ・メモリのアクセス方法及びその回路
JP2001216284A (ja) * 1999-11-25 2001-08-10 Denso Corp 電子制御装置
US6944649B1 (en) * 1999-11-25 2005-09-13 Denso Corporation Electronic control unit having single non-volatile memory for multiple central processing units and data retrieval method
JP2005215924A (ja) * 2004-01-29 2005-08-11 Dainichi Co Ltd 制御装置の通信方法および制御装置
JP2006323617A (ja) * 2005-05-19 2006-11-30 Fujitsu Ten Ltd メモリ管理方法及びメモリ管理装置
CN101114271A (zh) * 2006-07-28 2008-01-30 三星电子株式会社 在处理器之间具有主接口的可多路径访问的半导体存储器
US20080256348A1 (en) * 2007-03-21 2008-10-16 Prabhudesai Shantanu Prasad Method for configuration of a processing unit
US20090228895A1 (en) * 2008-03-04 2009-09-10 Jianzu Ding Method and system for polling network controllers

Also Published As

Publication number Publication date
BR112017011658A2 (pt) 2018-01-02
DE102015111270A1 (de) 2016-06-02
KR20170129674A (ko) 2017-11-27
CN107111577B (zh) 2020-07-14
WO2016089628A1 (en) 2016-06-09
CN107111577A (zh) 2017-08-29
CA2965826A1 (en) 2016-06-09
GB201509869D0 (en) 2015-07-22
EP3227782A1 (en) 2017-10-11
US20160154751A1 (en) 2016-06-02
US9720861B2 (en) 2017-08-01
GB2535249A (en) 2016-08-17
EP3227782B1 (en) 2022-06-15

Similar Documents

Publication Publication Date Title
ES2655852T3 (es) Procedimientos y aparatos para cancelar solicitudes de captura previa de datos para un bucle
JP5811245B1 (ja) 情報処理装置、メモリ順序保障方法、及び、プログラム
US20190220279A1 (en) Simulation of exclusive instructions
CN106663026B (zh) 针对事务型数据处理执行模式的调用堆栈维护
CN107735791B (zh) 安全模式状态的数据访问追踪
KR20140024060A (ko) 랭크-특정 순환 중복 검사
JP2017537392A (ja) デュアルプロセッサシステムによるメモリアクセス
KR102427949B1 (ko) 데이터 처리 장치에서의 시스템 에러 핸들링
US20140289501A1 (en) Technique for freeing renamed registers
US10719325B2 (en) System and method of VLIW instruction processing using reduced-width VLIW processor
WO2016085813A1 (en) Method and apparatus for preventing and managing corruption and flash memory contents
US20050060690A1 (en) Microprocessor system with software emulation processed by auxiliary hardware
CN105528252A (zh) 电脑系统
US9400758B2 (en) Reset method and network device
JP2017537392A5 (enExample)
US9983932B2 (en) Pipeline processor and an equal model compensator method and apparatus to store the processing result
US20110185156A1 (en) Executing watchpoint events for debugging in a "break before make" manner
KR102028729B1 (ko) 정적 스케쥴 프로세서의 논블로킹 실행 장치 및 방법
JP2017146703A (ja) 共有メモリ制御回路及び共有メモリ制御方法
KR102376396B1 (ko) 멀티 코어 프로세서 및 그것의 캐시 관리 방법
CN104809024A (zh) 推测中断信号
US20190114249A1 (en) Method of executing instructions of core, method of debugging core system, and core system
WO2010109631A1 (ja) 情報処理装置、情報処理方法及び情報処理プログラム
US9632797B2 (en) Updating a commit list to indicate data to be written to a firmware interface variable repository
CN112286466A (zh) 电子装置及空间复用方法

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20181106

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20181106

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20190823

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20190930

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20200608