Classifications

• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
  • G06F13/14—Handling requests for interconnection or transfer
  • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
  • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
  • G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
  • G06F13/1663—Access to shared memory
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F11/00—Error detection; Error correction; Monitoring
  • G06F11/30—Monitoring
  • G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
  • G06F11/3024—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is a central processing unit [CPU]
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F11/00—Error detection; Error correction; Monitoring
  • G06F11/30—Monitoring
  • G06F11/3055—Monitoring arrangements for monitoring the status of the computing system or of the computing system component, e.g. monitoring if the computing system is on, off, available, not available
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
  • G06F13/14—Handling requests for interconnection or transfer
  • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
  • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/46—Multiprogramming arrangements
  • G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/46—Multiprogramming arrangements
  • G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
  • G06F9/526—Mutual exclusion algorithms

Definitions

• the present invention relates generally to computer systems, and more particularly to methods and apparatuses for memory access by dual processor systems.
• Processor systems may utilise a common memory store (for example flash memory) for instructions and data. There may therefore be a need to control access to that memory to avoid conflicts between instruction read and data read and write processes.
• a common memory store for example flash memory
• GNSS Global Navigation Satellite System
• a method for controlling access to memory by a system comprising first and second processors, the method comprising the steps of generating or receiving data at the second processor for storage, disabling operation of the first processor by the second processor, disabling interrupts of the second processor, storing the data to the memory by the second processor, enabling interrupts of the second processor, and enabling the first processor.
• the method may further comprise the step of ascertaining the period for which the first processor was disabled.
• the processor may be reset if the period is greater than a threshold.
• the method may further comprise the step of monitoring the state of the first processor using the second processor.
• the method may further comprise the step of performing a reset of the first processor if the state of that first processor does not change for greater than a threshold time.
• the system may be a GNSS receiver, and the first processor is performing tracking operations.
• the threshold may be 50ms.
• the threshold time may be 2 seconds.
• the first and second processors may be in a single integrated circuit package.
• the method may further comprise the step of determining the stability of the first processor prior to disabling that processor, and only disabling the processor if it is stable. Determining the stability of the first processor comprises comparing the number of consecutive position calculations to a threshold, wherein the first processor is determined to be stable if the number of consecutive calculations exceeds the threshold. Determining the stability of the first processor comprises comparing the time since the processor was last disabled to a threshold, wherein the first processor is determined to be stable if the time is greater than the threshold. Determining the stability of the first processor comprises verifying that there is sufficient time prior to the next scheduled event to complete storing the data. [0016] The method may further comprise the step of assigning a priority to data to be stored, and storing data in an order defined at least in part by that priority.
• a dual-processor device comprising first and second processors, and a port for communication with a memory, wherein the device is configured to perform the method described herein.
• Figure 1 shows an outline schematic diagram of a dual-processor system
• Figure 2 shows a flow-chart of a method of controlling access to memory.
• FIG. 1 shows a simplified schematic diagram of a dual-processor GNSS receiver 10.
• the receiver comprises first 1 1 and second 12 processors, and is in communication with flash memory 13 via an appropriate port.
• the flash memory may be serial or parallel memory.
• Each processor conducts aspects of signal processing, position calculation, and other supporting tasks.
• the first and second processors are connected to exchange data and to allow interaction of the two processors.
• the first processor is a DSP processor performing tracking and signal processing tasks
• the second processor is a general-purpose processor, such as a RISC processor, performing general control tasks.
• the first and second processor are typically integrated in a single integrated circuit package.
• GNSS receivers need to store data such as Extended Ephemeris, Almanac, RTC, Crystal Learning tables, and UTC data at the same time as processing received signals.
• this data is stored to the same external flash memory from which both the processors are fetching their instructions.
• flash memory writes are controlled by one of the two processors. If data for storage is generated at the non-controlling processor it is transferred to the controlling processor for storage. The non-controlling processor is disabled and the controlling processor writes the data to the flash memory using a process which cannot be interrupted. Once the write has completed the non-controlling processor is re-enabled by the controlling processor and processing continues. Disabling the non-controlling processor pauses the processor such that it resumes operation at the same point.
• FIG. 2 shows a flow-chart of a specific method to control access to memory in a dual-processor GNSS device.
• the device comprises a tracking processor, which is typically a DSP processor and is utilised to processed received signals, and a general processor which provides position calculation and general control processes.
• step 20 data generated by the tracking processor and the general processor which must be stored to flash memory.
• Data generated by the tracking processor is first transferred to the general processor.
• step 21 it is verified at step 21 whether the receiver is stable.
• the receiver may be determined to be stable by counting consecutive valid position outputs. In an example, the receiver is determined to be stable after ten valid consecutive outputs. As set out in more detail below, further checks may also be made to ensure the data can be stored without excessive disruption.
• the tracking processor is disabled.
• Disabling the tracking processor may comprise issuing a pause command, turning the processor off, disabling all interrupts, or preventing any reads from the flash memory.
• the purpose of disabling the processor is to prevent access to the flash memory by the tracking processor, thus avoiding memory conflicts.
• a state machine is started on the general processor to monitor the status of the tracking processor. This state machine is used to ensure the tracking processor is re-enabled correctly.
• the data is packaged by the general processor such that it can be stored to the flash memory in a single operation and at step 25 the general processor writes the data to the flash memory. This is done using a critical section of code to ensure the process is not interrupted. Other techniques can also be utilised to ensure the process completes without interruption, for example by disabling all interrupts in the general processor before commencing the write operation, and then re-enabling them after completion.
• the general processor monitors (step 27) the time for which the tracking processor's interrupts were disabled and takes appropriate steps to ensure tracking operation is resumed correctly.
• the threshold applied at step 27 is determined according to the specific characteristics of the time required to write data and the ability of the receiver to handle periods of being disabled. Both of these values can vary very significantly and specific values may be selected for each configuration.
• the tracking processor may be reset if it was disabled for more than 50ms for Parallel Flash and 400ms for SQIF. After the reset satellite signals being tracked can re-synchronise with the general processor. Timings of this magnitude are most likely to be encountered when it is necessary to erase sectors of the flash memory during the write process. The process then completes at step 29.
• a state machine is started (step 23) in the general processor to monitor the state of the tracking processor. It is possible that the wake-up signal from the general processor to the tracking processor (step 26) is missed by the tracking processor and the tracking processor does not resume full operation.
• the state machine monitors the state of the tracking processor (step 30) and if that state machine has not moved for more than a threshold time then a reset is performed of the tracking processor at step 31 to resume operation.
• This threshold may be set to, for example, 2 seconds.
• the state machine may be de-activated once all data storage operations have been completed, and the tracking processor is in an operational state.
• the data storage operation may be initiated once it is detected that the receiver system is stable. It may also be important to ensure the data storage operation is run at an appropriate time to ensure time- sensitive features (for example generation of the 1PPS signal in a GNSS receiver) are not affected. Stability is determined in the above example by ensuring at least 10 consecutive positions have been calculated, but other means may also be used in addition or instead. For example, it may also be a requirement that all measurements from the tracking processor have been received and processed by the general processor. The general processor may also verify that there is sufficient time to allow the data storage operation before the next scheduled task. Furthermore, the stability check could utilise the time since completion of the last flash write or erase process. That is, the time the tracking processor has been enabled for since it was last disabled.
• Data for storage may be tagged with an indication of priority so that data stores can be scheduled appropriately to store the most important data first. All different data types for storage are prioritised. Additionally data for storage can be received from a host processor via a communication port. This type of data received from a host processor is assigned the highest priority for storage as soon as possible.
• An example of externally generated data is Server Generated Extended Ephemeris (SGEE) data.
• SGEE Server Generated Extended Ephemeris
• Priority may be assigned by the general processor, or by the originator of the data (for example the tracking processor may tag data with a priority).
• flash memory functions may not be appropriate for a dual-processor system operating as described herein.
• utilising erase suspend mode of a flash memory can lead to a significant increase in the time required for the operation and lead to greater disruption of the tracking processor while the general processor conducts memory operations.
• data write and erase operations are managed as described above such that the tracking processor is disabled according to a calculated schedule and can resume operation as quickly as possible.
• Any reference to 'an' item refers to one or more of those items.
• the term 'comprising' is used herein to mean including the method blocks or elements identified, but that such blocks or elements do not comprise an exclusive list and a method or apparatus may contain additional blocks or elements.

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• 2014
  • 2014-12-02 US US14/558,147 patent/US9720861B2/en active Active
• 2015
  • 2015-06-08 GB GB1509869.2A patent/GB2535249A/en not_active Withdrawn
  • 2015-07-13 DE DE102015111270.1A patent/DE102015111270A1/de not_active Withdrawn
  • 2015-11-20 EP EP15805685.3A patent/EP3227782B1/en not_active Not-in-force
  • 2015-11-20 CA CA2965826A patent/CA2965826A1/en not_active Abandoned
  • 2015-11-20 BR BR112017011658A patent/BR112017011658A2/pt not_active Application Discontinuation
  • 2015-11-20 KR KR1020177014529A patent/KR20170129674A/ko not_active Withdrawn
  • 2015-11-20 CN CN201580064825.2A patent/CN107111577B/zh active Active
  • 2015-11-20 WO PCT/US2015/061942 patent/WO2016089628A1/en not_active Ceased
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