BR112017011658A2 - acesso à memória por sistemas de processador duplo - Google Patents

acesso à memória por sistemas de processador duplo

Info

Publication number
BR112017011658A2
BR112017011658A2 BR112017011658A BR112017011658A BR112017011658A2 BR 112017011658 A2 BR112017011658 A2 BR 112017011658A2 BR 112017011658 A BR112017011658 A BR 112017011658A BR 112017011658 A BR112017011658 A BR 112017011658A BR 112017011658 A2 BR112017011658 A2 BR 112017011658A2
Authority
BR
Brazil
Prior art keywords
memory access
dual processor
processor systems
methods
dual
Prior art date
Application number
BR112017011658A
Other languages
English (en)
Portuguese (pt)
Inventor
Singh Abhijeet
Original Assignee
Qualcomm Technologies Int Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Technologies Int Ltd filed Critical Qualcomm Technologies Int Ltd
Publication of BR112017011658A2 publication Critical patent/BR112017011658A2/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
    • G06F13/1663—Access to shared memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
    • G06F9/526—Mutual exclusion algorithms
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
    • G06F11/3024—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is a central processing unit [CPU]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/3055—Monitoring arrangements for monitoring the status of the computing system or of the computing system component, e.g. monitoring if the computing system is on, off, available, not available
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Computing Systems (AREA)
  • Quality & Reliability (AREA)
  • Mathematical Physics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Multi Processors (AREA)
BR112017011658A 2014-12-02 2015-11-20 acesso à memória por sistemas de processador duplo BR112017011658A2 (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/558,147 US9720861B2 (en) 2014-12-02 2014-12-02 Memory access by dual processor systems
PCT/US2015/061942 WO2016089628A1 (en) 2014-12-02 2015-11-20 Memory access by dual processor systems

Publications (1)

Publication Number Publication Date
BR112017011658A2 true BR112017011658A2 (pt) 2018-01-02

Family

ID=53785083

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112017011658A BR112017011658A2 (pt) 2014-12-02 2015-11-20 acesso à memória por sistemas de processador duplo

Country Status (10)

Country Link
US (1) US9720861B2 (enExample)
EP (1) EP3227782B1 (enExample)
JP (1) JP2017537392A (enExample)
KR (1) KR20170129674A (enExample)
CN (1) CN107111577B (enExample)
BR (1) BR112017011658A2 (enExample)
CA (1) CA2965826A1 (enExample)
DE (1) DE102015111270A1 (enExample)
GB (1) GB2535249A (enExample)
WO (1) WO2016089628A1 (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6360387B2 (ja) 2014-08-19 2018-07-18 ルネサスエレクトロニクス株式会社 プロセッサシステム、エンジン制御システム及び制御方法
CN114253729B (zh) * 2021-12-23 2025-05-09 上海商米科技集团股份有限公司 适用于pos机双处理器间的通信系统、方法和装置
CN118915955A (zh) * 2023-05-08 2024-11-08 芯翼信息科技(上海)有限公司 Flash存储器的控制方法、装置、设备及存储介质

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4591975A (en) 1983-07-18 1986-05-27 Data General Corporation Data processing system having dual processors
JPH052529A (ja) * 1991-06-24 1993-01-08 Iwaki Electron Corp Ltd フラツシユ・メモリのアクセス方法及びその回路
US6161162A (en) * 1993-12-08 2000-12-12 Nec Corporation Multiprocessor system for enabling shared access to a memory
US5845130A (en) 1996-09-11 1998-12-01 Vlsi Technology, Inc. Mailbox traffic controller
US5918248A (en) * 1996-12-30 1999-06-29 Northern Telecom Limited Shared memory control algorithm for mutual exclusion and rollback
US6012121A (en) 1997-04-08 2000-01-04 International Business Machines Corporation Apparatus for flexible control of interrupts in multiprocessor systems
US5875342A (en) 1997-06-03 1999-02-23 International Business Machines Corporation User programmable interrupt mask with timeout
US6393590B1 (en) * 1998-12-22 2002-05-21 Nortel Networks Limited Method and apparatus for ensuring proper functionality of a shared memory, multiprocessor system
JP2001216284A (ja) * 1999-11-25 2001-08-10 Denso Corp 電子制御装置
US7130951B1 (en) 2002-04-18 2006-10-31 Advanced Micro Devices, Inc. Method for selectively disabling interrupts on a secure execution mode-capable processor
US7290080B2 (en) 2002-06-27 2007-10-30 Nazomi Communications Inc. Application processors and memory architecture for wireless applications
JP2005215924A (ja) * 2004-01-29 2005-08-11 Dainichi Co Ltd 制御装置の通信方法および制御装置
US7685354B1 (en) * 2004-06-30 2010-03-23 Sun Microsystems, Inc. Multiple-core processor with flexible mapping of processor cores to cache banks
US7873776B2 (en) * 2004-06-30 2011-01-18 Oracle America, Inc. Multiple-core processor with support for multiple virtual processors
JP2006323617A (ja) * 2005-05-19 2006-11-30 Fujitsu Ten Ltd メモリ管理方法及びメモリ管理装置
KR100772841B1 (ko) * 2006-07-28 2007-11-02 삼성전자주식회사 프로세서들간 호스트 인터페이싱 기능을 갖는 멀티패쓰억세스블 반도체 메모리 장치
US7617403B2 (en) * 2006-07-26 2009-11-10 International Business Machines Corporation Method and apparatus for controlling heat generation in a multi-core processor
US7680909B2 (en) 2007-03-21 2010-03-16 Ittiam Systems (P) Ltd. Method for configuration of a processing unit
US7808428B2 (en) 2007-10-08 2010-10-05 Hemisphere Gps Llc GNSS receiver and external storage device system and GNSS data processing method
US8191073B2 (en) * 2008-03-04 2012-05-29 Fortinet, Inc. Method and system for polling network controllers
GB2458499A (en) * 2008-03-20 2009-09-23 Cambridge Silicon Radio Ltd Sharing access to a data store by a host processor and a signal processor in a mobile phone
US20110179311A1 (en) * 2009-12-31 2011-07-21 Nachimuthu Murugasamy K Injecting error and/or migrating memory in a computing system
US8510492B2 (en) 2010-09-08 2013-08-13 Integrated Device Technology Inc. System and method for communication handshaking between a master processors and a slave processor
US8392635B2 (en) 2010-12-22 2013-03-05 Western Digital Technologies, Inc. Selectively enabling a host transfer interrupt
US9009702B2 (en) 2011-11-30 2015-04-14 Red Hat Israel, Ltd. Application-driven shared device queue polling in a virtualized computing environment
US20150006962A1 (en) * 2013-06-27 2015-01-01 Robert C. Swanson Memory dump without error containment loss

Also Published As

Publication number Publication date
DE102015111270A1 (de) 2016-06-02
KR20170129674A (ko) 2017-11-27
CN107111577B (zh) 2020-07-14
WO2016089628A1 (en) 2016-06-09
CN107111577A (zh) 2017-08-29
CA2965826A1 (en) 2016-06-09
GB201509869D0 (en) 2015-07-22
EP3227782A1 (en) 2017-10-11
US20160154751A1 (en) 2016-06-02
JP2017537392A (ja) 2017-12-14
US9720861B2 (en) 2017-08-01
GB2535249A (en) 2016-08-17
EP3227782B1 (en) 2022-06-15

Similar Documents

Publication Publication Date Title
EP3292466A4 (en) Quanton representation for emulating quantum-like computation on classical processors
EP3212072A4 (en) Sleep measurement computer system
DK3302448T3 (da) Erstattede heterocyclylafledninger som cdk-inhibitore
DK3163993T3 (da) Luftrørssystem til datacenter
EP3186713A4 (en) Routing direct memory access requests in a virtualized computing environment
EP3295301A4 (en) Parallel processing for solution space partitions
EP3120460A4 (en) Chips including classical and quantum computing processors
DK3305046T3 (da) Kølesystem til datacenter
DK3105218T3 (da) Cyclopropylaminer som lsd1-inhibitorer
HUE045984T2 (hu) Számítógépes képi alkalmazás feldolgozás
EP3108393A4 (en) Disease prediction system using open source data
EP3014416A4 (en) Multiple register memory access instructions, processors, methods, and systems
DK3313832T3 (da) 3-tetrazolyl-benzen-1,2-disulfonamidderivater som metallo-beta- lactamase-hæmmere
EP3198465A4 (en) Fast smp/asmp mode-switching hardware apparatus for low-cost low-power high performance multiple processor system
DK3538528T3 (da) Pyrrolamider som alpha v-integrinhæmmere
EP3195128A4 (en) Memory management in virtualized computing
DK3458460T3 (da) Imidazoler som histondemethylase-inhibitorer
EP3172667A4 (en) System for an instruction set agnostic runtime architecture
EP3158802A4 (en) Idle mode cell selection for licensed shared access
EP3123287A4 (en) Alternate dynamic keyboard for convertible tablet computers
EP3211535A4 (en) Write request processing method, processor and computer
EP3090350A4 (en) Social drive for sharing data
DK3619638T3 (da) Fremgangsmåde til sikker adgang til data
MX391160B (es) Método para acceder a los datos en una memoria en una dirección no alineada
BR112017011658A2 (pt) acesso à memória por sistemas de processador duplo

Legal Events

Date Code Title Description
B06U Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette]
B11B Dismissal acc. art. 36, par 1 of ipl - no reply within 90 days to fullfil the necessary requirements