JP2017536248A - ３次元集積回路（３ｄ ｉｃ）集積化のためのマイクロ電気機械システム（ｍｅｍｓ）結合剥離構造およびウェハ移載の方法 - Google Patents

３次元集積回路（３ｄ ｉｃ）集積化のためのマイクロ電気機械システム（ｍｅｍｓ）結合剥離構造およびウェハ移載の方法 Download PDF

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JP2017536248A
JP2017536248A JP2017514278A JP2017514278A JP2017536248A JP 2017536248 A JP2017536248 A JP 2017536248A JP 2017514278 A JP2017514278 A JP 2017514278A JP 2017514278 A JP2017514278 A JP 2017514278A JP 2017536248 A JP2017536248 A JP 2017536248A
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layer
stage
mems
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integrated circuits
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JP2017536248A5 (https=
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ジェ−シュン・ジェフリー・ラン
ウェンユエ・ジャン
ヤン・ドゥ
ヨン・ジュ・イ
シーチュン・グ
ジン・シエ
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クアルコム，インコーポレイテッド
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00—Three-dimensional [3D] integrated devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00—Three-dimensional [3D] integrated devices
    • H10D88/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/69215—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/43—Layouts of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/481—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes on the rear surfaces of the wafers or substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7412—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support the auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7432—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/744—Details of chemical or physical process used for separating the auxiliary support from a device or a wafer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips

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  • Micromachines (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Pressure Sensors (AREA)
JP2017514278A 2014-09-26 2015-09-08 ３次元集積回路（３ｄ ｉｃ）集積化のためのマイクロ電気機械システム（ｍｅｍｓ）結合剥離構造およびウェハ移載の方法 Pending JP2017536248A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/498,965 2014-09-26
US14/498,965 US9922956B2 (en) 2014-09-26 2014-09-26 Microelectromechanical system (MEMS) bond release structure and method of wafer transfer for three-dimensional integrated circuit (3D IC) integration
PCT/US2015/048930 WO2016048649A1 (en) 2014-09-26 2015-09-08 Microelectromechanical system (mems) bond release structure and method of wafer transfer for three-dimensional integrated circuit (3d ic) integration

Publications (2)

Publication Number Publication Date
JP2017536248A true JP2017536248A (ja) 2017-12-07
JP2017536248A5 JP2017536248A5 (https=) 2018-09-27

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JP2017514278A Pending JP2017536248A (ja) 2014-09-26 2015-09-08 ３次元集積回路（３ｄ ｉｃ）集積化のためのマイクロ電気機械システム（ｍｅｍｓ）結合剥離構造およびウェハ移載の方法

Country Status (10)

Country Link
US (1) US9922956B2 (https=)
EP (1) EP3198634A1 (https=)
JP (1) JP2017536248A (https=)
KR (1) KR20170066354A (https=)
CN (1) CN106688077A (https=)
BR (1) BR112017006167A2 (https=)
HK (1) HK1232339A1 (https=)
SG (1) SG11201700918RA (https=)
TW (1) TWI585820B (https=)
WO (1) WO2016048649A1 (https=)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019134165A (ja) * 2018-02-02 2019-08-08 インフィニオン テクノロジーズ アクチエンゲゼルシャフトＩｎｆｉｎｅｏｎ Ｔｅｃｈｎｏｌｏｇｉｅｓ ＡＧ ウェハ合成物および半導体コンポーネントの製造方法
CN113912005A (zh) * 2021-10-08 2022-01-11 天津大学 一种基于柔性铰链结构的xy全解耦微运动平台
WO2025235300A1 (en) * 2024-05-08 2025-11-13 Micron Technology, Inc. Corrosion-susceptible bonding layer in assisting semiconductor wafer debonding

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3007224A1 (en) * 2014-10-08 2016-04-13 Nxp B.V. Metallisation for semiconductor device
US10049915B2 (en) * 2015-01-09 2018-08-14 Silicon Genesis Corporation Three dimensional integrated circuit
JP6784969B2 (ja) * 2015-10-22 2020-11-18 天馬微電子有限公司 薄膜デバイスとその製造方法
FR3053159B1 (fr) * 2016-06-23 2019-05-10 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procede de fabrication d'une structure de transistors comportant une etape de bouchage
US10438838B2 (en) * 2016-09-01 2019-10-08 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure and related method
US10714446B2 (en) 2017-03-30 2020-07-14 Intel Corporation Apparatus with multi-wafer based device comprising embedded active and/or passive devices and method for forming such
US11211328B2 (en) * 2017-10-16 2021-12-28 SK Hynix Inc. Semiconductor memory device of three-dimensional structure
DE102018214017B4 (de) * 2018-02-07 2022-08-25 Infineon Technologies Ag Verfahren zum herstellen von dünnschichten und mikrosystemen mit dünnschichten
US20190371681A1 (en) * 2018-06-01 2019-12-05 Synaptics Incorporated Stacked wafer integrated circuit
US10504873B1 (en) * 2018-06-25 2019-12-10 Taiwan Semiconductor Manufacturing Co., Ltd. 3DIC structure with protective structure and method of fabricating the same and package
US10734285B2 (en) * 2018-06-28 2020-08-04 Taiwan Semiconductor Manufacturing Co., Ltd. Bonding support structure (and related process) for wafer stacking
KR102538181B1 (ko) 2018-10-24 2023-06-01 삼성전자주식회사 반도체 패키지
US10796976B2 (en) 2018-10-31 2020-10-06 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of forming the same
US10804202B2 (en) * 2019-02-18 2020-10-13 Sandisk Technologies Llc Bonded assembly including a semiconductor-on-insulator die and methods for making the same
US11195818B2 (en) * 2019-09-12 2021-12-07 Taiwan Semiconductor Manufacturing Company, Ltd. Backside contact for thermal displacement in a multi-wafer stacked integrated circuit
US11063022B2 (en) * 2019-09-17 2021-07-13 Taiwan Semiconductor Manufacturing Company, Ltd. Package and manufacturing method of reconstructed wafer
US11158580B2 (en) 2019-10-18 2021-10-26 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor devices with backside power distribution network and frontside through silicon via
US10910272B1 (en) * 2019-10-22 2021-02-02 Sandisk Technologies Llc Reusable support substrate for formation and transfer of semiconductor devices and methods of using the same
US11239204B2 (en) * 2019-11-25 2022-02-01 Sandisk Technologies Llc Bonded assembly containing laterally bonded bonding pads and methods of forming the same
US11088116B2 (en) * 2019-11-25 2021-08-10 Sandisk Technologies Llc Bonded assembly containing horizontal and vertical bonding interfaces and methods of forming the same
US11488939B2 (en) * 2020-01-20 2022-11-01 Monolithic 3D Inc. 3D semiconductor devices and structures with at least one vertical bus
US11270988B2 (en) * 2020-01-20 2022-03-08 Monolithic 3D Inc. 3D semiconductor device(s) and structure(s) with electronic control units
US12021028B2 (en) * 2020-01-20 2024-06-25 Monolithic 3D Inc. 3D semiconductor devices and structures with electronic circuit units
US11315903B2 (en) * 2020-03-05 2022-04-26 Nanya Technology Corporation Semiconductor device with connecting structure and method for fabricating the same
US11127628B1 (en) * 2020-03-16 2021-09-21 Nanya Technology Corporation Semiconductor device with connecting structure having a step-shaped conductive feature and method for fabricating the same
US11715755B2 (en) * 2020-06-15 2023-08-01 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and method for forming integrated high density MIM capacitor
KR102777683B1 (ko) * 2020-08-04 2025-03-10 에스케이하이닉스 주식회사 웨이퍼 대 웨이퍼 본딩 구조를 갖는 반도체 장치 및 그 제조방법
US11817392B2 (en) 2020-09-28 2023-11-14 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit
US11552055B2 (en) * 2020-11-20 2023-01-10 Qualcomm Incorporated Integrated circuit (IC) packages employing front side back-end-of-line (FS-BEOL) to back side back-end-of-line (BS-BEOL) stacking for three-dimensional (3D) die stacking, and related fabrication methods
US11682652B2 (en) * 2021-03-10 2023-06-20 Taiwan Semiconductor Manufacturing Company, Ltd. Notched wafer and bonding support structure to improve wafer stacking

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010504649A (ja) * 2006-09-20 2010-02-12 ザ ボード オブ トラスティーズ オブ ザ ユニヴァーシティー オブ イリノイ 転写可能な半導体構造、デバイス、及びデバイスコンポーネントを作成するための剥離方法
JP2014504457A (ja) * 2010-12-24 2014-02-20 アイ・オゥ・セミコンダクター・インコーポレイテッド 半導体デバイスのためのトラップリッチ層
US20140264770A1 (en) * 2013-03-15 2014-09-18 Sandia Corporation Method of forming through substrate vias (tsvs) and singulating and releasing die having the tsvs from a mechanical support substrate

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6888608B2 (en) 1995-09-06 2005-05-03 Kabushiki Kaisha Toshiba Liquid crystal display device
US6525415B2 (en) 1999-12-28 2003-02-25 Fuji Xerox Co., Ltd. Three-dimensional semiconductor integrated circuit apparatus and manufacturing method therefor
US7045878B2 (en) 2001-05-18 2006-05-16 Reveo, Inc. Selectively bonded thin film layer and substrate layer for processing of useful devices
US7420147B2 (en) 2001-09-12 2008-09-02 Reveo, Inc. Microchannel plate and method of manufacturing microchannel plate
US7435651B2 (en) * 2005-09-12 2008-10-14 Texas Instruments Incorporated Method to obtain uniform nitrogen profile in gate dielectrics
US7785938B2 (en) 2006-04-28 2010-08-31 Semiconductor Energy Laboratory Co., Ltd Semiconductor integrated circuit, manufacturing method thereof, and semiconductor device using semiconductor integrated circuit
US20080291767A1 (en) 2007-05-21 2008-11-27 International Business Machines Corporation Multiple wafer level multiple port register file cell
US7897428B2 (en) 2008-06-03 2011-03-01 International Business Machines Corporation Three-dimensional integrated circuits and techniques for fabrication thereof
US8742476B1 (en) 2012-11-27 2014-06-03 Monolithic 3D Inc. Semiconductor device and structure
US8330559B2 (en) 2010-09-10 2012-12-11 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level packaging
US8563396B2 (en) 2011-01-29 2013-10-22 International Business Machines Corporation 3D integration method using SOI substrates and structures produced thereby
US8970045B2 (en) 2011-03-31 2015-03-03 Soitec Methods for fabrication of semiconductor structures including interposers with conductive vias, and related structures and devices
US8368152B2 (en) 2011-04-18 2013-02-05 Taiwan Semiconductor Manufacturing Company, Ltd. MEMS device etch stop
US8729673B1 (en) 2011-09-21 2014-05-20 Sandia Corporation Structured wafer for device processing

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010504649A (ja) * 2006-09-20 2010-02-12 ザ ボード オブ トラスティーズ オブ ザ ユニヴァーシティー オブ イリノイ 転写可能な半導体構造、デバイス、及びデバイスコンポーネントを作成するための剥離方法
JP2014504457A (ja) * 2010-12-24 2014-02-20 アイ・オゥ・セミコンダクター・インコーポレイテッド 半導体デバイスのためのトラップリッチ層
US20140264770A1 (en) * 2013-03-15 2014-09-18 Sandia Corporation Method of forming through substrate vias (tsvs) and singulating and releasing die having the tsvs from a mechanical support substrate

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019134165A (ja) * 2018-02-02 2019-08-08 インフィニオン テクノロジーズ アクチエンゲゼルシャフトＩｎｆｉｎｅｏｎ Ｔｅｃｈｎｏｌｏｇｉｅｓ ＡＧ ウェハ合成物および半導体コンポーネントの製造方法
JP7438664B2 (ja) 2018-02-02 2024-02-27 インフィニオン テクノロジーズ アクチエンゲゼルシャフト ウェハ合成物および半導体コンポーネントの製造方法
CN113912005A (zh) * 2021-10-08 2022-01-11 天津大学 一种基于柔性铰链结构的xy全解耦微运动平台
CN113912005B (zh) * 2021-10-08 2023-02-03 天津大学 一种基于柔性铰链结构的xy全解耦微运动平台
WO2025235300A1 (en) * 2024-05-08 2025-11-13 Micron Technology, Inc. Corrosion-susceptible bonding layer in assisting semiconductor wafer debonding

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Publication number Publication date
SG11201700918RA (en) 2017-04-27
TW201633366A (zh) 2016-09-16
TWI585820B (zh) 2017-06-01
KR20170066354A (ko) 2017-06-14
CN106688077A (zh) 2017-05-17
BR112017006167A2 (pt) 2018-04-10
US20160093591A1 (en) 2016-03-31
EP3198634A1 (en) 2017-08-02
US9922956B2 (en) 2018-03-20
HK1232339A1 (zh) 2018-01-05
WO2016048649A1 (en) 2016-03-31

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