JP2017527940A - 高速フラッシュメモリシステム用のビット線レギュレータ - Google Patents
高速フラッシュメモリシステム用のビット線レギュレータ Download PDFInfo
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- JP2017527940A JP2017527940A JP2017503143A JP2017503143A JP2017527940A JP 2017527940 A JP2017527940 A JP 2017527940A JP 2017503143 A JP2017503143 A JP 2017503143A JP 2017503143 A JP2017503143 A JP 2017503143A JP 2017527940 A JP2017527940 A JP 2017527940A
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- bit line
- memory system
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/24—Bit-line control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
- G11C16/28—Sensing or reading circuits; Data output circuits using differential sensing or reference cells, e.g. dummy cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/30—Power supply circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/021—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in voltage or current generators
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
- G11C29/26—Accessing multiple arrays
- G11C29/28—Dependent multiple arrays, e.g. multi-bit arrays
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C2029/1204—Bit line control
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/04—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
Abstract
Description
Claims (20)
- メモリシステムであって、
行及び列に組織されているメモリセルのアレイであって、メモリセルの各列がビット線に連結される、アレイと、
バイアス電圧を各ビット線に印加するためのビット線レギュレータと、を備え、前記ビット線レギュレータが、
複数のトリムビットを出力するための第1の回路と、
前記複数のトリムビットに応じて前記バイアス電圧を調整する第2の回路と、を備える、メモリシステム。 - 前記第1の回路が、前記バイアス電圧と基準電圧との比較に基づいて前記トリムビットを生成する、請求項1に記載のメモリシステム。
- 前記第1の回路が、
前記バイアス電圧に基づいてサンプル電圧を生成するためのサンプルアンドホールド回路と、
前記サンプル電圧を基準電圧と比較し、出力を生成するためのコンパレータと、
前記コンパレータから前記出力を受け取り、前記トリムビットを生成するためのアービタと、を備える、請求項1に記載のメモリシステム。 - 前記第2の回路が、
前記トリムビットのうちの1つに応じて前記出力強度を調整するためのブースト回路を備える、請求項1に記載のメモリシステム。 - 前記第2の回路が、
前記出力強度を調整するための複数のブースト回路を備え、それぞれがトリムビットに応答する、請求項4に記載のメモリシステム。 - 前記第2の回路が、
前記ブースト回路を有効にするための制御信号を更に備える、請求項4に記載のメモリシステム。 - 前記第2の回路が、
前記複数のブースト回路を有効にするための制御信号を更に備える、請求項5に記載のメモリシステム。 - 前記メモリセルがフラッシュメモリセルを備える、請求項1に記載のメモリシステム。
- メモリシステムであって、
行及び列に組織されているメモリセルのアレイであって、メモリセルの各列がビット線に連結される、アレイと、
バイアス電圧を各ビット線に印加するためのビット線レギュレータと、を備え、前記ビット線レギュレータが、
前記バイアス電圧に基づいてサンプル電圧を生成するためのサンプルアンドホールド回路と、
前記サンプル電圧を基準電圧と比較し、出力を生成するためのコンパレータと、
前記コンパレータから前記出力を受け取り、トリムビットを生成するためのアービタと、
前記トリムビットのうちの1つ以上に応じて前記出力強度を調整するためのブースト回路を備える、メモリシステム。 - 前記メモリセルがフラッシュメモリセルを備える、請求項9に記載のメモリシステム。
- 前記トリムビットが8個のビットを備える、請求項9に記載のメモリシステム。
- 前記基準電圧が1.0ボルトである、請求項9に記載のメモリシステム。
- 前記アービタがコントローラを備える、請求項9に記載のメモリシステム。
- 前記アービタが個別論理を備える、請求項9に記載のメモリシステム。
- メモリシステム内でビット線のバイアス電圧を調整する方法であって、
前記ビット線の電圧をサンプリングして、サンプル電圧を生成することと、
前記サンプル電圧を基準電圧と比較して、出力を生成することと、
前記出力に応じて複数のトリムビットを生成することと、
前記複数のトリムビットに応じて前記バイアス電圧を変更することと、を含む、方法。 - 前記変更する工程が、ビット線レギュレータによって実施される、請求項15に記載の方法。
- 前記変更する工程が、1つ以上のブースト回路を前記ビット線に連結することを含む、請求項15に記載の方法。
- 前記変更する工程が、制御信号によって有効にされる、請求項15に記載の方法。
- 前記基準電圧が1.0ボルトである、請求項15に記載の方法。
- 前記ビット線を使用してメモリセルを読み出すことを更に含む、請求項15に記載の方法。
Applications Claiming Priority (5)
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CN201410429526.1 | 2014-07-22 | ||
CN201410429526.1A CN105336369B (zh) | 2014-07-22 | 2014-07-22 | 用于高速闪存存储器系统的位线调节器 |
US14/486,673 | 2014-09-15 | ||
US14/486,673 US9378834B2 (en) | 2014-07-22 | 2014-09-15 | Bitline regulator for high speed flash memory system |
PCT/US2015/035214 WO2016014164A1 (en) | 2014-07-22 | 2015-06-10 | Bitline regulator for high speed flash memory system |
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JP2017527940A true JP2017527940A (ja) | 2017-09-21 |
JP6225293B2 JP6225293B2 (ja) | 2017-11-01 |
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US (1) | US9378834B2 (ja) |
EP (1) | EP3172732B1 (ja) |
JP (1) | JP6225293B2 (ja) |
KR (1) | KR101808492B1 (ja) |
CN (1) | CN105336369B (ja) |
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US20160188716A1 (en) * | 2014-12-24 | 2016-06-30 | Quixey, Inc. | Crowd-Sourced Crawling |
CN108615541B (zh) * | 2016-12-09 | 2021-04-06 | 中芯国际集成电路制造(上海)有限公司 | 一种位线预充电和放电电路以及存储器 |
CN108470573A (zh) * | 2017-02-23 | 2018-08-31 | 中芯国际集成电路制造(上海)有限公司 | 非易失性存储器 |
US10141900B2 (en) | 2017-04-26 | 2018-11-27 | Sandisk Technologies Llc | Offset trimming for differential amplifier |
CN108492840B (zh) * | 2018-03-12 | 2020-11-13 | 武汉新芯集成电路制造有限公司 | 灵敏放大器 |
KR20210110376A (ko) * | 2019-03-26 | 2021-09-07 | 양쯔 메모리 테크놀로지스 씨오., 엘티디. | 다중 비트라인 바이어스 전압을 인가하여 비 휘발성 메모리 디바이스에서 프로그래밍하는 방법 |
US10811111B1 (en) | 2019-03-26 | 2020-10-20 | Yangtze Memory Technologies Co., Ltd. | Non-volatile memory device and method for programming in non-volatile memory device by applying multiple bitline bias voltages |
KR102652215B1 (ko) | 2019-04-30 | 2024-03-27 | 양쯔 메모리 테크놀로지스 씨오., 엘티디. | 판독 시간을 단축할 수 있는 메모리 시스템 |
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- 2014-09-15 US US14/486,673 patent/US9378834B2/en active Active
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2015
- 2015-06-10 KR KR1020177004735A patent/KR101808492B1/ko active IP Right Grant
- 2015-06-10 JP JP2017503143A patent/JP6225293B2/ja active Active
- 2015-06-10 EP EP15731202.6A patent/EP3172732B1/en active Active
- 2015-06-24 TW TW104120310A patent/TWI579859B/zh active
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TW201611032A (zh) | 2016-03-16 |
TWI579859B (zh) | 2017-04-21 |
US9378834B2 (en) | 2016-06-28 |
EP3172732A1 (en) | 2017-05-31 |
EP3172732B1 (en) | 2019-02-20 |
CN105336369A (zh) | 2016-02-17 |
KR101808492B1 (ko) | 2017-12-12 |
CN105336369B (zh) | 2019-09-10 |
KR20170024127A (ko) | 2017-03-06 |
JP6225293B2 (ja) | 2017-11-01 |
US20160027519A1 (en) | 2016-01-28 |
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