JP2017519418A5 - - Google Patents
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- JP2017519418A5 JP2017519418A5 JP2016567410A JP2016567410A JP2017519418A5 JP 2017519418 A5 JP2017519418 A5 JP 2017519418A5 JP 2016567410 A JP2016567410 A JP 2016567410A JP 2016567410 A JP2016567410 A JP 2016567410A JP 2017519418 A5 JP2017519418 A5 JP 2017519418A5
- Authority
- JP
- Japan
- Prior art keywords
- wires
- wire
- current
- current flow
- voltage sources
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 claims 12
- 238000004891 communication Methods 0.000 claims 7
- 230000008878 coupling Effects 0.000 claims 7
- 238000010168 coupling process Methods 0.000 claims 7
- 238000005859 coupling reaction Methods 0.000 claims 7
- 230000003213 activating effect Effects 0.000 claims 2
- 230000004913 activation Effects 0.000 claims 1
- 239000002131 composite material Substances 0.000 claims 1
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US14/278,682 US9710412B2 (en) | 2014-05-15 | 2014-05-15 | N-factorial voltage mode driver |
| US14/278,682 | 2014-05-15 | ||
| PCT/US2015/030227 WO2015175439A1 (en) | 2014-05-15 | 2015-05-11 | N-factorial voltage mode driver |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2017519418A JP2017519418A (ja) | 2017-07-13 |
| JP2017519418A5 true JP2017519418A5 (enExample) | 2018-06-14 |
Family
ID=53277048
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2016567410A Pending JP2017519418A (ja) | 2014-05-15 | 2015-05-11 | N階乗電圧モードドライバ |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US9710412B2 (enExample) |
| EP (1) | EP3143740A1 (enExample) |
| JP (1) | JP2017519418A (enExample) |
| KR (1) | KR20170005102A (enExample) |
| CN (1) | CN106462527B (enExample) |
| WO (1) | WO2015175439A1 (enExample) |
Families Citing this family (25)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9288089B2 (en) | 2010-04-30 | 2016-03-15 | Ecole Polytechnique Federale De Lausanne (Epfl) | Orthogonal differential vector signaling |
| US9251873B1 (en) | 2010-05-20 | 2016-02-02 | Kandou Labs, S.A. | Methods and systems for pin-efficient memory controller interface using vector signaling codes for chip-to-chip communications |
| WO2014172377A1 (en) | 2013-04-16 | 2014-10-23 | Kandou Labs, S.A. | Methods and systems for high bandwidth communications interface |
| JP6317474B2 (ja) | 2014-02-02 | 2018-04-25 | カンドウ ラボズ ソシエテ アノニム | 制約isi比を用いる低電力チップ間通信の方法および装置 |
| KR102240544B1 (ko) | 2014-02-28 | 2021-04-19 | 칸도우 랩스 에스에이 | 클록 임베디드 벡터 시그널링 코드 |
| US11240076B2 (en) | 2014-05-13 | 2022-02-01 | Kandou Labs, S.A. | Vector signaling code with improved noise margin |
| US9509437B2 (en) | 2014-05-13 | 2016-11-29 | Kandou Labs, S.A. | Vector signaling code with improved noise margin |
| US9112550B1 (en) | 2014-06-25 | 2015-08-18 | Kandou Labs, SA | Multilevel driver for high speed chip-to-chip communications |
| US9900186B2 (en) | 2014-07-10 | 2018-02-20 | Kandou Labs, S.A. | Vector signaling codes with increased signal to noise characteristics |
| US9432082B2 (en) | 2014-07-17 | 2016-08-30 | Kandou Labs, S.A. | Bus reversable orthogonal differential vector signaling codes |
| US9461862B2 (en) | 2014-08-01 | 2016-10-04 | Kandou Labs, S.A. | Orthogonal differential vector signaling codes with embedded clock |
| EP3700154B1 (en) | 2015-06-26 | 2024-10-02 | Kandou Labs, S.A. | High speed communications system |
| US10055372B2 (en) | 2015-11-25 | 2018-08-21 | Kandou Labs, S.A. | Orthogonal differential vector signaling codes with embedded clock |
| WO2017190102A1 (en) * | 2016-04-28 | 2017-11-02 | Kandou Labs, S.A. | Low power multilevel driver |
| EP3610576B1 (en) | 2017-04-14 | 2022-12-28 | Kandou Labs, S.A. | Pipelined forward error correction for vector signaling code channel |
| DE112018002643T5 (de) | 2017-05-22 | 2020-05-07 | Invention Mine, Llc | Multimodale datengetriebene taktwiederherstellungsschaltung |
| US10116468B1 (en) | 2017-06-28 | 2018-10-30 | Kandou Labs, S.A. | Low power chip-to-chip bidirectional communications |
| US10693587B2 (en) | 2017-07-10 | 2020-06-23 | Kandou Labs, S.A. | Multi-wire permuted forward error correction |
| KR102349415B1 (ko) * | 2017-08-07 | 2022-01-11 | 삼성전자주식회사 | 펄스 진폭 변조 송신기 및 펄스 진폭 변조 수신기 |
| US10496583B2 (en) | 2017-09-07 | 2019-12-03 | Kandou Labs, S.A. | Low power multilevel driver for generating wire signals according to summations of a plurality of weighted analog signal components having wire-specific sub-channel weights |
| US10467177B2 (en) | 2017-12-08 | 2019-11-05 | Kandou Labs, S.A. | High speed memory interface |
| EP3732840B1 (en) | 2017-12-28 | 2024-05-01 | Kandou Labs, S.A. | Synchronously-switched multi-input demodulating comparator |
| US10554450B2 (en) * | 2018-03-14 | 2020-02-04 | Samsung Display Co., Ltd. | High resolution voltage-mode driver |
| US12063034B2 (en) | 2022-08-30 | 2024-08-13 | Kandou Labs SA | Line driver impedance calibration for multi-wire data bus |
| WO2024049482A1 (en) | 2022-08-30 | 2024-03-07 | Kandou Labs SA | Pre-scaler for orthogonal differential vector signalling |
Family Cites Families (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3360861B2 (ja) * | 1993-03-02 | 2003-01-07 | 株式会社ソニー木原研究所 | シリアルディジタルデータの伝送方法及び伝送装置 |
| US6005895A (en) | 1996-12-20 | 1999-12-21 | Rambus Inc. | Apparatus and method for multilevel signaling |
| US6556628B1 (en) * | 1999-04-29 | 2003-04-29 | The University Of North Carolina At Chapel Hill | Methods and systems for transmitting and receiving differential signals over a plurality of conductors |
| US6452420B1 (en) * | 2001-05-24 | 2002-09-17 | National Semiconductor Corporation | Multi-dimensional differential signaling (MDDS) |
| US7167527B1 (en) * | 2002-05-02 | 2007-01-23 | Integrated Memory Logic, Inc. | System and method for multi-symbol interfacing |
| US7358869B1 (en) | 2003-08-20 | 2008-04-15 | University Of Pittsburgh | Power efficient, high bandwidth communication using multi-signal-differential channels |
| JP2005086662A (ja) * | 2003-09-10 | 2005-03-31 | Seiko Epson Corp | 半導体装置 |
| US7227382B1 (en) | 2005-02-01 | 2007-06-05 | Advanced Micro Devices, Inc. | Transmit based equalization using a voltage mode driver |
| US7567616B2 (en) * | 2005-02-17 | 2009-07-28 | Realtek Semiconductor Corp. | Feedback equalizer for a communications receiver |
| US8222917B2 (en) * | 2005-11-03 | 2012-07-17 | Agate Logic, Inc. | Impedance matching and trimming apparatuses and methods using programmable resistance devices |
| US7746937B2 (en) * | 2006-04-14 | 2010-06-29 | Formfactor, Inc. | Efficient wired interface for differential signals |
| WO2007125963A1 (ja) * | 2006-04-27 | 2007-11-08 | Panasonic Corporation | 多重差動伝送システム |
| US8649460B2 (en) * | 2007-06-05 | 2014-02-11 | Rambus Inc. | Techniques for multi-wire encoding with an embedded clock |
| US8159375B2 (en) * | 2007-10-01 | 2012-04-17 | Rambus Inc. | Simplified receiver for use in multi-wire communication |
| US8848810B2 (en) * | 2008-03-05 | 2014-09-30 | Qualcomm Incorporated | Multiple transmitter system and method |
| US7710144B2 (en) * | 2008-07-01 | 2010-05-04 | International Business Machines Corporation | Controlling for variable impedance and voltage in a memory system |
| EP2412136B1 (en) | 2009-03-27 | 2017-03-01 | Rambus Inc. | Voltage mode transmitter equalizer |
| US20110133773A1 (en) | 2009-12-04 | 2011-06-09 | Uniram Technology Inc. | High Performance Output Drivers and Anti-Reflection Circuits |
| US9319043B2 (en) | 2010-02-02 | 2016-04-19 | Nokia Technologies Oy | Generation of differential signals |
| US8208578B2 (en) * | 2010-06-21 | 2012-06-26 | North Carolina State University | Systems, methods, and computer readable media for fractional pre-emphasis of multi-mode interconnect |
| US9071220B2 (en) | 2013-03-07 | 2015-06-30 | Qualcomm Incorporated | Efficient N-factorial differential signaling termination network |
-
2014
- 2014-05-15 US US14/278,682 patent/US9710412B2/en active Active
-
2015
- 2015-05-11 JP JP2016567410A patent/JP2017519418A/ja active Pending
- 2015-05-11 KR KR1020167034948A patent/KR20170005102A/ko not_active Withdrawn
- 2015-05-11 CN CN201580025096.XA patent/CN106462527B/zh active Active
- 2015-05-11 EP EP15726782.4A patent/EP3143740A1/en not_active Withdrawn
- 2015-05-11 WO PCT/US2015/030227 patent/WO2015175439A1/en not_active Ceased
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