JP2017519356A - 電子ビームによる一方向の層上金属 - Google Patents
電子ビームによる一方向の層上金属 Download PDFInfo
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- JP2017519356A JP2017519356A JP2016566227A JP2016566227A JP2017519356A JP 2017519356 A JP2017519356 A JP 2017519356A JP 2016566227 A JP2016566227 A JP 2016566227A JP 2016566227 A JP2016566227 A JP 2016566227A JP 2017519356 A JP2017519356 A JP 2017519356A
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Images
Classifications
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- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/02—Details
- H01J37/04—Arrangements of electrodes and associated parts for generating or controlling the discharge, e.g. electron-optical arrangement, ion-optical arrangement
- H01J37/045—Beam blanking or chopping, i.e. arrangements for momentarily interrupting exposure to the discharge
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/30—Electron-beam or ion-beam tubes for localised treatment of objects
- H01J37/317—Electron-beam or ion-beam tubes for localised treatment of objects for changing properties of the objects or for applying thin layers thereon, e.g. for ion implantation
- H01J37/3174—Particle-beam lithography, e.g. electron beam lithography
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/30—Electron-beam or ion-beam tubes for localised treatment of objects
- H01J37/317—Electron-beam or ion-beam tubes for localised treatment of objects for changing properties of the objects or for applying thin layers thereon, e.g. for ion implantation
- H01J37/3174—Particle-beam lithography, e.g. electron beam lithography
- H01J37/3177—Multi-beam, e.g. fly's eye, comb probe
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0277—Electrolithographic processes
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
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Abstract
Description
当該出願は、米国仮特許出願第62/012,220号(出願日:2014年6月13日)による恩恵を主張する。当該仮出願の内容は全て、参照により本願に組み込まれる。
(1)ビアおよびカットの全ての設計ルールを簡略化して、ビアが占有可能で、ラインカットの開始位置および終了位置である位置の数を削減する。
(2)ビア間の距離と同様に、カットの開始および終了の配置の暗号化は、n*最短距離として暗号化される(これによって、カットの開始位置および終了位置のそれぞれの64ビットのアドレスを送信する必要がなくなる。ビア位置についても同様である)。
(3)ツールのカラム毎に、ウェハのこの部分に含まれるカットおよびビアを形成するために必要なデータのみを、カラムコンピュータに転送する(各カラムは、(2)と同様に暗号化された状態で、必要なデータのみを受信する)。および/または
(4)ツール内のカラム毎に、送信されるエリアは、上部および下部でn本のラインずつ、さらに、幅方向はxずつ、増加する(したがって、対応するカラムコンピュータは、ウェハ全体のデータを送信しなくても、ウェハ温度および位置合わせの変化についてオンザフライで調整が可能である)。ある実施形態において、1または複数のこのようなデータ削減方法を実装することで、少なくともある程度までは電子ビームツールを簡略化することが可能になる。例えば、マルチカラム電子ビームツールにおいて一の専用カラムに通常対応付けられている専用のコンピュータまたはプロセッサは、簡略化されるとしてもよいし、または、全て削除されるとしてもよい。つまり、オンボード専用ロジック機能を持つ一のカラムは簡略化されて、ロジック機能をボード外に移動させるとしてもよいし、または、電子ビームツールの各カラムに必要なオンボードロジック機能の量を削減するとしてもよい。
前のカットからの間隔
A:+5(間隙1102として図示)、+1、
B:x(カットなし)(xが何であっても暗号化されると、距離についてカットなし)
C:+1(左側のカットの終了ポイント)、+4(カット1102の開始位置と縦方向に位置合わせされている大きなカットの開始位置)、+3(この大きなカットの終了位置)
D:+3、+4、
E:+3,+2,+1,+4
Claims (20)
- 集積回路のメタライゼーション層のレイアウトであって、前記レイアウトは、
第1の幅および第1のピッチを持ち第1の方向に平行な、複数の一方向ラインを有する第1の領域と、
第2の幅および第2のピッチを持ち前記第1の方向に平行な、複数の一方向ラインを有する第2の領域と、
第3の幅および第3のピッチを持ち前記第1の方向に平行な、複数の一方向ラインを有する第3の領域と
を備え、
前記第2の幅および前記第2のピッチはそれぞれ、前記第1の幅および前記第1のピッチとは異なり、
前記第3の幅は、前記第1の幅および前記第2の幅とは異なり、前記第3のピッチは前記第1のピッチおよび前記第2のピッチとは異なる
レイアウト。 - 前記第1の方向と直交する第2の方向において、前記第2の領域の前記複数の一方向ラインは、前記第1の領域の前記複数の一方向ラインとは重ならず、前記第3の領域の前記複数の一方向ラインは、前記第1の領域の前記複数の一方向ラインまたは前記第2の領域の前記複数の一方向ラインとは重ならない
請求項1に記載のレイアウト。 - 前記第1の方向と直交する第2の方向において、前記第2の領域の前記複数の一方向ラインのうち一部は、前記第1の領域の前記複数の一方向ラインと重なる
請求項1または2に記載のレイアウト。 - 前記第2の領域の前記複数の一方向ラインと、前記第1の領域の前記複数の一方向ラインとは、交互嵌合している
請求項3に記載のレイアウト。 - 前記第2の幅は前記第1の幅の1.5倍であり、前記第2のピッチは前記第1のピッチの1.5倍であり、前記第3の幅は前記第1の幅の3倍であり、前記第3のピッチは前記第1のピッチの3倍である
請求項1から4のいずれか一項に記載のレイアウト。 - 前記第1の領域はロジック領域であり、前記第2の領域はアナログ/IO領域であり、前記第3の領域はSRAM領域である
請求項1から5のいずれか一項に記載のレイアウト。 - 前記レイアウトの前記第1の領域、前記第2の領域または前記第3の領域はいずれも、段差、直交方向のラインまたはフックを含むラインを含まない
請求項1から6のいずれか一項に記載のレイアウト。 - 集積回路のメタライゼーション層であって、前記メタライゼーション層は、
第1の幅および第1のピッチを持ち第1の方向に平行な、複数の一方向ワイヤを有する第1の領域と、
第2の幅および第2のピッチを持ち前記第1の方向に平行な、複数の一方向ワイヤを有する第2の領域と、
第3の幅および第3のピッチを持ち前記第1の方向に平行な、複数の一方向ワイヤを有する第3の領域と
を備え、
前記第2の幅および前記第2のピッチはそれぞれ、前記第1の幅および前記第1のピッチとは異なり、
前記第3の幅は、前記第1の幅および前記第2の幅とは異なり、前記第3のピッチは、前記第1のピッチおよび前記第2のピッチとは異なる
メタライゼーション層。 - 前記第1の方向と直交する第2の方向において、前記第2の領域の前記複数の一方向ワイヤは、前記第1の領域の前記複数の一方向ワイヤとは重ならず、前記第3の領域の前記複数の一方向ワイヤは、前記第1の領域の前記複数の一方向ワイヤ、または、前記第2の領域の前記複数の一方向ワイヤとは重ならない
請求項8に記載のメタライゼーション層。 - 前記第1の方向と直交する第2の方向において、前記第2の領域の前記複数の一方向ワイヤの一部は、前記第1の領域の前記複数の一方向ワイヤと重なる
請求項8に記載のメタライゼーション層。 - 前記第2の領域の前記複数の一方向ワイヤと、前記第1の領域の前記複数の一方向ワイヤとは、交互嵌合している
請求項10に記載のメタライゼーション層。 - 前記第2の幅は前記第1の幅の1.5倍であり、前記第2のピッチは前記第1のピッチの1.5倍であり、前記第3の幅は前記第1の幅の3倍であり、前記第3のピッチは前記第1のピッチの3倍である
請求項8から11のいずれか一項に記載のメタライゼーション層。 - 前記第1の領域はロジック領域であり、前記第2の領域はアナログ/IO領域であり、前記第3の領域はSRAM領域である
請求項8から12のいずれか一項に記載のメタライゼーション層。 - 前記メタライゼーション層の前記第1の領域、前記第2の領域または前記第3の領域はいずれも、複数の段差、複数の直交方向のワイヤまたは複数のフックを含む複数のワイヤを含まない
請求項8から13のいずれか一項に記載のメタライゼーション層。 - 半導体構造用のパターンを形成する方法であって、
基板の上方に複数のラインで構成されるパターンを形成する段階を備え、
前記複数のラインで構成されるパターンは、
第1の幅および第1のピッチを持ち第1の方向に平行な、複数の一方向ラインを有する第1の領域と、
第2の幅および第2のピッチを持ち前記第1の方向に平行な、複数の一方向ラインを有する第2の領域と、
第3の幅および第3のピッチを持ち前記第1の方向に平行な、複数の一方向ラインを有する第3の領域と、
を有し、
前記第2の幅および前記第2のピッチはそれぞれ、前記第1の幅および前記第1のピッチとは異なり、
前記第3の幅は、前記第1の幅および前記第2の幅とは異なり、前記第3のピッチは、前記第1のピッチおよび前記第2のピッチとは異なり、
前記方法はさらに、
電子ビームツールのスキャン方向に平行に前記複数のラインで構成されるパターンを提供するべく、前記電子ビームツールにおいて前記基板を位置合わせする段階と、
前記スキャン方向に沿って前記基板をスキャンすることによって前記複数のラインで構成されるパターンについて複数のライン断絶部を設けるべく、前記複数のラインで構成されるパターンの内部または上方に複数のカットで構成されるパターンを形成する段階と
を備え、
前記スキャン方向は、前記第1の方向に直交する方向である
方法。 - 前記複数のカットで構成されるパターンを形成する段階は、3ビームスタッガードブランカアパーチャアレイを利用する段階を有する
請求項15に記載の方法。 - 前記複数のカットで構成されるパターンを形成する段階は、ユニバーサルカッターブランカアパーチャアレイを利用する段階を有する
請求項15に記載の方法。 - 前記複数のカットで構成されるパターンを形成する段階は、非ユニバーサルカッターブランカアパーチャアレイを利用する段階を有する
請求項15に記載の方法。 - 前記複数のラインで構成されるパターンを形成する段階は、ピッチ半減技術またはピッチ四分割技術を利用する段階を有する
請求項15から18のいずれか一項に記載の方法。 - 前記複数のカットで構成されるパターンを形成する段階は、フォトレジスト材料の層のうち複数の領域を露光する段階を有する
請求項15から19のいずれか一項に記載の方法。
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- 2014-12-19 KR KR1020167031167A patent/KR102395478B1/ko active IP Right Grant
- 2014-12-19 CN CN201480078816.4A patent/CN106463352B/zh active Active
- 2014-12-19 WO PCT/US2014/071645 patent/WO2015191102A1/en active Application Filing
- 2014-12-19 JP JP2016566227A patent/JP6522662B2/ja active Active
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KR20190032225A (ko) * | 2017-09-18 | 2019-03-27 | 아이엠에스 나노패브릭케이션 게엠베하 | 제한된 배치 그리드를 이용하여 타겟을 조사하는 방법 |
JP2019071411A (ja) * | 2017-09-18 | 2019-05-09 | アイエムエス ナノファブリケーション ゲーエムベーハー | 限定的位置付けグリッドを用いるターゲットの照射方法 |
JP7178841B2 (ja) | 2017-09-18 | 2022-11-28 | アイエムエス ナノファブリケーション ゲーエムベーハー | 限定的位置付けグリッドを用いるターゲットの照射方法 |
US11569064B2 (en) | 2017-09-18 | 2023-01-31 | Ims Nanofabrication Gmbh | Method for irradiating a target using restricted placement grids |
KR102633436B1 (ko) | 2017-09-18 | 2024-02-15 | 아이엠에스 나노패브릭케이션 게엠베하 | 제한된 배치 그리드를 이용하여 타겟을 조사하는 방법 |
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KR20170015885A (ko) | 2017-02-10 |
EP3155648A1 (en) | 2017-04-19 |
KR102395478B1 (ko) | 2022-05-09 |
JP6522662B2 (ja) | 2019-05-29 |
CN106463352B (zh) | 2020-06-19 |
WO2015191102A1 (en) | 2015-12-17 |
EP3155648A4 (en) | 2018-03-07 |
US20170077029A1 (en) | 2017-03-16 |
US10014256B2 (en) | 2018-07-03 |
CN106463352A (zh) | 2017-02-22 |
TWI567575B (zh) | 2017-01-21 |
TW201606536A (zh) | 2016-02-16 |
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