JP2017511044A - エラー検出最適化を容易にするための共有バスを介したビット割振り - Google Patents

エラー検出最適化を容易にするための共有バスを介したビット割振り Download PDF

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Publication number
JP2017511044A
JP2017511044A JP2016554356A JP2016554356A JP2017511044A JP 2017511044 A JP2017511044 A JP 2017511044A JP 2016554356 A JP2016554356 A JP 2016554356A JP 2016554356 A JP2016554356 A JP 2016554356A JP 2017511044 A JP2017511044 A JP 2017511044A
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Prior art keywords
word
bit
optimization
significant
error detection
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JP2016554356A
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Japanese (ja)
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JP2017511044A5 (enExample
Inventor
祥一郎 仙石
祥一郎 仙石
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クアルコム，インコーポレイテッド
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Publication of JP2017511044A publication Critical patent/JP2017511044A/ja
Publication of JP2017511044A5 publication Critical patent/JP2017511044A5/ja
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1675—Temporal synchronisation or re-synchronisation of redundant processing components
    • G06F11/1679—Temporal synchronisation or re-synchronisation of redundant processing components at clock signal level
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test buses, lines or interfaces, e.g. stuck-at or open line faults
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
    • G06F11/3027—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is a bus
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
    • H03M13/095—Error detection codes other than CRC and single parity bit codes
    • H03M13/096—Checksums
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0016—Inter-integrated circuit (I2C)

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Computing Systems (AREA)
  • Probability & Statistics with Applications (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Information Transfer Systems (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
JP2016554356A 2014-02-28 2015-02-28 エラー検出最適化を容易にするための共有バスを介したビット割振り Pending JP2017511044A (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201461946647P 2014-02-28 2014-02-28
US61/946,647 2014-02-28
US14/634,106 US20150248373A1 (en) 2014-02-28 2015-02-27 Bit allocation over a shared bus to facilitate an error detection optimization
US14/634,106 2015-02-27
PCT/US2015/018202 WO2015131164A1 (en) 2014-02-28 2015-02-28 Bit allocation over a shared bus to facilitate an error detection optimization

Publications (2)

Publication Number Publication Date
JP2017511044A true JP2017511044A (ja) 2017-04-13
JP2017511044A5 JP2017511044A5 (enExample) 2018-03-22

Family

ID=54006839

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2016554356A Pending JP2017511044A (ja) 2014-02-28 2015-02-28 エラー検出最適化を容易にするための共有バスを介したビット割振り

Country Status (6)

Country Link
US (1) US20150248373A1 (enExample)
EP (1) EP3111561A1 (enExample)
JP (1) JP2017511044A (enExample)
KR (1) KR20160125411A (enExample)
CN (1) CN106068505A (enExample)
WO (1) WO2015131164A1 (enExample)

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US9778971B2 (en) * 2011-09-27 2017-10-03 Mitsubishi Electric Corporation Slave device, master device, and communication method
US9690725B2 (en) 2014-01-14 2017-06-27 Qualcomm Incorporated Camera control interface extension with in-band interrupt
US9996488B2 (en) 2013-09-09 2018-06-12 Qualcomm Incorporated I3C high data rate (HDR) always-on image sensor 8-bit operation indicator and buffer over threshold indicator
US9519603B2 (en) 2013-09-09 2016-12-13 Qualcomm Incorporated Method and apparatus to enable multiple masters to operate in a single master bus architecture
US10353837B2 (en) 2013-09-09 2019-07-16 Qualcomm Incorporated Method and apparatus to enable multiple masters to operate in a single master bus architecture
EP3055929A1 (en) 2013-10-09 2016-08-17 Qualcomm Incorporated ERROR DETECTION CAPABILITY OVER CCIe PROTOCOL
US9684624B2 (en) 2014-01-14 2017-06-20 Qualcomm Incorporated Receive clock calibration for a serial bus
WO2015126983A1 (en) * 2014-02-18 2015-08-27 Qualcomm Incorporated Technique to avoid metastability condition and avoid unintentional state changes of legacy i2c devices on a multi-mode bus
US10019306B2 (en) * 2016-04-27 2018-07-10 Western Digital Technologies, Inc. Collision detection for slave storage devices
WO2017189206A1 (en) * 2016-04-27 2017-11-02 Qualcomm Incorporated I3c high data rate (hdr) always-on image sensor 8-bit operation indicator and buffer over threshold indicator
JP6786871B2 (ja) 2016-05-18 2020-11-18 ソニー株式会社 通信装置、通信方法、プログラム、および、通信システム
US20180054216A1 (en) * 2016-08-22 2018-02-22 Qualcomm Incorporated Flipped bits for error detection and correction for symbol transition clocking transcoding
JP6953226B2 (ja) * 2017-08-04 2021-10-27 ソニーセミコンダクタソリューションズ株式会社 通信装置、通信方法、プログラム、および、通信システム
JP7031961B2 (ja) 2017-08-04 2022-03-08 ソニーセミコンダクタソリューションズ株式会社 通信装置、通信方法、プログラム、および、通信システム
JP2023089317A (ja) * 2020-05-11 2023-06-28 ソニーセミコンダクタソリューションズ株式会社 通信装置及び通信システム
TWI837031B (zh) * 2023-06-28 2024-03-21 明泰科技股份有限公司 I2c匯流排監控裝置

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JPS60500696A (ja) * 1983-03-09 1985-05-09 ラ・テレフオニ・アンデユストリエル・エ・コメルシアル・テリク・アルカテル 時多重伝送のための２進デ−タのコ−ド変換法及びデバイス
JP2005210159A (ja) * 2004-01-20 2005-08-04 Sharp Corp データ伝送装置およびデータ伝送方法
US20080152026A1 (en) * 2006-12-22 2008-06-26 Nir Dahan Sender, receiver and method of transferring information from a sender to a receiver
JP2010250048A (ja) * 2009-04-15 2010-11-04 Panasonic Corp 送信装置、受信装置、データ伝送システム、及び画像表示装置

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JP5510275B2 (ja) * 2010-11-08 2014-06-04 株式会社デンソー 通信システム、マスタノード、スレーブノード
CN202372971U (zh) * 2010-11-29 2012-08-08 意法半导体股份有限公司 电子设备和电子系统
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Publication number Priority date Publication date Assignee Title
JPS58501698A (ja) * 1981-10-08 1983-10-06 クリエイティプ・ストラテジィズ・プロプライエタリ−・リミテッド デ−タ通信システム
JPS60500696A (ja) * 1983-03-09 1985-05-09 ラ・テレフオニ・アンデユストリエル・エ・コメルシアル・テリク・アルカテル 時多重伝送のための２進デ−タのコ−ド変換法及びデバイス
JP2005210159A (ja) * 2004-01-20 2005-08-04 Sharp Corp データ伝送装置およびデータ伝送方法
US20080152026A1 (en) * 2006-12-22 2008-06-26 Nir Dahan Sender, receiver and method of transferring information from a sender to a receiver
JP2010250048A (ja) * 2009-04-15 2010-11-04 Panasonic Corp 送信装置、受信装置、データ伝送システム、及び画像表示装置

Also Published As

Publication number Publication date
EP3111561A1 (en) 2017-01-04
US20150248373A1 (en) 2015-09-03
CN106068505A (zh) 2016-11-02
WO2015131164A1 (en) 2015-09-03
KR20160125411A (ko) 2016-10-31

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