JP2017168582A - 半導体モジュール - Google Patents
半導体モジュール Download PDFInfo
- Publication number
- JP2017168582A JP2017168582A JP2016051416A JP2016051416A JP2017168582A JP 2017168582 A JP2017168582 A JP 2017168582A JP 2016051416 A JP2016051416 A JP 2016051416A JP 2016051416 A JP2016051416 A JP 2016051416A JP 2017168582 A JP2017168582 A JP 2017168582A
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- Prior art keywords
- wiring pattern
- transistor
- pad
- region
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 58
- 238000006243 chemical reaction Methods 0.000 claims abstract description 39
- 239000000758 substrate Substances 0.000 claims abstract description 39
- 239000003990 capacitor Substances 0.000 description 32
- 239000000463 material Substances 0.000 description 32
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 16
- 229910052802 copper Inorganic materials 0.000 description 16
- 239000010949 copper Substances 0.000 description 16
- 238000010586 diagram Methods 0.000 description 12
- 229910000679 solder Inorganic materials 0.000 description 9
- 229910052782 aluminium Inorganic materials 0.000 description 8
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 8
- 239000013256 coordination polymer Substances 0.000 description 8
- 230000017525 heat dissipation Effects 0.000 description 8
- 230000004048 modification Effects 0.000 description 7
- 238000012986 modification Methods 0.000 description 7
- 238000000034 method Methods 0.000 description 6
- 239000000919 ceramic Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 4
- 238000010521 absorption reaction Methods 0.000 description 2
- 238000006073 displacement reaction Methods 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 239000003985 ceramic capacitor Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
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- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/32—Means for protecting converters other than automatic disconnection
- H02M1/325—Means for protecting converters other than automatic disconnection with means for allowing continuous operation despite a fault, i.e. fault tolerant converters
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Abstract
【解決手段】半導体モジュール1は、回路基板10と、電力変換回路を構成する上及び下アーム用の第1及び第2トランジスタTr1,Tr2とを備える。回路基板は、第1及び第2絶縁部とそれらの間の導電層112とを有する基板11と、第1及び第2入力端子21,22が接続される第1及び第2入力用配線パターン12,13と、出力端子23が接続される出力用配線パターン14と、を備える。第1及び第2トランジスタは、第1及び第2入力用配線パターンを介して第1及び第2入力端子に電気的に接続されており、導電層は、第1入力用配線パターンと対向する第1領域と第1領域に電気的に接続される第2領域とを有する。第2領域は、第2入力用配線パターンに電気的に接続されており、導電層は、第1入力用配線パターン及び出力用配線パターンと第2絶縁部により絶縁されている。
【選択図】図2
Description
最初に、本発明の実施形態の内容を列記して説明する。
本発明の実施形態の具体例を、以下に図面を参照しつつ説明する。本発明はこれらの例示に限定されるものではなく、特許請求の範囲によって示され、特許請求の範囲と均等の意味及び範囲内でのすべての変更が含まれることが意図される。図面の説明においては同一要素には同一符号を付し、重複する説明を省略する。
図10は、半導体モジュール1の変形例である半導体モジュール1Aの一例を示す模式図である。図10では、ケース2の図示は省略しているが、半導体モジュール1Aはケース2を備えてもよい。
Claims (5)
- 電力変換回路を含む半導体モジュールであって、
回路基板と、
前記回路基板に搭載されており、前記電力変換回路における上アームを構成する第1トランジスタと、
前記回路基板に搭載されており、前記電力変換回路における下アームを構成しており前記第1トランジスタに電気的に直列接続される第2トランジスタと、
を備え、
前記回路基板は、
第1絶縁部、前記第1絶縁部上に設けられる第2絶縁部及び前記第1絶縁部と前記第2絶縁部との間に配置される導電層を有する基板と、
前記第2絶縁部上に設けられており、前記電力変換回路に第1電力を供給する第1入力端子が電気的に接続されると共に、前記第1トランジスタが搭載される第1入力用配線パターンと、
前記第2絶縁部上に設けられており、前記電力変換回路に前記第1電力より低い第2電力を供給する第2入力端子が電気的に接続される第2入力用配線パターンと、
前記第2絶縁部上に設けられており、前記電力変換回路からの出力電力を取り出す出力端子が接続されると共に、前記第2トランジスタが搭載される出力用配線パターンと、
を備え、
前記第1トランジスタは、前記第1入力用配線パターンを介して前記第1電力が入力されるように、前記第1入力用配線パターンに電気的に接続されており、
前記第2トランジスタは、前記第2入力用配線パターンを介して前記第2電力が入力されるように、前記第2入力用配線パターンに電気的に接続されており、
前記導電層は、
第1領域と、
前記第1領域に電気的に接続される第2領域と、
を有し、
前記第1領域は、前記第1入力用配線パターンと対向しており、
前記第2領域は、前記第2入力用配線パターンに電気的に接続されており、
前記導電層は、前記第1入力用配線パターン及び前記出力用配線パターンと前記第2絶縁部により絶縁されている、
半導体モジュール。 - 前記出力用配線パターンの一部は、前記第1入力用配線パターンと前記第2入力用配線パターンの間に配置されている、
請求項1に記載の半導体モジュール。 - 前記基板の厚さ方向からみて、前記導電層は、前記出力用配線パターンと重なっていない、
請求項1又は2に記載の半導体モジュール。 - 前記回路基板は、前記第2絶縁部上において、前記第1入力用配線パターンに隣接して設けられる補助配線パターンを有し、
前記導電層は、前記補助配線パターンと電気的に接続されており、
前記補助配線パターンと前記第1入力用配線パターンは、サージ電圧吸収素子により接続されている、
請求項1〜3の何れか一項に記載の半導体モジュール。 - 前記第1トランジスタを複数有し、
複数の前記第1トランジスタは、前記第1入力用配線パターンに搭載されると共に、電気的に並列接続されており、
前記第2トランジスタを複数有し、
複数の前記第2トランジスタは、前記出力用配線パターンに搭載されると共に、電気的に並列接続されている、
請求項1〜4の何れか一項に記載の半導体モジュール。
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US16/078,218 US10541208B2 (en) | 2016-03-15 | 2017-01-31 | Semiconductor module for a power conversion circuit for reliably reducing a voltage surge |
PCT/JP2017/003388 WO2017159081A1 (ja) | 2016-03-15 | 2017-01-31 | 半導体モジュール |
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WO2021029220A1 (ja) * | 2019-08-09 | 2021-02-18 | ローム株式会社 | パワーモジュール |
WO2023127317A1 (ja) * | 2021-12-27 | 2023-07-06 | 富士電機株式会社 | 半導体モジュール |
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US9256560B2 (en) | 2009-07-29 | 2016-02-09 | Solarflare Communications, Inc. | Controller integration |
US10916531B2 (en) * | 2016-11-24 | 2021-02-09 | Sumitomo Electric Industries, Ltd. | Semiconductor module |
US10181447B2 (en) * | 2017-04-21 | 2019-01-15 | Invensas Corporation | 3D-interconnect |
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JPH0358465A (ja) * | 1989-07-26 | 1991-03-13 | Nec Corp | 樹脂封止型半導体装置 |
JP2007019292A (ja) * | 2005-07-08 | 2007-01-25 | Tdk Corp | 電子部品モジュール用積層基板および電子部品モジュール |
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WO2023127317A1 (ja) * | 2021-12-27 | 2023-07-06 | 富士電機株式会社 | 半導体モジュール |
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