JP2017157849A - Method of producing chip component and chip component - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a chip component and a chip component capable of improving miniaturization and productivity, dimensional accuracy of external dimensions, and external appearance.SOLUTION: The method of manufacturing a chip component includes the steps of: forming an element in each of a plurality of chip component regions set on the surface of a substrate; forming a groove having a predetermined depth from the surface of the substrate in a boundary region of the plurality of chip component regions; and grinding the back surface of the substrate until reaching the groove to divide the substrate into a plurality of chip components.SELECTED DRAWING: Figure 27G

Description

  The present invention relates to a chip part manufacturing method and a chip part.

In the chip resistor disclosed in the following Patent Document 1, elements such as a resistance film and a main electrode connected to both ends of the resistance film are formed on the surface of a chip-type insulating substrate.
When manufacturing this chip resistor, a material substrate having a plurality of elements formed on the surface is cut along a predetermined dividing line at the boundary of the elements by a dicing saw, and is divided for each insulating substrate. Then, when the electrode surface of each insulating substrate is plated, a chip resistor is completed.

Japanese Patent Laid-Open No. 2001-76912

  In the case of Patent Document 1, since the material substrate is cut with a dicing saw, the corner portion of each insulating substrate divided by the cutting is square, so that chipping (breaking or chipping) easily occurs at the corner portion. When chipping occurs, the chip resistor becomes defective in appearance, and thus the productivity of the chip resistor may be hindered. Further, in chip components such as chip resistors, it is desired not only to improve productivity and appearance but also to reduce size and improve dimensional accuracy.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a chip component manufacturing method and a chip component that can be miniaturized and improved in productivity, external dimension accuracy, and external appearance.

  A feature of the present invention is that a step of forming an element in each of a plurality of chip component regions set on the surface of the substrate and a groove having a predetermined depth from the surface of the substrate in a boundary region of the plurality of chip component regions And a step of grinding the back surface of the substrate until reaching the groove to divide the substrate into a plurality of chip components. According to this method, since a plurality of chip component regions formed on the substrate can be divided into individual chip components all at once, the productivity of the chip components can be improved.

Moreover, you may include the process of forming a protective film in the side wall of the said groove | channel.
Further, the step of forming the groove may include a step of forming a resist pattern corresponding to the boundary region and a step of forming the groove by etching using the resist pattern as a mask. According to this method, since the groove can be formed with high accuracy by etching, it is possible to improve the external dimension accuracy of each chip component divided by the groove. In addition, since the groove interval can be reduced according to the resist pattern, the chip component formed between adjacent grooves can be miniaturized. Further, in the case of etching, the chip component is not cut out, so that the occurrence of chipping at the corner portion of the chip component can be reduced, and the appearance of the chip component can be improved.

The etching may be plasma etching. According to this method, since the grooves can be formed with higher accuracy and the intervals between the grooves can be further miniaturized, the external dimension accuracy and appearance of the chip component can be further improved, and further miniaturization can be achieved.
The step of forming the element may include a step of forming a resistor, and the chip component may be a chip resistor. According to this method, it is possible to provide a chip resistor that can be miniaturized and improved in productivity, external dimension accuracy, and external appearance.

  The step of forming the resistor includes a step of forming a resistor film on the surface of the substrate, a step of forming a wiring film so as to be in contact with the resistor film, the resistor film, and the wiring film Forming a plurality of resistors by patterning, and forming an external connection electrode on the substrate for externally connecting the element; and forming the plurality of resistors on the external connection electrode Forming a plurality of fuses to be detachably connected on the substrate. According to this method, the chip resistor can easily and quickly cope with a plurality of types of resistance values by selecting and cutting one or a plurality of fuses. In other words, chip resistors having various resistance values can be realized with a common design by combining a plurality of resistors having different resistance values.

The step of forming the element may include a step of forming a capacitor element, and the chip component may be a chip capacitor. According to this method, it is possible to provide a chip capacitor that can be miniaturized and improved in productivity, external dimension accuracy, and external appearance.
The step of forming the capacitor element includes a step of forming a capacitive film on the surface of the substrate, a step of forming an electrode film in contact with the capacitive film, and dividing the electrode film into a plurality of electrode film portions. A step of forming a plurality of capacitor elements corresponding to the plurality of electrode film portions; a step of forming external connection electrodes for externally connecting the elements; and the plurality of capacitor elements And forming a plurality of fuses on the substrate so as to be detachably connected to the external connection electrodes. According to this method, the chip capacitor can easily and quickly cope with a plurality of types of capacitance values by selecting and cutting one or a plurality of fuses. In other words, chip capacitors having various capacitance values can be realized by a common design by combining a plurality of capacitor elements having different capacitance values.

Further, the planar shape of each chip component region may be a rectangle having two orthogonal sides of 0.4 mm or less and 0.2 mm or less, respectively. According to this method, an extremely small chip component can be provided.
A band-shaped boundary region having a width of 1 μm to 60 μm may be provided between the plurality of chip component regions. According to this method, an extremely small chip component can be provided.

The present invention is characterized in that a substrate, a plurality of element elements formed on the surface of the substrate, an external connection electrode formed on the surface of the substrate, and a plurality of elements formed on the surface of the substrate A chip component including a plurality of fuses each detachably connecting an element to the external connection electrode, wherein the side surface of the substrate is a rough surface of an irregular pattern.
With regard to this configuration, when the substrate is divided into a plurality of chip parts in the groove by forming a groove having a predetermined depth from the surface of the substrate by etching using a resist pattern, each chip part has a A side surface becomes a rough surface of an irregular pattern. When etching is used in this way, since a plurality of element elements formed on the substrate can be divided into individual chip parts at the same time, the productivity of the chip parts can be improved. In addition, since the grooves can be formed with high accuracy by etching, it is possible to improve the external dimension accuracy of each chip component divided by the grooves. In addition, since the groove interval can be reduced according to the resist pattern, the chip component formed between adjacent grooves can be miniaturized. Further, in the case of etching, the chip component is not cut out, so that the occurrence of chipping at the corner portion of the chip component can be reduced, and the appearance of the chip component can be improved.

Moreover, you may include the protective film formed in the said side surface.
The element element is a resistor including a resistor film formed on a surface of the substrate and a wiring film laminated in contact with the resistor film, and the chip component is a chip resistor. May be. According to this configuration, it is possible to provide a chip resistor that can be miniaturized and improved in productivity, outer dimension accuracy, and appearance. In the chip resistor, it is possible to easily and quickly cope with a plurality of types of resistance values by selecting and cutting one or a plurality of fuses. In other words, chip resistors having various resistance values can be realized with a common design by combining a plurality of resistors having different resistance values.

  The element element may be a capacitor element including a capacitive film formed on the surface of the substrate and an electrode film formed in contact with the capacitive film, and the chip component may be a chip capacitor. . According to this configuration, it is possible to provide a chip capacitor that can be reduced in size and improved in productivity, outer dimension accuracy, and appearance. In the chip capacitor, by selecting and cutting one or a plurality of fuses, it is possible to easily and quickly cope with a plurality of types of capacitance values. In other words, chip capacitors having various capacitance values can be realized by a common design by combining a plurality of capacitor elements having different capacitance values.

  Further, the chip component may be a chip inductor or a chip diode.

FIG. 1A is a schematic perspective view for explaining a configuration of a chip resistor according to an embodiment of the present invention, and FIG. 1B is a diagram illustrating the chip resistor mounted on a circuit board. It is a typical side view which shows a state. FIG. 2 is a plan view of the chip resistor, showing the arrangement relationship of the first connection electrode, the second connection electrode and the element, and the configuration of the element in plan view. FIG. 3A is a plan view illustrating a part of the element shown in FIG. 2 in an enlarged manner. FIG. 3B is a longitudinal sectional view in the length direction along BB of FIG. 3A drawn to explain the configuration of the resistor in the element. FIG. 3C is a longitudinal sectional view in the width direction along CC of FIG. 3A drawn to explain the configuration of the resistor in the element. FIG. 4 is a diagram showing the electrical characteristics of the resistor film line and the wiring film with circuit symbols and electrical circuit diagrams. 5A is a partially enlarged plan view of a region including a fuse film drawn by enlarging a part of the plan view of the chip resistor shown in FIG. 2, and FIG. 5B is a plan view of FIG. 5A. It is a figure which shows the cross-sectional structure in alignment with BB. FIG. 6 is an electric circuit diagram of the element according to the embodiment of the present invention. FIG. 7 is an electric circuit diagram of an element according to another embodiment of the present invention. FIG. 8 is an electric circuit diagram of an element according to still another embodiment of the present invention. FIG. 9 is a schematic cross-sectional view of a chip resistor. FIG. 10A is a schematic cross-sectional view showing a method of manufacturing the chip resistor shown in FIG. FIG. 10B is a schematic sectional view showing a step subsequent to FIG. 10A. FIG. 10C is an illustrative sectional view showing a step subsequent to FIG. 10B. FIG. 10D is an illustrative sectional view showing a step subsequent to FIG. 10C. FIG. 10E is an illustrative sectional view showing a step subsequent to FIG. 10D. FIG. 10F is an illustrative sectional view showing a step subsequent to FIG. 10E. FIG. 10G is an illustrative sectional view showing a step subsequent to FIG. 10F. FIG. 11 is a schematic plan view of a part of a resist pattern used for forming a groove in the process of FIG. 10B. 12A is a schematic plan view of the substrate after the grooves are formed in the step of FIG. 10B, and FIG. 12B is a partially enlarged view of FIG. FIG. 13A is a schematic cross-sectional view during the manufacture of the chip resistor according to one embodiment of the present invention. FIG. 13B is a schematic cross-sectional view during the manufacture of the chip resistor according to the comparative example. 14 (a) and 14 (b) are schematic perspective views showing a state in which a polyimide sheet is attached to a substrate in the step of FIG. 10D. FIG. 15 is a schematic perspective view showing a semi-finished chip resistor immediately after the process of FIG. 10G. FIG. 16 is a first schematic diagram showing a step subsequent to FIG. 10G. FIG. 17 is a second schematic diagram showing a step subsequent to FIG. 10G. FIG. 18A is a schematic perspective view for explaining the configuration of the chip resistor according to the embodiment of the first reference example, and FIG. 18B is a diagram illustrating the chip resistor mounted on the mounting substrate. It is a typical side view which shows the state made. FIG. 19 is a plan view of the chip resistor, showing the arrangement relationship of the first connection electrode, the second connection electrode and the element, and the configuration of the element in plan view. 20A is a plan view illustrating a part of the element shown in FIG. 19 in an enlarged manner. FIG. 20B is a longitudinal sectional view in the length direction along BB of FIG. 20A drawn for explaining the configuration of the resistor in the element. FIG. 20C is a longitudinal sectional view in the width direction along CC of FIG. 20A drawn for explaining the configuration of the resistor in the element. FIG. 21 is a diagram showing the electrical characteristics of the resistor film line and the wiring film with circuit symbols and electrical circuit diagrams. 22A is a partially enlarged plan view of a region including a fuse drawn by enlarging a part of the plan view of the chip resistor shown in FIG. 19, and FIG. 22B is a plan view of FIG. It is a figure which shows the cross-sectional structure which follows BB. FIG. 23 is an electric circuit diagram of an element according to the embodiment of the first reference example. FIG. 24 is an electric circuit diagram of an element according to another embodiment of the first reference example. FIG. 25 is an electric circuit diagram of an element according to still another embodiment of the first reference example. FIG. 26 is a schematic cross-sectional view of a chip resistor. FIG. 27A is a schematic cross-sectional view showing a manufacturing method of the chip resistor shown in FIG. FIG. 27B is a schematic sectional view showing a step subsequent to FIG. 27A. FIG. 27C is an illustrative sectional view showing a step subsequent to FIG. 27B. FIG. 27D is an illustrative sectional view showing a step subsequent to FIG. 27C. FIG. 27E is an illustrative sectional view showing a step subsequent to FIG. 27D. FIG. 27F is a schematic sectional view showing a step subsequent to FIG. 27E. FIG. 27G is an illustrative sectional view showing a step subsequent to FIG. 27F. FIG. 28 is a schematic plan view of a part of a resist pattern used for forming a groove in the step of FIG. 27B. FIG. 29A is a schematic cross-sectional view showing the chip resistor after the step of FIG. 27G. FIG. 29B is a schematic sectional view showing a step subsequent to FIG. 29A. FIG. 29C is an illustrative sectional view showing a step subsequent to FIG. 29B. FIG. 29D is an illustrative sectional view showing a step subsequent to FIG. 29C. FIG. 30A is a schematic cross-sectional view showing the chip resistor after the step of FIG. 27G. FIG. 30B is a schematic sectional view showing a step subsequent to FIG. 30A. FIG. 30C is an illustrative sectional view showing a step subsequent to FIG. 30B. FIG. 31A is a schematic longitudinal sectional view when the chip resistor is cut along the longitudinal direction, and FIG. 31B is a view when the chip resistor is cut along the short direction. FIG. 31C is a schematic longitudinal sectional view, and FIG. 31C is a plan view of the chip resistor. FIG. 32 shows a chip resistor according to a first modification of the first reference example, and FIG. 32A is a schematic longitudinal sectional view when the chip resistor is cut along the longitudinal direction. FIG. 32B is a schematic longitudinal sectional view when the chip resistor is cut along the short direction. FIG. 33 shows a chip resistor according to a second modification of the first reference example, and FIG. 33 (a) is a schematic longitudinal sectional view when the chip resistor is cut along the longitudinal direction. FIG. 33B is a schematic longitudinal sectional view when the chip resistor is cut along the short direction, and FIG. 33C is a plan view of the chip resistor. FIG. 34 shows a chip resistor according to a third modification of the first reference example, and FIG. 34 (a) is a schematic longitudinal sectional view when the chip resistor is cut along the longitudinal direction. FIG. 34B is a schematic longitudinal sectional view when the chip resistor is cut along the short direction. FIG. 35 shows a chip resistor according to a fourth modification of the first reference example, and FIG. 35 (a) is a schematic longitudinal sectional view when the chip resistor is cut along the longitudinal direction. FIG. 35B is a schematic longitudinal sectional view when the chip resistor is cut along the short direction. FIG. 36 shows a chip resistor according to a fifth modification of the first reference example, and FIG. 36A is a schematic longitudinal sectional view when the chip resistor is cut along the longitudinal direction. FIG. 36B is a schematic longitudinal sectional view when the chip resistor is cut along the short direction. FIG. 37 is a plan view of a chip capacitor according to another embodiment of the first reference example. 38 is a cross-sectional view taken along section line XXXVIII-XXXVIII in FIG. FIG. 39 is an exploded perspective view showing a part of the structure of the chip capacitor separately. FIG. 40 is a circuit diagram showing an internal electrical configuration of the chip capacitor. FIG. 41A is a schematic perspective view for explaining the configuration of the chip resistor according to the embodiment of the second reference example, and FIG. 41B is a diagram illustrating the chip resistor mounted on the mounting substrate. It is a typical side view which shows the state made. FIG. 42 is a plan view of the chip resistor, showing the arrangement relationship of the first connection electrode, the second connection electrode and the element, and the configuration of the element in plan view. FIG. 43A is an enlarged plan view of a part of the element shown in FIG. FIG. 43B is a longitudinal sectional view in the length direction along BB of FIG. 43A drawn to explain the configuration of the resistor in the element. FIG. 43C is a longitudinal sectional view in the width direction along CC of FIG. 43A drawn to explain the configuration of the resistor in the element. FIG. 44 is a diagram showing the electrical characteristics of the resistor film line and the wiring film with circuit symbols and electrical circuit diagrams. 45 (a) is a partially enlarged plan view of a region including a fuse drawn by enlarging a part of the plan view of the chip resistor shown in FIG. 42, and FIG. 45 (b) is a plan view of FIG. It is a figure which shows the cross-sectional structure which follows BB. FIG. 46 is an electric circuit diagram of an element according to the embodiment of the second reference example. FIG. 47 is an electric circuit diagram of an element according to another embodiment of the second reference example. FIG. 48 is an electric circuit diagram of an element according to still another embodiment of the second reference example. FIG. 49 is a schematic cross-sectional view of a chip resistor. FIG. 50A is a schematic cross-sectional view showing a method for manufacturing the chip resistor shown in FIG. 49. FIG. 50B is a schematic sectional view showing a step subsequent to FIG. 50A. FIG. 50C is an illustrative sectional view showing a step subsequent to FIG. 50B. FIG. 50D is an illustrative sectional view showing a step subsequent to FIG. 50C. FIG. 50E is an illustrative sectional view showing a step subsequent to FIG. 50D. FIG. 50F is a schematic sectional view showing a step subsequent to FIG. 50E. FIG. 50G is an illustrative sectional view showing a step subsequent to FIG. 50F. FIG. 51 is a schematic plan view of a part of a resist pattern used for forming a groove in the step of FIG. 50B. FIG. 52A is a schematic cross-sectional view showing the chip resistor after the step of FIG. 50G. FIG. 52B is a schematic sectional view showing a step subsequent to FIG. 52A. FIG. 52C is an illustrative sectional view showing a step subsequent to FIG. 52B. FIG. 52D is an illustrative sectional view showing a step subsequent to FIG. 52C. FIG. 53A is a schematic cross-sectional view showing the chip resistor after the step of FIG. 50G. FIG. 53B is an illustrative sectional view showing a step subsequent to FIG. 53A. FIG. 53C is an illustrative sectional view showing a step subsequent to FIG. 53B. 54A is a schematic longitudinal sectional view when the chip resistor is cut along the longitudinal direction, and FIG. 54B is a view when the chip resistor is cut along the short direction. FIG. 54C is a schematic longitudinal sectional view, and FIG. 54C is a plan view of the chip resistor. FIG. 55 shows a chip resistor according to a first modification of the second reference example, and FIG. 55 (a) is a schematic longitudinal sectional view when the chip resistor is cut along the longitudinal direction. FIG. 55B is a schematic longitudinal sectional view when the chip resistor is cut along the short direction. FIG. 56 shows a chip resistor according to a second modification of the second reference example, and FIG. 56 (a) is a schematic longitudinal sectional view when the chip resistor is cut along the longitudinal direction. FIG. 56B is a schematic longitudinal sectional view when the chip resistor is cut along the short direction, and FIG. 56C is a plan view of the chip resistor. FIG. 57 shows a chip resistor according to a third modification of the second reference example, and FIG. 57A is a schematic longitudinal sectional view when the chip resistor is cut along the longitudinal direction. FIG. 57B is a schematic longitudinal sectional view when the chip resistor is cut along the short direction. FIG. 58 shows a chip resistor according to a fourth modification of the second reference example, and FIG. 58 (a) is a schematic longitudinal sectional view when the chip resistor is cut along the longitudinal direction. FIG. 58B is a schematic longitudinal sectional view when the chip resistor is cut along the short direction. FIG. 59 shows a chip resistor according to a fifth modification of the second reference example, and FIG. 59 (a) is a schematic longitudinal sectional view when the chip resistor is cut along the longitudinal direction. FIG. 59B is a schematic longitudinal sectional view when the chip resistor is cut along the short direction. FIG. 60 is a plan view of a chip capacitor according to another embodiment of the second reference example. 61 is a cross-sectional view taken along section line LXI-LXI in FIG. FIG. 62 is an exploded perspective view showing a part of the structure of the chip capacitor separately. FIG. 63 is a circuit diagram showing an internal electrical configuration of the chip capacitor. FIG. 64A is a schematic perspective view for explaining the configuration of the chip resistor according to the embodiment of the third reference example, and FIG. 64B is a diagram illustrating the chip resistor mounted on the mounting substrate. It is a typical side view which shows the state made. FIG. 65 is a plan view of the chip resistor, showing the arrangement relationship between the first connection electrode, the second connection electrode and the element, and the configuration of the element in plan view. 66A is a plan view illustrating a part of the element shown in FIG. 65 in an enlarged manner. 66B is a longitudinal cross-sectional view in the length direction along BB of FIG. 66A drawn for explaining the configuration of the resistor in the element. 66C is a longitudinal cross-sectional view in the width direction along CC of FIG. 66A drawn for explaining the configuration of the resistor in the element. FIG. 67 is a diagram showing the electrical characteristics of the resistor film line and the wiring film with circuit symbols and electrical circuit diagrams. FIG. 68A is a partially enlarged plan view of a region including a fuse drawn by enlarging a part of the plan view of the chip resistor shown in FIG. 65, and FIG. 68B is a plan view of FIG. It is a figure which shows the cross-sectional structure which follows BB. FIG. 69 is an electric circuit diagram of an element according to the embodiment of the third reference example. FIG. 70 is an electric circuit diagram of an element according to another embodiment of the third reference example. FIG. 71 is an electric circuit diagram of an element according to still another embodiment of the third reference example. FIG. 72 is a schematic cross-sectional view of a chip resistor. FIG. 73A is a schematic cross-sectional view showing a method for manufacturing the chip resistor shown in FIG. 72. FIG. 73B is a schematic sectional view showing a step subsequent to FIG. 73A. FIG. 73C is an illustrative sectional view showing a step subsequent to FIG. 73B. FIG. 73D is an illustrative sectional view showing a step subsequent to FIG. 73C. FIG. 73E is an illustrative sectional view showing a step subsequent to FIG. 73D. FIG. 73F is a schematic sectional view showing a step subsequent to FIG. 73E. FIG. 73G is an illustrative sectional view showing a step subsequent to FIG. 73F. FIG. 74 is a schematic plan view of a part of a resist pattern used for forming a groove in the step of FIG. 73B. 75A is a schematic cross-sectional view showing the chip resistor after the step of FIG. 73G. FIG. 75B is a schematic sectional view showing a step subsequent to FIG. 75A. FIG. 75C is an illustrative sectional view showing a step subsequent to FIG. 75B. FIG. 75D is an illustrative sectional view showing a step subsequent to FIG. 75C. FIG. 76A is a schematic cross-sectional view showing the chip resistor after the step of FIG. 73G. FIG. 76B is an illustrative sectional view showing a step subsequent to FIG. 76A. FIG. 76C is an illustrative sectional view showing a step subsequent to FIG. 76B. FIG. 77A is a schematic longitudinal sectional view when the chip resistor is cut along the longitudinal direction, and FIG. 77B is a view when the chip resistor is cut along the short direction. FIG. 77C is a schematic longitudinal sectional view, and FIG. 77C is a plan view of the chip resistor. FIG. 78 shows a chip resistor according to a first modification of the third reference example, and FIG. 78 (a) is a schematic longitudinal sectional view when the chip resistor is cut along the longitudinal direction. FIG. 78B is a schematic longitudinal sectional view when the chip resistor is cut along the short direction. FIG. 79 shows a chip resistor according to a second modification of the third reference example, and FIG. 79A is a schematic longitudinal sectional view when the chip resistor is cut along the longitudinal direction. FIG. 79B is a schematic longitudinal sectional view of the chip resistor taken along the short direction, and FIG. 79C is a plan view of the chip resistor. FIG. 80 shows a chip resistor according to a third modification of the third reference example, and FIG. 80A is a schematic longitudinal sectional view when the chip resistor is cut along the longitudinal direction. FIG. 80B is a schematic longitudinal sectional view when the chip resistor is cut along the short direction. FIG. 81 shows a chip resistor according to a fourth modification of the third reference example, and FIG. 81 (a) is a schematic longitudinal sectional view when the chip resistor is cut along the longitudinal direction. FIG. 81B is a schematic longitudinal sectional view when the chip resistor is cut along the short direction. FIG. 82 shows a chip resistor according to a fifth modification of the third reference example, and FIG. 82 (a) is a schematic longitudinal sectional view when the chip resistor is cut along the longitudinal direction. FIG. 82B is a schematic longitudinal sectional view when the chip resistor is cut along the short direction. FIG. 83 is a plan view of a chip capacitor according to another embodiment of the third reference example. 84 is a cross-sectional view taken along section line LXXXIV-LXXXIV in FIG. 83. FIG. 85 is an exploded perspective view showing a part of the structure of the chip capacitor separately. FIG. 86 is a circuit diagram showing an internal electrical configuration of the chip capacitor. FIG. 87A is a schematic perspective view for explaining the configuration of the chip resistor according to the embodiment of the fourth reference example, and FIG. 87B is a diagram illustrating the chip resistor mounted on the mounting substrate. It is typical sectional drawing which shows the state made. FIG. 88 is a plan view of the chip resistor, showing the arrangement relationship of the first connection electrode, the second connection electrode and the element, and the configuration of the element in plan view. 89A is a plan view illustrating a part of the element shown in FIG. 88 in an enlarged manner. FIG. 89B is a longitudinal sectional view in the length direction taken along the line BB of FIG. 89A drawn to explain the configuration of the resistor in the element. FIG. 89C is a longitudinal sectional view in the width direction along CC of FIG. 89A drawn to explain the configuration of the resistor in the element. FIG. 90 is a diagram showing the electrical characteristics of the resistor film line and the wiring film with circuit symbols and electrical circuit diagrams. FIG. 91A is a partially enlarged plan view of a region including a fuse drawn by enlarging a part of the plan view of the chip resistor shown in FIG. 88, and FIG. 91B is a plan view of FIG. It is a figure which shows the cross-sectional structure which follows BB. FIG. 92 is an electric circuit diagram of an element according to the embodiment of the fourth reference example. FIG. 93 is an electric circuit diagram of an element according to another embodiment of the fourth reference example. FIG. 94 is an electric circuit diagram of an element according to still another embodiment of the fourth reference example. FIG. 95 is a schematic cross-sectional view of a chip resistor. FIG. 96A is a schematic cross-sectional view showing a method for manufacturing the chip resistor shown in FIG. 95. FIG. 96B is a schematic sectional view showing a step subsequent to FIG. 96A. FIG. 96C is an illustrative sectional view showing a step subsequent to FIG. 96B. FIG. 96D is an illustrative sectional view showing a step subsequent to FIG. 96C. FIG. 96E is an illustrative sectional view showing a step subsequent to FIG. 96D. FIG. 96F is a schematic sectional view showing a step subsequent to FIG. 96E. FIG. 96G is an illustrative sectional view showing a step subsequent to FIG. 96F. FIG. 96H is an illustrative sectional view showing a step subsequent to FIG. 96G. FIG. 97 is a schematic plan view of a part of the resist pattern used for forming the first groove in the step of FIG. 96B. FIG. 98 is a diagram for explaining a manufacturing process of the first connection electrode and the second connection electrode. FIG. 99 is a schematic diagram for explaining how the completed chip resistor is accommodated in the embossed carrier tape. FIG. 100 is a schematic cross-sectional view of a chip resistor according to a first modification example of the fourth reference example. FIG. 101 is a schematic cross-sectional view of a chip resistor according to a second modification of the fourth reference example. FIG. 102 is a schematic cross-sectional view of a chip resistor according to a third modification of the fourth reference example. FIG. 103 is a schematic cross-sectional view of a chip resistor according to a fourth modification of the fourth reference example. FIG. 104 is a schematic cross-sectional view of a chip resistor according to a fifth modification example of the fourth reference example. FIG. 105 is a plan view of a chip capacitor according to another embodiment of the fourth reference example. 106 is a cross-sectional view taken along section line CVI-CVI of FIG. FIG. 107 is an exploded perspective view showing a part of the structure of the chip capacitor separately. FIG. 108 is a circuit diagram showing an internal electrical configuration of the chip capacitor. FIG. 109 is a perspective view illustrating an appearance of a smartphone that is an example of an electronic device in which the chip component of the fourth reference example is used. FIG. 110 is a schematic plan view showing a configuration of an electronic circuit assembly housed in the housing of the smartphone. FIG. 111A is a schematic perspective view for explaining the configuration of the chip resistor according to the embodiment of the fifth reference example, and FIG. 111B is a diagram illustrating the chip resistor mounted on the mounting substrate. It is typical sectional drawing which shows the state made. FIG. 112 is a plan view of the chip resistor, showing the arrangement relationship of the first connection electrode, the second connection electrode and the element, and the configuration of the element in plan view. FIG. 113A is a plan view illustrating a part of the element shown in FIG. 112 in an enlarged manner. FIG. 113B is a longitudinal sectional view in the length direction along BB of FIG. 113A drawn to explain the configuration of the resistor in the element. FIG. 113C is a longitudinal sectional view in the width direction along CC of FIG. 113A drawn to explain the structure of the resistor in the element. FIG. 114 is a diagram showing the electrical characteristics of the resistor film line and the wiring film with circuit symbols and electrical circuit diagrams. FIG. 115 (a) is a partially enlarged plan view of a region including a fuse drawn by enlarging a part of the plan view of the chip resistor shown in FIG. 112, and FIG. It is a figure which shows the cross-sectional structure which follows BB. FIG. 116 is an electric circuit diagram of an element according to the embodiment of the fifth reference example. FIG. 117 is an electric circuit diagram of an element according to another embodiment of the fifth reference example. FIG. 118 is an electric circuit diagram of an element according to still another embodiment of the fifth reference example. FIG. 119 is a schematic cross-sectional view of the chip resistor. 120A is a schematic sectional view showing a method for manufacturing the chip resistor shown in FIG. 119. FIG. FIG. 120B is a schematic sectional view showing a step subsequent to FIG. 120A. FIG. 120C is an illustrative sectional view showing a step subsequent to FIG. 120B. FIG. 120D is an illustrative sectional view showing a step subsequent to FIG. 120C. FIG. 120E is a schematic sectional view showing a step subsequent to FIG. 120D. FIG. 120F is a schematic sectional view showing a step subsequent to FIG. 120E. FIG. 120G is a schematic sectional view showing a step subsequent to FIG. 120F. FIG. 120H is an illustrative sectional view showing a step subsequent to FIG. 120G. FIG. 121 is a schematic plan view of a part of a resist pattern used for forming the first groove in the step of FIG. 120B. FIG. 122 is a diagram for explaining a manufacturing process of the first connection electrode and the second connection electrode. FIG. 123 is a schematic diagram for explaining how the completed chip resistor is accommodated in the embossed carrier tape. FIG. 124 is a schematic cross-sectional view of a chip resistor according to a first modification of the fifth reference example. FIG. 125 is a schematic cross-sectional view of a chip resistor according to a second modification example of the fifth reference example. FIG. 126 is a schematic cross-sectional view of a chip resistor according to a third modification of the fifth reference example. FIG. 127 is a schematic cross-sectional view of a chip resistor according to a fourth modification example of the fifth reference example. FIG. 128 is a schematic cross-sectional view of a chip resistor according to a fifth modification example of the fifth reference example. FIG. 129 is a plan view of a chip capacitor according to another embodiment of the fifth reference example. 130 is a cross-sectional view taken along section line CXXX-CXXX in FIG. 129. FIG. 131 is an exploded perspective view showing a part of the structure of the chip capacitor separately. FIG. 132 is a circuit diagram showing an internal electrical configuration of the chip capacitor. FIG. 133 is a perspective view illustrating an appearance of a smartphone that is an example of an electronic device in which the chip component of the fifth reference example is used. FIG. 134 is a schematic plan view showing the configuration of the electronic circuit assembly housed inside the housing of the smartphone.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1A is a schematic perspective view for explaining a configuration of a chip resistor according to an embodiment of the present invention, and FIG. 1B is a diagram illustrating the chip resistor mounted on a circuit board. It is a typical side view which shows a state.
The chip resistor 1 is a minute chip component and has a rectangular parallelepiped shape as shown in FIG. Regarding the dimensions of the chip resistor 1, the length L in the long side direction is about 0.3 mm, the width W in the short side direction is about 0.15 mm, and the thickness T is about 0.1 mm.

The chip resistor 1 is formed by forming a plurality of chip resistors 1 in a lattice shape on a substrate, forming grooves in the substrate, and then polishing the back surface (or dividing the substrate by the grooves) to obtain individual chips. It is obtained by separating the resistor 1.
The chip resistor 1 mainly includes a substrate 2, a first connection electrode 3 and a second connection electrode 4 that are external connection electrodes, and an element 5.

  The substrate 2 has a substantially rectangular parallelepiped chip shape. In the substrate 2, the upper surface in FIG. 1A is an element formation surface 2A. The element formation surface 2A is the surface of the substrate 2 and has a substantially rectangular shape. The surface opposite to the element formation surface 2A in the thickness direction of the substrate 2 is a back surface 2B. The element formation surface 2A and the back surface 2B have substantially the same shape. In addition to the element formation surface 2A and the back surface 2B, the substrate 2 has a side surface 2C, a side surface 2D, a side surface 2E, and a side surface 2F that extend orthogonally to these surfaces and connect these surfaces.

  The side surface 2C extends between one end edge in the longitudinal direction of the element formation surface 2A and the back surface 2B (the left front edge in FIG. 1A), and the side surface 2D extends in the longitudinal direction of the element formation surface 2A and the back surface 2B. It is constructed between the other ends in the direction (the edge on the right back side in FIG. 1A). The side surface 2C and the side surface 2D are both end surfaces of the substrate 2 in the longitudinal direction. The side surface 2E is provided between one end edge in the short direction of the element formation surface 2A and the back surface 2B (the left edge on the left side in FIG. 1A), and the side surface 2F includes the element formation surface 2A and the back surface 2B. Between the other edges in the short direction (the edge on the right front side in FIG. 1A). The side surface 2E and the side surface 2F are both end surfaces of the substrate 2 in the lateral direction. Each of the side surface 2C and the side surface 2D intersects (strictly, orthogonally) with each of the side surface 2E and the side surface 2F.

  In the substrate 2, the entire element formation surface 2 </ b> A is covered with the insulating film 23. Therefore, strictly speaking, in FIG. 1A, the entire area of the element formation surface 2A is located on the inner side (back side) of the insulating film 23 and is not exposed to the outside. Further, the insulating film 23 on the element formation surface 2A is covered with a resin film 24. The resin film 24 protrudes from the element formation surface 2A to the end portion on the element formation surface 2A side (the upper end portion in FIG. 1A) of each of the side surface 2C, the side surface 2D, the side surface 2E, and the side surface 2F. The insulating film 23 and the resin film 24 will be described in detail later.

  In the rectangular parallelepiped substrate 2, a crossing portion 11 (a corner portion forming a boundary between the adjacent ones) 11 where the adjacent ones of the back surface 2B, the side surface 2C, the side surface 2D, the side surface 2E, and the side surface 2F intersect is chamfered. It is shaped into a round shape and rounded. Here, in each crossing part 11, it is preferable that a round-shaped curvature radius is 20 micrometers or less.

  Thus, in the outline of the board | substrate 2 in each of planar view (bottom view) and side view, all the bent parts (intersection part 11) are round shape. Therefore, chipping can be prevented from occurring at each round-shaped crossing portion 11 (corner portion) when the chip resistor 1 holding the crossing portion 11 is handled or transported. Thereby, in the manufacture of the chip resistor 1, it is possible to improve the yield (improvement of productivity).

  The first connection electrode 3 and the second connection electrode 4 are formed on the element formation surface 2 </ b> A of the substrate 2 and are partially exposed from the resin film 24. Each of the first connection electrode 3 and the second connection electrode 4 is configured, for example, by stacking Ni (nickel), Pd (palladium), and Au (gold) on the element formation surface 2A in this order. The first connection electrode 3 and the second connection electrode 4 are arranged at intervals in the longitudinal direction of the element formation surface 2A, and are long in the short direction of the element formation surface 2A. In FIG. 1A, on the element formation surface 2A, the first connection electrode 3 is provided near the side surface 2C, and the second connection electrode 4 is provided near the side surface 2D.

  The element 5 is a circuit element, and is formed in a region between the first connection electrode 3 and the second connection electrode 4 on the element formation surface 2A of the substrate 2, and from above by the insulating film 23 and the resin film 24. It is covered. The element 5 of this embodiment is a circuit network in which a plurality of thin film resistors (thin film resistors) R made of TiN (titanium nitride) or TiON (titanium oxynitride) are arranged in a matrix on the element formation surface 2A. A configured resistor 56. The element 5 (resistor R) is electrically connected to a wiring film 22 described later, and is electrically connected to the first connection electrode 3 and the second connection electrode 4 via the wiring film 22. Thereby, in the chip resistor 1, a resistance circuit including the element 5 is formed between the first connection electrode 3 and the second connection electrode 4.

  As shown in FIG. 1B, the first connection electrode 3 and the second connection electrode 4 are opposed to the circuit board 9, and electrical and mechanical to the circuit (not shown) of the circuit board 9 by the solder 13. Thus, the chip resistor 1 can be mounted on the circuit board 9 (flip chip connection). The first connection electrode 3 and the second connection electrode 4 that function as external connection electrodes are formed of gold (Au) or are plated with gold in order to improve solder wettability and reliability. It is desirable.

FIG. 2 is a plan view of the chip resistor, showing the arrangement relationship of the first connection electrode, the second connection electrode and the element, and the configuration of the element in plan view.
Referring to FIG. 2, as an example, element 5 that is a resistor network includes eight resistors R arranged in the row direction (longitudinal direction of substrate 2) and the column direction (of substrate 2). It has a total of 352 resistors R composed of 44 resistors R arranged along the width direction. Each resistor R has an equal resistance value. That is, the group of resistors R (element 5, resistor 56) is formed of a plurality of resistors R having the same resistance value.

  A plurality of types of resistance unit bodies (unit resistances) are formed by grouping and electrically connecting a large number of these resistor bodies R every predetermined number of 1 to 64 pieces. The formed plural types of resistance unit bodies are connected in a predetermined manner via the connecting conductor film C. Further, a plurality of fuse films (fuses) that can be blown on the element formation surface 2A of the substrate 2 in order to electrically incorporate the resistance unit body into the element 5 or to electrically separate it from the element 5. ) F is provided. The plurality of fuse films F and connection conductor films C are arranged along the inner side of the second connection electrode 3 so that the arrangement region is linear. More specifically, a plurality of fuse films F and connecting conductor films C are arranged in a straight line.

FIG. 3A is a plan view illustrating a part of the element shown in FIG. 2 in an enlarged manner. FIG. 3B is a longitudinal sectional view in the length direction along BB of FIG. 3A drawn to explain the configuration of the resistor in the element. FIG. 3C is a longitudinal sectional view in the width direction along CC of FIG. 3A drawn to explain the configuration of the resistor in the element.
The configuration of the resistor R will be described with reference to FIGS. 3A, 3B, and 3C.

The chip resistor 1 further includes an insulating layer 20 and a resistor film 21 in addition to the wiring film 22, the insulating film 23, and the resin film 24 described above (see FIGS. 3B and 3C). The insulating layer 20, the resistor film 21, the wiring film 22, the insulating film 23, and the resin film 24 are formed on the substrate 2 (element formation surface 2A).
The insulating layer 20 is made of SiO ₂ (silicon oxide). The insulating layer 20 covers the entire area of the element formation surface 2A of the substrate 2. The insulating layer 20 has a thickness of about 10,000 mm. The insulating layer 20 and the insulating film 23 are different from each other.

  The resistor film 21 constitutes the resistor R. The resistor film 21 is made of TiN or TiON, and is laminated on the surface of the insulating layer 20. The thickness of the resistor film 21 is about 2000 mm. The resistor film 21 forms a plurality of lines (hereinafter referred to as “resistor film line 21 </ b> A”) extending in a line between the first connection electrode 3 and the second connection electrode 4. 21A may be cut at a predetermined position in the line direction (see FIG. 3A).

A wiring film 22 is laminated on the resistor film line 21A. The wiring film 22 is made of Al (aluminum) or an alloy of aluminum and Cu (copper) (AlCu alloy). The thickness of the wiring film 22 is about 8000 mm. The wiring film 22 is laminated on the resistor film line 21A with a constant interval R in the line direction.
FIG. 4 shows the electrical characteristics of the resistor film line 21A and the wiring film 22 of this configuration as circuit symbols. That is, as shown in FIG. 4A, each of the resistor film lines 21A in the region of the predetermined interval R forms one resistor R having a certain resistance value r.

In the region where the wiring film 22 is laminated, the resistor film lines 21 </ b> A are short-circuited by the wiring film 22 by electrically connecting the resistors R adjacent to each other. Therefore, a resistance circuit is formed which is formed by connecting in series the resistor R of the resistor r shown in FIG.
Further, since the adjacent resistor film lines 21A are connected to each other by the resistor film 21 and the wiring film 22, the resistor network of the element 5 shown in FIG. 3A is shown in FIG. A resistor circuit (consisting of R unit resistors) is formed. As described above, the resistor film 21 and the wiring film 22 constitute the element 5.

Here, based on the characteristic that the same-shaped and large-sized resistor films 21 formed on the substrate 2 have substantially the same value, a large number of resistors R arranged in a matrix on the substrate 2 have the same resistance. Has a value.
Further, the wiring film 22 laminated on the resistor film line 21A forms a resistor R and also serves as a connecting wiring film for connecting a plurality of resistors R to form a resistance unit body. Plays.

5A is a partially enlarged plan view of a region including a fuse film drawn by enlarging a part of the plan view of the chip resistor shown in FIG. 2, and FIG. 5B is a plan view of FIG. 5A. It is a figure which shows the cross-sectional structure in alignment with BB.
As shown in FIGS. 5A and 5B, the above-described fuse film F and connecting conductor film C are also formed by the wiring film 22 laminated on the resistor film 21 forming the resistor R. . That is, the fuse film F and the connecting conductor film C are formed of Al or AlCu alloy, which is the same metal material as the wiring film 22, on the same layer as the wiring film 22 stacked on the resistor film line 21A forming the resistor R. Is formed.

  That is, in the same layer laminated on the resistor film 21, the wiring film for forming the resistor R, the fuse film F, the connecting conductor film C, and the element 5 are connected to the first connection electrode 3. A wiring film for connecting to the second connection electrode 4 is formed as the wiring film 22 using the same metal material (Al or AlCu alloy). Note that the fuse film F is different from (differentiated from) the wiring film 22 because the fuse film F is formed so as to be easily cut and other circuit elements around the fuse film F. This is because they are arranged so that they do not exist.

  Here, in the wiring film 22, a region where the fuse film F is disposed is referred to as a trimming target region X (see FIGS. 2 and 5A). The trimming target region X is a linear region along the inner side of the second connection electrode 3, and not only the fuse film F but also the connecting conductor film C is disposed in the trimming target region X. Further, a resistor film 21 is formed below the wiring film 22 in the trimming target region X (see FIG. 5B). The fuse film F is a wiring having a larger inter-wiring distance (separated from the surroundings) than the portion other than the trimming target region X in the wiring film 22.

The fuse film F is not only a part of the wiring film 22 but also a group (fuse element) of a part of the resistor R (resistor film 21) and a part of the wiring film 22 on the resistor film 21. May point.
The fuse film F has been described only in the case where the same layer as the connecting conductor film C is used. However, the connecting conductor film C is formed by stacking another conductor film on the conductor film C. The resistance value may be lowered. Even in this case, if the conductor film is not laminated on the fuse film F, the fusing property of the fuse film F does not deteriorate.

FIG. 6 is an electric circuit diagram of the element according to the embodiment of the present invention.
Referring to FIG. 6, the element 5 includes a reference resistance unit R8, a resistance unit R64, two resistance units R32, a resistance unit R16, a resistance unit R8, a resistance unit R4, a resistance unit R2, The resistance unit body R1, the resistance unit body R / 2, the resistance unit body R / 4, the resistance unit body R / 8, the resistance unit body R / 16, and the resistance unit body R / 32 are arranged in this order from the first connection electrode 3. It is configured by connecting in series. Each of the reference resistance unit R8 and the resistance unit bodies R64 to R2 is configured by connecting in series the same number of resistors R as the last number (“64” in the case of R64). The resistance unit R1 is composed of one resistor R. Each of the resistance unit bodies R / 2 to R / 32 is configured by connecting in parallel the same number of resistors R as the last number of itself (“32” in the case of R / 32). The meaning of the number at the end of the resistance unit body is the same in FIGS. 7 and 8 described later.

One fuse film F is connected in parallel to each of the resistance unit bodies R64 to R / 32 other than the reference resistance unit body R8. The fuse films F are connected in series either directly or via a connecting conductor film C (see FIG. 5A).
As shown in FIG. 6, in the state where all the fuse films F are not blown, the element 5 is composed of eight resistors R provided in series between the first connection electrode 3 and the second connection electrode 4. A resistance circuit of the reference resistance unit R8 (resistance value 8r) is configured. For example, if the resistance value r of one resistor R is r = 8Ω, the chip resistor 1 in which the first connection electrode 3 and the second connection electrode 4 are connected by a resistance circuit of 8r = 64Ω is configured. Yes.

  Further, in a state where all the fuse films F are not blown, a plurality of types of resistance unit bodies other than the reference resistance unit body R8 are short-circuited. That is, 12 types of 13 resistance unit bodies R64 to R / 32 are connected in series to the reference resistance unit body R8, but each resistance unit body is short-circuited by the fuse film F connected in parallel. Therefore, when viewed electrically, each resistance unit is not incorporated in the element 5.

  In the chip resistor 1 according to this embodiment, the fuse film F is selectively blown by, for example, laser light according to a required resistance value. Thereby, the resistance unit body in which the fuse films F connected in parallel are melted is incorporated into the element 5. Therefore, the entire resistance value of the element 5 can be a resistance value in which resistance unit bodies corresponding to the blown fuse film F are connected in series and incorporated.

  In particular, in the plurality of types of resistance unit bodies, the resistor R having the same resistance value is one, two, four, eight, sixteen, thirty-two, etc. in series. The number of the series resistor unit bodies connected by increasing the number of resistors and the resistors R having the same resistance value are two, four, eight, sixteen, etc. in parallel. A plurality of types of parallel resistance units connected in increasing numbers are provided. Therefore, by selectively fusing the fuse film F (including the above-described fuse element), the resistance value of the entire element 5 (resistor 56) is adjusted finely and digitally to an arbitrary resistance value. Thus, the chip resistor 1 can generate a desired value of resistance.

FIG. 7 is an electric circuit diagram of an element according to another embodiment of the present invention.
Instead of configuring the element 5 by connecting the reference resistance unit R / 16 and the resistance unit R64 to the resistance unit R / 32 in series as described above, the element 5 may be configured as shown in FIG. Absent. Specifically, between the first connection electrode 3 and the second connection electrode 4, the reference resistance unit body R / 16 and the 12 types of resistance unit bodies R / 16, R / 8, R / 4, R / 2, R1 , R2, R4, R8, R16, R32, R64, and R128 may be used to form the element 5 by a series connection circuit.

  In this case, the fuse film F is connected in series to each of the 12 types of resistance unit bodies other than the reference resistance unit body R / 16. In a state where all the fuse films F are not blown, each resistance unit body is electrically incorporated into the element 5. If the fuse film F is selectively blown, for example, by laser light, according to the required resistance value, a resistance unit body corresponding to the blown fuse film F (a resistance unit body in which the fuse film F is connected in series) ) Is electrically separated from the element 5, the resistance value of the entire chip resistor 1 can be adjusted.

FIG. 8 is an electric circuit diagram of an element according to still another embodiment of the present invention.
The feature of the element 5 shown in FIG. 8 is that it has a circuit configuration in which a series connection of a plurality of types of resistance unit bodies and a parallel connection of a plurality of types of resistance unit bodies are connected in series. As in the previous embodiment, the plurality of types of resistance unit bodies connected in series are connected to the fuse film F in parallel for each resistance unit body. The fuse film F is short-circuited. Therefore, when the fuse film F is melted, the resistance unit body short-circuited by the fuse film F to be melted is electrically incorporated into the element 5.

On the other hand, a fuse film F is connected in series to each of a plurality of types of resistance unit bodies connected in parallel. Therefore, by fusing the fuse film F, the resistance unit body to which the blown fuse film F is connected in series can be electrically disconnected from the parallel connection of the resistance unit bodies.
With this configuration, for example, a small resistance of 1 kΩ or less is made on the parallel connection side, and if a resistance circuit of 1 kΩ or more is made on the series connection side, a wide range from a small resistance of several Ω to a large resistance of several MΩ is obtained. Resistor circuits can be made using a network of resistors constructed with an equal basic design.

As described above, in the chip resistor 1, the connection state of the plurality of resistors R (resistance unit bodies) can be changed in the trimming target region X.
FIG. 9 is a schematic cross-sectional view of a chip resistor.
Next, the chip resistor 1 will be described in more detail with reference to FIG. For convenience of explanation, in FIG. 9, the element 5 described above is shown in a simplified manner, and each element other than the substrate 2 is hatched.

Here, the insulating film 23 and the resin film 24 described above will be described.
The insulating film 23 is a film made of, for example, SiN (silicon nitride), and has a thickness of 1000 to 5000 mm (here, about 3000 mm). The insulating film 23 is provided over the entire area of the element formation surface 2A, and covers the resistor film 21 and each wiring film 22 (that is, the element 5) on the resistor film 21 from the surface (upper side in FIG. 9). The upper surface of each resistor R in the element 5 is covered. For this reason, the insulating film 23 also covers the wiring film 22 in the above-described trimming target region X (see FIG. 5B). The insulating film 23 is in contact with the element 5 (the wiring film 22 and the resistor film 21), and is also in contact with the insulating layer 20 in a region other than the resistor film 21. Thereby, the insulating film 23 functions as a protective film that covers the entire element forming surface 2A and protects the element 5 and the insulating layer 20.

Further, the insulating film 23 prevents a short circuit between the resistors R other than the wiring film 22 (short circuit between adjacent resistor film lines 21A).
Note that the surface of the end 23A located at the edge of the element formation surface 2A in the insulating film 23 swells toward the side (outside the chip resistor 1 (substrate 2) in the direction along the element formation surface 2A). It is curved so that it comes out.

Although not shown, the insulating film 23 protrudes from the element formation surface 2A and is a portion exposed to the side surfaces 2C to 2F in the insulating layer 20 or a boundary portion with the element formation surface 2A in each of the side surfaces 2C to 2F. May be coated.
The resin film 24 protects the element formation surface 2A of the chip resistor 1 together with the insulating film 23, and is made of a resin such as polyimide. The thickness of the resin film 24 is about 5 μm. The resin film 24 covers the entire surface of the insulating film 23 (including the resistor film 21 and the wiring film 22 covered with the insulating film 23) over the entire area, and the element formation surface on each of the side surfaces 2C to 2F. The boundary part with 2A (upper end part in FIG. 9) and the part exposed to the side surfaces 2C to 2F in the insulating layer 20 are covered. Therefore, portions of the four side surfaces 2 </ b> C to 2 </ b> F opposite to the element formation surface 2 </ b> A (lower side in FIG. 9) are exposed to the outside as the outer surface of the chip resistor 1.

  Thus, since the insulating film 23 covers the resistor film 21 (thin film resistor R) and the wiring film 22 and the resin film 24 covers the surface of the insulating film 23, the thin film resistor R and the wiring film 22 ( The element formation surface 2 </ b> A) can be double protected by the insulating film 23 and the resin film 24. Furthermore, since the foreign film is prevented from adhering to the thin film resistor R and the wiring film 22 by the insulating film 23 and the resin film 24, a short circuit in the thin film resistor R and the wiring film 22 can be prevented.

  In the resin film 24, portions that coincide with the four side surfaces 2 </ b> C to 2 </ b> F in a plan view are arcuate bulging portions 24 </ b> A that bulge to the side (outside) of the substrate 2 from these side surfaces. That is, the resin film 24 (the bulging portion 24A) protrudes beyond the side surfaces 2C to 2F (corresponding side surfaces) on the side surfaces 2C to 2F. Such a resin film 24 has a round-shaped side surface 24B convex toward the side in the arcuate bulge portion 24A.

  Here, at the intersection 27 that forms the boundary between the element formation surface 2A and each of the side surfaces 2C to 2F, the element formation surface 2A and each of the side surfaces 2C to 2F intersect. It is an angular shape that is different from the round shape (round shape of the intersecting portion 11). Therefore, the bulging portion 24 </ b> A covers each crossing portion 27. In this case, occurrence of chipping at the intersection 27 can be prevented by the resin film 24. Further, since the bulging portion 24A bulges outward (outside the substrate 2 in the direction along the element forming surface 2A) from the side surfaces 2C to 2F at the intersection portion 27, the chip resistor 1 is moved to the surroundings. At the time of contact, the bulging portion 24A first comes into contact with the surrounding thing to alleviate the impact caused by the contact, so that the impact can be prevented from reaching the element 5 and the like. In particular, since the bulging portion 24A has the round-shaped side surface 24B, the impact caused by the contact can be smoothly reduced.

In addition, the resin film 24 is provided in a region away from the intersecting portion 27 side (from the back surface 2B to the element formation surface 2A side) on the side surfaces 2C to 2F. However, there may be a configuration in which the resin film 24 does not cover the side surfaces 2C to 2F (a configuration in which all of the side surfaces 2C to 2F are exposed).
In the resin film 24, one opening 25 is formed at two positions separated in plan view. Each opening 25 is a through hole that continuously penetrates the resin film 24 and the insulating film 23 in the respective thickness directions. Therefore, the opening 25 is formed not only in the resin film 24 but also in the insulating film 23. A part of the wiring film 22 is exposed from each opening 25. A portion of the wiring film 22 exposed from each opening 25 is a pad region 22A for external connection.

  Of the two openings 25, one opening 25 is filled with the first connection electrode 3, and the other opening 25 is filled with the second connection electrode 4. A part of each of the first connection electrode 3 and the second connection electrode 4 protrudes from the opening 25 on the surface of the resin film 24. The first connection electrode 3 is electrically connected to the wiring film 22 in the pad region 22 </ b> A in the opening 25 through the one opening 25. The second connection electrode 4 is electrically connected to the wiring film 22 in the pad region 22 </ b> A in the opening 25 through the other opening 25. Thereby, each of the first connection electrode 3 and the second connection electrode 4 is electrically connected to the element 5. Here, the wiring film 22 forms wiring connected to each of the group of resistors R (resistor 56), the first connection electrode 3, and the second connection electrode 4.

  As described above, the resin film 24 and the insulating film 23 in which the opening 25 is formed cover the element formation surface 2 </ b> A in a state where the first connection electrode 3 and the second connection electrode 4 are exposed from the opening 25. Therefore, electrical connection between the chip resistor 1 and the circuit board 9 can be achieved via the first connection electrode 3 and the second connection electrode 4 protruding from the opening 25 on the surface of the resin film 24 ( (Refer FIG.1 (b)).

10A to 10G are schematic sectional views showing a method for manufacturing the chip resistor shown in FIG.
First, as shown in FIG. 10A, a substrate 30 as a base of the substrate 2 is prepared. In this case, the front surface 30A of the substrate 30 is the element formation surface 2A of the substrate 2, and the back surface 30B of the substrate 30 is the back surface 2B of the substrate 2.

Then, the insulating layer 20 made of SiO ₂ or the like is formed on the surface 30A of the substrate 30, and the element 5 (the resistor R and the wiring film 22 connected to the resistor R) is formed on the insulating layer 20. Specifically, first, a TiN or TiON resistor film 21 is formed on the entire surface of the insulating layer 20 by sputtering, and an aluminum (Al) wiring film 22 is stacked on the resistor film 21. . Thereafter, using a photolithography process, the resistor film 21 and the wiring film 22 are selectively removed by, for example, dry etching, and as shown in FIG. 3A, a resistor having a certain width in which the resistor film 21 is stacked in a plan view. A configuration is obtained in which the body membrane lines 21A are arranged in the column direction at regular intervals. At this time, a region in which the resistor film line 21A and the wiring film 22 are partially cut is formed, and the fuse film F and the connecting conductor film C are formed in the trimming target region X (see FIG. 2). ). Subsequently, the wiring film 22 stacked on the resistor film line 21A is selectively removed. As a result, the element 5 having a configuration in which the wiring film 22 is laminated on the resistor film line 21A with a predetermined interval R is obtained.

  Referring to FIG. 10A, the elements 5 are formed at a number of locations on the surface 30 </ b> A of the substrate 30 according to the number of chip resistors 1 formed on one substrate 30. One region where the element 5 (the resistor 56 described above) is formed on the substrate 30 is referred to as a chip resistor region Y. On the surface 30A of the substrate 30, a plurality of chip resistor regions Y each having a resistor 56 (that is, Element 5) is formed. A region between adjacent chip resistor regions Y on the surface 30A of the substrate 30 is referred to as a boundary region Z.

  Next, as shown in FIG. 10A, an insulating film (CVD insulating film) 45 made of SiN is formed over the entire surface 30A of the substrate 30 by a CVD (Chemical Vapor Deposition) method. The formed CVD insulating film 45 has a thickness of 1000 to 5000 mm (here, about 3000 mm). The CVD insulating film 45 covers all of the insulating layer 20 and the element 5 (the resistor film 21 and the wiring film 22) on the insulating layer 20, and is in contact with them. Therefore, the CVD insulating film 45 also covers the wiring film 22 in the aforementioned trimming target region X (see FIG. 2). Further, since the CVD insulating film 45 is formed over the entire area of the surface 30A of the substrate 30, the CVD insulating film 45 is formed to extend to a region other than the trimming target region X on the surface 30A. Thereby, the CVD insulating film 45 becomes a protective film for protecting the entire surface 30A (including the element 5 on the surface 30A).

Next, as illustrated in FIG. 10B, a resist pattern 41 is formed over the entire surface 30 </ b> A of the substrate 30 so as to cover the entire CVD insulating film 45. An opening 42 is formed in the resist pattern 41.
FIG. 11 is a schematic plan view of a part of a resist pattern used for forming a groove in the process of FIG. 10B.

  Referring to FIG. 11, openings 42 in resist pattern 41 are viewed in plan view when a large number of chip resistors 1 (in other words, chip resistor regions Y described above) are arranged in a matrix (also in a lattice shape). And the area between the contours of the adjacent chip resistors 1 (the hatched portion in FIG. 11, in other words, the boundary area Z). Therefore, the entire shape of the opening 42 is a lattice shape having a plurality of linear portions 42A and 42B orthogonal to each other.

In the resist pattern 41, the straight portions 42A and 42B orthogonal to each other in the opening 42 are connected to each other while maintaining a state orthogonal to each other (without bending). Therefore, the intersecting portion 43 of the straight portions 42A and 42B is pointed so as to form approximately 90 ° in plan view.
Referring to FIG. 10B, each of CVD insulating film 45, insulating layer 20, and substrate 30 is selectively removed by plasma etching using resist pattern 41 as a mask. As a result, the material of the substrate 30 is removed in the boundary region Z between the adjacent elements 5 (chip resistor region Y). As a result, a groove 44 that penetrates the CVD insulating film 45 and the insulating layer 20 and reaches the middle of the thickness of the substrate 30 is formed at a position (boundary region Z) that coincides with the opening 42 of the resist pattern 41 in plan view. The The groove 44 has a side surface 44A that faces each other and a bottom surface 44B that connects a lower end of the facing side surface 44A (an end on the back surface 30B side of the substrate 30). The depth of the groove 44 with respect to the surface 30A of the substrate 30 is about 100 μm, and the width of the groove 44 (the interval between the opposing side surfaces 44A) is about 20 μm.

12A is a schematic plan view of the substrate after the grooves are formed in the step of FIG. 10B, and FIG. 12B is a partially enlarged view of FIG.
Referring to FIG. 12B, the overall shape of the groove 44 is a lattice shape that coincides with the opening 42 (see FIG. 11) of the resist pattern 41 in plan view. On the surface 30A of the substrate 30, the rectangular frame portion (boundary region Z) in the groove 44 surrounds the chip resistor region Y where the elements 5 are formed. A portion where the element 5 is formed on the substrate 30 is a semi-finished product 50 of the chip resistor 1. On the surface 30 </ b> A of the substrate 30, the semi-finished products 50 are located one by one in the chip resistor region Y surrounded by the grooves 44, and these semi-finished products 50 are arranged in a matrix.

Then, according to the sharply intersecting portion 43 (see FIG. 11) in the opening 42 of the resist pattern 41, the corner portion 60 (corresponding to the intersecting portion 11 of the chip resistor 1) of the semi-finished product 50 in a plan view is substantially perpendicular. Pointed to.
After the groove 44 is formed as shown in FIG. 10B, the resist pattern 41 is removed, and the CVD insulating film 45 is selectively removed by etching using the mask 65 as shown in FIG. 10C. In the mask 65, an opening 66 is formed in a portion of the CVD insulating film 45 that coincides with each pad region 22A (see FIG. 9) in plan view. As a result, a portion corresponding to the opening 66 in the CVD insulating film 45 is removed by etching, and the opening 25 is formed in the portion. As a result, the CVD insulating film 45 is formed so as to expose each pad region 22A in the opening 25. Two openings 25 are formed for one semi-finished product 50.

FIG. 13A is a schematic cross-sectional view during the manufacture of the chip resistor according to one embodiment of the present invention. FIG. 13B is a schematic cross-sectional view during the manufacture of the chip resistor according to the comparative example.
In each semi-finished product 50, after forming two openings 25 in the CVD insulating film 45 as shown in FIG. 10C, a probe 70 of a resistance measuring device (not shown) is brought into contact with the pad region 22A of each opening 25, The entire resistance value of the element 5 is detected. Then, as shown in FIG. 13A, by irradiating the arbitrary fuse film F with the laser light L through the CVD insulating film 45, the wiring film 22 in the trimming target region X is trimmed with the laser light L, The fuse film F is blown. The blown fuse film F is a portion trimmed (fused) in the wiring film 22 in the trimming target region X described above. Thus, by fusing (trimming) the fuse film F so as to have a necessary resistance value, the resistance value of the entire semi-finished product 50 (in other words, the chip resistor 1) can be adjusted as described above.

  The power (energy) of the laser beam L in this embodiment is 1.2 μJ to 2.7 μJ, and the spot diameter of the laser beam L is 3 μm to 5 μm. Further, when the laser light L is transmitted through the CVD insulating film 45, the portion of the CVD insulating film 45 through which the laser light L is transmitted is cut, and the resistor film 21 is also melted at the place where the wiring film 22 is melted. A part of the insulating layer 20 is cut off together with the wiring film 22.

  As described above, the entire wiring film 22 constituting the fuse film F is covered with the CVD insulating film 45. For this reason, the laser light L applied to the wiring film 22 in the trimming target region X passes through the CVD insulating film 45 in the trimming target region X and then reaches the wiring film 22 (fuse film F). In this way, the energy of the laser beam L can be efficiently concentrated (accumulated) in the fuse film F, so that the fuse film F can be surely and quickly blown (laser trimming) by the laser beam L. In addition, since the CVD insulating film 45 is in contact with the wiring film 22, the wiring film 22 is reliably covered with the CVD insulating film 45, so that the energy of the laser beam can be efficiently concentrated on the wiring film 22. Thus, reliable trimming of the wiring film 22 can be effectively realized.

In addition, since the wiring film 22 is covered with the CVD insulating film 45, even if a fragment is generated by laser trimming, the fragment becomes a foreign substance 68 and contacts the wiring film 22 (element 5) to cause a short circuit. Absent. That is, a short circuit caused by trimming can be prevented.
As described above, with respect to fusing of the fuse film F (in other words, trimming of the wiring film 22 in the fuse film F), the fusing property is improved and the yield is improved, so that the productivity of the chip resistor 1 is improved. Can do.

  Here, since the CVD insulating film 45 is formed by the CVD method, the CVD insulating film 45 (particularly, compared with the case where the same material as the CVD insulating film 45 is pasted on the wiring film 22 to form the film). The film quality of the CVD insulating film 45) in the entire trimming target region X can be stabilized. Thereby, the wiring film 22 can be covered with the CVD insulating film 45 without leakage. Therefore, reliable trimming of the wiring film 22 can be realized in any part of the trimming target region X. That is, by using such a CVD insulating film 45, it is possible to reliably improve the fusing property and the yield of the fuse film F.

  Further, as described above, the CVD insulating film 45 desirably has a thickness of 1000 to 5000 mm. In this case, since the energy of the laser beam can be efficiently concentrated on the wiring film 22, reliable trimming of the wiring film 22 can be effectively realized. When the CVD insulating film 45 is thinner than 1000 mm, the effect of efficiently concentrating the energy of the laser light L on the fuse film F is reduced. On the contrary, if the CVD insulating film 45 is thicker than 5000 mm, it becomes difficult to cut the CVD insulating film 45 with the laser light L, so that the fuse film F is difficult to be blown (trimmed).

Further, since the SiN generation temperature of the CVD insulating film 45 at the time of CVD is lower than the melting temperature of Al or AlCu alloy of the wiring film 22, the CVD insulating film 45 is formed on the wiring film 22 without melting the wiring film 22. Can be formed. On the contrary, if the CVD insulating film 45 is SiO ₂ (silicon oxide), the generation temperature of SiO ₂ is higher than the melting temperature of Al or AlCu alloy, so that the wiring film is formed when the CVD insulating film 45 made of SiO ₂ is generated. As a result, the CVD insulating film 45 cannot be formed on the wiring film 22.

  Unlike the present invention as described above, in the case of the comparative example in which the wiring film 22 is exposed without being covered with the CVD insulating film 45 as shown in FIG. 13B, the energy of the laser light L is the fuse film. It cannot be concentrated (accumulated) in F, but dispersed around the fuse film F. Specifically, the energy of the laser beam L is reflected on the surface of the wiring film 22, dispersed in the wiring film 22, or absorbed by the resistor film 21 and the insulating layer 20. For this reason, it is difficult to reliably blow the fuse film F with the laser beam L, and it takes time to blow the fuse film F. Furthermore, since the wiring film 22 (element 5) is exposed, the foreign matter 68 described above may adhere to the element 5 and a short circuit may occur in the element 5.

After adjusting the resistance value of the entire semi-finished product 50 as described above, a photosensitive resin sheet 46 made of polyimide is pasted on the substrate 30 from above the CVD insulating film 45 as shown in FIG. 10D. To wear.
14 (a) and 14 (b) are schematic perspective views showing a state in which a polyimide sheet is attached to a substrate in the step of FIG. 10D.

Specifically, as shown in FIG. 14A, after a polyimide sheet 46 is placed on the substrate 30 (strictly, the CVD insulating film 45 on the substrate 30) from the surface 30A side, The sheet 46 is pressed against the substrate 30 by the rotating roller 47 as shown in FIG.
As shown in FIG. 10D, when the sheet 46 is attached to the entire surface of the CVD insulating film 45, a part of the sheet 46 slightly enters the groove 44 side, but the element 5 side ( The sheet 46 does not reach the bottom surface 44B of the groove 44 only by covering a part of the surface 30A side). Therefore, in the groove 44 between the sheet 46 and the bottom surface 44 </ b> B of the groove 44, a space S having almost the same size as the groove 44 is formed. At this time, the thickness of the sheet 46 is 10 μm to 30 μm. A part of the sheet 46 enters each opening 25 of the CVD insulating film 45 and closes the opening 25.

Next, the sheet 46 is subjected to heat treatment. As a result, the thickness of the sheet 46 is thermally contracted to about 5 μm.
Next, as shown in FIG. 10E, the sheet 46 is patterned, and portions of the sheet 46 that coincide with the grooves 44 and the pad regions 22A (openings 25) of the wiring film 22 in a plan view are selectively removed. Specifically, the sheet 46 is exposed and developed in the pattern using a mask 62 in which openings 61 having a pattern that matches (matches) the groove 44 and each pad region 22A in plan view. As a result, the sheet 46 is separated above the groove 44 and each pad region 22A, and the edge portion separated in the sheet 46 overlaps with the side surface 44A of the groove 44 while hanging slightly to the groove 44 side. The bulging portion 24A (having the round-shaped side surface 24B) described above is naturally formed. By forming the bulging portion 24 </ b> A, the above-described intersecting portion 27 is covered with the sheet 46.

At this time, portions of the sheet 46 that have entered the respective openings 25 of the CVD insulating film 45 are also removed, so that the openings 25 are opened.
Next, a Ni / Pd / Au laminated film constituted by laminating Ni, Pd and Au is formed on the pad region 22A in each opening 25 by electroless plating. At this time, the Ni / Pd / Au laminated film protrudes from the opening 25 to the surface of the sheet 46. Thereby, the Ni / Pd / Au laminated film in each opening 25 becomes the first connection electrode 3 and the second connection electrode 4 shown in FIG. 10F.

Next, after a current inspection between the first connection electrode 3 and the second connection electrode 4 is performed, the substrate 30 is ground from the back surface 30B.
Specifically, after forming the groove 44, as shown in FIG. 10G, a thin plate-like support base 71 made of PET (polyethylene terephthalate) is connected to the first connection in each semi-finished product 50 via an adhesive 72. It is affixed to the electrode 3 and the second connection electrode 4 side (that is, the element formation surface 2A). Thereby, each semi-finished product 50 is supported by the support base material 71. Here, for example, a laminate sheet can be used as the support substrate 71 in which the adhesive 72 is integrated.

  In a state where each semi-finished product 50 is supported by the support base 71, the substrate 30 is ground from the back surface 30B side. When the substrate 30 is thinned by grinding until the bottom surface 44B (see FIG. 10F) of the groove 44 is reached, there is no connection between the adjacent semi-finished products 50, so the substrate 30 is divided with the groove 44 as a boundary. The products 50 are separated individually. That is, the substrate 30 is cut (divided) in the groove 44 (in other words, the boundary region Z), and thereby the individual semi-finished products 50 are cut out.

Thereafter, the back surface 30B of the substrate 30 in each semi-finished product 50 is polished and mirror-finished.
In each semi-finished product 50, the portion that formed the side surface 44A of the groove 44 becomes one of the side surfaces 2C to 2F of the substrate 2 in the chip resistor 1, and the back surface 30B becomes the back surface 2B. That is, the step of forming the groove 44 described above (see FIG. 10B) is included in the step of forming the side surfaces 2C to 2F. Then, the CVD insulating film 45 becomes the insulating film 23. Further, the separated sheet 46 becomes the resin film 24.

  Even if the chip size of the chip resistor 1 is small, the semi-finished product 50 (chip resistor 1) is separated by grinding the substrate 30 from the back surface 30B after the grooves 44 are formed in this way. can do. Therefore, as compared with the conventional case where the chip resistor 1 is divided into individual pieces by dicing the substrate 30 with a dicing saw, the cost can be reduced and the time can be shortened and the yield can be improved by omitting the dicing process.

FIG. 15 is a schematic perspective view showing a semi-finished chip resistor immediately after the process of FIG. 10G.
In the state immediately after separating the semi-finished products 50, each semi-finished product 50 continues to stick to the support base 71 and is supported by the support base 71 as shown in FIG. 15. At this time, in each semi-finished product 50, the back surface 30 </ b> B (back surface 2 </ b> B) side is exposed from the support base material 71. As shown in the enlarged view of the part surrounded by the broken-line circle in FIG. 15, in the semi-finished product 50, the intersecting portions 11 of adjacent ones of the back surface 2B, the side surface 2C, the side surface 2D, the side surface 2E, and the side surface 2F are substantially perpendicular. Pointed to.

FIG. 16 is a first schematic diagram showing a step subsequent to FIG. 10G. FIG. 17 is a second schematic diagram showing a step subsequent to FIG. 10G.
Referring to FIG. 16, after separating the semi-finished products 50 by grinding from the back surface 30B as described above, the side surface (in FIG. 16) opposite to the side on which the semi-finished product 50 is adhered on the support base 71. The rotation shaft 75 is connected to the gravity center position of the lower side surface. The rotating shaft 75 can rotate in both the clockwise direction CW and the counterclockwise direction CCW around the axis by receiving a driving force from a motor (not shown). The support base 71 in a state of supporting the semi-finished product 50 rotates together with the rotation shaft 75 (integral rotation) in a plane along the back surface 30B of the semi-finished product 50.

  And the etching nozzle 76 is arrange | positioned so that the side which the semi-finished product 50 adhered in the support base material 71 may be faced. The etching nozzle 76 is, for example, a tubular shape extending in parallel with the support base 71, and a supply port 77 is formed at a position facing the semi-finished product 50. The etching nozzle 76 is connected to a tank (not shown) filled with a chemical solution or the like. Referring to FIG. 17, the etching nozzle 76 can swing with the side opposite to the supply port 77 side as a fulcrum P as shown by a broken line arrow in a state parallel to the support base 71. The rotating shaft 75 and the etching nozzle 76 constitute a part of the spin etcher 80.

  After the semi-finished product 50 is individually separated and the back surface 30B is polished, the support base 71 rotates in a predetermined pattern in one or both of the clockwise direction CW and the counterclockwise direction CCW, and the etching nozzle 76 swings. In this state, the etching agent (etching liquid) is uniformly sprayed from the supply port 77 of the etching nozzle 76 to the back surface 2B side of each semi-finished product 50 supported by the support base 71. Thereby, each semi-finished product 50 supported by the support base material 71 is isotropically subjected to chemical etching (wet etching) from the back surface 2B side. In particular, in each semi-finished product 50, the intersections 11 between adjacent ones of the back surface 2B, the side surface 2C, the side surface 2D, the side surface 2E, and the side surface 2F are isotropically etched. When the intersection 11 before etching is pointed (see FIG. 15), the corner of each intersection 11 is likely to be scraped due to crystal defects or the like accompanying the etching. Specifically, it is shaped into a round shape (see an enlarged portion surrounded by a broken-line circle in FIG. 17). Further, the isotropic etching is performed in a state where the support base material 71 is rotated, so that the etching agent is uniformly bathed on the intersecting portions 11 of the respective semi-finished products 50, and thus the intersecting portions 11 of the respective semi-finished products 50. Can be uniformly shaped into a round shape. Further, isotropic etching is performed on the plurality of semi-finished products 50 (chip resistors 1) supported by the support base 71. Thereby, in the some semi-finished product 50, the cross | intersection part 11 of each semi-finished product 50 can be shaped in round shape at once.

  In the isotropic etching, the etching solution is preferably sprayed toward the back surface 2B side of each semi-finished product 50 (spray spray). If the etching solution remains liquid, not only the intersection 11 but also the back surface 2B, the side surface 2C, the side surface 2D, the side surface 2E, and the side surface 2F will be etched. When the liquid is discharged, the mist-like etching liquid easily adheres to the intersecting portion 11 and the intersecting portion 11 is preferentially etched. Each crossing portion 11 can be shaped into a round shape while suppressing etching.

  When each intersection 11 becomes round, the etching process is finished, and the chip resistor 1 (see FIG. 9) is completed. Thereafter, a rinse solution (water) is poured onto the chip resistor 1 from the etching nozzle 76, and the chip resistor 1 is cleaned. At this time, the support base 71 may be rotating, or the etching nozzle 76 may be swung. After cleaning, the chip resistor 1 is peeled off from the support base 71 and mounted on the circuit board 9 (see FIG. 1B) described above, for example.

Here, the etching solution may be either acidic or alkaline, but when the crossing portion 11 is isotropically etched, it is preferable to use an acidic etching solution. When an alkaline etching solution is used, the crossing portions 11 are anisotropically etched, so that it takes time to make each crossing portion 11 round as compared with the case where an acidic etching solution is used. As an example of an acidic etching solution, a mixture of H ₂ SO ₄ (sulfuric acid) and CH ₃ COOH (acetic acid) in a base solution of HF (hydrogen fluoride) and HNO ₃ (nitric acid) is used. In this etching solution, the viscosity is adjusted with sulfuric acid, and the etching rate is adjusted with acetic acid.

As mentioned above, although embodiment of this invention was described, this invention can also be implemented with another form.
For example, when the substrate 30 is divided into individual chip resistors 1, the substrate 30 is ground from the back surface 30B side to the bottom surface 44B of the groove 44 (see FIG. 10F). Instead, the substrate 30 may be divided into individual chip resistors 1 by selectively removing the portion of the substrate 30 that coincides with the groove 44 in plan view from the back surface 30B. Alternatively, the substrate 30 may be diced by a dicing blade (not shown) and divided into individual chip resistors 1.

In addition, the chip resistor 1 (the first connection electrode 3, the second connection electrode 4, the element 5 and the like) may be formed on the substrate 2 using a semiconductor manufacturing process. In this case, the substrate 2 and the substrate 30 are A semiconductor substrate made of Si (silicon) may be used.
In addition, various design changes can be made within the scope of matters described in the claims.

  The chip resistor of the above invention is formed on the element formation surface, a substrate having a back surface opposite to the element formation surface, a substrate connecting the element formation surface and the back surface, and the element formation surface. A resistor, an external connection electrode electrically connected to the resistor and disposed on the element formation surface, and a resin film that covers the element formation surface in a state where the external connection electrode is exposed, The intersection where the back surface and the side surface of the substrate intersect has a round shape, and the intersection portion where the element formation surface and the side surface of the substrate intersect each other has a shape different from the round shape. According to this configuration, the occurrence of chipping at the intersection (corner portion) between the back surface and the side surface of the substrate can be prevented, and productivity can be improved.

It is preferable that the substrate has a plurality of the side surfaces intersecting each other, and a crossing portion where the plurality of side surfaces intersect has a round shape. According to this configuration, in the substrate, it is possible to prevent occurrence of chipping not only at the intersection between the back surface and the side surface but also at the intersection between the side surfaces.
It is preferable that the radius of curvature of the round shape is 20 μm or less. It is preferable that an insulating layer is provided between the substrate and the resistor.

  The resistor includes a thin film resistor formed on the element formation surface, a chip resistor is further connected to the thin film resistor and includes a wiring film formed on the element formation surface, and the resin film The thin film resistor and the wiring film are preferably covered. According to this configuration, since foreign matter is prevented from adhering to the thin film resistor and the wiring film, a short circuit in the thin film resistor and the wiring film can be prevented.

Preferably, the resistor is formed of a plurality of thin film resistors having the same resistance value, and a connection state of the plurality of thin film resistors can be changed in a predetermined trimming target region.
It is preferable that the chip resistor further includes a protective film formed on the element formation surface so as to cover the thin film resistor and the wiring film, and the resin film is formed so as to cover the surface of the protective film. . According to this configuration, the thin film resistor and the wiring film can be double protected by the protective film and the resin film.

It is preferable that the resin film covers an intersection where the element formation surface and the side surface of the substrate intersect. According to this configuration, occurrence of chipping at the intersection between the element formation surface and the side surface of the substrate can be prevented by the resin film.
It is preferable that the resin film bulges outward from the substrate at an intersection where the element formation surface and the side surface of the substrate intersect. According to this configuration, when the chip resistor comes into contact with the surrounding thing, the bulged portion in the resin film first comes into contact with the surrounding thing to alleviate the impact caused by the contact. It can be prevented that it reaches the elements.

It is preferable that the resin film is provided in a region away from the back surface to the element formation surface side on the side surface of the substrate. Moreover, it is preferable that the said resin film contains a polyimide.
The method of manufacturing a chip resistor according to the present invention includes a step of forming a plurality of chip resistor regions each having a resistance on an element forming surface of a substrate, and a boundary region between adjacent chip resistor regions. In the step of removing the material and forming a side surface orthogonal to the element formation surface, the step of cutting out the chip resistor by dividing the substrate in the boundary region, and the chip resistor divided, And a step of shaping the intersecting portion where the back surface and the side surface intersect into a round shape by etching from the back surface side opposite to the element formation surface. According to this method, it is possible to manufacture a chip resistor in which the intersection of the back surface and the side surface of the substrate has a round shape.

In the step of forming the side surface, it is preferable that a plurality of the side surfaces intersecting each other is formed, the etching is isotropic etching, and a crossing portion where the plurality of side surfaces intersect is shaped into a round shape. Thereby, in the substrate, it is possible to manufacture a chip resistor in which not only the intersection between the back surface and the side surface but also the intersection between the side surfaces has a round shape.
It is preferable that the etching includes a step of discharging an etching solution in a mist toward the back side of the chip resistor. As a result, the mist-like etching solution easily adheres to the intersection, and the intersection is preferentially etched. Therefore, the intersection can be shaped into a round shape while suppressing the etching of the back surface and each side surface.

It is preferable to further include a step of forming a resin film that covers the element formation surface. Thereby, the element formation surface can be protected by the resin film.
It is preferable that the step of forming the resin film includes a step of covering the intersecting portion where the element formation surface and the side surface of the substrate intersect with the resin film. Thereby, since the intersection part between the element formation surface and the side surface of the substrate can be protected by the resin film, occurrence of chipping at the intersection part can be prevented.

The step of forming the side surface includes the step of forming a groove in the substrate at a boundary region between adjacent chip resistor regions, and the step of cutting out the chip resistor from the back surface side to the groove It is preferable to include a step of thinning until it reaches. Thereby, a chip resistor can be separated into pieces.
After forming the groove, including a step of attaching a support base material to the element formation surface, the thinning step is performed from the back side of the substrate supported by the support base material, and the etching is performed. It is preferable to be executed for the plurality of chip resistors supported by the support substrate. Thereby, in a plurality of chip resistors, the intersection of each chip resistor can be rounded at a time.

It is preferable that the etching is performed in a state where the support base material is rotated in a plane along the back surface. As a result, since the etching agent is uniformly applied to the intersections of the chip resistors, the intersections of the chip resistors can be uniformly shaped into a round shape.
<Invention According to First Reference Example>
(1) Features of the invention according to the first reference example For example, the features of the invention according to the first reference example are the following A1 to A14.
(A1) A step of forming elements in a plurality of chip component regions set on the surface of the substrate, and a step of forming a groove having a predetermined depth from the surface of the substrate in a boundary region of the plurality of chip component regions, Grinding the back surface of the substrate until it reaches the groove, and dividing the substrate into a plurality of chip components.

According to this method, since a plurality of chip component regions formed on the substrate can be divided into individual chip components all at once, the productivity of the chip components can be improved.
(A2) The chip component according to A1, wherein the step of forming the groove includes a step of forming a resist pattern corresponding to the boundary region and a step of forming the groove by etching using the resist pattern as a mask. Manufacturing method.

According to this method, since the groove can be formed with high accuracy by etching, it is possible to improve the external dimension accuracy of each chip component divided by the groove. In addition, since the groove interval can be reduced according to the resist pattern, the chip component formed between adjacent grooves can be miniaturized. Further, in the case of etching, the chip component is not cut out, so that the occurrence of chipping at the corner portion of the chip component can be reduced, and the appearance of the chip component can be improved.
(A3) The manufacturing method of the chip component according to A2, wherein the etching is plasma etching.

According to this method, since the grooves can be formed with higher accuracy and the intervals between the grooves can be further miniaturized, the external dimension accuracy and appearance of the chip component can be further improved, and further miniaturization can be achieved.
(A4) The method of manufacturing a chip component according to any one of A1 to A3, wherein the step of forming the element includes a step of forming a resistor, and the chip component is a chip resistor.

According to this method, it is possible to provide a chip resistor that can be miniaturized and improved in productivity, external dimension accuracy, and external appearance.
(A5) The step of forming the resistor includes a step of forming a resistor film on the surface of the substrate, a step of forming a wiring film so as to be in contact with the resistor film, the resistor film, and the wiring Forming a plurality of the resistors by patterning a film, forming an external connection electrode for externally connecting the element on the substrate, and forming the plurality of resistors on the external connection electrode. And a step of forming a plurality of fuses that are detachably connected to the substrate on the substrate.

According to this method, the chip resistor can easily and quickly cope with a plurality of types of resistance values by selecting and cutting one or a plurality of fuses. In other words, chip resistors having various resistance values can be realized with a common design by combining a plurality of resistors having different resistance values.
(A6) The method of manufacturing a chip component according to any one of A1 to A3, wherein the step of forming the element includes a step of forming a capacitor element, and the chip component is a chip capacitor.

According to this method, it is possible to provide a chip capacitor that can be miniaturized and improved in productivity, external dimension accuracy, and external appearance.
(A7) The step of forming the capacitor element includes a step of forming a capacitive film on the surface of the substrate, a step of forming an electrode film in contact with the capacitive film, and dividing the electrode film into a plurality of electrode film portions. Forming a plurality of capacitor elements corresponding to the plurality of electrode film portions, forming an external connection electrode for externally connecting the elements, and the plurality of capacitor elements. The method of manufacturing a chip part according to A6, further comprising: forming a plurality of fuses that are detachably connected to the external connection electrodes on the substrate.

According to this method, the chip capacitor can easily and quickly cope with a plurality of types of capacitance values by selecting and cutting one or a plurality of fuses. In other words, chip capacitors having various capacitance values can be realized by a common design by combining a plurality of capacitor elements having different capacitance values.
(A8) The chip part manufacturing method according to any one of A1 to A7, wherein the planar shape of each chip part region is a rectangle having two orthogonal sides of 0.4 mm or less and 0.2 mm or less, respectively.

According to this method, an extremely small chip component can be provided.
(A9) The chip component manufacturing method according to any one of A1 to A8, wherein a band-shaped boundary region having a width of 1 μm to 60 μm is provided between the plurality of chip component regions.
According to this method, an extremely small chip component can be provided.
(A10) A substrate, a plurality of element elements formed on the surface of the substrate, an external connection electrode formed on the surface of the substrate, and formed on the surface of the substrate, wherein the plurality of element elements are A chip component including a plurality of fuses each severably connected to an external connection electrode, wherein a side surface of the substrate is a rough surface of an irregular pattern.

With regard to this configuration, when the substrate is divided into a plurality of chip parts in the groove by forming a groove having a predetermined depth from the surface of the substrate by etching using a resist pattern, each chip part has a A side surface becomes a rough surface of an irregular pattern. When etching is used in this way, since a plurality of element elements formed on the substrate can be divided into individual chip parts at the same time, the productivity of the chip parts can be improved. In addition, since the grooves can be formed with high accuracy by etching, it is possible to improve the external dimension accuracy of each chip component divided by the grooves. In addition, since the groove interval can be reduced according to the resist pattern, the chip component formed between adjacent grooves can be miniaturized. Further, in the case of etching, the chip component is not cut out, so that the occurrence of chipping at the corner portion of the chip component can be reduced, and the appearance of the chip component can be improved.
(A11) The element element is a resistor including a resistor film formed on a surface of the substrate and a wiring film laminated in contact with the resistor film, and the chip component is a chip resistor. The chip component according to A10.

According to this configuration, it is possible to provide a chip resistor that can be miniaturized and improved in productivity, outer dimension accuracy, and appearance. In the chip resistor, it is possible to easily and quickly cope with a plurality of types of resistance values by selecting and cutting one or a plurality of fuses. In other words, chip resistors having various resistance values can be realized with a common design by combining a plurality of resistors having different resistance values.
(A12) The element element is a capacitor element including a capacitive film formed on a surface of the substrate and an electrode film formed in contact with the capacitive film, and the chip component is a chip capacitor. A10 Chip components as described in

According to this configuration, it is possible to provide a chip capacitor that can be reduced in size and improved in productivity, outer dimension accuracy, and appearance. In the chip capacitor, by selecting and cutting one or a plurality of fuses, it is possible to easily and quickly cope with a plurality of types of capacitance values. In other words, chip capacitors having various capacitance values can be realized by a common design by combining a plurality of capacitor elements having different capacitance values.
(A13) The chip component may be a chip inductor.
(A14) The chip component may be a chip diode.
(2) Embodiment of Invention According to First Reference Example Hereinafter, an embodiment of a first reference example will be described in detail with reference to the accompanying drawings. Note that the reference numerals shown in FIGS. 18 to 40 are effective only in these drawings, and even if they are used in other embodiments, they do not indicate the same elements as those in the other embodiments.

FIG. 18A is a schematic perspective view for explaining the configuration of the chip resistor according to the embodiment of the first reference example, and FIG. 18B is a diagram illustrating the chip resistor mounted on the mounting substrate. It is a typical side view which shows the state made.
This chip resistor a1 is a minute chip component and has a rectangular parallelepiped shape as shown in FIG. The planar shape of the chip resistor a1 is a rectangle having two orthogonal sides (long side a81, short side a82) of 0.4 mm or less and 0.2 mm or less, respectively. Preferably, regarding the dimensions of the chip resistor a1, the length L (the length of the long side a81) is about 0.3 mm, the width W (the length of the short side a82) is about 0.15 mm, and the thickness T is about 0.1 mm.

The chip resistor a1 is formed by forming a plurality of chip resistors a1 in a lattice shape on a substrate, forming grooves in the substrate, and then polishing the back surface (or dividing the substrate by the grooves) to obtain individual chips. It is obtained by separating the resistor a1.
The chip resistor a1 includes a substrate a2 constituting a main body (resistor main body) of the chip resistor a1, a first connection electrode a3 and a second connection electrode a4 serving as external connection electrodes, a first connection electrode a3 and a second connection electrode. It mainly includes an element a5 externally connected by a connection electrode a4.

  The substrate a2 has a substantially rectangular parallelepiped chip shape. In the substrate a2, the upper surface in FIG. 18A is a surface a2A. The surface a2A is a surface (element formation surface) on which the element a5 is formed on the substrate a2, and has a substantially rectangular shape. A surface opposite to the front surface a2A in the thickness direction of the substrate a2 is a back surface a2B. The front surface a2A and the back surface a2B have substantially the same shape and are parallel to each other. However, the front surface a2A is larger than the back surface a2B. Therefore, the back surface a2B fits inside the surface a2A in a plan view as viewed from the direction orthogonal to the surface a2A. The rectangular edge defined by the pair of long sides a81 and the short side a82 on the front surface a2A is referred to as an edge portion a85, and the rectangular edge defined by the pair of long sides a81 and the short side a82 on the back surface a2B is defined. , It will be called edge a90.

In addition to the front surface a2A and the back surface a2B, the substrate a2 has a side surface a2C, a side surface a2D, a side surface a2E, and a side surface a2F that extend across these surfaces and connect these surfaces.
The side surface a2C is constructed between the short sides a82 on one side in the longitudinal direction on the front surface a2A and the back surface a2B (left front side in FIG. 18A), and the side surface a2D is on the other side in the longitudinal direction on the front surface a2A and the back surface a2B ( It is constructed between the short sides a82 on the right back side in FIG. The side surface a2C and the side surface a2D are both end surfaces of the substrate a2 in the longitudinal direction. The side surface a2E is constructed between the long sides a81 on one side in the short direction of the front surface a2A and the back surface a2B (the left back side in FIG. 18A), and the side surface a2F is the short direction of the front surface a2A and the back surface a2B. It is constructed between the long sides a81 on the other side (the right front side in FIG. 18A). The side surface a2E and the side surface a2F are both end surfaces of the substrate a2 in the lateral direction. Each of the side surface a2C and the side surface a2D intersects (substantially orthogonal) with each of the side surface a2E and the side surface a2F. As described above, since the front surface a2A is larger than the back surface a2B, each of the side surfaces a2C to a2F has an isosceles trapezoid shape having an upper bottom on the back surface a2B side and a lower bottom on the front surface a2A side. That is, the side shape of the chip resistor a1 is an isosceles trapezoid. Therefore, adjacent ones on the surface a2A to the side surface a2F form an acute angle or an obtuse angle. Specifically, the surface a2A and each of the side surface a2C, the side surface a2D, the side surface a2E, and the side surface a2F are acute angles, and the back surface a2B and each of the side surface a2C, the side surface a2D, the side surface a2E, and the side surface a2F are obtuse angles. It is done. For convenience of explanation, in each figure after FIG. 18, each of the side surfaces a2C to a2F is shown inclined (exaggerated) from the actual side.

  In the substrate a2, the entire area of the surface a2A and the side surfaces a2C to a2F is covered with the insulating film a23. Therefore, strictly speaking, in FIG. 18A, the entire areas of the surface a2A and the side surfaces a2C to a2F are located on the inner side (back side) of the insulating film a23 and are not exposed to the outside. Further, the chip resistor a1 has a resin film a24. The resin film a24 includes a first resin film a24A and a second resin film a24B different from the first resin film a24A. The first resin film a24A is formed in regions slightly apart from the edge a85 of the surface a2A to the back surface a2B side in each of the side surface a2C, the side surface a2D, the side surface a2E, and the side surface a2F. The second resin film a24B covers a portion of the insulating film a23 on the surface a2A that does not overlap with the edge a85 of the surface a2A (an inner region of the edge a85). The insulating film a23 and the resin film a24 will be described in detail later.

  The first connection electrode a3 and the second connection electrode a4 are formed in a region inside the edge a85 on the surface a2A of the substrate a2, and are partially exposed from the second resin film a24B on the surface a2A. Yes. In other words, the second resin film a24B covers the surface a2A (strictly, the insulating film a23 on the surface a2A) so as to expose the first connection electrode a3 and the second connection electrode a4. Each of the first connection electrode a3 and the second connection electrode a4 is configured, for example, by stacking Ni (nickel), Pd (palladium), and Au (gold) on the surface a2A in this order. The first connection electrode a3 and the second connection electrode a4 are arranged at intervals in the longitudinal direction of the surface a2A, and are long in the short direction of the surface a2A. In FIG. 18A, on the surface a2A, the first connection electrode a3 is provided near the side surface a2C, and the second connection electrode a4 is provided near the side surface a2D.

  The element a5 is a circuit element, and is formed in a region between the first connection electrode a3 and the second connection electrode a4 on the surface a2A of the substrate a2, and from above by the insulating film a23 and the second resin film a24B. It is covered. The element a5 constitutes the resistor body described above. The element a5 of this embodiment is a resistor a56. The resistor a56 is configured by a circuit network in which a plurality of (unit) resistors R having equal resistance values are arranged in a matrix on the surface a2A. The resistor R is made of TiN (titanium nitride), TiON (titanium oxynitride) or TiSiON. The element a5 is electrically connected to a wiring film a22, which will be described later, and is electrically connected to the first connection electrode a3 and the second connection electrode a4 via the wiring film a22.

  As shown in FIG. 18B, the first connection electrode a3 and the second connection electrode a4 are opposed to the mounting substrate a9, and the solder and a13 are electrically and mechanically connected to the circuit (not shown) of the mounting substrate a9. Thus, the chip resistor a1 can be mounted on the mounting substrate a9 (flip chip connection). The first connection electrode a3 and the second connection electrode a4 functioning as external connection electrodes are made of gold (Au) or plated with gold in order to improve solder wettability and reliability. It is desirable.

FIG. 19 is a plan view of the chip resistor, showing the arrangement relationship between the first connection electrode, the second connection electrode and the element, and the configuration (layout pattern) of the element in plan view.
Referring to FIG. 19, element a5 is a resistance network. Specifically, the element a5 includes eight resistors R arranged along the row direction (longitudinal direction of the substrate a2) and 44 resistors arranged along the column direction (width direction of the substrate a2). It has a total of 352 resistors R composed of the body R. These resistors R are a plurality of element elements that constitute a resistance network of the element a5.

  A plurality of types of resistor circuits R are formed by grouping and electrically connecting a large number of these resistors R every predetermined number of 1 to 64. The formed plurality of types of resistance circuits are connected in a predetermined manner by a conductor film D (a wiring film formed of a conductor). Further, a plurality of fuses (fuses) that can be cut (fused) on the surface a2A of the substrate a2 in order to electrically incorporate a resistance circuit with respect to the element a5 or to electrically separate it from the element a5. F is provided. The plurality of fuses F and the conductor film D are arranged along the inner side of the second connection electrode a3 so that the arrangement region is linear. More specifically, the plurality of fuses F and the conductor film D are arranged so as to be adjacent to each other, and the arrangement direction thereof is linear. The plurality of fuses F connect a plurality of types of resistance circuits (a plurality of resistors R for each resistance circuit) to the second connection electrode a3 so as to be cut (separable). The plurality of fuses F and the conductor film D constitute the resistor body described above.

20A is a plan view illustrating a part of the element shown in FIG. 19 in an enlarged manner. FIG. 20B is a longitudinal sectional view in the length direction along BB of FIG. 20A drawn for explaining the configuration of the resistor in the element. FIG. 20C is a longitudinal sectional view in the width direction along CC of FIG. 20A drawn for explaining the configuration of the resistor in the element.
The configuration of the resistor R will be described with reference to FIGS. 20A, 20B, and 20C.

The chip resistor a1 further includes an insulating layer a20 and a resistor film a21 in addition to the wiring film a22, insulating film a23, and resin film a24 described above (see FIGS. 20B and 20C). The insulating layer a20, the resistor film a21, the wiring film a22, the insulating film a23, and the resin film a24 are formed on the substrate a2 (surface a2A).
The insulating layer a20 is made of SiO ₂ (silicon oxide). The insulating layer a20 covers the entire surface a2A of the substrate a2. The insulating layer a20 has a thickness of about 10,000 mm.

  The resistor film a21 is formed on the insulating layer a20. The resistor film a21 is formed of TiN, TiON, or TiSiON. The thickness of the resistor film a21 is about 2000 mm. The resistor film a21 constitutes a plurality of resistor films (hereinafter referred to as “resistor film line a21A”) extending linearly in parallel between the first connection electrode a3 and the second connection electrode a4. The resistor film line a21A may be cut at a predetermined position in the line direction (see FIG. 20A).

  A wiring film a22 is laminated on the resistor film line a21A. The wiring film a22 is made of Al (aluminum) or an alloy of aluminum and Cu (copper) (AlCu alloy). The thickness of the wiring film a22 is about 8000 mm. The wiring film a22 is laminated on the resistor film line a21A with a constant interval R in the line direction, and is in contact with the resistor film line a21A.

The electrical characteristics of the resistor film line a21A and the wiring film a22 having this configuration are shown by circuit symbols as shown in FIG. That is, as shown in FIG. 21A, the resistor film lines a21A in the region of the predetermined interval R each form one resistor R having a constant resistance value r.
And in the area | region where the wiring film a22 was laminated | stacked, the resistor film line a21A is short-circuited by the said wiring film a22 by electrically connecting the resistors R with which the wiring film a22 adjoins. Therefore, a resistance circuit is formed which is formed by connecting in series the resistor R of the resistor r shown in FIG.

  Further, since the adjacent resistor film lines a21A are connected by the resistor film a21 and the wiring film a22, the resistor network of the element a5 shown in FIG. 20A is shown in FIG. A resistor circuit (consisting of R unit resistors) is formed. As described above, the resistor film a21 and the wiring film a22 constitute the resistor R and the resistor circuit (that is, the element a5). Each resistor R includes a resistor film line a21A (resistor film a21) and a plurality of wiring films a22 stacked on the resistor film line a21A at regular intervals in the line direction. A resistor film line a21A at a constant interval R where a22 is not laminated constitutes one resistor R. The resistor film line a21A in the portion constituting the resistor R has the same shape and size. Therefore, the multiple resistors R arranged in a matrix on the substrate a2 have equal resistance values.

In addition, the wiring film a22 laminated on the resistor film line a21A forms the resistor R and also serves as a conductor film D for connecting a plurality of resistors R to form a resistor circuit. (See FIG. 19).
22A is a partially enlarged plan view of a region including a fuse drawn by enlarging a part of the plan view of the chip resistor shown in FIG. 19, and FIG. 22B is a plan view of FIG. It is a figure which shows the cross-sectional structure which follows BB.

  As shown in FIGS. 22A and 22B, the above-described fuse F and conductor film D are also formed by the wiring film a22 laminated on the resistor film a21 forming the resistor R. That is, the fuse F and the conductor film D are formed on the same layer as the wiring film a22 stacked on the resistor film line a21A forming the resistor R by using Al or AlCu alloy which is the same metal material as the wiring film a22. Yes. As described above, the wiring film a22 is also used as a conductor film D that electrically connects a plurality of resistors R in order to form a resistance circuit.

  That is, in the same layer laminated on the resistor film a21, the wiring film for forming the resistor R, the fuse F, the conductor film D, and the element a5 are connected to the first connection electrode a3 and the second electrode. A wiring film for connecting to the connection electrode a4 is formed using the same metal material (Al or AlCu alloy) as the wiring film a22. Note that the fuse F is made different from (differentiated from) the wiring film a22 because the fuse F is formed so as to be easily cut and no other circuit elements exist around the fuse F. This is because they are arranged in such a manner.

  Here, in the wiring film a22, a region where the fuse F is arranged is referred to as a trimming target region X (see FIGS. 19 and 22A). The trimming target region X is a linear region along the inner side of the second connection electrode a3. In the trimming target region X, not only the fuse F but also the conductor film D is disposed. A resistor film a21 is also formed below the wiring film a22 in the trimming target region X (see FIG. 22B). The fuse F is a wiring having a larger inter-wiring distance (separated from the surroundings) than the portion other than the trimming target region X in the wiring film a22.

The fuse F indicates not only a part of the wiring film a22 but also a group (fuse element) of a part of the resistor R (resistor film a21) and a part of the wiring film a22 on the resistor film a21. It may be.
Further, the fuse F has been described only in the case where the same layer as the conductor film D is used. However, in the conductor film D, another conductor film is further laminated thereon to lower the resistance value of the entire conductor film D. You may do it. Even in this case, if a conductive film is not laminated on the fuse F, the fusing property of the fuse F will not deteriorate.

FIG. 23 is an electric circuit diagram of an element according to the embodiment of the first reference example.
Referring to FIG. 23, element a5 includes a reference resistance circuit R8, a resistance circuit R64, two resistance circuits R32, a resistance circuit R16, a resistance circuit R8, a resistance circuit R4, a resistance circuit R2, a resistance circuit R1, and a resistance circuit R. / 2, resistor circuit R / 4, resistor circuit R / 8, resistor circuit R / 16, resistor circuit R / 32 are connected in series from the first connection electrode a3 in this order. Each of the reference resistor circuit R8 and the resistor circuits R64 to R2 is configured by connecting in series the same number of resistors R as the last number (“64” in the case of R64). The resistor circuit R1 is composed of one resistor R. Each of the resistance circuits R / 2 to R / 32 is configured by connecting in parallel the same number of resistors R as the last number of itself (“32” in the case of R / 32). The meaning of the number at the end of the resistor circuit is the same in FIGS. 24 and 25 described later.

One fuse F is connected in parallel to each of the resistor circuits R64 to R / 32 other than the reference resistor circuit R8. The fuses F are connected in series either directly or via a conductor film D (see FIG. 22A).
In a state where all the fuses F are not blown as shown in FIG. 23, the element a5 is a reference composed of a series connection of eight resistors R provided between the first connection electrode a3 and the second connection electrode a4. A resistor circuit of the resistor circuit R8 is configured. For example, if the resistance value r of one resistor R is r = 8Ω, the chip resistor in which the first connection electrode a3 and the second connection electrode a4 are connected by a resistance circuit (reference resistance circuit R8) of 8r = 64Ω. A device a1 is configured.

  Further, in a state where all the fuses F are not blown, a plurality of types of resistor circuits other than the reference resistor circuit R8 are short-circuited. That is, 12 types and 13 resistor circuits R64 to R / 32 are connected in series to the reference resistor circuit R8, but each resistor circuit is short-circuited by the fuse F connected in parallel. From an electrical viewpoint, each resistance circuit is not incorporated in the element a5.

  In the chip resistor a1 according to this embodiment, the fuse F is selectively blown by, for example, laser light according to a required resistance value. As a result, the resistance circuit in which the fuses F connected in parallel are melted is incorporated into the element a5. Therefore, the entire resistance value of the element a5 can be set to a resistance value in which a resistance circuit corresponding to the blown fuse F is connected in series.

  In particular, a plurality of types of resistor circuits have one, two, four, eight, sixteen, thirty-two, etc. resistors R having the same resistance value in series, and a geometric sequence having a common ratio of two. The number of resistors R is increased, and a plurality of types of series resistor circuits and resistors R having the same resistance value are connected in parallel to 2, 4, 8, 16,. A plurality of types of parallel resistance circuits are provided which are connected by increasing the number of resistors R in a geometric sequence. Therefore, by selectively fusing the fuse F (including the above-described fuse element), the resistance value of the entire element a5 (resistor a56) is adjusted finely and digitally to an arbitrary resistance value. Thus, a resistor having a desired value can be generated in the chip resistor a1.

FIG. 24 is an electric circuit diagram of an element according to another embodiment of the first reference example.
Instead of configuring the element a5 by connecting the reference resistor circuit R8 and the resistor circuits R64 to R / 32 in series as shown in FIG. 23, the element a5 may be configured as shown in FIG. Specifically, between the first connection electrode a3 and the second connection electrode a4, the reference resistance circuit R / 16 and 12 types of resistance circuits R / 16, R / 8, R / 4, R / 2, R1, R2 , R4, R8, R16, R32, R64, R128, and the element a5 may be configured by a series connection circuit with a parallel connection circuit.

  In this case, a fuse F is connected in series to each of the 12 types of resistor circuits other than the reference resistor circuit R / 16. In a state where all the fuses F are not blown, each resistance circuit is electrically incorporated into the element a5. If the fuse F is selectively blown by a laser beam, for example, according to a required resistance value, a resistance circuit corresponding to the blown fuse F (a resistance circuit in which the fuse F is connected in series) becomes the element a5. Therefore, the resistance value of the entire chip resistor a1 can be adjusted.

FIG. 25 is an electric circuit diagram of an element according to still another embodiment of the first reference example.
The feature of the element a5 shown in FIG. 25 is that the circuit configuration is such that a series connection of a plurality of types of resistance circuits and a parallel connection of a plurality of types of resistance circuits are connected in series. As in the previous embodiment, fuses F are connected in parallel to each of the plurality of resistor circuits connected in series, and the plurality of resistor circuits connected in series are all short-circuited by the fuse F. It is in a state. Therefore, when the fuse F is blown, the resistance circuit short-circuited by the blown fuse F is electrically incorporated into the element a5.

On the other hand, a fuse F is connected in series to each of the plurality of types of resistor circuits connected in parallel. Therefore, by blowing the fuse F, the resistor circuit to which the blown fuse F is connected in series can be electrically disconnected from the parallel connection of the resistor circuit.
With this configuration, for example, a small resistance of 1 kΩ or less is made on the parallel connection side, and if a resistance circuit of 1 kΩ or more is made on the series connection side, a wide range from a small resistance of several Ω to a large resistance of several MΩ is obtained. Resistor circuits can be made using a network of resistors constructed with an equal basic design. That is, the chip resistor a1 can easily and quickly cope with a plurality of types of resistance values by selecting and cutting one or a plurality of fuses F. In other words, chip resistors a1 having various resistance values can be realized with a common design by combining a plurality of resistors R having different resistance values.

As described above, in the chip resistor a1, in the trimming target region X, the connection state of the plurality of resistors R (resistance circuit) can be changed.
FIG. 26 is a schematic cross-sectional view of a chip resistor.
Next, the chip resistor a1 will be described in more detail with reference to FIG. For convenience of explanation, in FIG. 26, the above-described element a5 is simplified and each element other than the substrate a2 is hatched.

Here, the insulating film a23 and the resin film a24 described above will be described.
The insulating film a23 is made of, for example, SiN (silicon nitride), and has a thickness of 1000 to 5000 mm (here, about 3000 mm). The insulating film a23 is provided over the entire area of the surface a2A and the side surfaces a2C to a2F. The insulating film a23 on the surface a2A covers the resistor film a21 and each wiring film a22 (that is, the element a5) on the resistor film a21 from the surface (upper side in FIG. 26), and each resistor in the element a5 The upper surface of R is covered. Therefore, the insulating film a23 also covers the wiring film a22 in the trimming target region X described above (see FIG. 22B). The insulating film a23 is in contact with the element a5 (the wiring film a22 and the resistor film a21), and is also in contact with the insulating layer a20 in a region other than the resistor film a21. Thus, the insulating film a23 on the surface a2A functions as a protective film that covers the entire surface a2A and protects the element a5 and the insulating layer a20. On the surface a2A, the insulating film a23 prevents a short circuit between the resistors R other than the wiring film a22 (short circuit between adjacent resistor film lines a21A).

  On the other hand, the insulating film a23 provided on each of the side surfaces a2C to a2F functions as a protective layer that protects each of the side surfaces a2C to a2F. The boundary between each of the side surfaces a2C to a2F and the surface a2A is the edge a85 described above, but the insulating film a23 also covers the boundary (edge a85). In the insulating film a23, a portion covering the edge a85 (a portion overlapping the edge a85) is referred to as an end a23A.

The resin film a24 protects the surface a2A of the chip resistor a1 together with the insulating film a23, and is made of a resin such as polyimide. The thickness of the resin film a24 is about 5 μm.
As described above, the resin film a24 includes the first resin film a24A and the second resin film a24B.
The first resin film a24A covers a part of the side surfaces a2C to a2F that is slightly separated from the edge a85 (the end a23A of the insulating film a23) toward the back surface a2B. Specifically, the first resin film a <b> 24 </ b> A is formed in each of the side surfaces a <b> 2 </ b> C to a <b> 2 </ b> F in a region having a gap K from the edge a <b> 85 of the front surface a <b> 2 </ b> A to the back surface a <b> 2 </ b> B side. However, the first resin film a24A is arranged to be biased toward the front surface a2A rather than the back surface a2B. The first resin films a24A on the side surfaces a2C and 2D extend in a streak pattern along the short side a82 and are formed over the entire region in the direction of the short side a82 (see FIG. 18A). The first resin films a24A on the side surfaces a2E and 2F extend in a streak shape along the long side a81 and are formed over the entire area in the direction of the long side a81 (see FIG. 18A). The first resin film a24A on each of the side surfaces a2C to a2F projects outward from the edge (edge portion a85) of the surface a2A. Specifically, the first resin film a24A bulges outward in an arc shape from the edge a85 in the direction along the surface a2A. Therefore, in plan view, the first resin film a24A forms the outline of the chip resistor a1.

  The second resin film a24B covers substantially the entire surface of the insulating film a23 on the surface a2A (including the resistor film a21 and the wiring film a22 covered with the insulating film a23). Specifically, the second resin film a24B is formed away from the end a23A so as not to cover the end a23A (the edge a85 of the surface a2A) of the insulating film a23. Therefore, the first resin film a24A and the second resin film a24B are not continuous and are interrupted at the end a23A (the entire area of the edge a85). Thereby, end part a23A (entire area of edge part a85) of insulating film a23 is exposed outside.

  In the second resin film a24B, one opening a25 is formed at two positions apart from each other in plan view. Each opening a25 is a through hole that continuously penetrates the second resin film a24B and the insulating film a23 in the respective thickness directions. Therefore, the opening a25 is formed not only in the second resin film a24B but also in the insulating film a23. A part of the wiring film a22 is exposed from each opening a25. A portion exposed from each opening a25 in the wiring film a22 is a pad region a22A for external connection.

  Of the two openings a25, one opening a25 is filled with the first connection electrode a3, and the other opening a25 is filled with the second connection electrode a4. A part of each of the first connection electrode a3 and the second connection electrode a4 protrudes from the opening a25 on the surface of the second resin film a24B. The first connection electrode a3 is electrically connected to the wiring film a22 in the pad region a22A in the opening a25 through the one opening a25. The second connection electrode a4 is electrically connected to the wiring film a22 in the pad region a22A in the opening a25 through the other opening a25. Thereby, each of the first connection electrode a3 and the second connection electrode a4 is electrically connected to the element a5. Here, the wiring film a22 forms a wiring connected to the group of resistors R (resistor a56), the first connection electrode a3, and the second connection electrode a4.

  As described above, the second resin film a24B and the insulating film a23 in which the opening a25 is formed cover the surface a2A in a state where the first connection electrode a3 and the second connection electrode a4 are exposed from the opening a25. Therefore, electrical connection between the chip resistor a1 and the mounting substrate a9 can be achieved via the first connection electrode a3 and the second connection electrode a4 protruding from the opening a25 on the surface of the second resin film a24B. (See FIG. 18B).

  Here, in the second resin film a24B, the portion located between the first connection electrode a3 and the second connection electrode a4 (referred to as “center portion a24C”) is the first connection electrode a3 and the second connection electrode. It is higher than a4 (away from the surface a2A). That is, the central portion a24C has a surface a24D that is higher than the first connection electrode a3 and the second connection electrode a4. The surface a24D is convexly curved in a direction away from the surface a2A.

27A to 27G are schematic sectional views showing a method for manufacturing the chip resistor shown in FIG.
First, as shown in FIG. 27A, a substrate a30 that is a base of the substrate a2 is prepared. In this case, the surface a30A of the substrate a30 is the surface a2A of the substrate a2, and the back surface a30B of the substrate a30 is the back surface a2B of the substrate a2.

Then, the surface a30A of the substrate a30 is thermally oxidized to form an insulating layer a20 made of SiO ₂ or the like on the surface a30A, and the element a5 (the resistor R and the wiring film a22 connected to the resistor R is formed on the insulating layer a20. ). Specifically, first, a TiN, TiON, or TiSiON resistor film a21 is formed on the entire surface of the insulating layer a20 by sputtering, and aluminum is further formed on the resistor film a21 so as to be in contact with the resistor film a21. A (Al) wiring film a22 is laminated. Thereafter, using a photolithography process, the resistor film a21 and the wiring film a22 are selectively removed and patterned by dry etching such as RIE (Reactive Ion Etching), for example, as shown in FIG. In a plan view, a configuration is obtained in which the resistor film lines a21A having a certain width on which the resistor films a21 are stacked are arranged in the column direction at regular intervals. At this time, a region in which the resistor film line a21A and the wiring film a22 are partially cut is formed, and the fuse F and the conductor film D are formed in the trimming target region X (see FIG. 19). Subsequently, the wiring film a22 laminated on the resistor film line a21A is selectively removed by wet etching, for example. As a result, an element a5 having a configuration in which the wiring film a22 is laminated with a predetermined interval R on the resistor film line a21A is obtained. At this time, in order to confirm whether or not the resistor film a21 and the wiring film a22 are formed with target dimensions, the resistance value of the entire element a5 may be measured.

  Referring to FIG. 27A, the element a5 is formed at a number of locations on the surface a30A of the substrate a30 according to the number of chip resistors a1 formed on one substrate a30. A single region where the element a5 (the resistor a56 described above) is formed on the substrate a30 is referred to as a chip component region Y (or a chip resistor region Y). A plurality of chips each having a resistor a56 on the surface a30A of the substrate a30. The component region Y (that is, the element a5) is formed (set). One chip component region Y coincides with a plan view of one completed chip resistor a1 (see FIG. 26). A region between adjacent chip component regions Y on the surface a30A of the substrate a30 is referred to as a boundary region Z. The boundary region Z has a belt shape and extends in a lattice shape in plan view. One chip component region Y is arranged in one lattice defined by the boundary region Z. Since the width of the boundary region Z is as extremely narrow as 1 μm to 60 μm (for example, 20 μm), many chip component regions Y can be secured on the substrate a30, and as a result, mass production of the chip resistors a1 becomes possible.

  Next, as shown in FIG. 27A, an insulating film a45 made of SiN is formed over the entire surface a30A of the substrate a30 by a CVD (Chemical Vapor Deposition) method. The insulating film a45 covers all of the insulating layer a20 and the element a5 (the resistor film a21 and the wiring film a22) on the insulating layer a20 and is in contact with them. Therefore, the insulating film a45 also covers the wiring film a22 in the trimming target region X (see FIG. 19) described above. In addition, since the insulating film a45 is formed over the entire surface a30A of the substrate a30, the insulating film a45 is formed to extend to a region other than the trimming target region X on the surface a30A. Thereby, the insulating film a45 becomes a protective film for protecting the entire surface a30A (including the element a5 on the surface a30A).

Next, as illustrated in FIG. 27B, a resist pattern a41 is formed over the entire surface a30A of the substrate a30 so as to cover the entire insulating film a45. An opening a42 is formed in the resist pattern a41.
FIG. 28 is a schematic plan view of a part of a resist pattern used for forming a groove in the step of FIG. 27B.

  Referring to FIG. 28, the opening a42 of the resist pattern a41 has a plan view when a large number of chip resistors a1 (in other words, the above-described chip component region Y) are arranged in a matrix (also in a lattice shape). It corresponds to (corresponds to) the region between the outlines of the adjacent chip resistors a1 (the hatched portion in FIG. 28, in other words, the boundary region Z). Therefore, the entire shape of the opening a42 is a lattice shape having a plurality of linear portions a42A and a42B orthogonal to each other.

In the resist pattern a41, the straight portions a42A and a42B orthogonal to each other in the opening a42 are connected to each other while maintaining a state orthogonal to each other (without being curved). Therefore, the intersecting portion a43 of the straight portions a42A and a42B is pointed so as to form approximately 90 ° in a plan view.
Referring to FIG. 27B, each of insulating film a45, insulating layer a20, and substrate a30 is selectively removed by plasma etching using resist pattern a41 as a mask. As a result, the material of the substrate a30 is removed in the boundary region Z between the adjacent elements a5 (chip component region Y). As a result, a position (boundary region Z) coinciding with the opening a42 of the resist pattern a41 in plan view passes through the insulating film a45 and the insulating layer a20 and reaches from the surface a30A of the substrate a30 to the middle of the thickness of the substrate a30. A groove a44 having a predetermined depth is formed. The groove a44 is partitioned by a pair of side walls a44A facing each other and a bottom wall a44B connecting the lower ends of the pair of side walls a44A (the end on the back surface a30B side of the substrate a30). The depth of the groove a44 based on the surface a30A of the substrate a30 is about 100 μm, and the width of the groove a44 (the interval between the opposing side walls a44A) is about 20 μm. However, the width of the groove a44 increases as it approaches the bottom wall a44B. Therefore, the side surface (section screen 44C) that defines the groove a44 in each side wall a44A is inclined with respect to the plane H perpendicular to the surface a30A of the substrate a30.

  The overall shape of the groove a44 in the substrate a30 is a lattice shape that coincides with the opening a42 (see FIG. 28) of the resist pattern a41 in plan view. On the surface a30A of the substrate a30, a rectangular frame portion (boundary region Z) in the groove a44 surrounds the chip component region Y where each element a5 is formed. A portion of the substrate a30 where the element a5 is formed is a semi-finished product a50 of the chip resistor a1. On the surface a30A of the substrate a30, the semi-finished products a50 are located one by one in the chip component region Y surrounded by the groove a44, and these semi-finished products a50 are arranged in a matrix. By forming the groove a44 in this manner, the substrate a30 is separated into the substrate a2 (the resistor main body described above) for each of the plurality of chip component regions Y.

  After the groove a44 is formed as shown in FIG. 27B, the resist pattern a41 is removed, and the insulating film a45 is selectively removed by etching using the mask a65 as shown in FIG. 27C. In the mask a65, an opening a66 is formed in a portion of the insulating film a45 that coincides with each pad region a22A (see FIG. 26) in plan view. Thereby, a portion of the insulating film a45 that coincides with the opening a66 is removed by etching, and an opening a25 is formed in the portion. Thus, the insulating film a45 is formed so as to expose each pad region a22A in the opening a25. Two openings a25 are formed for one semi-finished product a50.

  In each semi-finished product a50, after the two openings a25 are formed in the insulating film a45, the probe a70 of the resistance measuring device (not shown) is brought into contact with the pad region a22A of each opening a25, so that the entire resistance value of the element a5 is obtained. Is detected. Then, by irradiating a laser beam (not shown) to an arbitrary fuse F (see FIG. 19) through the insulating film a45, the wiring film a22 in the trimming target region X is trimmed with the laser beam, and the fuse F is melted. In this way, by fusing (trimming) the fuse F so as to have a necessary resistance value, the resistance value of the entire semi-finished product a50 (in other words, the chip resistor a1) can be adjusted as described above. At this time, since the insulating film a45 is a cover film that covers the element a5, it is possible to prevent a debris or the like generated during fusing from adhering to the element a5 and causing a short circuit. Further, since the insulating film a45 covers the fuse F (resistor film a21), the energy of the laser beam can be stored in the fuse F and the fuse F can be blown surely.

  Thereafter, SiN is formed on the insulating film a45 by the CVD method, and the insulating film a45 is thickened. At this time, as shown in FIG. 27D, the insulating film a45 is also formed over the entire inner peripheral surface of the groove a44 (the above-described section screen 44C of the side wall a44A and the upper surface of the bottom wall a44B). The final insulating film a45 (the state shown in FIG. 27D) has a thickness of 1000 to 5000 mm (here, about 3000 mm). At this time, a part of the insulating film a45 enters each opening a25 and closes the opening a25.

  Thereafter, a photosensitive resin liquid made of polyimide is spray-applied onto the substrate a30 from above the insulating film a45 to form a photosensitive resin coating film a46 as shown in FIG. 27D. The liquid photosensitive resin flows without being able to stay at the entrance of the groove a44 (the portion corresponding to the end a23A of the insulating film a23 or the edge a85 of the substrate a2). Therefore, the liquid photosensitive resin is a region on the back surface a30B side (bottom wall a44B side) of the side surface a30A of the substrate a30 on the side wall a44A (section screen 44C) of the groove a44 and the end portion of the insulating film a23 on the surface a30A. It adheres to the area | region remove | deviated from a23A, and becomes a coating film a46 (resin film | membrane) in each area | region. The coating film a <b> 46 on the surface a <b> 30 </ b> A has a shape that is convexly curved upward due to surface tension.

The coating film a46 formed on the side wall a44A of the groove a44 only covers a part of the side wall a44A of the groove a44 on the element a5 side (surface a30A side). It has not reached a44B. Therefore, the groove a44 is not blocked by the coating film a46.
Next, heat treatment (curing treatment) is performed on the coating film a46. As a result, the thickness of the coating film a46 is thermally contracted, and the coating film a46 is cured to stabilize the film quality.

  Next, as shown in FIG. 27E, the coating film a46 is patterned, and portions of the coating film a46 on the surface a30A that coincide with the pad regions a22A (openings a25) of the wiring film a22 in plan view are selectively removed. Specifically, the coating film a46 is exposed and developed with the pattern using the mask a62 in which the opening a61 having a pattern that matches (matches) with each pad region a22A in plan view is formed. As a result, the coating film a46 is separated above each pad region a22A. Next, the insulating film a45 on each pad region a22A is removed by RIE using a mask (not shown), thereby opening each opening a25 and exposing the pad region a22A.

  Next, a Ni / Pd / Au laminated film formed by laminating Ni, Pd, and Au is formed on the pad region a22A in each opening a25 by electroless plating. At this time, the Ni / Pd / Au laminated film protrudes from the opening a25 to the surface of the coating film a46. Thereby, the Ni / Pd / Au laminated film in each opening a25 becomes the first connection electrode a3 and the second connection electrode a4 shown in FIG. 27F. In addition, the upper surfaces of the first connection electrode a3 and the second connection electrode a4 are at positions below the upper end of the coating film a46 that is convexly curved on the surface a30A.

Next, after conducting an energization inspection between the first connection electrode a3 and the second connection electrode a4, the substrate a30 is ground from the back surface a30B.
Specifically, after forming the groove a44, as shown in FIG. 27G, a support tape a71 having a thin plate shape made of PET (polyethylene terephthalate) and having an adhesive surface a72 is formed on each of the semi-finished products a50 on the adhesive surface a72. Are attached to the first connection electrode a3 and the second connection electrode a4 side (that is, the surface a30A). Thereby, each semi-finished product a50 is supported by the support tape a71. Here, as the support tape a71, for example, a laminate tape can be used.

  With each semi-finished product a50 supported by the support tape a71, the substrate a30 is ground from the back surface a30B side. When the substrate a30 is thinned by grinding until it reaches the upper surface of the bottom wall a44B (see FIG. 27F) of the groove a44, there is no connection between the adjacent semi-finished products a50. Then, the semi-finished product a50 is individually separated to be a finished product of the chip resistor a1. That is, the substrate a30 is cut (divided) in the groove a44 (in other words, the boundary region Z), and thereby the individual chip resistors a1 are cut out. The chip resistor a1 may be cut out by etching the substrate a30 from the back surface a30B side to the bottom wall a44B of the groove a44.

  In each completed chip resistor a1, the portion that formed the section screen 44C of the side wall a44A of the groove a44 becomes one of the side surfaces a2C to a2F of the substrate a2, and the back surface a30B becomes the back surface a2B. That is, as described above, the step of forming the groove a44 by etching (see FIG. 27B) is included in the step of forming the side surfaces a2C to a2F. In the step of forming the groove a44, the side surface (section screen 44C) of the substrate a30 in the plurality of chip component regions Y (chip resistors a1) is inclined with respect to the plane H perpendicular to the surface a30A of the substrate a30. Can be shaped at once (see FIG. 27B). In other words, forming the groove a44 shapes the side surfaces a2C to a2F of the substrate a2 of each chip resistor a1 at a time so as to have a portion inclined with respect to the plane H.

  By forming the groove a <b> 44 by etching, the side surfaces a <b> 2 </ b> C to a <b> 2 </ b> F in the completed chip resistor a <b> 1 are rough surfaces with irregular patterns. Incidentally, when the groove a44 is mechanically formed with a dicing saw (not shown), a large number of streaks forming a grinding trace of the dicing saw remain in a regular pattern on the side surfaces a2C to a2F. Even if the side surfaces a2C to a2F are etched, this streak cannot be completely erased.

Further, the insulating film a45 becomes the insulating film a23, and the separated coating film a46 becomes the resin film a24.
As described above, if the substrate a30 is ground from the back surface a30B side after the groove a44 is formed, a plurality of chip component regions Y formed on the substrate a30 are divided into individual chip resistors a1 (chip components) all at once. (A plurality of chip resistors a1 can be obtained at a time). Therefore, the productivity of the chip resistor a1 can be improved by shortening the manufacturing time of the plurality of chip resistors a1. Incidentally, when a substrate a30 having a diameter of 8 inches is used, about 500,000 chip resistors a1 can be cut out. When the chip resistor a1 is cut out by forming the groove a44 in the substrate a30 using only a dicing saw (not shown), the dicing saw is moved many times to form many grooves a44 in the substrate a30. Therefore, the manufacturing time of the chip resistor a1 becomes long. However, if the groove a44 is formed by etching as in the first reference example, such a problem can be solved.

  That is, even if the chip size of the chip resistor a1 is small, the chip resistor a1 is separated at a time by grinding the substrate a30 from the back surface a30B after the groove a44 is formed in this way. be able to. Therefore, as compared with the conventional case where the chip resistor a1 is divided into pieces by dicing the substrate a30 with a dicing saw as in the prior art, cost reduction and time reduction can be achieved and the yield can be improved by omitting the dicing process.

  In addition, since the groove a44 can be formed with high accuracy by etching, in each chip resistor a1 divided by the groove a44, it is possible to improve the external dimension accuracy. In particular, if plasma etching is used, the groove a44 can be formed with higher accuracy. Specifically, the dimensional tolerance of the chip resistor a1 when the groove a44 is formed using a general dicing saw is ± 20 μm, whereas in the first reference example, the dimensional tolerance of the chip resistor a1 is Can be reduced to about ± 5 μm. Further, since the interval between the grooves a44 can be reduced according to the resist pattern a41 (see FIG. 28), the chip resistor a1 formed between the adjacent grooves a44 can be reduced in size. Further, in the case of etching, unlike the case of using a dicing saw, the chip resistor a1 is not cut out, so that the corner portions a11 (FIG. 18 (FIG. 18)) adjacent to each other on the side surfaces a2C to a2F of the chip resistor a1. It is possible to reduce the occurrence of chipping in a), and to improve the appearance of the chip resistor a1.

  When the individual chip resistors a1 are cut out by grinding the substrate a30 from the back surface a30B side, the chip resistors a1 may be cut out earlier or later. That is, when cutting out the chip resistor a1, a slight time difference may occur between the chip resistors a1. In this case, the chip resistor a1 previously cut out may vibrate left and right, and may contact the adjacent chip resistor a1. At this time, in each chip resistor a1, since the resin film a24 (first resin film a24A) functions as a bumper, the chip resistor a1 adjacent to the chip resistor a1 while being supported by the support tape a71 prior to singulation. Even if they collide with each other, the resin films a24 first contact each other in the chip resistors a1, so that the corner portion a12 on the front surface a2A and the back surface a2B side of the chip resistor a1 (particularly, the edge portion a85 on the surface a2A side). ) Can be avoided or suppressed. In particular, since the first resin film a24A projects outward from the edge a85 of the surface a2A of the chip resistor a1, the edge a85 does not come into contact with the surrounding parts, so that the chipping at the edge a85 is prevented. Can be avoided or suppressed.

Note that the back surface a2B of the completed chip resistor a1 may be made a mirror surface by polishing or etching to clean the back surface a2B.
29A to 29D are schematic cross-sectional views illustrating the chip resistor recovery process after the process of FIG. 27G.
FIG. 29A shows a state in which a plurality of chip resistors a1 that are separated into pieces continue to adhere to the support tape a71. In this state, as shown in FIG. 29B, a thermal foam sheet a73 is attached to the back surface a2B of the substrate a2 of each chip resistor a1. The thermally foamed sheet a73 includes a sheet-like sheet main body a74 and a large number of expanded particles a75 kneaded in the sheet main body a74.

  The adhesive strength of the sheet main body a74 is stronger than the adhesive strength on the adhesive surface a72 of the support tape a71. Therefore, after sticking the thermal foam sheet a73 on the back surface a2B of the substrate a2 of each chip resistor a1, as shown in FIG. 29C, the support tape a71 is peeled off from each chip resistor a1, and the chip resistor a1 is removed. Transfer to the thermal foam sheet a73. At this time, if the support tape a71 is irradiated with ultraviolet rays (see the dotted arrow in FIG. 29B), the adhesiveness of the adhesive surface a72 is reduced, so that the support tape a71 is easily peeled off from each chip resistor a1.

  Next, the thermal foam sheet a73 is heated. As a result, as shown in FIG. 29D, in the thermally foamed sheet a73, the foamed particles a75 in the sheet main body a74 foam and swell from the surface of the sheet main body a74. As a result, the contact area between the thermal foam sheet a73 and the back surface a2B of the substrate a2 of each chip resistor a1 is reduced, and all the chip resistors a1 are naturally peeled off (dropped off) from the thermal foam sheet a73. The chip resistor a1 collected in this way is mounted on the mounting substrate a9 (see FIG. 18B) or is accommodated in an accommodation space formed on an embossed carrier tape (not shown). In this case, the processing time can be shortened compared to the case where the chip resistors a1 are peeled off one by one from the support tape a71 or the thermal foam sheet a73. Of course, with a plurality of chip resistors a1 attached to the support tape a71 (see FIG. 29A), a predetermined number of chip resistors a1 may be directly peeled off from the support tape a71 without using the thermal foam sheet a73. .

30A to 30C are schematic cross-sectional views illustrating a chip resistor recovery step (modified example) after the step of FIG. 27G.
Each chip resistor a1 can be recovered by another method shown in FIGS. 30A to 30C.
FIG. 30A shows a state in which a plurality of chip resistors a1 that are separated into pieces continue to adhere to the support tape a71, as in FIG. 29A. In this state, as shown in FIG. 30B, the transfer tape a77 is adhered to the back surface a2B of the substrate a2 of each chip resistor a1. The transfer tape a77 has a stronger adhesive force than the adhesive surface a72 of the support tape a71. Therefore, as shown in FIG. 30C, after attaching the transfer tape a77 to each chip resistor a1, the support tape a71 is peeled off from each chip resistor a1. At this time, as described above, the support tape a71 may be irradiated with ultraviolet rays (see the dotted arrow in FIG. 30B) in order to reduce the adhesiveness of the adhesive surface a72.

  Frames a78 of a recovery device (not shown) are attached to both ends of the transfer tape a77. The frames a78 on both sides can move in a direction toward or away from each other. After the support tape a71 is peeled from each chip resistor a1, when the frames a78 on both sides are moved away from each other, the transfer tape a77 expands and becomes thin. As a result, the adhesive force of the transfer tape a77 is reduced, so that each chip resistor a1 is easily peeled off from the transfer tape a77. In this state, when the suction nozzle a76 of the transport device (not shown) is directed to the surface a2A side of the chip resistor a1, the chip resistor a1 is transferred to the transfer tape by the suction force generated by the transport device (not shown). It is peeled off from a77 and sucked by the suction nozzle a76. At this time, when the chip resistor a1 is pushed up to the suction nozzle a76 side through the transfer tape a77 from the opposite side to the suction nozzle a76 by the protrusion a79 shown in FIG. 30C, the chip resistor a1 is smoothly peeled off from the transfer tape a77. be able to. The chip resistor a1 thus collected is transported by a transport device (not shown) while being attracted to the suction nozzle a76.

  FIGS. 31 to 36 are longitudinal sectional views of the chip resistor according to the embodiment or the modification, and FIGS. 31 and 33 also show plan views. In FIG. 31 to FIG. 36, for convenience of explanation, illustration of the above-described insulating film a23 and the like is omitted, and only the substrate a2, the first connection electrode a3, the second connection electrode a4, and the resin film a24 are illustrated. In addition, in FIG. 31C and FIG. 33C, the resin film a24 is not shown.

As shown in FIGS. 31 to 36, each of the side surfaces a2C to a2F of the substrate a2 has a portion inclined with respect to the plane H perpendicular to the surface a2A of the substrate a2.
In the chip resistor a1 shown in FIGS. 31 and 32, each of the side surfaces a2C to a2F is a plane along the plane E inclined with respect to the plane H described above. Further, the surface a2A of the substrate a2 and each of the side surfaces a2C to a2F of the substrate a2 form an acute angle. For this reason, the edge a90 of the back surface a2B of the substrate a2 retreats inward of the substrate a2 with respect to the edge a85 of the surface a2A of the substrate a2. Specifically, in plan view, the rectangular edge a90 that outlines the back surface a2B is positioned inside the rectangular edge a85 that outlines the front surface a2A (see FIG. 31C). Therefore, with respect to any of the side surfaces a2C to a2F, the plane E is inclined so as to recede inward of the substrate a2 from the edge a85 of the front surface a2A toward the edge a90 of the back surface a2B. Therefore, each of the side surfaces a2C to a2F in the chip resistor a1 has a trapezoidal shape (substantially isosceles trapezoidal shape) that narrows toward the back surface a2B side.

Here, in the resin film a24, as described above, in each of the side surfaces a2C to a2F, the first resin film a24A is in a region away from the boundary (edge a85) between each side surface and the surface a2A toward the back surface a2B side. The second resin film a24B is formed on the surface a2A.
On the other hand, as shown in FIG. 32, the first resin film a24A on each of the side surfaces a2C to a2F may not be separated from the second resin film a24B at the boundary (edge portion a85) between each side surface and the surface a2A. Good. In this case, the resin film a24 is continuously formed from each of the side surfaces a2C to a2F over the surface a2A.

  In the chip resistor a1 shown in FIG. 33, each of the side surfaces a2C to a2F is a plane along the plane G inclined with respect to the plane H described above. Further, the surface a2A of the substrate a2 and each of the side surfaces a2C to a2F of the substrate a2 form an obtuse angle. For this reason, the edge a90 of the back surface a2B of the substrate a2 protrudes outward of the substrate a2 with respect to the edge a85 of the surface a2A of the substrate a2. Specifically, in plan view, the rectangular edge a90 that outlines the back surface a2B is located outside the rectangular edge a85 that outlines the front surface a2A (see FIG. 33C). Therefore, with respect to any of the side surfaces a2C to a2F, the plane G is inclined so as to protrude outward from the substrate a2 toward the edge a90 of the back surface a2B from the edge a85 of the front surface a2A. Therefore, each of the side surfaces a2C to a2F in the chip resistor a1 has a trapezoid (substantially isosceles trapezoidal) shape that narrows toward the surface a2A.

  Further, each of the side surfaces a2C to a2F does not need to be a plane inclined with respect to the plane H described above, and is a curved surface that is convexly curved inward of the substrate a2 as shown in FIGS. Thus, it is only necessary to have a portion inclined to the plane H (a curved surface portion having the planes E and G described above as tangents). In this case, the surface a2A of the substrate a2 and each of the side surfaces a2C to a2F of the substrate a2 form an acute angle, and the back surface a2B of the substrate a2 and each of the side surfaces a2C to a2F of the substrate a2 form an acute angle. Yes.

  In FIG. 34, the edge a90 of the back surface a2B of the substrate a2 is not shifted to either the outside or the inside of the substrate a2 with respect to the edge a85 of the surface a2A of the substrate a2, and overlaps in plan view. . In FIG. 35, the edge a90 of the back surface a2B of the substrate a2 is set back inward of the substrate a2 with respect to the edge a85 of the surface a2A of the substrate a2. In FIG. 36, the edge a90 of the back surface a2B of the substrate a2 projects outward from the substrate a2 with respect to the edge a85 of the surface a2A of the substrate a2.

The side surfaces a2C to a2F shown in FIGS. 31 to 36 can be realized by appropriately setting the etching conditions for forming the groove a44 by etching. That is, the shape of the side surfaces a2C to a2F on the substrate a2 can be controlled by the etching technique.
As described above, in the chip resistor a1, one of the edge a85 of the front surface a2A and the edge a90 of the back surface a2B of the substrate a2 protrudes more outward from the substrate a2 than the other (in the case of FIG. 35). except). Therefore, since the corner part (corner part) a12 in the front surface a2A and the back surface a2B of the chip resistor a1 does not become a right angle, the chipping in the corner part a12 (particularly the obtuse corner part a12) can be reduced.

  In particular, in the chip resistor a1 shown in FIGS. 31 and 32, the corner part a12 (the corner part a12 of the edge part a90) on the back surface a2B of the substrate a2 has an obtuse angle, so that chipping at the corner part a12 can be reduced. In the chip resistor a1 shown in FIG. 33, since the corner part a12 (the corner part a12 of the edge part a85) on the surface a2A of the substrate a2 has an obtuse angle, chipping at the corner part a12 can be reduced.

  When the chip resistor a1 is mounted on the mounting substrate a9 (see FIG. 18B), the suction nozzle (not shown) is attached after the back surface a2B of the chip resistor a1 is sucked to the suction nozzle (not shown) of the automatic mounting machine. The chip resistor a1 is mounted on the mounting substrate a9. Prior to adsorbing the chip resistor a1 to the adsorption nozzle (not shown), the outline of the chip resistor a1 is recognized from the front surface a2A side or the back surface a2B side, and then adsorbed on the back surface a2B of the chip resistor a1. A position to be adsorbed by a nozzle (not shown) is determined. Here, when one of the edge a85 and the edge a90 protrudes outward from the substrate a2 than the other, the outline of the chip component when the image is recognized from the front surface a2A side or the back surface a2B side of the substrate a2 is as follows. The substrate a2 is clearly constituted by only one of the edge a85 of the front surface a2A and the edge a90 of the back surface a2B (the edge protruding outward of the substrate a2). Therefore, since the outline of the chip resistor a1 can be correctly recognized, a desired portion (for example, a central portion) on the back surface a2B of the chip resistor a1 is accurately attracted to the suction nozzle (not shown), and the chip resistor a1 can be accurately mounted on the mounting substrate a9 (see FIG. 18B). That is, it is possible to improve the mounting position accuracy.

  In particular, in the case of the chip resistor a1 shown in FIGS. 31 and 33 to 36, the second resin film a24B on each of the side surfaces a2C to a2F is spaced from the surface a2A so that the edge a85 of the substrate a2 is exposed. It is formed in the open area. Further, in the case of the chip resistor a1 shown in FIGS. 31 and 34 to 36, the surface a2A of the substrate a2 and each of the side surfaces a2C to a2F form an acute angle. Therefore, since the edge a85 of the surface a2A of the substrate a2 stands out, the outline (edge a85) of the chip resistor a1 becomes clearer and easier to recognize, so that the chip resistor a1 can be more accurately attached to the mounting substrate a9. Can be implemented. In other words, the outline of the chip resistor a1 can be easily recognized by the edge a85, and thereby the chip resistor a1 can be attracted to the suction nozzle (not shown) at an accurate position. When the edge a85 or the edge a90 is focused for image recognition, the first resin film a24A is not in focus because the first resin film a24A is not in focus. The part a85 or the edge part a90 and the first resin film a24A are not confused.

On the other hand, if priority is given to the prevention of chipping at the corner portion a12 over the improvement of the mounting position accuracy, the corner portion a12 (here, the corner portion a12 on the surface a2A side) of the substrate a2 is used as the resin film as shown in FIG. It may be covered with a24. In this case, chipping at the corner portion a12 can be reliably avoided or suppressed.
Further, the surface a2A of the substrate a2 is protected by the second resin film a24B. In particular, the surface a24D of the second resin film a24B (center portion a24C) has a height higher than that of the first connection electrode a3 and the second connection electrode a4 (FIGS. 31B and 32B). 33 (b), FIG. 34 (b), FIG. 35 (b), and FIG. 36 (b), illustration is omitted). Therefore, when the chip resistor a1 is mounted on the mounting substrate a9 as shown in FIG. 18B, if the substrate a2 receives an impact from the mounting substrate a9 on the surface a2A side, the second resin film a24B (center Since the portion a24C) is initially subjected to an impact, the surface a2A of the substrate a2 can be reliably protected by relaxing the impact with the second resin film a24B.

  Although the embodiment of the first reference example has been described above, the first reference example can be implemented in other forms. For example, as an example of the chip component of the first reference example, the chip resistor a1 is disclosed in the above-described embodiment, but the first reference example can also be applied to a chip component such as a chip capacitor, a chip inductor, or a chip diode. Below, a chip capacitor is explained.

FIG. 37 is a plan view of a chip capacitor according to another embodiment of the first reference example. 38 is a cross-sectional view taken along section line XXXVIII-XXXVIII in FIG. FIG. 39 is an exploded perspective view showing a part of the structure of the chip capacitor separately.
In the chip capacitor a101 to be described, the same reference numerals are given to the portions corresponding to the portions described in the above-described chip resistor a1, and detailed description thereof will be omitted. In the chip capacitor a101, the parts denoted by the same reference numerals as those described for the chip resistor a1 have the same configuration as the parts described for the chip resistor a1, unless otherwise specified. The same effect as the part demonstrated by a1 can be show | played.

  Referring to FIG. 37, similarly to the chip resistor a1, the chip capacitor a101 includes the substrate a2, the first connection electrode a3 disposed on the substrate a2 (on the surface a2A side of the substrate a2), and the substrate a2. And a second connection electrode a4. In this embodiment, the substrate a2 has a rectangular shape in plan view. A first connection electrode a3 and a second connection electrode a4 are disposed at both ends in the longitudinal direction of the substrate a2. In this embodiment, the first connection electrode a3 and the second connection electrode a4 have a substantially rectangular planar shape extending in the short direction of the substrate a2. On the surface a2A of the substrate a2, a plurality of capacitor elements C1 to C9 are arranged in a capacitor arrangement region a105 between the first connection electrode a3 and the second connection electrode a4. The plurality of capacitor elements C1 to C9 are a plurality of element elements (capacitor elements) constituting the element a5 described above, and each of the second connection electrodes a4 via a plurality of fuse units a107 (corresponding to the fuse F described above). Is electrically connected.

  As shown in FIGS. 38 and 39, an insulating layer a20 is formed on the surface a2A of the substrate a2, and a lower electrode film a111 is formed on the surface of the insulating layer a20. The lower electrode film a111 extends over substantially the entire capacitor arrangement region a105. Further, the lower electrode film a111 is formed to extend to a region immediately below the first connection electrode a3. More specifically, the lower electrode film a111 includes a capacitor electrode region a111A that functions as a common lower electrode of the capacitor elements C1 to C9 in the capacitor arrangement region a105, and an external electrode lead that is disposed immediately below the first connection electrode a3. And a pad region a111B. The capacitor electrode region a111A is located in the capacitor arrangement region a105, and the pad region a111B is located immediately below the first connection electrode a3 and is in contact with the first connection electrode a3.

  A capacitor film (dielectric film) a112 is formed so as to cover and contact the lower electrode film a111 (capacitor electrode area a111A) in the capacitor arrangement region a105. The capacitive film a112 is formed over the entire capacitor electrode region a111A (capacitor placement region a105). In this embodiment, the capacitive film a112 further covers the insulating layer a20 outside the capacitor arrangement region a105.

  An upper electrode film a113 is formed on the capacitor film a112. In FIG. 37, the upper electrode film a113 is colored for clarity. The upper electrode film a113 includes a capacitor electrode region a113A located in the capacitor arrangement region a105, a pad region a113B located immediately below the second connection electrode a4 and in contact with the second connection electrode a4, and the capacitor electrode region a113A and the pad region. a fuse region a113C disposed between the a113B and the a113B.

  In the capacitor electrode region a113A, the upper electrode film a113 is divided (separated) into a plurality of electrode film parts (upper electrode film parts) a131 to a139. In this embodiment, each of the electrode film portions a131 to a139 is formed in a rectangular shape, and extends in a band shape from the fuse region a113C toward the first connection electrode a3. The plurality of electrode film portions a <b> 131 to a <b> 139 are opposed to the lower electrode film a <b> 111 with a plurality of types of facing areas with the capacitor film a <b> 112 interposed therebetween (while in contact with the capacitor film a <b> 112). More specifically, the facing area of the electrode film portions a131 to a139 with respect to the lower electrode film a111 may be determined to be 1: 2: 4: 8: 16: 32: 64: 128: 128. In other words, the plurality of electrode film portions a131 to a139 include a plurality of electrode film portions having different facing areas, and more specifically, a plurality of facing areas set so as to form a geometric sequence with a common ratio of 2. It includes electrode film portions a131 to a138 (or a131 to a137, a139). As a result, the plurality of capacitor elements C1 to C9 configured by the electrode film portions a131 to a139 and the lower electrode film a111 facing each other with the capacitor film a112 interposed therebetween include a plurality of capacitor elements having different capacitance values. . When the ratio of the facing areas of the electrode film portions a131 to a139 is as described above, the ratio of the capacitance values of the capacitor elements C1 to C9 is equal to the ratio of the facing areas, and is 1: 2: 4: 8: 16: 32. : 64: 128: 128. That is, the plurality of capacitor elements C1 to C9 include a plurality of capacitor elements C1 to C8 (or C1 to C7, C9) having capacitance values set so as to form a geometric sequence with a common ratio of 2.

  In this embodiment, the electrode film portions a131 to a135 are formed in a strip shape having the same width and a length ratio set to 1: 2: 4: 8: 16. The electrode film portions a135, a136, a137, a138, and a139 are formed in a strip shape having the same length and the width ratio set to 1: 2: 4: 8: 8. The electrode film portions a135 to a139 are formed to extend over a range from the edge on the second connection electrode a4 side of the capacitor arrangement region a105 to the edge on the first connection electrode a3 side. a134 is formed shorter than that.

The pad region a113B is formed substantially similar to the second connection electrode a4, and has a substantially rectangular planar shape. As shown in FIG. 38, the upper electrode film a113 in the pad region a113B is in contact with the second connection electrode a4.
The fuse region a113C is arranged along one long side of the pad region a113B (long side on the inner side with respect to the peripheral edge of the substrate a2). The fuse region a113C includes a plurality of fuse units a107 arranged along the one long side of the pad region a113B.

  The fuse unit a107 is integrally formed of the same material as the pad region a113B of the upper electrode film a113. The plurality of electrode film portions a131 to a139 are formed integrally with one or a plurality of fuse units a107, and are connected to the pad region a113B via the fuse units a107, and are connected via the pad region a113B. It is electrically connected to the second connection electrode a4. As shown in FIG. 37, the electrode film portions a131 to a136 having a relatively small area are connected to the pad region a113B by one fuse unit a107, and the electrode film portions a137 to 139 having a relatively large area include a plurality of electrode film portions a137 to 139. It is connected to the pad area a113B via the fuse unit a107. It is not necessary to use all the fuse units a107, and in this embodiment, some of the fuse units a107 are unused.

  The fuse unit a107 includes a first wide portion a107A for connection to the pad region a113B, a second wide portion a107B for connection to the electrode film portions a131 to a139, and first and second wide portions a107A and 7B. And a narrow portion a107C connecting the two. The narrow portion a <b> 107 </ b> C is configured to be cut (fused) by laser light. Accordingly, unnecessary electrode film portions of the electrode film portions a131 to a139 can be electrically disconnected from the first and second connection electrodes a3 and a4 by cutting the fuse unit a107.

  Although not shown in FIGS. 37 and 39, as shown in FIG. 38, the surface of the chip capacitor a101 including the surface of the upper electrode film a113 is covered with the insulating film a23 described above. The insulating film a23 is made of, for example, a nitride film, and is formed so as to extend not only to the upper surface of the chip capacitor a101 but also to the side surfaces a2C to a2F of the substrate a2 and cover the entire side surfaces a2C to a2F. Furthermore, the above-described resin film a24 is formed on the insulating film a23. In the resin film a24, the first resin film a24A covers the portion on the surface a2A side in the side surfaces a2C to a2F, and the second resin film a24B covers the surface a2A, but the resin film a24 is the edge of the surface a2A. It is interrupted at a85 and the edge a85 is exposed.

  The insulating film a23 and the resin film a24 are protective films that protect the surface of the chip capacitor a101. In these, the openings a25 described above are formed in regions corresponding to the first connection electrode a3 and the second connection electrode a4, respectively. The opening a25 penetrates the insulating film a23 and the resin film a24 so as to expose a part of the pad region a111B of the lower electrode film a111 and a part of the pad region a113B of the upper electrode film a113. Furthermore, in this embodiment, the opening a25 corresponding to the first connection electrode a3 also penetrates the capacitive film a112.

  A first connection electrode a3 and a second connection electrode a4 are embedded in the opening a25, respectively. Thereby, the first connection electrode a3 is bonded to the pad region a111B of the lower electrode film a111, and the second connection electrode a4 is bonded to the pad region a113B of the upper electrode film a113. The first and second external electrodes a3, 4 are formed so as to protrude from the surface of the resin film a24. Thereby, the chip capacitor a101 can be flip-chip bonded to the mounting substrate.

  FIG. 40 is a circuit diagram showing an internal electrical configuration of the chip capacitor a101. A plurality of capacitor elements C1 to C9 are connected in parallel between the first connection electrode a3 and the second connection electrode a4. Between each of the capacitor elements C1 to C9 and the second connection electrode a4, fuses F1 to F9 each composed of one or a plurality of fuse units a107 are interposed in series.

  When all the fuses F1 to F9 are connected, the capacitance value of the chip capacitor a101 is equal to the sum of the capacitance values of the capacitor elements C1 to C9. When one or more fuses selected from the plurality of fuses F1 to F9 are cut, the capacitor element corresponding to the cut fuse is cut off, and the capacitance of the chip capacitor a101 is equal to the capacitance value of the cut capacitor element. The value decreases.

  Therefore, the capacitance value between the pad regions a111B and a113B (total capacitance value of the capacitor elements C1 to C9) is measured, and then one or more appropriately selected from the fuses F1 to F9 according to the desired capacitance value. If the fuse is blown with a laser beam, adjustment to a desired capacitance value (laser trimming) can be performed. In particular, if the capacitance values of the capacitor elements C1 to C8 are set to form a geometric sequence with a common ratio of 2, the capacitor element C1 having the minimum capacitance value (the value of the first term of the geometric sequence). Fine adjustment is possible to match the target capacitance value with accuracy corresponding to the capacitance value.

For example, the capacitance values of the capacitor elements C1 to C9 may be determined as follows.
C1 = 0.03125pF
C2 = 0.0625pF
C3 = 0.125pF
C4 = 0.25pF
C5 = 0.5pF
C6 = 1pF
C7 = 2pF
C8 = 4pF
C9 = 4pF
In this case, the capacitance of the chip capacitor a101 can be finely adjusted with a minimum fitting accuracy of 0.03125 pF. Further, by appropriately selecting a fuse to be cut from the fuses F1 to F9, it is possible to provide a chip capacitor a101 having an arbitrary capacitance value between 10 pF and 18 pF.

  As described above, according to this embodiment, the plurality of capacitor elements C1 to C9 that can be separated by the fuses F1 to F9 are provided between the first connection electrode a3 and the second connection electrode a4. Capacitor elements C1 to C9 include a plurality of capacitor elements having different capacitance values, more specifically, a plurality of capacitor elements having capacitance values set so as to form a geometric sequence. As a result, by selecting one or more fuses from the fuses F1 to F9 and fusing them with laser light, it is possible to cope with a plurality of types of capacitance values without changing the design and accurately match the desired capacitance values. The chip capacitor a101 that can be embedded can be realized with a common design.

Details of each part of the chip capacitor a101 will be described below.
Referring to FIG. 37, substrate a2 has a rectangular shape such as 0.3 mm × 0.15 mm and 0.4 mm × 0.2 mm in plan view (preferably, a size of 0.4 mm × 0.2 mm or less). You may have. The capacitor placement region a105 is generally a square region having one side corresponding to the length of the short side of the substrate a2. The thickness of the substrate a2 may be about 150 μm. Referring to FIG. 38, substrate a2 may be, for example, a substrate that is thinned by grinding or polishing from the back surface side (surface on which capacitor elements C1 to C9 are not formed). As a material of the substrate a2, a semiconductor substrate typified by a silicon substrate may be used, a glass substrate may be used, or a resin film may be used.

The insulating layer a20 may be an oxide film such as a silicon oxide film. The film thickness may be about 500 to 2000 mm.
The lower electrode film a111 is preferably a conductive film, particularly a metal film, and may be, for example, an aluminum film. The lower electrode film a111 made of an aluminum film can be formed by sputtering. Similarly, the upper electrode film a113 is preferably composed of a conductive film, particularly a metal film, and may be an aluminum film. The upper electrode film a113 made of an aluminum film can be formed by sputtering. The patterning for dividing the capacitor electrode region a113A of the upper electrode film a113 into electrode film portions a131 to a139 and further shaping the fuse region a113C into a plurality of fuse units a107 can be performed by photolithography and etching processes.

The capacitor film a112 can be made of, for example, a silicon nitride film, and the film thickness can be 500 to 2000 mm (for example, 1000 mm). The capacitive film a112 may be a silicon nitride film formed by plasma CVD (chemical vapor deposition).
The insulating film a23 can be made of, for example, a silicon nitride film, and can be formed by, for example, a plasma CVD method. The film thickness may be about 8000 mm. As described above, the resin film a24 can be composed of a polyimide film or other resin film.

  The first and second connection electrodes a3 and a4 include, for example, a nickel layer in contact with the lower electrode film a111 or the upper electrode film a113, a palladium layer stacked on the nickel layer, and a gold layer stacked on the palladium layer. For example, it can be formed by a plating method (more specifically, an electroless plating method). The nickel layer contributes to improving the adhesion to the lower electrode film a111 or the upper electrode film a113, and the palladium layer is formed from the material of the upper electrode film or the lower electrode film and the gold of the uppermost layer of the first and second connection electrodes a3, a4. It functions as a diffusion preventing layer that suppresses mutual diffusion.

The manufacturing process of such a chip capacitor a101 is the same as the manufacturing process of the chip resistor a1 after forming the element a5.
When the element a5 (capacitor element) is formed in the chip capacitor a101, first, an oxide film (for example, a silicon oxide film) is formed on the surface of the substrate a30 (substrate a2) by the thermal oxidation method and / or the CVD method. An insulating layer a20 is formed. Next, a lower electrode film a111 made of an aluminum film is formed over the entire surface of the insulating layer a20 by, for example, sputtering. The film thickness of the lower electrode film a111 may be about 8000 mm. Next, a resist pattern corresponding to the final shape of the lower electrode film a111 is formed on the surface of the lower electrode film by photolithography. Using this resist pattern as a mask, the lower electrode film is etched to obtain the lower electrode film a111 having the pattern shown in FIG. The etching of the lower electrode film a111 can be performed by, for example, reactive ion etching.

  Next, a capacitor film a112 made of a silicon nitride film or the like is formed on the lower electrode film a111 by, for example, plasma CVD. In the region where the lower electrode film a111 is not formed, the capacitor film a112 is formed on the surface of the insulating layer a20. Next, the upper electrode film a113 is formed on the capacitor film a112. The upper electrode film a113 is made of, for example, an aluminum film and can be formed by a sputtering method. The film thickness may be about 8000 mm. Next, a resist pattern corresponding to the final shape of the upper electrode film a113 is formed on the surface of the upper electrode film a113 by photolithography. By etching using the resist pattern as a mask, the upper electrode film a113 is patterned into a final shape (see FIG. 37 and the like). Thereby, the upper electrode film a113 has a portion divided into a plurality of electrode film portions a131 to 139 in the capacitor electrode region a113A, and has a plurality of fuse units a107 in the fuse region a113C. It is shaped into a pattern having a connected pad region a113B. Etching for patterning the upper electrode film a113 may be performed by wet etching using an etchant such as phosphoric acid or by reactive ion etching.

  Thus, the element a5 (capacitor elements C1 to C9 and the fuse unit a107) in the chip capacitor a101 is formed. After the element a5 is formed, the insulating film a45 is formed by plasma CVD so as to cover the element a5 (the upper electrode film a113 and the capacitor film a112 in the region where the upper electrode film a113 is not formed) (FIG. 27A). After that, after the groove a44 is formed (see FIG. 27B), the opening a25 is formed (see FIG. 27C). Then, the probe a70 is pressed against the pad region a113B of the upper electrode film a113 and the pad region a111B of the lower electrode film a111 exposed from the opening a25, and the total capacitance values of the plurality of capacitor elements C0 to C9 are measured ( (See FIG. 27C). Based on the measured total capacitance value, the capacitor element to be disconnected, that is, the fuse to be disconnected, is selected according to the target capacitance value of the chip capacitor a101.

  From this state, laser trimming for fusing the fuse unit a107 is performed. That is, a laser beam is applied to the fuse unit a107 constituting the fuse selected according to the measurement result of the total capacitance value, and the narrow portion a107C (see FIG. 37) of the fuse unit a107 is melted. As a result, the corresponding capacitor element is separated from the pad region a113B. When the laser light is applied to the fuse unit a107, the energy of the laser light is accumulated in the vicinity of the fuse unit a107 by the action of the insulating film a45 that is a cover film, and thereby the fuse unit a107 is melted. Thereby, the capacitance value of the chip capacitor a101 can be surely set to the target capacitance value.

  Next, a silicon nitride film is deposited on the cover film (insulating film a45) by, for example, plasma CVD to form an insulating film a23. In the final form, the cover film described above is integrated with the insulating film a23 and constitutes a part of the insulating film a23. The insulating film a23 formed after the fuse is cut enters into the opening of the cover film destroyed at the same time when the fuse is blown, and covers and protects the cut surface of the fuse unit a107. Therefore, the insulating film a23 prevents foreign matter from entering the cut portion of the fuse unit a107 and moisture from entering. Thereby, a highly reliable chip capacitor a101 can be manufactured. The insulating film a23 may be formed so as to have a film thickness of about 8000 mm as a whole.

Next, the coating film a46 described above is formed (see FIG. 27D). Thereafter, the opening a25 closed by the coating film a46 and the insulating film a23 is opened (see FIG. 27E), and the first connection electrode a3 and the second connection electrode a4 are formed in the opening a25 by, for example, electroless plating. Grown (see FIG. 27F).
Thereafter, as in the case of the chip resistor a1, when the substrate a30 is ground from the back surface a30B (see FIG. 27G), individual pieces of the chip capacitor a101 can be cut out.

  In the patterning of the upper electrode film a113 using the photolithography process, the electrode film portions a131 to a149 having a small area can be formed with high accuracy, and the fuse unit a107 having a fine pattern can be formed. Then, after patterning the upper electrode film a113, the fuse to be cut is determined through measurement of the total capacitance value. By cutting the determined fuse, it is possible to obtain the chip capacitor a101 that is accurately adjusted to the desired capacitance value.

The chip parts (chip resistor a1 and chip capacitor a101) of the first reference example have been described above, but the first reference example can be implemented in other forms.
For example, in the above-described embodiment, in the case of the chip resistor a1, the plurality of resistor circuits have a plurality of resistor circuits having resistance values forming a series of geometric ratios with a common ratio r (0 <r, r ≠ 1) = 2. However, the common ratio of the geometric sequence may be a number other than two. Also, in the case of the chip capacitor a101, an example in which the capacitor element has a plurality of capacitor elements having capacitance values forming a geometric sequence with a common ratio r (0 <r, r ≠ 1) = 2 is shown. However, the common ratio of the geometric sequence may be a number other than two.

In the chip resistor a1 and the chip capacitor a101, the insulating layer a20 is formed on the surface of the substrate a2. However, if the substrate a2 is an insulating substrate, the insulating layer a20 can be omitted.
In the chip capacitor a101, only the upper electrode film a113 is divided into a plurality of electrode film parts. However, only the lower electrode film a111 is divided into a plurality of electrode film parts, or the upper electrode film a113. Both the lower electrode film a111 may be divided into a plurality of electrode film portions. Furthermore, in the above-described embodiment, an example in which the upper electrode film or the lower electrode film and the fuse unit are integrated is shown. However, the fuse unit is formed of a conductor film different from the upper electrode film or the lower electrode film. May be. In the above-described chip capacitor a101, a single-layer capacitor structure having an upper electrode film a113 and a lower electrode film a111 is formed. Another electrode film is laminated on the upper electrode film a113 via a capacitive film. Thus, a plurality of capacitor structures may be stacked.

In the chip capacitor a101, a conductive substrate may be used as the substrate a2, the conductive substrate may be used as a lower electrode, and the capacitor film a112 may be formed so as to be in contact with the surface of the conductive substrate. In this case, one external electrode may be drawn from the back surface of the conductive substrate.
<Invention According to Second Reference Example>
(1) Features of the invention according to the second reference example For example, the features of the invention according to the second reference example are the following B1 to B19.
(B1) including a substrate, an element formed on the surface of the substrate, and an external connection electrode provided on the surface of the substrate, the side surface of the substrate being in a plane perpendicular to the surface of the substrate A chip component having an inclined portion.

According to this configuration, in the chip component, one of the edge portion on the front surface and the edge portion on the back surface of the substrate protrudes more outward than the other. Therefore, since the corner part (corner part) of the chip part does not become a right angle, chipping at the corner part (particularly an obtuse corner part) can be reduced. In this case, the outline of the chip component when the image is recognized from the front surface side or the back surface side of the substrate is either the front edge or the back edge of the substrate (the edge protruding outward from the substrate). It is made up of only clear. Therefore, since the outline of the chip component can be correctly recognized, the chip component can be mounted on the mounting substrate with high accuracy. That is, it is possible to improve the mounting position accuracy.
(B2) The chip component according to B1, wherein the side surface of the substrate is a plane along a plane inclined with respect to a plane perpendicular to the surface of the substrate.

According to this configuration, in the chip component, one of the edge portion of the front surface and the back surface edge of the substrate can be reliably projected outward from the substrate.
(B3) The chip component according to B1 or B2, wherein an edge of the back surface of the substrate is recessed inward of the substrate with respect to an edge of the surface of the substrate.
According to this configuration, in the chip component, since the corner portion on the back surface of the substrate has an obtuse angle, chipping at the corner portion can be reduced.
(B4) The chip component according to B1 or B2, wherein an edge of the back surface of the substrate protrudes outward from the edge of the surface of the substrate.

According to this configuration, in the chip component, since the corner portion on the surface of the substrate has an obtuse angle, chipping at the corner portion can be reduced.
(B5) The chip component according to any one of B1 to B4, wherein a surface of the substrate and a side surface of the substrate form an acute angle.
According to this configuration, since the edge of the surface of the substrate stands out, the outline of the chip component becomes clearer and easier to recognize, so that the chip component can be mounted on the mounting substrate with higher accuracy.
(B6) Any of B1 to B5, wherein the element includes a plurality of element elements, and further includes a plurality of fuses provided on the substrate and detachably connected to the external connection electrodes. The chip component according to claim 1.
(B7) The chip component according to B6, wherein the element element is a resistor including a resistor film formed on the substrate and a wiring film laminated so as to be in contact with the resistor film.

According to this configuration, the chip component becomes a chip resistor, and the chip resistor can easily and quickly respond to a plurality of types of resistance values by selecting and cutting one or a plurality of fuses. it can. In other words, chip resistors having various resistance values can be realized with a common design by combining a plurality of resistors having different resistance values.
(B8) The chip component according to B6, wherein the element element is a capacitor element having a capacitive film formed on the substrate and an electrode film in contact with the capacitive film.

According to this configuration, the chip component becomes a chip capacitor, and the chip capacitor can easily and quickly cope with a plurality of types of capacitance values by selecting and cutting one or a plurality of fuses. In other words, chip capacitors having various capacitance values can be realized by a common design by combining a plurality of capacitor elements having different capacitance values.
(B9) The chip component may be a chip inductor.
(B10) The chip component may be a chip diode.
(B11) forming an element on the surface of the substrate; forming an external connection electrode on the surface of the substrate; A method for manufacturing a chip component, comprising:

According to this method, in the completed chip component, one of the front edge and the rear edge of the substrate protrudes outward from the substrate rather than the other. Therefore, since the corner part (corner part) of the chip part does not become a right angle, chipping at the corner part (particularly an obtuse corner part) can be reduced. In this case, the outline of the chip component when the image is recognized from the front surface side or the back surface side of the substrate is either the front edge or the back edge of the substrate (the edge protruding outward from the substrate). It is made up of only clear. Therefore, since the outline of the chip component can be correctly recognized, the chip component can be mounted on the mounting substrate with high accuracy. That is, it is possible to improve the mounting position accuracy.
(B12) A step of forming elements and external connection electrodes in a plurality of chip component regions set on the surface of the substrate, respectively, and a boundary region between the plurality of chip component regions having a predetermined depth from the surface of the substrate. And forming a groove defined by a side wall having a portion inclined with respect to a plane perpendicular to the surface of the substrate, and grinding the back surface of the substrate until it reaches the groove, whereby a plurality of the substrates are formed. And a step of dividing the chip part into chip parts.

According to this method, in the step of forming the groove, the side surfaces of the substrate in the plurality of chip components can be shaped at a time so as to have a portion inclined with respect to a plane perpendicular to the surface of the substrate. Also, by grinding the back surface of the substrate until it reaches the groove, a plurality of chip component pieces can be obtained from the substrate at a time. Therefore, it is possible to shorten the manufacturing time of a plurality of chip parts.
(B13) The method of manufacturing a chip component according to B11 or B12, including a step of shaping the side surface of the substrate so as to be a plane along a plane inclined with respect to a plane perpendicular to the surface of the substrate.

According to this method, in the chip component, one of the front surface edge and the back surface edge of the substrate can be reliably projected outward from the other than the other.
(B14) The method of manufacturing a chip part according to any one of B11 to B13, including a step of retracting an edge of the back surface of the substrate inward of the substrate with respect to an edge of the surface of the substrate.
According to this method, in the chip component, since the corner portion on the back surface of the substrate has an obtuse angle, chipping at the corner portion can be reduced.
(B15) The method of manufacturing a chip component according to any one of B11 to B13, including a step of projecting an edge of the back surface of the substrate outward from the edge of the surface of the substrate. .

According to this method, in the chip component, the corner portion on the surface of the substrate has an obtuse angle, so that chipping at the corner portion can be reduced.
(B16) The method of manufacturing a chip part according to any one of B11 to B15, wherein the surface of the substrate and the side surface of the substrate form an acute angle.
According to this method, since the edge of the surface of the substrate stands out, the outline of the chip component becomes clearer and easier to recognize, so that the chip component can be mounted on the mounting substrate with higher accuracy (higher mounting position accuracy). Can be improved).
(B17) Any of B11 to B16, wherein the element includes a plurality of element elements, and includes a step of providing a plurality of fuses that connect the plurality of element elements to the external connection electrodes in a severable manner on the substrate. A method for manufacturing a chip part according to claim 1.
(B18) The chip component manufacturing method according to B17, wherein the element element is a resistor including a resistor film formed on the substrate and a wiring film laminated so as to be in contact with the resistor film. .

According to this method, the chip component becomes a chip resistor, and the chip resistor can easily and quickly respond to a plurality of types of resistance values by selecting and cutting one or a plurality of fuses. it can. In other words, chip resistors having various resistance values can be realized with a common design by combining a plurality of resistors having different resistance values.
(B19) The method for manufacturing a chip component according to B17, wherein the element element is a capacitor element having a capacitive film formed on the substrate and an electrode film in contact with the capacitive film.

According to this method, the chip component becomes a chip capacitor, and the chip capacitor can easily and quickly respond to a plurality of types of capacitance values by selecting and cutting one or a plurality of fuses. In other words, chip capacitors having various capacitance values can be realized by a common design by combining a plurality of capacitor elements having different capacitance values.
(2) Embodiment of Invention According to Second Reference Example Hereinafter, an embodiment of a second reference example will be described in detail with reference to the accompanying drawings. In addition, the code | symbol shown in FIGS. 41-63 is effective only in these drawings, and even if it is used for other embodiment, it does not show the same element as the code | symbol of the said other embodiment.

FIG. 41A is a schematic perspective view for explaining the configuration of the chip resistor according to the embodiment of the second reference example, and FIG. 41B is a diagram illustrating the chip resistor mounted on the mounting substrate. It is a typical side view which shows the state made.
This chip resistor b1 is a minute chip component and has a rectangular parallelepiped shape as shown in FIG. The planar shape of the chip resistor b1 is a rectangle having two orthogonal sides (long side b81, short side b82) of 0.4 mm or less and 0.2 mm or less, respectively. Preferably, regarding the dimensions of the chip resistor b1, the length L (the length of the long side b81) is about 0.3 mm, the width W (the length of the short side b82) is about 0.15 mm, and the thickness T is about 0.1 mm.

The chip resistor b1 is formed by forming a plurality of chip resistors b1 in a lattice shape on a substrate, forming grooves in the substrate, and then polishing the back surface (or dividing the substrate by the grooves) to obtain individual chips. It is obtained by separating the resistor b1.
The chip resistor b1 includes a substrate b2 constituting a main body (resistor main body) of the chip resistor b1, a first connection electrode b3 and a second connection electrode b4 that serve as external connection electrodes, a first connection electrode b3, and a second connection electrode. It mainly includes an element b5 externally connected by a connection electrode b4.

  The substrate b2 has a substantially rectangular parallelepiped chip shape. In the substrate b2, the upper surface in FIG. 41A is the surface b2A. The surface b2A is a surface (element formation surface) on which the element b5 is formed on the substrate b2, and has a substantially rectangular shape. The surface opposite to the front surface b2A in the thickness direction of the substrate b2 is a back surface b2B. The front surface b2A and the back surface b2B have substantially the same shape and are parallel to each other. However, the front surface b2A is larger than the back surface b2B. Therefore, the back surface b2B fits inside the surface b2A in a plan view viewed from the direction orthogonal to the surface b2A. The rectangular edge defined by the pair of long sides b81 and short side b82 on the front surface b2A is referred to as an edge b85, and the rectangular edge defined by the pair of long sides b81 and short side b82 on the back surface b2B The edge b90.

In addition to the front surface b2A and the back surface b2B, the substrate b2 has a side surface b2C, a side surface b2D, a side surface b2E, and a side surface b2F that extend across these surfaces and connect these surfaces.
The side surface b2C is constructed between the short sides b82 on one side in the longitudinal direction on the front surface b2A and the back surface b2B (left front side in FIG. 41A), and the side surface b2D is on the other side in the longitudinal direction on the front surface b2A and the back surface b2B ( It is constructed between the short sides b82 on the right back side in FIG. The side surface b2C and the side surface b2D are both end surfaces of the substrate b2 in the longitudinal direction. The side surface b2E is constructed between the long sides b81 on one side in the short direction of the front surface b2A and the back surface b2B (the left back side in FIG. 41A), and the side surface b2F is the short direction of the front surface b2A and the back surface b2B. It is constructed between the long sides b81 on the other side (the right front side in FIG. 41A). The side surface b2E and the side surface b2F are both end surfaces of the substrate b2 in the lateral direction. Each of the side surface b2C and the side surface b2D intersects (substantially orthogonal) with each of the side surface b2E and the side surface b2F. As described above, since the front surface b2A is larger than the rear surface b2B, each of the side surfaces b2C to b2F has an isosceles trapezoidal shape having an upper bottom on the rear surface b2B side and a lower bottom on the front surface b2A side. That is, the side shape of the chip resistor b1 is an isosceles trapezoid. Therefore, adjacent ones of the surface b2A to the side surface b2F form an acute angle or an obtuse angle. Specifically, the surface b2A and each of the side surface b2C, the side surface b2D, the side surface b2E, and the side surface b2F are acute angles, and the back surface b2B and each of the side surface b2C, the side surface b2D, the side surface b2E, and the side surface b2F are obtuse angles. It is done. For convenience of explanation, in each figure after FIG. 41, each of the side faces b2C to b2F is shown inclined (exaggerated) from the actual side.

  In the substrate b2, the entire surface b2A and side surfaces b2C to b2F are covered with the insulating film b23. Therefore, strictly speaking, in FIG. 41A, the entire areas of the surface b2A and the side surfaces b2C to b2F are located on the inner side (back side) of the insulating film b23 and are not exposed to the outside. Further, the chip resistor b1 has a resin film b24. The resin film b24 includes a first resin film b24A and a second resin film b24B different from the first resin film b24A. The first resin film b24A is formed in regions slightly apart from the edge b85 of the surface b2A to the back surface b2B side in each of the side surface b2C, the side surface b2D, the side surface b2E, and the side surface b2F. The second resin film b24B covers a portion of the insulating film b23 on the surface b2A that does not overlap with the edge b85 of the surface b2A (an inner region of the edge b85). The insulating film b23 and the resin film b24 will be described in detail later.

  The first connection electrode b3 and the second connection electrode b4 are formed in a region inside the edge b85 on the surface b2A of the substrate b2, and are partially exposed from the second resin film b24B on the surface b2A. Yes. In other words, the second resin film b24B covers the surface b2A (strictly, the insulating film b23 on the surface b2A) so as to expose the first connection electrode b3 and the second connection electrode b4. Each of the first connection electrode b3 and the second connection electrode b4 is configured by, for example, stacking Ni (nickel), Pd (palladium), and Au (gold) on the surface b2A in this order. The first connection electrode b3 and the second connection electrode b4 are arranged at intervals in the longitudinal direction of the surface b2A, and are long in the short direction of the surface b2A. In FIG. 41A, on the surface b2A, the first connection electrode b3 is provided near the side surface b2C, and the second connection electrode b4 is provided near the side surface b2D.

  The element b5 is a circuit element, and is formed in a region between the first connection electrode b3 and the second connection electrode b4 on the surface b2A of the substrate b2, and from above by the insulating film b23 and the second resin film b24B. It is covered. The element b5 constitutes the resistor body described above. The element b5 in this embodiment is a resistor b56. The resistor b56 is configured by a circuit network in which a plurality of (unit) resistors R having equal resistance values are arranged in a matrix on the surface b2A. The resistor R is made of TiN (titanium nitride), TiON (titanium oxynitride) or TiSiON. The element b5 is electrically connected to a wiring film b22, which will be described later, and is electrically connected to the first connection electrode b3 and the second connection electrode b4 via the wiring film b22.

  As shown in FIG. 41 (b), the first connection electrode b3 and the second connection electrode b4 are opposed to the mounting substrate b9, and electrical and mechanical to the circuit (not shown) of the mounting substrate b9 by the solder b13. Thus, the chip resistor b1 can be mounted on the mounting substrate b9 (flip chip connection). The first connection electrode b3 and the second connection electrode b4 that function as external connection electrodes are formed of gold (Au) or gold-plated on the surface in order to improve solder wettability and reliability. It is desirable.

FIG. 42 is a plan view of the chip resistor, showing the arrangement relationship between the first connection electrode, the second connection electrode and the element, and the configuration (layout pattern) of the element in plan view.
Referring to FIG. 42, element b5 is a resistor network. Specifically, the element b5 includes eight resistors R arranged along the row direction (longitudinal direction of the substrate b2) and 44 resistors arranged along the column direction (width direction of the substrate b2). It has a total of 352 resistors R composed of the body R. These resistors R are a plurality of element elements that constitute a resistance network of the element b5.

  A plurality of types of resistor circuits R are formed by grouping and electrically connecting a large number of these resistors R every predetermined number of 1 to 64. The formed plurality of types of resistance circuits are connected in a predetermined manner by a conductor film D (a wiring film formed of a conductor). Furthermore, a plurality of fuses (fuses) that can be cut (fused) on the surface b2A of the substrate b2 in order to electrically incorporate a resistance circuit with respect to the element b5 or to electrically separate it from the element b5. F is provided. The plurality of fuses F and the conductor film D are arranged along the inner side of the second connection electrode b3 so that the arrangement region is linear. More specifically, the plurality of fuses F and the conductor film D are arranged so as to be adjacent to each other, and the arrangement direction thereof is linear. The plurality of fuses F connect a plurality of types of resistor circuits (a plurality of resistors R for each resistor circuit) to the second connection electrode b3 so as to be cut (separable). The plurality of fuses F and the conductor film D constitute the resistor body described above.

FIG. 43A is an enlarged plan view of a part of the element shown in FIG. FIG. 43B is a longitudinal sectional view in the length direction along BB of FIG. 43A drawn to explain the configuration of the resistor in the element. FIG. 43C is a longitudinal sectional view in the width direction along CC of FIG. 43A drawn to explain the configuration of the resistor in the element.
The configuration of the resistor R will be described with reference to FIGS. 43A, 43B, and 43C.

The chip resistor b1 further includes an insulating layer b20 and a resistor film b21 in addition to the wiring film b22, the insulating film b23, and the resin film b24 described above (see FIGS. 43B and 43C). The insulating layer b20, the resistor film b21, the wiring film b22, the insulating film b23, and the resin film b24 are formed on the substrate b2 (surface b2A).
The insulating layer b20 is made of SiO ₂ (silicon oxide). The insulating layer b20 covers the entire surface b2A of the substrate b2. The insulating layer b20 has a thickness of about 10,000 mm.

  The resistor film b21 is formed on the insulating layer b20. The resistor film b21 is formed of TiN, TiON, or TiSiON. The thickness of the resistor film b21 is about 2000 mm. The resistor film b21 constitutes a plurality of resistor films (hereinafter referred to as “resistor film line b21A”) extending linearly in parallel between the first connection electrode b3 and the second connection electrode b4. The resistor film line b21A may be cut at a predetermined position in the line direction (see FIG. 43A).

  A wiring film b22 is stacked on the resistor film line b21A. The wiring film b22 is made of Al (aluminum) or an alloy of aluminum and Cu (copper) (AlCu alloy). The thickness of the wiring film b22 is about 8000 mm. The wiring film b22 is laminated on the resistor film line b21A with a constant interval R in the line direction, and is in contact with the resistor film line b21A.

The electrical characteristics of the resistor film line b21A and the wiring film b22 having this configuration are shown by circuit symbols as shown in FIG. That is, as shown in FIG. 44A, each portion of the resistor film line b21A in the region of the predetermined interval R forms one resistor R having a constant resistance value r.
In the region where the wiring film b22 is laminated, the resistor film line b21A is short-circuited by the wiring film b22 by electrically connecting the resistors R adjacent to each other. Therefore, a resistance circuit is formed which is formed by connecting in series the resistor R of the resistor r shown in FIG.

  Further, since the adjacent resistor film lines b21A are connected by the resistor film b21 and the wiring film b22, the resistor network of the element b5 shown in FIG. 43A is shown in FIG. A resistor circuit (consisting of R unit resistors) is formed. As described above, the resistor film b21 and the wiring film b22 constitute the resistor R and the resistor circuit (that is, the element b5). Each resistor R includes a resistor film line b21A (resistor film b21) and a plurality of wiring films b22 stacked on the resistor film line b21A at a predetermined interval in the line direction. A resistor film line b21A at a constant interval R where b22 is not stacked constitutes one resistor R. The resistor film lines b <b> 21 </ b> A in the portion constituting the resistor R are all equal in shape and size. Therefore, the multiple resistors R arranged in a matrix on the substrate b2 have the same resistance value.

The wiring film b22 laminated on the resistor film line b21A forms a resistor R and also serves as a conductor film D for connecting a plurality of resistors R to form a resistor circuit. (See FIG. 42).
45 (a) is a partially enlarged plan view of a region including a fuse drawn by enlarging a part of the plan view of the chip resistor shown in FIG. 42, and FIG. 45 (b) is a diagram of FIG. 45 (a). It is a figure which shows the cross-sectional structure which follows BB.

  As shown in FIGS. 45A and 45B, the above-described fuse F and conductor film D are also formed by the wiring film b22 laminated on the resistor film b21 forming the resistor R. That is, the fuse F and the conductor film D are formed on the same layer as the wiring film b22 laminated on the resistor film line b21A forming the resistor R by Al or AlCu alloy which is the same metal material as the wiring film b22. Yes. As described above, the wiring film b22 is also used as the conductor film D that electrically connects the plurality of resistors R in order to form a resistance circuit.

  That is, in the same layer laminated on the resistor film b21, the wiring film for forming the resistor R, the fuse F, the conductor film D, and the element b5 are connected to the first connection electrode b3 and the second connection film b2. A wiring film for connection to the connection electrode b4 is formed using the same metal material (Al or AlCu alloy) as the wiring film b22. Note that the fuse F is different from the wiring film b22 (differentiated) because the fuse F is formed so as to be easily cut and no other circuit elements exist around the fuse F. This is because they are arranged in such a manner.

  Here, in the wiring film b22, a region where the fuse F is arranged is referred to as a trimming target region X (see FIGS. 42 and 45A). The trimming target region X is a linear region along the inner side of the second connection electrode b3. In the trimming target region X, not only the fuse F but also the conductor film D is disposed. In addition, a resistor film b21 is also formed below the wiring film b22 in the trimming target region X (see FIG. 45B). The fuse F is a wiring having a larger inter-wiring distance (separated from the surroundings) than the portion other than the trimming target region X in the wiring film b22.

The fuse F indicates not only a part of the wiring film b22 but also a group (fuse element) of a part of the resistor R (resistor film b21) and a part of the wiring film b22 on the resistor film b21. It may be.
Further, the fuse F has been described only in the case where the same layer as the conductor film D is used. However, in the conductor film D, another conductor film is further laminated thereon to lower the resistance value of the entire conductor film D. You may do it. Even in this case, if a conductive film is not laminated on the fuse F, the fusing property of the fuse F will not deteriorate.

FIG. 46 is an electric circuit diagram of an element according to the embodiment of the second reference example.
Referring to FIG. 46, element b5 includes reference resistance circuit R8, resistance circuit R64, two resistance circuits R32, resistance circuit R16, resistance circuit R8, resistance circuit R4, resistance circuit R2, resistance circuit R1, and resistance circuit R. / 2, resistor circuit R / 4, resistor circuit R / 8, resistor circuit R / 16, resistor circuit R / 32 are connected in series from the first connection electrode b3 in this order. Each of the reference resistor circuit R8 and the resistor circuits R64 to R2 is configured by connecting in series the same number of resistors R as the last number (“64” in the case of R64). The resistor circuit R1 is composed of one resistor R. Each of the resistance circuits R / 2 to R / 32 is configured by connecting in parallel the same number of resistors R as the last number of itself (“32” in the case of R / 32). The meaning of the number at the end of the resistor circuit is the same in FIGS. 47 and 48 described later.

One fuse F is connected in parallel to each of the resistor circuits R64 to R / 32 other than the reference resistor circuit R8. The fuses F are connected in series either directly or via a conductor film D (see FIG. 45A).
As shown in FIG. 46, in a state where all the fuses F are not blown, the element b5 is a reference composed of a series connection of eight resistors R provided between the first connection electrode b3 and the second connection electrode b4. A resistor circuit of the resistor circuit R8 is configured. For example, if the resistance value r of one resistor R is r = 8Ω, the chip resistor in which the first connection electrode b3 and the second connection electrode b4 are connected by a resistance circuit (reference resistance circuit R8) of 8r = 64Ω. A container b1 is configured.

  Further, in a state where all the fuses F are not blown, a plurality of types of resistor circuits other than the reference resistor circuit R8 are short-circuited. That is, 12 types and 13 resistor circuits R64 to R / 32 are connected in series to the reference resistor circuit R8, but each resistor circuit is short-circuited by the fuse F connected in parallel. From an electrical viewpoint, each resistance circuit is not incorporated in the element b5.

  In the chip resistor b1 according to this embodiment, the fuse F is selectively blown by, for example, laser light according to a required resistance value. Thereby, the resistance circuit in which the fuse F connected in parallel is blown is incorporated in the element b5. Therefore, the entire resistance value of the element b5 can be set to a resistance value in which resistance circuits corresponding to the fused fuse F are connected in series.

  In particular, a plurality of types of resistor circuits have one, two, four, eight, sixteen, thirty-two, etc. resistors R having the same resistance value in series, and a geometric sequence having a common ratio of two. The number of resistors R is increased, and a plurality of types of series resistor circuits and resistors R having the same resistance value are connected in parallel to 2, 4, 8, 16,. A plurality of types of parallel resistance circuits are provided which are connected by increasing the number of resistors R in a geometric sequence. Therefore, by selectively fusing the fuse F (including the above-described fuse element), the resistance value of the entire element b5 (resistor b56) is adjusted finely and digitally to an arbitrary resistance value. Thus, a resistor having a desired value can be generated in the chip resistor b1.

FIG. 47 is an electric circuit diagram of an element according to another embodiment of the second reference example.
Instead of configuring the element b5 by connecting the reference resistor circuit R8 and the resistor circuits R64 to R / 32 in series as shown in FIG. 46, the element b5 may be configured as shown in FIG. Specifically, between the first connection electrode b3 and the second connection electrode b4, the reference resistance circuit R / 16 and 12 types of resistance circuits R / 16, R / 8, R / 4, R / 2, R1, R2 , R4, R8, R16, R32, R64, R128 may be configured by a series connection circuit with a parallel connection circuit.

  In this case, a fuse F is connected in series to each of the 12 types of resistor circuits other than the reference resistor circuit R / 16. In a state where all the fuses F are not blown, each resistance circuit is electrically incorporated into the element b5. If the fuse F is selectively blown by, for example, a laser beam according to the required resistance value, the resistance circuit corresponding to the blown fuse F (the resistance circuit in which the fuse F is connected in series) is the element b5. Therefore, the resistance value of the entire chip resistor b1 can be adjusted.

FIG. 48 is an electric circuit diagram of an element according to still another embodiment of the second reference example.
A feature of the element b5 shown in FIG. 48 is that a circuit configuration in which a series connection of a plurality of types of resistance circuits and a parallel connection of a plurality of types of resistance circuits are connected in series. As in the previous embodiment, fuses F are connected in parallel to each of the plurality of resistor circuits connected in series, and the plurality of resistor circuits connected in series are all short-circuited by the fuse F. It is in a state. Therefore, when the fuse F is blown, the resistance circuit short-circuited by the blown fuse F is electrically incorporated into the element b5.

On the other hand, a fuse F is connected in series to each of the plurality of types of resistor circuits connected in parallel. Therefore, by blowing the fuse F, the resistor circuit to which the blown fuse F is connected in series can be electrically disconnected from the parallel connection of the resistor circuit.
With this configuration, for example, a small resistance of 1 kΩ or less is made on the parallel connection side, and if a resistance circuit of 1 kΩ or more is made on the series connection side, a wide range from a small resistance of several Ω to a large resistance of several MΩ is obtained. Resistor circuits can be made using a network of resistors constructed with an equal basic design. That is, in the chip resistor b1, by selecting and cutting one or a plurality of fuses F, it is possible to easily and quickly cope with a plurality of types of resistance values. In other words, by combining a plurality of resistors R having different resistance values, chip resistors b1 having various resistance values can be realized with a common design.

As described above, in the chip resistor b1, in the trimming target region X, the connection state of the plurality of resistors R (resistance circuit) can be changed.
FIG. 49 is a schematic cross-sectional view of a chip resistor.
Next, the chip resistor b1 will be described in more detail with reference to FIG. For convenience of explanation, in FIG. 49, the element b5 described above is simplified and each element other than the substrate b2 is hatched.

Here, the insulating film b23 and the resin film b24 described above will be described.
The insulating film b23 is made of, for example, SiN (silicon nitride), and has a thickness of 1000 to 5000 mm (here, about 3000 mm). The insulating film b23 is provided over the entire area of the surface b2A and the side surfaces b2C to b2F. The insulating film b23 on the surface b2A covers the resistor film b21 and each wiring film b22 (that is, the element b5) on the resistor film b21 from the surface (upper side in FIG. 49), and each resistor in the element b5. The upper surface of R is covered. Therefore, the insulating film b23 also covers the wiring film b22 in the trimming target region X described above (see FIG. 45B). The insulating film b23 is in contact with the element b5 (the wiring film b22 and the resistor film b21), and is also in contact with the insulating layer b20 in a region other than the resistor film b21. Accordingly, the insulating film b23 on the surface b2A functions as a protective film that covers the entire surface b2A and protects the element b5 and the insulating layer b20. On the surface b2A, the insulating film b23 prevents a short circuit between the resistors R other than the wiring film b22 (short circuit between adjacent resistor film lines b21A).

  On the other hand, the insulating film b23 provided on each of the side surfaces b2C to b2F functions as a protective layer that protects each of the side surfaces b2C to b2F. The boundary between each of the side surfaces b2C to b2F and the surface b2A is the aforementioned edge b85, but the insulating film b23 also covers the boundary (edge b85). In the insulating film b23, a portion covering the edge b85 (a portion overlapping the edge b85) is referred to as an end b23A.

The resin film b24 protects the surface b2A of the chip resistor b1 together with the insulating film b23, and is made of a resin such as polyimide. The thickness of the resin film b24 is about 5 μm.
As described above, the resin film b24 includes the first resin film b24A and the second resin film b24B.
The first resin film b24A covers a part of the side surfaces b2C to b2F that is slightly separated from the edge b85 (end b23A of the insulating film b23) toward the back surface b2B. Specifically, the first resin film b24A is formed in each of the side surfaces b2C to b2F in a region having a gap K from the edge b85 of the surface b2A to the back surface b2B side. However, the first resin film b24A is arranged to be biased toward the front surface b2A rather than the back surface b2B. The first resin films b24A on the side surfaces b2C and b2D extend in a streak pattern along the short side b82, and are formed over the entire region in the direction of the short side b82 (see FIG. 41A). The first resin films b24A on the side surfaces b2E and b2F extend in a streak shape along the long side b81 and are formed over the entire region in the direction of the long side b81 (see FIG. 41A). The first resin film b24A on each of the side surfaces b2C to b2F projects outward from the edge (edge b85) of the surface b2A. Specifically, the first resin film b24A bulges outward in an arc shape from the edge b85 in the direction along the surface b2A. Therefore, the first resin film b24A forms the outline of the chip resistor b1 in plan view.

  The second resin film b24B covers substantially the entire surface of the insulating film b23 on the surface b2A (including the resistor film b21 and the wiring film b22 covered with the insulating film b23). Specifically, the second resin film b24B is formed away from the end b23A so as not to cover the end b23A (the edge b85 of the surface b2A) of the insulating film b23. Therefore, the first resin film b24A and the second resin film b24B are not continuous and are interrupted at the end b23A (the entire area of the edge b85). As a result, the end b23A (the entire area of the edge b85) of the insulating film b23 is exposed to the outside.

  In the second resin film b24B, one opening b25 is formed at two positions apart in plan view. Each opening b25 is a through hole that continuously penetrates the second resin film b24B and the insulating film b23 in the respective thickness directions. Therefore, the opening b25 is formed not only in the second resin film b24B but also in the insulating film b23. A part of the wiring film b22 is exposed from each opening b25. A portion of the wiring film b22 exposed from each opening b25 is a pad region b22A for external connection.

  Of the two openings b25, one opening b25 is filled with the first connection electrode b3, and the other opening b25 is filled with the second connection electrode b4. A part of each of the first connection electrode b3 and the second connection electrode b4 protrudes from the opening b25 on the surface of the second resin film b24B. The first connection electrode b3 is electrically connected to the wiring film b22 in the pad region b22A in the opening b25 through the one opening b25. The second connection electrode b4 is electrically connected to the wiring film b22 in the pad region b22A in the opening b25 through the other opening b25. Thereby, each of the first connection electrode b3 and the second connection electrode b4 is electrically connected to the element b5. Here, the wiring film b22 forms a wiring connected to each of the group of resistors R (resistor b56), the first connection electrode b3, and the second connection electrode b4.

  As described above, the second resin film b24B and the insulating film b23 in which the opening b25 is formed cover the surface b2A in a state where the first connection electrode b3 and the second connection electrode b4 are exposed from the opening b25. Therefore, electrical connection between the chip resistor b1 and the mounting substrate b9 can be achieved via the first connection electrode b3 and the second connection electrode b4 that protrude from the opening b25 on the surface of the second resin film b24B. (See FIG. 41 (b)).

  Here, in the second resin film b24B, the portion (referred to as “central portion b24C”) located between the first connection electrode b3 and the second connection electrode b4 is referred to as the first connection electrode b3 and the second connection electrode. It is higher than b4 (away from the surface b2A). That is, the central portion b24C has a surface b24D that is higher than the first connection electrode b3 and the second connection electrode b4. The surface b24D is convexly curved in a direction away from the surface b2A.

50A to 50G are schematic sectional views showing a method for manufacturing the chip resistor shown in FIG.
First, as shown in FIG. 50A, a substrate b30 as a base of the substrate b2 is prepared. In this case, the surface b30A of the substrate b30 is the surface b2A of the substrate b2, and the back surface b30B of the substrate b30 is the back surface b2B of the substrate b2.

Then, the surface b30A of the substrate b30 is thermally oxidized to form an insulating layer b20 made of SiO ₂ or the like on the surface b30A, and the element b5 (the resistor R and the wiring film b22 connected to the resistor R is formed on the insulating layer b20. ). Specifically, first, a TiN, TiON, or TiSiON resistor film b21 is formed on the entire surface of the insulating layer b20 by sputtering, and aluminum is further formed on the resistor film b21 so as to be in contact with the resistor film b21. A (Al) wiring film b22 is laminated. Thereafter, using a photolithography process, the resistor film b21 and the wiring film b22 are selectively removed and patterned by dry etching such as RIE (Reactive Ion Etching), for example, as shown in FIG. In a plan view, a configuration is obtained in which resistor film lines b21A having a certain width on which the resistor films b21 are stacked are arranged in the column direction with a certain interval. At this time, a region in which the resistor film line b21A and the wiring film b22 are partially cut is formed, and the fuse F and the conductor film D are formed in the trimming target region X (see FIG. 42). Subsequently, the wiring film b22 laminated on the resistor film line b21A is selectively removed by wet etching, for example. As a result, an element b5 having a configuration in which the wiring film b22 is laminated with a predetermined interval R on the resistor film line b21A is obtained. At this time, in order to ascertain whether or not the resistor film b21 and the wiring film b22 are formed with target dimensions, the resistance value of the entire element b5 may be measured.

  Referring to FIG. 50A, the element b5 is formed at a number of locations on the surface b30A of the substrate b30 according to the number of chip resistors b1 formed on one substrate b30. When one region where the element b5 (the resistor b56 described above) is formed on the substrate b30 is referred to as a chip component region Y (or a chip resistor region Y), a plurality of chips each having a resistor b56 are provided on the surface b30A of the substrate b30. The component region Y (that is, the element b5) is formed (set). One chip component region Y coincides with a plan view of one completed chip resistor b1 (see FIG. 49). A region between adjacent chip component regions Y on the surface b30A of the substrate b30 is referred to as a boundary region Z. The boundary region Z has a belt shape and extends in a lattice shape in plan view. One chip component region Y is arranged in one lattice defined by the boundary region Z. Since the width of the boundary region Z is as extremely narrow as 1 μm to 60 μm (for example, 20 μm), many chip component regions Y can be secured on the substrate b30, and as a result, mass production of the chip resistors b1 becomes possible.

  Next, as shown in FIG. 50A, an insulating film b45 made of SiN is formed over the entire surface b30A of the substrate b30 by a CVD (Chemical Vapor Deposition) method. The insulating film b45 covers and contacts all of the insulating layer b20 and the element b5 (resistor film b21 and wiring film b22) on the insulating layer b20. Therefore, the insulating film b45 also covers the wiring film b22 in the trimming target region X (see FIG. 42) described above. In addition, since the insulating film b45 is formed over the entire surface b30A of the substrate b30, the insulating film b45 is formed to extend to a region other than the trimming target region X on the surface b30A. Thereby, the insulating film b45 becomes a protective film for protecting the entire surface b30A (including the element b5 on the surface b30A).

Next, as shown in FIG. 50B, a resist pattern b41 is formed over the entire surface b30A of the substrate b30 so as to cover the entire insulating film b45. An opening b42 is formed in the resist pattern b41.
FIG. 51 is a schematic plan view of a part of a resist pattern used for forming a groove in the step of FIG. 50B.

  Referring to FIG. 51, the opening b42 of the resist pattern b41 is a plan view when a large number of chip resistors b1 (in other words, the above-described chip component region Y) are arranged in a matrix (also in a lattice shape). It corresponds (corresponds) to the region between the outlines of the adjacent chip resistors b1 (the hatched portion in FIG. 51, in other words, the boundary region Z). Therefore, the overall shape of the opening b42 is a lattice shape having a plurality of linear portions b42A and b42B orthogonal to each other.

In the resist pattern b41, the straight portions b42A and b42B orthogonal to each other in the opening b42 are connected to each other while maintaining a state orthogonal to each other (without being bent). Therefore, the intersecting portion b43 of the straight portions b42A and b42B is pointed so as to form approximately 90 ° in a plan view.
Referring to FIG. 50B, each of insulating film b45, insulating layer b20, and substrate b30 is selectively removed by plasma etching using resist pattern b41 as a mask. As a result, the material of the substrate b30 is removed in the boundary region Z between the adjacent elements b5 (chip component region Y). As a result, the position (boundary region Z) coinciding with the opening b42 of the resist pattern b41 in plan view reaches the middle of the thickness of the substrate b30 from the surface b30A of the substrate b30 through the insulating film b45 and the insulating layer b20. A groove b44 having a predetermined depth is formed. The groove b44 is partitioned by a pair of side walls b44A facing each other and a bottom wall b44B connecting the lower ends of the pair of side walls b44A (the end on the back surface b30B side of the substrate b30). The depth of the groove b44 with respect to the surface b30A of the substrate b30 is about 100 μm, and the width of the groove b44 (the interval between the opposing side walls b44A) is around 20 μm. However, the width of the groove b44 increases as it approaches the bottom wall b44B. Therefore, the side surface (section screen b44C) that partitions the groove b44 in each side wall b44A is inclined with respect to the plane H perpendicular to the surface b30A of the substrate b30.

  The overall shape of the groove b44 in the substrate b30 is a lattice shape that coincides with the opening b42 (see FIG. 51) of the resist pattern b41 in plan view. Then, on the surface b30A of the substrate b30, a rectangular frame portion (boundary region Z) in the groove b44 surrounds the chip component region Y where each element b5 is formed. The portion where the element b5 is formed on the substrate b30 is a semi-finished product b50 of the chip resistor b1. On the surface b30A of the substrate b30, the semi-finished products b50 are located one by one in the chip component region Y surrounded by the groove b44, and these semi-finished products b50 are arranged in a matrix. By forming the groove b44 in this way, the substrate b30 is separated into the substrate b2 (the resistor main body described above) for each of the plurality of chip component regions Y.

  After the groove b44 is formed as shown in FIG. 50B, the resist pattern b41 is removed, and the insulating film b45 is selectively removed by etching using the mask b65 as shown in FIG. 50C. In the mask b65, an opening b66 is formed in a portion of the insulating film b45 that coincides with each pad region b22A (see FIG. 49) in plan view. Thus, the portion of the insulating film b45 that coincides with the opening b66 is removed by etching, and the opening b25 is formed in the portion. As a result, the insulating film b45 is formed so as to expose each pad region b22A in the opening b25. Two openings b25 are formed for one semi-finished product b50.

  In each semi-finished product b50, after the two openings b25 are formed in the insulating film b45, the probe b70 of the resistance measuring device (not shown) is brought into contact with the pad region b22A of each opening b25, so that the entire resistance value of the element b5 is obtained. Is detected. Then, by irradiating a laser beam (not shown) through the insulating film b45 to an arbitrary fuse F (see FIG. 42), the wiring film b22 in the trimming target region X is trimmed with the laser beam, and the fuse F is melted. In this way, by fusing (trimming) the fuse F so as to have a required resistance value, the resistance value of the entire semi-finished product b50 (in other words, the chip resistor b1) can be adjusted as described above. At this time, since the insulating film b45 is a cover film that covers the element b5, it is possible to prevent a short circuit from occurring due to debris or the like generated at the time of fusing attached to the element b5. Further, since the insulating film b45 covers the fuse F (resistor film b21), the energy of the laser beam can be stored in the fuse F and the fuse F can be surely blown.

  Thereafter, SiN is formed on the insulating film b45 by the CVD method, and the insulating film b45 is thickened. At this time, as shown in FIG. 50D, the insulating film b45 is also formed over the entire inner peripheral surface of the groove b44 (the section screen b44C of the side wall b44A and the upper surface of the bottom wall b44B). The final insulating film b45 (the state shown in FIG. 50D) has a thickness of 1000 to 5000 mm (here, about 3000 mm). At this time, a part of the insulating film b45 enters each opening b25 and closes the opening b25.

  Thereafter, a photosensitive resin liquid made of polyimide is spray-applied onto the substrate b30 from above the insulating film b45 to form a photosensitive resin coating film b46 as shown in FIG. 50D. The liquid photosensitive resin cannot flow and flows at the entrance of the groove b44 (a portion corresponding to the end b23A of the insulating film b23 or the edge b85 of the substrate b2). Therefore, the liquid photosensitive resin is a region on the back surface b30B side (bottom wall b44B side) of the side surface b30A of the substrate b30 on the side wall b44A (division screen b44C) of the groove b44 and the end of the insulating film b23 on the surface b30A. It adheres to the area | region remove | deviated from b23A, and becomes a coating film b46 (resin film) in each area | region. The coating film b46 on the surface b30A has a shape that is convexly curved upward due to surface tension.

The coating film b46 formed on the side wall b44A of the groove b44 only covers a part of the side wall b44A of the groove b44 on the element b5 side (surface b30A side). It has not reached b44B. Therefore, the groove b44 is not blocked by the coating film b46.
Next, the coating film b46 is subjected to heat treatment (curing treatment). As a result, the thickness of the coating film b46 is thermally contracted, and the coating film b46 is cured to stabilize the film quality.

  Next, as shown in FIG. 50E, the coating film b46 is patterned, and portions of the coating film b46 on the surface b30A that coincide with the pad regions b22A (openings b25) of the wiring film b22 in plan view are selectively removed. Specifically, the coating film b46 is exposed and developed with the pattern using the mask b62 in which the opening b61 having a pattern that matches (matches) with each pad region b22A in plan view. Thereby, the coating film b46 is separated above each pad region b22A. Next, the insulating film b45 on each pad region b22A is removed by RIE using a mask (not shown), whereby each opening b25 is opened and the pad region b22A is exposed.

  Next, a Ni / Pd / Au laminated film formed by laminating Ni, Pd, and Au is formed on the pad region b22A in each opening b25 by electroless plating. At this time, the Ni / Pd / Au laminated film protrudes from the opening b25 to the surface of the coating film b46. Thereby, the Ni / Pd / Au laminated film in each opening b25 becomes the first connection electrode b3 and the second connection electrode b4 shown in FIG. 50F. Note that the upper surfaces of the first connection electrode b3 and the second connection electrode b4 are at positions below the upper end of the coating film b46 that is convexly curved on the surface b30A.

Next, after conducting an energization inspection between the first connection electrode b3 and the second connection electrode b4, the substrate b30 is ground from the back surface b30B.
Specifically, after forming the groove b44, as shown in FIG. 50G, a support tape b71 having a thin plate shape made of PET (polyethylene terephthalate) and having an adhesive surface b72 is formed on each of the semi-finished products b50 on the adhesive surface b72. Are attached to the first connection electrode b3 and the second connection electrode b4 side (that is, the surface b30A). Thereby, each semi-finished product b50 is supported by the support tape b71. Here, for example, a laminate tape can be used as the support tape b71.

  With each semi-finished product b50 supported by the support tape b71, the substrate b30 is ground from the back surface b30B side. When the substrate b30 is thinned by grinding until it reaches the upper surface of the bottom wall b44B (see FIG. 50F) of the groove b44, there is no connection between the adjacent semi-finished products b50, so the substrate b30 is divided with the groove b44 as a boundary. Then, the semi-finished product b50 is individually separated to be a finished product of the chip resistor b1. That is, the substrate b30 is cut (divided) in the groove b44 (in other words, the boundary region Z), and thereby the individual chip resistors b1 are cut out. The chip resistor b1 may be cut out by etching the substrate b30 from the back surface b30B side to the bottom wall b44B of the groove b44.

  In each completed chip resistor b1, the portion that formed the section screen b44C of the side wall b44A of the groove b44 becomes one of the side surfaces b2C to b2F of the substrate b2, and the back surface b30B becomes the back surface b2B. That is, as described above, the step of forming the groove b44 by etching (see FIG. 50B) is included in the step of forming the side surfaces b2C to b2F. Then, in the step of forming the groove b44, a portion in which the side surface (section screen b44C) of the substrate b30 in the plurality of chip component regions Y (chip resistors b1) is inclined with respect to the plane H perpendicular to the surface b30A of the substrate b30 Can be shaped at once (see FIG. 50B). In other words, forming the groove b44 shapes the side surfaces b2C to b2F of the substrate b2 of each chip resistor b1 at a time so as to have a portion inclined with respect to the plane H.

  By forming the groove b44 by etching, the side surfaces b2C to b2F of the completed chip resistor b1 are rough surfaces having irregular patterns. Incidentally, when the groove b44 is mechanically formed with a dicing saw (not shown), a large number of streaks forming grinding marks of the dicing saw remain in a regular pattern on the side surfaces b2C to b2F. Even if the side surfaces b2C to b2F are etched, this streak cannot be completely erased.

Further, the insulating film b45 becomes the insulating film b23, and the separated coating film b46 becomes the resin film b24.
As described above, if the substrate b30 is ground from the back surface b30B side after the groove b44 is formed, a plurality of chip component regions Y formed on the substrate b30 are divided into individual chip resistors b1 (chip components) all at once. (A plurality of pieces of chip resistors b1 can be obtained at a time). Therefore, the productivity of the chip resistor b1 can be improved by shortening the manufacturing time of the plurality of chip resistors b1. Incidentally, if a substrate b30 having a diameter of 8 inches is used, about 500,000 chip resistors b1 can be cut out. When the chip resistor b1 is cut out by forming the groove b44 in the substrate b30 using only a dicing saw (not shown), the dicing saw is moved many times to form a large number of grooves b44 in the substrate b30. Therefore, the manufacturing time of the chip resistor b1 becomes long. However, if the groove b44 is formed by etching as in the second reference example, such a problem can be solved.

  That is, even if the chip size of the chip resistor b1 is small, the chip resistor b1 is separated at once by grinding the substrate b30 from the back surface b30B after the groove b44 is formed in this way. be able to. Therefore, as compared with the conventional case where the chip resistor b1 is separated into pieces by dicing the substrate b30 with a dicing saw, the cost can be reduced and the time can be shortened and the yield can be improved.

  In addition, since the groove b44 can be formed with high accuracy by etching, the accuracy of the external dimension can be improved in each chip resistor b1 divided by the groove b44. In particular, if plasma etching is used, the groove b44 can be formed with higher accuracy. Specifically, the dimensional tolerance of the chip resistor b1 when the groove b44 is formed using a general dicing saw is ± 20 μm, whereas in the second reference example, the dimensional tolerance of the chip resistor b1 Can be reduced to about ± 5 μm. Further, since the interval between the grooves b44 can be reduced according to the resist pattern b41 (see FIG. 51), the chip resistor b1 formed between the adjacent grooves b44 can be downsized. Further, in the case of etching, unlike the case of using a dicing saw, the chip resistor b1 is not cut out, so that the corner portions b11 of adjacent ones on the side surfaces b2C to b2F of the chip resistor b1 (FIG. 41 ( It is possible to reduce the occurrence of chipping in a), and to improve the appearance of the chip resistor b1.

  When each chip resistor b1 is cut out by grinding the substrate b30 from the back surface b30B side, the chip resistor b1 may be cut out earlier or later. That is, when cutting out the chip resistor b1, a slight time difference may occur between the chip resistors b1. In this case, the chip resistor b1 cut out first may vibrate left and right and come into contact with the adjacent chip resistor b1. At this time, in each chip resistor b1, since the resin film b24 (first resin film b24A) functions as a bumper, the chip resistors b1 adjacent to each other while being supported by the support tape b71 prior to singulation. Even if they collide with each other, the resin films b24 first come into contact with each other in the chip resistors b1, so that the corner b12 on the front surface b2A and back surface b2B side of the chip resistor b1 (particularly the edge b85 on the front surface b2A side). ) Can be avoided or suppressed. In particular, since the first resin film b24A projects outward from the edge b85 of the surface b2A of the chip resistor b1, the edge b85 does not come into contact with the surrounding parts, so that chipping at the edge b85 is prevented. Can be avoided or suppressed.

Note that the back surface b2B may be cleaned by polishing or etching the back surface b2B of the substrate b2 in the completed chip resistor b1.
52A to 52D are schematic cross-sectional views showing the recovery process of the chip resistor after the process of FIG. 50G.
FIG. 52A shows a state in which a plurality of chip resistors b1 that are separated into pieces continue to adhere to the support tape b71. In this state, as shown in FIG. 52B, a thermal foam sheet b73 is attached to the back surface b2B of the substrate b2 of each chip resistor b1. The thermally foamed sheet b73 includes a sheet-like sheet main body b74 and a large number of expanded particles b75 kneaded in the sheet main body b74.

  The adhesive strength of the sheet body b74 is stronger than the adhesive strength on the adhesive surface b72 of the support tape b71. Therefore, after sticking the thermal foam sheet b73 on the back surface b2B of the substrate b2 of each chip resistor b1, as shown in FIG. 52C, the support tape b71 is peeled off from each chip resistor b1, and the chip resistor b1 is removed. Transfer to the thermal foam sheet b73. At this time, if the support tape b71 is irradiated with ultraviolet rays (see the dotted arrow in FIG. 52B), the adhesiveness of the adhesive surface b72 is lowered, so that the support tape b71 is easily peeled off from each chip resistor b1.

  Next, the thermal foam sheet b73 is heated. Thereby, as shown in FIG. 52D, in the thermally foamed sheet b73, each foamed particle b75 in the sheet main body b74 is foamed and swells from the surface of the sheet main body b74. As a result, the contact area between the thermal foam sheet b73 and the back surface b2B of the substrate b2 of each chip resistor b1 is reduced, and all the chip resistors b1 are naturally peeled off (dropped off) from the thermal foam sheet b73. The chip resistor b1 collected in this manner is mounted on the mounting substrate b9 (see FIG. 41B) or is accommodated in an accommodation space formed on an embossed carrier tape (not shown). In this case, the processing time can be shortened compared to the case where the chip resistors b1 are peeled off one by one from the support tape b71 or the thermal foam sheet b73. Of course, with a plurality of chip resistors b1 attached to the support tape b71 (see FIG. 52A), a predetermined number of chip resistors b1 may be directly peeled off from the support tape b71 without using the thermal foam sheet b73. .

53A to 53C are schematic cross-sectional views showing the chip resistor recovery step (modified example) after the step of FIG. 50G.
Each chip resistor b1 can be recovered by another method shown in FIGS. 53A to 53C.
FIG. 53A shows a state in which a plurality of singulated chip resistors b1 are still attached to the support tape b71, as in FIG. 52A. In this state, as shown in FIG. 53B, the transfer tape b77 is adhered to the back surface b2B of the substrate b2 of each chip resistor b1. The transfer tape b77 has stronger adhesive force than the adhesive surface b72 of the support tape b71. Therefore, as shown in FIG. 53C, after attaching the transfer tape b77 to each chip resistor b1, the support tape b71 is peeled off from each chip resistor b1. At this time, as described above, the support tape b71 may be irradiated with ultraviolet rays (see the dotted arrow in FIG. 53B) in order to reduce the adhesiveness of the adhesive surface b72.

  Frames b78 of a collection device (not shown) are attached to both ends of the transfer tape b77. The frames b78 on both sides can move in a direction toward or away from each other. After the support tape b71 is peeled off from each chip resistor b1, when the frames b78 on both sides are moved away from each other, the transfer tape b77 expands and becomes thin. As a result, the adhesive force of the transfer tape b77 is reduced, so that each chip resistor b1 is easily peeled off from the transfer tape b77. In this state, when the suction nozzle b76 of the transport device (not shown) is directed to the surface b2A side of the chip resistor b1, the chip resistor b1 is transferred to the transfer tape by the suction force generated by the transport device (not shown). It is peeled off from b77 and sucked by the suction nozzle b76. At this time, when the chip resistor b1 is pushed up to the suction nozzle b76 side through the transfer tape b77 from the opposite side to the suction nozzle b76 by the protrusion b79 shown in FIG. 53C, the chip resistor b1 is smoothly peeled off from the transfer tape b77. be able to. The chip resistor b1 collected in this manner is transported by a transport device (not shown) while being attracted to the suction nozzle b76.

  54 to 59 are longitudinal sectional views of the chip resistor according to the embodiment or the modification, and FIGS. 54 and 56 also show plan views. 54 to 59, for convenience of explanation, illustration of the above-described insulating film b23 and the like is omitted, and only the substrate b2, the first connection electrode b3, the second connection electrode b4, and the resin film b24 are illustrated. In FIG. 54C and FIG. 56C, the resin film b24 is not shown.

As shown in FIGS. 54 to 59, each of the side surfaces b2C to b2F of the substrate b2 has a portion inclined with respect to the plane H perpendicular to the surface b2A of the substrate b2.
In the chip resistor b1 shown in FIGS. 54 and 55, each of the side surfaces b2C to b2F is a plane along the plane E inclined with respect to the plane H described above. Further, the surface b2A of the substrate b2 and each of the side surfaces b2C to b2F of the substrate b2 form an acute angle. Therefore, the edge b90 of the back surface b2B of the substrate b2 is retracted inward of the substrate b2 with respect to the edge b85 of the surface b2A of the substrate b2. Specifically, in plan view, the rectangular edge b90 that outlines the back surface b2B is positioned inside the rectangular edge b85 that outlines the front surface b2A (see FIG. 54C). Therefore, for any of the side surfaces b2C to b2F, the plane E is inclined so as to recede from the edge b85 of the front surface b2A toward the edge b90 of the back surface b2B inward of the substrate b2. Therefore, each of the side surfaces b2C to b2F in the chip resistor b1 has a trapezoidal shape (substantially isosceles trapezoidal shape) that narrows toward the back surface b2B side.

Here, in the resin film b24, as described above, the first resin film b24A is located in a region away from the boundary (edge b85) between each side surface and the surface b2A toward the back surface b2B side in each of the side surfaces b2C to b2F. The second resin film b24B is formed on the surface b2A.
On the other hand, as shown in FIG. 55, the first resin film b24A on each of the side surfaces b2C to b2F may not be separated from the second resin film b24B at the boundary (edge b85) between each side surface and the surface b2A. Good. In this case, the resin film b24 is continuously formed from each of the side surfaces b2C to b2F over the surface b2A.

  In the chip resistor b1 shown in FIG. 56, each of the side surfaces b2C to b2F is a plane along the plane G inclined with respect to the plane H described above. Further, the surface b2A of the substrate b2 and each of the side surfaces b2C to b2F of the substrate b2 form an obtuse angle. Therefore, the edge b90 of the back surface b2B of the substrate b2 projects outward from the substrate b2 with respect to the edge b85 of the surface b2A of the substrate b2. Specifically, in plan view, the rectangular edge b90 that outlines the back surface b2B is located outside the rectangular edge b85 that outlines the front surface b2A (see FIG. 56C). Therefore, with respect to any of the side surfaces b2C to b2F, the plane G is inclined so as to project outward from the substrate b2 from the edge b85 of the front surface b2A toward the edge b90 of the back surface b2B. Therefore, each of the side surfaces b2C to b2F in the chip resistor b1 has a trapezoidal shape (substantially isosceles trapezoidal shape) that narrows toward the surface b2A.

  Further, each of the side surfaces b2C to b2F does not need to be a plane inclined with respect to the plane H described above, and is a curved surface that is convexly curved inward of the substrate b2 as shown in FIGS. Thus, it is only necessary to have a portion inclined to the plane H (a curved surface portion having the planes E and G described above as tangents). In this case, the surface b2A of the substrate b2 and each of the side surfaces b2C to b2F of the substrate b2 form an acute angle, and the back surface b2B of the substrate b2 and each of the side surfaces b2C to b2F of the substrate b2 form an acute angle. Yes.

  In FIG. 57, the edge b90 of the back surface b2B of the substrate b2 is not shifted to either the outside or the inside of the substrate b2 with respect to the edge b85 of the surface b2A of the substrate b2, and overlaps in plan view. . In FIG. 58, the edge b90 of the back surface b2B of the substrate b2 retreats inward of the substrate b2 with respect to the edge b85 of the surface b2A of the substrate b2. In FIG. 59, the edge b90 of the back surface b2B of the substrate b2 protrudes outward of the substrate b2 with respect to the edge b85 of the surface b2A of the substrate b2.

The side surfaces b2C to b2F shown in FIGS. 54 to 59 can be realized by appropriately setting the etching conditions for forming the groove b44 by etching. That is, the shape of the side surfaces b2C to b2F on the substrate b2 can be controlled by the etching technique.
As described above, in the chip resistor b1, one of the edge b85 of the front surface b2A and the edge b90 of the back surface b2B of the substrate b2 projects outward from the substrate b2 more than the other (the case of FIG. 58). except). Therefore, since the corner part (corner part) b12 in the front surface b2A and the back surface b2B of the chip resistor b1 does not become a right angle, chipping in the corner part b12 (particularly the obtuse corner part b12) can be reduced.

  In particular, in the chip resistor b1 shown in FIGS. 54 and 55, the corner b12 (the corner b12 of the edge b90) on the back surface b2B of the substrate b2 has an obtuse angle, so that chipping at the corner b12 can be reduced. In the chip resistor b1 shown in FIG. 56, the corner b12 (the corner b12 of the edge b85) on the surface b2A of the substrate b2 has an obtuse angle, so that chipping at the corner b12 can be reduced.

  When the chip resistor b1 is mounted on the mounting substrate b9 (see FIG. 41B), the suction nozzle (not shown) is attached after the back surface b2B of the chip resistor b1 is sucked to the suction nozzle (not shown) of the automatic mounting machine. The chip resistor b1 is mounted on the mounting substrate b9. Prior to adsorbing the chip resistor b1 to the adsorption nozzle (not shown), the outline of the chip resistor b1 is recognized from the front surface b2A side or the back surface b2B side, and then adsorbed on the back surface b2B of the chip resistor b1. A position to be adsorbed by a nozzle (not shown) is determined. Here, when one of the edge b85 and the edge b90 protrudes outward from the substrate b2 than the other, the outline of the chip component when the image is recognized from the front surface b2A side or the back surface b2B side of the substrate b2 is as follows. The substrate b2 is clearly composed of only one of the edge b85 of the front surface b2A and the edge b90 of the back surface b2B (the edge protruding outward from the substrate b2). Therefore, since the outline of the chip resistor b1 can be correctly recognized, a desired portion (for example, a central portion) on the back surface b2B of the chip resistor b1 is accurately attracted to a suction nozzle (not shown), and the chip resistor b1 can be accurately mounted on the mounting board b9 (see FIG. 41B). That is, it is possible to improve the mounting position accuracy.

  In particular, in the case of the chip resistor b1 shown in FIGS. 54 and 56 to 59, the second resin film b24B on each of the side surfaces b2C to b2F is spaced from the surface b2A so that the edge b85 of the substrate b2 is exposed. It is formed in the open area. Further, in the case of the chip resistor b1 shown in FIGS. 54 and 57 to 59, the surface b2A of the substrate b2 and each of the side surfaces b2C to b2F form an acute angle. Therefore, since the edge b85 of the surface b2A of the substrate b2 stands out, the outline (edge b85) of the chip resistor b1 becomes clearer and easier to recognize, so that the chip resistor b1 can be more accurately attached to the mounting substrate b9. Can be implemented. That is, the edge b85 can easily recognize the outline of the chip resistor b1, and thereby the chip resistor b1 can be attracted to a suction nozzle (not shown) at an accurate position. When the edge b85 or the edge b90 is focused for image recognition, the first resin film b24A is not in focus because the first resin film b24A is not focused. The part b85 or the edge part b90 and the first resin film b24A are not confused.

On the other hand, if priority is given to the prevention of chipping at the corner portion b12 over the improvement of the mounting position accuracy, the corner portion b12 of the substrate b2 (here, the corner portion b12 on the surface b2A side) is placed on the resin film as shown in FIG. It may be covered with b24. In this case, chipping at the corner portion b12 can be reliably avoided or suppressed.
Further, the surface b2A of the substrate b2 is protected by the second resin film b24B. In particular, the surface b24D of the second resin film b24B (center portion b24C) has a height higher than that of the first connection electrode b3 and the second connection electrode b4 (FIGS. 54B and 55B). 56 (b), 57 (b), 58 (b) and 59 (b), illustration is omitted). Therefore, when the chip resistor b1 is mounted on the mounting substrate b9 as shown in FIG. 41B, if the substrate b2 receives an impact from the mounting substrate b9 on the surface b2A side, the second resin film b24B (center Since the portion b24C) is initially subjected to an impact, the surface b2A of the substrate b2 can be reliably protected by relaxing the impact by the second resin film b24B.

  The embodiment of the second reference example has been described above, but the second reference example can be implemented in other forms. For example, as an example of the chip component of the second reference example, the chip resistor b1 is disclosed in the above-described embodiment, but the second reference example can also be applied to a chip component such as a chip capacitor, a chip inductor, or a chip diode. Below, a chip capacitor is explained.

FIG. 60 is a plan view of a chip capacitor according to another embodiment of the second reference example. 61 is a cross-sectional view taken along section line LXI-LXI in FIG. FIG. 62 is an exploded perspective view showing a part of the structure of the chip capacitor separately.
In the chip capacitor b101 described below, the same reference numerals are given to the portions corresponding to the portions described in the above-described chip resistor b1, and detailed description thereof will be omitted. In the chip capacitor b101, a portion denoted by the same reference numeral as that described for the chip resistor b1 has the same configuration as the portion described for the chip resistor b1, unless otherwise specified. The same effect as the part demonstrated by b1 can be show | played.

  Referring to FIG. 60, similarly to the chip resistor b1, the chip capacitor b101 includes the substrate b2, the first connection electrode b3 disposed on the substrate b2 (on the surface b2A side of the substrate b2), and the substrate b2. And a second connection electrode b4. In this embodiment, the substrate b2 has a rectangular shape in plan view. A first connection electrode b3 and a second connection electrode b4 are disposed at both ends in the longitudinal direction of the substrate b2. In this embodiment, the first connection electrode b3 and the second connection electrode b4 have a substantially rectangular planar shape extending in the short direction of the substrate b2. On the surface b2A of the substrate b2, a plurality of capacitor elements C1 to C9 are arranged in a capacitor arrangement region b105 between the first connection electrode b3 and the second connection electrode b4. The plurality of capacitor elements C1 to C9 are a plurality of element elements (capacitor elements) constituting the element b5 described above, and each of the second connection electrodes b4 via a plurality of fuse units b107 (corresponding to the above-described fuse F). Is electrically connected.

  As shown in FIGS. 61 and 62, an insulating layer b20 is formed on the surface b2A of the substrate b2, and a lower electrode film b111 is formed on the surface of the insulating layer b20. The lower electrode film b111 extends over substantially the entire capacitor arrangement region b105. Further, the lower electrode film b111 is formed to extend to a region immediately below the first connection electrode b3. More specifically, the lower electrode film b111 includes a capacitor electrode region b111A that functions as a common lower electrode of the capacitor elements C1 to C9 in the capacitor arrangement region b105, and an external electrode lead that is disposed immediately below the first connection electrode b3. And a pad region b111B. The capacitor electrode region b111A is located in the capacitor arrangement region b105, and the pad region b111B is located immediately below the first connection electrode b3 and is in contact with the first connection electrode b3.

  A capacitor film (dielectric film) b112 is formed so as to cover and be in contact with the lower electrode film b111 (capacitor electrode area b111A) in the capacitor arrangement region b105. The capacitor film b112 is formed over the entire capacitor electrode region b111A (capacitor arrangement region b105). In this embodiment, the capacitance film b112 further covers the insulating layer b20 outside the capacitor arrangement region b105.

  An upper electrode film b113 is formed on the capacitance film b112. In FIG. 60, for clarity, the upper electrode film b113 is colored. The upper electrode film b113 includes a capacitor electrode region b113A located in the capacitor arrangement region b105, a pad region b113B located immediately below the second connection electrode b4 and in contact with the second connection electrode b4, and a capacitor electrode region b113A and the pad region. and a fuse region b113C arranged between b113B.

  In the capacitor electrode region b113A, the upper electrode film b113 is divided (separated) into a plurality of electrode film parts (upper electrode film parts) b131 to b139. In this embodiment, each of the electrode film portions b131 to b139 is formed in a rectangular shape, and extends in a strip shape from the fuse region b113C toward the first connection electrode b3. The plurality of electrode film parts b131 to b139 are opposed to the lower electrode film b111 with a plurality of types of facing areas with the capacitor film b112 interposed therebetween (while in contact with the capacitor film b112). More specifically, the facing area of the electrode film portions b131 to b139 with respect to the lower electrode film b111 may be determined to be 1: 2: 4: 8: 16: 32: 64: 128: 128. That is, the plurality of electrode film portions b131 to b139 include a plurality of electrode film portions having different facing areas, and more specifically, a plurality of facing areas set so as to form a geometric sequence with a common ratio of 2. It includes electrode film portions b131 to b138 (or b131 to b137, b139). As a result, the plurality of capacitor elements C1 to C9 respectively configured by the electrode film portions b131 to b139 and the lower electrode film b111 facing each other with the capacitance film b112 interposed therebetween include a plurality of capacitor elements having different capacitance values. . When the ratio of the facing areas of the electrode film portions b131 to b139 is as described above, the ratio of the capacitance values of the capacitor elements C1 to C9 is equal to the ratio of the facing areas, and is 1: 2: 4: 8: 16: 32. : 64: 128: 128. That is, the plurality of capacitor elements C1 to C9 include a plurality of capacitor elements C1 to C8 (or C1 to C7, C9) having capacitance values set so as to form a geometric sequence with a common ratio of 2.

  In this embodiment, the electrode film portions b131 to b135 are formed in a strip shape having the same width and a length ratio set to 1: 2: 4: 8: 16. The electrode film portions b135, b136, b137, b138, and b139 are formed in a strip shape having the same length and the width ratio set to 1: 2: 4: 8: 8. The electrode film portions b135 to b139 are formed to extend over a range from the edge on the second connection electrode b4 side to the edge on the first connection electrode b3 side of the capacitor arrangement region b105. b134 is formed shorter than that.

The pad region b113B is formed substantially similar to the second connection electrode b4 and has a substantially rectangular planar shape. As shown in FIG. 61, the upper electrode film b113 in the pad region b113B is in contact with the second connection electrode b4.
The fuse region b113C is arranged along one long side of the pad region b113B (long side on the inner side with respect to the peripheral edge of the substrate b2). The fuse region b113C includes a plurality of fuse units b107 arranged along the one long side of the pad region b113B.

  The fuse unit b107 is integrally formed of the same material as the pad region b113B of the upper electrode film b113. The plurality of electrode film portions b131 to b139 are formed integrally with one or a plurality of fuse units b107, and are connected to the pad region b113B via the fuse units b107, and the pad regions b113B are connected to the electrode film portions b131 to b139. It is electrically connected to the second connection electrode b4. As shown in FIG. 60, the electrode film portions b131 to b136 having a relatively small area are connected to the pad region b113B by a single fuse unit b107, and the electrode film portions b137 to b139 having a relatively large area include a plurality of electrode film portions b137 to b139. It is connected to the pad region b113B through the fuse unit b107. Not all the fuse units b107 need be used, and in this embodiment, some of the fuse units b107 are unused.

  The fuse unit b107 includes a first wide portion b107A for connection to the pad region b113B, a second wide portion b107B for connection to the electrode film portions b131 to b139, and first and second wide portions b107A and 7B. And a narrow portion b107C connecting between the two. The narrow portion b107C is configured to be cut (fused) by laser light. Accordingly, unnecessary electrode film portions of the electrode film portions b131 to b139 can be electrically separated from the first and second connection electrodes b3 and 4 by cutting the fuse unit b107.

  Although not shown in FIGS. 60 and 62, as shown in FIG. 61, the surface of the chip capacitor b101 including the surface of the upper electrode film b113 is covered with the insulating film b23 described above. The insulating film b23 is made of, for example, a nitride film, and is formed so as to extend not only to the upper surface of the chip capacitor b101 but also to the side surfaces b2C to b2F of the substrate b2 and cover the entire side surfaces b2C to b2F. Further, the above-described resin film b24 is formed on the insulating film b23. In the resin film b24, the first resin film b24A covers the surface b2A side portion of the side surfaces b2C to b2F, and the second resin film b24B covers the surface b2A, but the resin film b24 is an edge of the surface b2A. It is interrupted at b85 and the edge b85 is exposed.

  The insulating film b23 and the resin film b24 are protective films that protect the surface of the chip capacitor b101. In these, the openings b25 described above are formed in regions corresponding to the first connection electrode b3 and the second connection electrode b4, respectively. The opening b25 penetrates the insulating film b23 and the resin film b24 so as to expose a part of the pad region b111B of the lower electrode film b111 and a part of the pad region b113B of the upper electrode film b113. Furthermore, in this embodiment, the opening b25 corresponding to the first connection electrode b3 also penetrates the capacitive film b112.

  A first connection electrode b3 and a second connection electrode b4 are embedded in the opening b25, respectively. Accordingly, the first connection electrode b3 is bonded to the pad region b111B of the lower electrode film b111, and the second connection electrode b4 is bonded to the pad region b113B of the upper electrode film b113. The first and second external electrodes b3 and b4 are formed so as to protrude from the surface of the resin film b24. As a result, the chip capacitor b101 can be flip-chip bonded to the mounting substrate.

  FIG. 63 is a circuit diagram showing an internal electrical configuration of the chip capacitor b101. A plurality of capacitor elements C1 to C9 are connected in parallel between the first connection electrode b3 and the second connection electrode b4. Between each of the capacitor elements C1 to C9 and the second connection electrode b4, fuses F1 to F9 each composed of one or a plurality of fuse units b107 are interposed in series.

  When all the fuses F1 to F9 are connected, the capacitance value of the chip capacitor b101 is equal to the sum of the capacitance values of the capacitor elements C1 to C9. When one or more fuses selected from the plurality of fuses F1 to F9 are disconnected, the capacitor element corresponding to the disconnected fuse is disconnected, and the capacitance of the chip capacitor b101 is equal to the capacitance value of the disconnected capacitor element. The value decreases.

  Therefore, the capacitance value between the pad regions b111B and b113B (total capacitance value of the capacitor elements C1 to C9) is measured, and then one or more appropriately selected from the fuses F1 to F9 according to the desired capacitance value. If the fuse is blown with a laser beam, adjustment to a desired capacitance value (laser trimming) can be performed. In particular, if the capacitance values of the capacitor elements C1 to C8 are set to form a geometric sequence with a common ratio of 2, the capacitor element C1 having the minimum capacitance value (the value of the first term of the geometric sequence). Fine adjustment is possible to match the target capacitance value with accuracy corresponding to the capacitance value.

For example, the capacitance values of the capacitor elements C1 to C9 may be determined as follows.
C1 = 0.03125pF
C2 = 0.0625pF
C3 = 0.125pF
C4 = 0.25pF
C5 = 0.5pF
C6 = 1pF
C7 = 2pF
C8 = 4pF
C9 = 4pF
In this case, the capacitance of the chip capacitor b101 can be finely adjusted with a minimum fitting accuracy of 0.03125 pF. Further, by appropriately selecting a fuse to be cut from the fuses F1 to F9, the chip capacitor b101 having an arbitrary capacitance value between 10 pF and 18 pF can be provided.

  As described above, according to this embodiment, the plurality of capacitor elements C1 to C9 that can be separated by the fuses F1 to F9 are provided between the first connection electrode b3 and the second connection electrode b4. Capacitor elements C1 to C9 include a plurality of capacitor elements having different capacitance values, more specifically, a plurality of capacitor elements having capacitance values set so as to form a geometric sequence. As a result, by selecting one or more fuses from the fuses F1 to F9 and fusing them with laser light, it is possible to cope with a plurality of types of capacitance values without changing the design and accurately match the desired capacitance values. The chip capacitor b101 that can be embedded can be realized with a common design.

Details of each part of the chip capacitor b101 will be described below.
Referring to FIG. 60, substrate b2 has a rectangular shape such as 0.3 mm × 0.15 mm, 0.4 mm × 0.2 mm, etc. (preferably 0.4 mm × 0.2 mm or less) in plan view. You may have. The capacitor arrangement region b105 is a square region having one side corresponding to the length of the short side of the substrate b2. The thickness of the substrate b2 may be about 150 μm. Referring to FIG. 61, substrate b2 may be, for example, a substrate that has been thinned by grinding or polishing from the back side (the surface on which capacitor elements C1 to C9 are not formed). As a material of the substrate b2, a semiconductor substrate typified by a silicon substrate may be used, a glass substrate may be used, or a resin film may be used.

The insulating layer b20 may be an oxide film such as a silicon oxide film. The film thickness may be about 500 to 2000 mm.
The lower electrode film b111 is preferably a conductive film, particularly a metal film, and may be, for example, an aluminum film. The lower electrode film b111 made of an aluminum film can be formed by sputtering. Similarly, the upper electrode film b113 is preferably composed of a conductive film, particularly a metal film, and may be an aluminum film. The upper electrode film b113 made of an aluminum film can be formed by sputtering. Patterning for dividing the capacitor electrode region b113A of the upper electrode film b113 into electrode film portions b131 to b139 and further shaping the fuse region b113C into a plurality of fuse units b107 can be performed by photolithography and etching processes.

The capacitor film b112 can be made of, for example, a silicon nitride film, and the film thickness can be 500 to 2000 mm (for example, 1000 mm). The capacitor film b112 may be a silicon nitride film formed by plasma CVD (chemical vapor deposition).
The insulating film b23 can be composed of, for example, a silicon nitride film, and can be formed by, for example, a plasma CVD method. The film thickness may be about 8000 mm. As described above, the resin film b24 can be composed of a polyimide film or other resin film.

  The first and second connection electrodes b3 and b4 include, for example, a nickel layer in contact with the lower electrode film b111 or the upper electrode film b113, a palladium layer stacked on the nickel layer, and a gold layer stacked on the palladium layer. For example, it can be formed by a plating method (more specifically, an electroless plating method). The nickel layer contributes to improving the adhesion to the lower electrode film b111 or the upper electrode film b113, and the palladium layer is formed from the material of the upper electrode film or the lower electrode film and the gold of the uppermost layer of the first and second connection electrodes b3, b4. It functions as a diffusion preventing layer that suppresses mutual diffusion.

The manufacturing process of such a chip capacitor b101 is the same as the manufacturing process of the chip resistor b1 after forming the element b5.
When the element b5 (capacitor element) is formed in the chip capacitor b101, first, an oxide film (for example, a silicon oxide film) is formed on the surface of the substrate b30 (substrate b2) by the thermal oxidation method and / or the CVD method. An insulating layer b20 is formed. Next, a lower electrode film b111 made of an aluminum film is formed over the entire surface of the insulating layer b20 by, for example, sputtering. The film thickness of the lower electrode film b111 may be about 8000 mm. Next, a resist pattern corresponding to the final shape of the lower electrode film b111 is formed on the surface of the lower electrode film by photolithography. The lower electrode film is etched using the resist pattern as a mask, whereby the lower electrode film b111 having the pattern shown in FIG. 60 and the like is obtained. The etching of the lower electrode film b111 can be performed by, for example, reactive ion etching.

  Next, a capacitor film b112 made of a silicon nitride film or the like is formed on the lower electrode film b111 by, for example, plasma CVD. In the region where the lower electrode film b111 is not formed, the capacitor film b112 is formed on the surface of the insulating layer b20. Next, the upper electrode film b113 is formed on the capacitor film b112. The upper electrode film b113 is made of, for example, an aluminum film and can be formed by a sputtering method. The film thickness may be about 8000 mm. Next, a resist pattern corresponding to the final shape of the upper electrode film b113 is formed on the surface of the upper electrode film b113 by photolithography. By etching using the resist pattern as a mask, the upper electrode film b113 is patterned into a final shape (see FIG. 60 and the like). Thereby, the upper electrode film b113 has a portion divided into a plurality of electrode film portions b131 to b139 in the capacitor electrode region b113A, and has a plurality of fuse units b107 in the fuse region b113C. It is shaped into a pattern having a connected pad region b113B. Etching for patterning the upper electrode film b113 may be performed by wet etching using an etchant such as phosphoric acid or by reactive ion etching.

  Thus, the element b5 (capacitor elements C1 to C9 and the fuse unit b107) in the chip capacitor b101 is formed. After the formation of the element b5, the insulating film b45 is formed by plasma CVD so as to cover all the element b5 (the upper electrode film b113 and the capacitor film b112 in the region where the upper electrode film b113 is not formed) (FIG. 50A). Thereafter, after the groove b44 is formed (see FIG. 50B), the opening b25 is formed (see FIG. 50C). Then, the probe b70 is pressed against the pad region b113B of the upper electrode film b113 and the pad region b111B of the lower electrode film b111 exposed from the opening b25, and the total capacitance values of the plurality of capacitor elements C0 to C9 are measured ( (See FIG. 50C). Based on the measured total capacitance value, the capacitor element to be disconnected, that is, the fuse to be disconnected, is selected according to the target capacitance value of the chip capacitor b101.

  From this state, laser trimming for fusing the fuse unit b107 is performed. That is, a laser beam is applied to the fuse unit b107 constituting the fuse selected according to the measurement result of the total capacitance value, and the narrow portion b107C (see FIG. 60) of the fuse unit b107 is blown. As a result, the corresponding capacitor element is separated from the pad region b113B. When the laser beam is applied to the fuse unit b107, the energy of the laser beam is accumulated in the vicinity of the fuse unit b107 by the action of the insulating film b45 which is a cover film, and thereby the fuse unit b107 is melted. Thereby, the capacitance value of the chip capacitor b101 can be surely set to the target capacitance value.

  Next, a silicon nitride film is deposited on the cover film (insulating film b45) by, for example, plasma CVD to form an insulating film b23. In the final form, the cover film described above is integrated with the insulating film b23 and constitutes a part of the insulating film b23. The insulating film b23 formed after the fuse is cut enters into the opening of the cover film destroyed at the same time when the fuse is blown, and covers and protects the cut surface of the fuse unit b107. Therefore, the insulating film b23 prevents foreign matters from entering the cut portion of the fuse unit b107 and moisture from entering. Thereby, a highly reliable chip capacitor b101 can be manufactured. The insulating film b23 may be formed so as to have a film thickness of about 8000 mm as a whole.

Next, the coating film b46 described above is formed (see FIG. 50D). Thereafter, the opening b25 closed by the coating film b46 and the insulating film b23 is opened (see FIG. 50E), and the first connection electrode b3 and the second connection electrode b4 are formed in the opening b25 by, for example, electroless plating. Grown (see FIG. 50F).
Thereafter, as in the case of the chip resistor b1, when the substrate b30 is ground from the back surface b30B (see FIG. 50G), the chip capacitor b101 can be cut out.

  In the patterning of the upper electrode film b113 using the photolithography process, the electrode film portions b131 to b149 having a small area can be formed with high accuracy, and the fuse unit b107 having a fine pattern can be formed. Then, after patterning the upper electrode film b113, the fuse to be cut is determined through measurement of the total capacitance value. By cutting the determined fuse, it is possible to obtain a chip capacitor b101 that is accurately adjusted to a desired capacitance value.

The chip parts (chip resistor b1 and chip capacitor b101) of the second reference example have been described above, but the second reference example can be implemented in other forms.
For example, in the above-described embodiment, in the case of the chip resistor b1, the plurality of resistor circuits have a plurality of resistor circuits having resistance values forming a geometric sequence of the common ratio r (0 <r, r ≠ 1) = 2. However, the common ratio of the geometric sequence may be a number other than two. Also, in the case of the chip capacitor b101, an example is shown in which the capacitor element has a plurality of capacitor elements having capacitance values forming a geometric sequence with a common ratio r (0 <r, r ≠ 1) = 2. However, the common ratio of the geometric sequence may be a number other than two.

In the chip resistor b1 and the chip capacitor b101, the insulating layer b20 is formed on the surface of the substrate b2. However, if the substrate b2 is an insulating substrate, the insulating layer b20 can be omitted.
In the chip capacitor b101, only the upper electrode film b113 is divided into a plurality of electrode film parts. However, only the lower electrode film b111 is divided into a plurality of electrode film parts, or the upper electrode film b113 is divided. Both the lower electrode film b111 may be divided into a plurality of electrode film portions. Furthermore, in the above-described embodiment, an example in which the upper electrode film or the lower electrode film and the fuse unit are integrated is shown. However, the fuse unit is formed of a conductor film different from the upper electrode film or the lower electrode film. May be. Further, in the above-described chip capacitor b101, a single-layer capacitor structure having the upper electrode film b113 and the lower electrode film b111 is formed, but another electrode film is laminated on the upper electrode film b113 via a capacitive film. Thus, a plurality of capacitor structures may be stacked.

In the chip capacitor b101, a conductive substrate may be used as the substrate b2, the conductive substrate may be used as a lower electrode, and the capacitor film b112 may be formed so as to be in contact with the surface of the conductive substrate. In this case, one external electrode may be drawn from the back surface of the conductive substrate.
<Invention According to Third Reference Example>
(1) Features of the invention according to the third reference example For example, the features of the invention according to the third reference example are the following C1 to C23.
(C1) A chip part including a main body, an electrode provided on the surface of the main body, and a resin film formed on a side surface of the main body.

According to this configuration, since the resin film functions as a bumper in the chip parts, even if adjacent chip parts are supported by the support tape or the like prior to singulation, even if the adjacent chip parts collide with each other, In the component, since the resin films first contact each other, chipping at the corner portion of the chip component can be avoided or suppressed.
(C2) The chip component according to C1, wherein the resin film projects outward from the edge of the surface of the main body.

According to this configuration, since the corner portion on the surface of the chip component does not come into contact with surrounding objects, chipping at the corner portion can be avoided or suppressed.
(C3) The chip component according to C1 or C2, wherein the resin film is formed so as to expose an edge of a surface of the main body.
In order to mount a chip component on a mounting substrate, the chip component is generally sucked and moved by a suction nozzle of an automatic mounting machine. Prior to adsorbing the chip component to the adsorption nozzle, the image of the outline of the chip component is recognized from the front side or the back side, and then the position of the chip component to be adsorbed by the adsorption nozzle is determined. For example, since the edge of the surface of the main body is exposed, the outline of the chip component can be easily recognized by the edge, and the chip component can be sucked to the suction nozzle at an accurate position.
(C4) The chip component according to any one of C1 to C3, wherein the resin film is formed in a region spaced from the surface of the main body on a side surface of the main body.

According to this structure, the edge of the surface of a main body can be exposed reliably.
(C5) The chip component according to C1 or C2, wherein the resin film is continuously formed from the side surface to the surface of the main body.
According to this configuration, since the corner portion on the surface of the main body is covered with the resin film, chipping at the corner portion can be reliably avoided or suppressed.
(C6) The chip component according to any one of C1 to C5, wherein a surface and a side surface of the main body form an acute angle or an obtuse angle.

According to this structure, since the corner part of a main body is not a right angle, the chipping in a corner part (especially obtuse corner part) can be avoided or suppressed.
(C7) The chip component according to any one of C1 to C6, further including another resin film covering the surface of the main body so as to expose the electrode.
According to this configuration, the surface of the main body can be protected by the another resin film.
(C8) The chip component according to C7, wherein the another resin film has a surface having a height higher than that of the electrode.

According to this configuration, when the main body receives an impact on the surface side, the other resin film is initially subjected to the impact, so by mitigating the impact with the other resin film, The surface of the main body can be reliably protected.
(C9) The main body includes a substrate and a plurality of resistors formed on the substrate, and each resistor is stacked so as to be in contact with the resistor film formed on the surface of the substrate and the resistor film. The chip component according to any one of C1 to C8, including the wiring film formed, and the electrode is electrically connected to the wiring film.

According to this configuration, the chip component becomes a chip resistor, and can cope with a plurality of types of resistance values by combining a plurality of resistors.
(C10) The chip component according to C9, wherein the main body further includes a plurality of fuses that are formed on the substrate and detachably connect the plurality of resistors to the electrodes.
According to this configuration, a chip component that is a chip resistor can easily and quickly respond to a plurality of types of resistance values by selecting and cutting one or a plurality of fuses. In other words, chip resistors having various resistance values can be realized with a common design by combining a plurality of resistors having different resistance values.
(C11) The chip component may be a chip inductor.
(C12) The chip component may be a chip diode.
(C13) The chip component may be a chip capacitor.
(C14) forming an electrode in each chip component region of the substrate including a plurality of chip component regions, forming a groove having a predetermined depth from the surface of the substrate in a boundary region of the plurality of chip component regions, A step of separating the plurality of chip component regions into a main body, a step of forming the resin film on the side surface of each main body by forming a resin film on the side surface of the groove, and a back surface of the substrate reaching the groove Grinding the chip and dividing the substrate into a plurality of chip parts.

According to this method, since the completed chip parts have a resin film functioning as a bumper on the side surface, adjacent chip parts that collide with each other while being supported by the support tape or the like collide with each other prior to singulation. However, since the resin films first contact each other in the chip parts, chipping at the corners of the chip parts can be avoided or suppressed.
(C15) The chip component manufacturing method according to C14, wherein the groove is formed by etching.

According to this method, a groove can be formed at a time in the boundary region of all the chip component regions on the substrate, so that it is possible to shorten the time required for manufacturing the chip component.
(C16) The method for manufacturing a chip part according to C14 or C15, wherein the resin film is formed so as to protrude outward from the edge of the surface of the main body.
According to this method, since the corner portion on the surface of the chip component does not come into contact with surrounding objects, chipping at the corner portion can be avoided or suppressed.
(C17) The chip component manufacturing method according to any one of C14 to C16, wherein the resin film is formed so as to expose an edge of a surface of the main body.

In order to mount a chip component on a mounting substrate, the chip component is generally sucked and moved by a suction nozzle of an automatic mounting machine. Prior to adsorbing the chip component to the adsorption nozzle, the image of the outline of the chip component is recognized from the front side or the back side, and then the position of the chip component to be adsorbed by the adsorption nozzle is determined. For example, since the edge of the surface of the main body is exposed, the outline of the chip component can be easily recognized by the edge, and the chip component can be sucked to the suction nozzle at an accurate position.
(C18) The chip component manufacturing method according to any one of C14 to C17, wherein the resin film is formed in a region spaced from the surface of the main body on a side surface of the main body.

According to this method, the edge of the surface of the main body can be reliably exposed.
(C19) The chip component manufacturing method according to any one of C14 to C16, wherein the resin film is continuously formed from a side surface to a surface of the main body.
According to this method, since the corner portion on the surface of the main body is covered with the resin film, chipping at the corner portion can be reliably avoided or suppressed.
(C20) The method for manufacturing a chip part according to any one of C14 to C19, wherein the surface and the side surface of the main body form an acute angle or an obtuse angle.

According to this method, since the corner portion of the main body is not a right angle, chipping at the corner portion (particularly an obtuse corner portion) can be avoided or suppressed.
(C21) The method of manufacturing a chip part according to any one of C14 to C20, including a step of forming another resin film that covers the surface of the main body so as to expose the electrode.
According to this method, the surface of the main body can be protected by the another resin film.
(C22) The method of manufacturing a chip component according to C21, wherein the another resin film has a surface having a height higher than that of the electrode.

According to this method, when the main body receives an impact on the surface side, since the other resin film is initially subjected to the impact, by relaxing the impact with the other resin film, The surface of the main body can be reliably protected.
(C23) The main body includes a substrate and a plurality of resistors formed on the substrate, and each resistor is stacked so as to be in contact with the resistor film formed on the surface of the substrate and the resistor film. The chip component manufacturing method according to any one of C14 to C22, wherein the electrode is electrically connected to the wiring film.

According to this method, the chip component becomes a chip resistor, and a plurality of resistance values can be handled by combining a plurality of resistors.
(2) Embodiment of Invention According to Third Reference Example Hereinafter, an embodiment of the third reference example will be described in detail with reference to the accompanying drawings. Note that the reference numerals shown in FIGS. 64 to 86 are effective only in these drawings, and even if they are used in other embodiments, they do not indicate the same elements as those in the other embodiments.

FIG. 64A is a schematic perspective view for explaining the configuration of the chip resistor according to the embodiment of the third reference example, and FIG. 64B is a diagram illustrating the chip resistor mounted on the mounting substrate. It is a typical side view which shows the state made.
This chip resistor c1 is a minute chip part, and has a rectangular parallelepiped shape as shown in FIG. The planar shape of the chip resistor c1 is a rectangle with two orthogonal sides (long side c81, short side c82) of 0.4 mm or less and 0.2 mm or less, respectively. Preferably, regarding the dimensions of the chip resistor c1, the length L (the length of the long side c81) is about 0.3 mm, the width W (the length of the short side c82) is about 0.15 mm, and the thickness T is about 0.1 mm.

The chip resistor c1 is formed by forming a plurality of chip resistors c1 in a lattice shape on a substrate, forming grooves in the substrate, and then polishing the back surface (or dividing the substrate by the grooves) to obtain individual chips. It is obtained by separating the resistor c1.
The chip resistor c1 includes a substrate c2 constituting a main body (resistor main body) of the chip resistor c1, a first connection electrode c3 and a second connection electrode c4 that are external connection electrodes, a first connection electrode c3, and a second connection electrode c2. It mainly includes an element c5 that is externally connected by a connection electrode c4.

  The substrate c2 has a substantially rectangular parallelepiped chip shape. In the substrate c2, the upper surface in FIG. 64A is the surface c2A. The surface c2A is a surface (element formation surface) on which the element c5 is formed on the substrate c2, and has a substantially rectangular shape. The surface opposite to the front surface c2A in the thickness direction of the substrate c2 is a back surface c2B. The front surface c2A and the back surface c2B have substantially the same shape and are parallel to each other. However, the front surface c2A is larger than the back surface c2B. Therefore, the back surface c2B fits inside the surface c2A in a plan view viewed from the direction orthogonal to the surface c2A. The rectangular edge defined by the pair of long sides c81 and short side c82 on the front surface c2A is referred to as edge c85, and the rectangular edge defined by the pair of long sides c81 and short side c82 on the back surface c2B is defined as the edge c85. , And referred to as edge c90.

In addition to the front surface c2A and the back surface c2B, the substrate c2 has a side surface c2C, a side surface c2D, a side surface c2E, and a side surface c2F that extend across these surfaces and connect these surfaces.
The side surface c2C is constructed between the short sides c82 on one side in the longitudinal direction on the front surface c2A and the back surface c2B (the left front side in FIG. 64A), and the side surface c2D is on the other side in the longitudinal direction on the front surface c2A and the back surface c2B ( It is installed between the short sides c82 on the right back side in FIG. 64 (a). The side surface c2C and the side surface c2D are both end surfaces of the substrate c2 in the longitudinal direction. The side surface c2E is constructed between the long sides c81 on one side in the short side direction on the front surface c2A and the back surface c2B (the left back side in FIG. 64A), and the side surface c2F is the short direction on the front surface c2A and the back surface c2B. It is installed between the long sides c81 on the other side (the right front side in FIG. 64A). The side surface c2E and the side surface c2F are both end surfaces of the substrate c2 in the lateral direction. Each of the side surface c2C and the side surface c2D intersects (substantially orthogonal) with each of the side surface c2E and the side surface c2F. As described above, since the front surface c2A is larger than the rear surface c2B, each of the side surfaces c2C to c2F has an isosceles trapezoidal shape having an upper bottom on the rear surface c2B side and a lower bottom on the front surface c2A side. That is, the side shape of the chip resistor c1 is an isosceles trapezoidal shape. Therefore, adjacent ones of the surface c2A to the side surface c2F form an acute angle or an obtuse angle. Specifically, the front surface c2A and each of the side surface c2C, the side surface c2D, the side surface c2E, and the side surface c2F are acute angles, and the back surface c2B and each of the side surface c2C, the side surface c2D, the side surface c2E, and the side surface c2F are obtuse angles. It is done. For convenience of explanation, in each figure after FIG. 64, each of the side faces c2C to c2F is shown inclined (exaggerated) from the actual side.

  In the substrate c2, the entire area of the surface c2A and the side surfaces c2C to c2F is covered with the insulating film c23. Therefore, strictly speaking, in FIG. 64A, the entire area of the surface c2A and the side surfaces c2C to c2F is located on the inner side (back side) of the insulating film c23 and is not exposed to the outside. Furthermore, the chip resistor c1 has a resin film c24. The resin film c24 includes a first resin film c24A and a second resin film c24B different from the first resin film c24A. The first resin film c24A is formed in regions slightly apart from the edge c85 of the surface c2A to the back surface c2B side in each of the side surface c2C, the side surface c2D, the side surface c2E, and the side surface c2F. The second resin film c24B covers a portion of the insulating film c23 on the surface c2A that does not overlap with the edge c85 of the surface c2A (an inner region of the edge c85). The insulating film c23 and the resin film c24 will be described in detail later.

  The first connection electrode c3 and the second connection electrode c4 are formed in a region inside the edge c85 on the surface c2A of the substrate c2, and are partially exposed from the second resin film c24B on the surface c2A. Yes. In other words, the second resin film c24B covers the surface c2A (strictly, the insulating film c23 on the surface c2A) so as to expose the first connection electrode c3 and the second connection electrode c4. Each of the first connection electrode c3 and the second connection electrode c4 is configured, for example, by stacking Ni (nickel), Pd (palladium), and Au (gold) on the surface c2A in this order. The first connection electrode c3 and the second connection electrode c4 are arranged at intervals in the longitudinal direction of the surface c2A, and are long in the short direction of the surface c2A. In FIG. 64A, on the surface c2A, the first connection electrode c3 is provided near the side surface c2C, and the second connection electrode c4 is provided near the side surface c2D.

  The element c5 is a circuit element, and is formed in a region between the first connection electrode c3 and the second connection electrode c4 on the surface c2A of the substrate c2, and from above by the insulating film c23 and the second resin film c24B. It is covered. The element c5 constitutes the resistor body described above. The element c5 of this embodiment is a resistor c56. The resistor c56 is configured by a circuit network in which a plurality of (unit) resistors R having equal resistance values are arranged in a matrix on the surface c2A. The resistor R is made of TiN (titanium nitride), TiON (titanium oxynitride) or TiSiON. The element c5 is electrically connected to a wiring film c22 described later, and is electrically connected to the first connection electrode c3 and the second connection electrode c4 via the wiring film c22.

  As shown in FIG. 64 (b), the first connection electrode c3 and the second connection electrode c4 are opposed to the mounting board c9, and electrical and mechanical to the circuit (not shown) of the mounting board c9 by solder c13. Thus, the chip resistor c1 can be mounted on the mounting substrate c9 (flip chip connection). The first connection electrode c3 and the second connection electrode c4 that function as external connection electrodes are formed of gold (Au) or gold-plated on the surface in order to improve solder wettability and reliability. It is desirable.

FIG. 65 is a plan view of the chip resistor, showing the arrangement relationship between the first connection electrode, the second connection electrode and the element, and the configuration (layout pattern) of the element in plan view.
Referring to FIG. 65, element c5 is a resistor network. Specifically, the element c5 includes eight resistors R arranged along the row direction (longitudinal direction of the substrate c2) and 44 resistors arranged along the column direction (width direction of the substrate c2). It has a total of 352 resistors R composed of the body R. These resistors R are a plurality of element elements that constitute a resistance network of the element c5.

  A plurality of types of resistor circuits R are formed by grouping and electrically connecting a large number of these resistors R every predetermined number of 1 to 64. The formed plurality of types of resistance circuits are connected in a predetermined manner by a conductor film D (a wiring film formed of a conductor). Furthermore, a plurality of fuses (fuses) that can be cut (fused) on the surface c2A of the substrate c2 in order to electrically incorporate a resistance circuit with respect to the element c5 or to electrically separate it from the element c5. F is provided. The plurality of fuses F and conductor films D are arranged along the inner side of the second connection electrode c3 so that the arrangement region is linear. More specifically, the plurality of fuses F and the conductor film D are arranged so as to be adjacent to each other, and the arrangement direction thereof is linear. The plurality of fuses F connect a plurality of types of resistor circuits (a plurality of resistors R for each resistor circuit) to the second connection electrode c3 so as to be cut (separable). The plurality of fuses F and the conductor film D constitute the resistor body described above.

66A is a plan view illustrating a part of the element shown in FIG. 65 in an enlarged manner. 66B is a longitudinal cross-sectional view in the length direction along BB of FIG. 66A drawn for explaining the configuration of the resistor in the element. 66C is a longitudinal cross-sectional view in the width direction along CC of FIG. 66A drawn for explaining the configuration of the resistor in the element.
The configuration of the resistor R will be described with reference to FIGS. 66A, 66B, and 66C.

The chip resistor c1 further includes an insulating layer c20 and a resistor film c21 in addition to the wiring film c22, the insulating film c23, and the resin film c24 described above (see FIGS. 66B and 66C). The insulating layer c20, the resistor film c21, the wiring film c22, the insulating film c23, and the resin film c24 are formed on the substrate c2 (surface c2A).
The insulating layer c20 is made of SiO ₂ (silicon oxide). The insulating layer c20 covers the entire surface c2A of the substrate c2. The insulating layer c20 has a thickness of about 10,000 mm.

  The resistor film c21 is formed on the insulating layer c20. The resistor film c21 is formed of TiN, TiON, or TiSiON. The thickness of the resistor film c21 is about 2000 mm. The resistor film c21 constitutes a plurality of resistor films (hereinafter referred to as “resistor film line c21A”) extending linearly in parallel between the first connection electrode c3 and the second connection electrode c4. The resistor film line c21A may be cut at a predetermined position in the line direction (see FIG. 66A).

  A wiring film c22 is stacked on the resistor film line c21A. The wiring film c22 is made of Al (aluminum) or an alloy of aluminum and Cu (copper) (AlCu alloy). The thickness of the wiring film c22 is about 8000 mm. The wiring film c22 is laminated on the resistor film line c21A at a predetermined interval R in the line direction, and is in contact with the resistor film line c21A.

The electrical characteristics of the resistor film line c21A and the wiring film c22 having this configuration are indicated by circuit symbols as shown in FIG. That is, as shown in FIG. 67A, each portion of the resistor film line c21A in the region of the predetermined interval R forms one resistor R having a constant resistance value r.
And in the area | region where the wiring film c22 was laminated | stacked, the resistor film line c21A is short-circuited by the said wiring film c22 by electrically connecting the resistors R with which the wiring film c22 adjoins. Therefore, a resistor circuit is formed which is formed by connecting in series the resistor R of the resistor r shown in FIG. 67 (b).

  Further, since the adjacent resistor film lines c21A are connected by the resistor film c21 and the wiring film c22, the resistance network of the element c5 shown in FIG. 66A is shown in FIG. A resistor circuit (consisting of R unit resistors) is formed. As described above, the resistor film c21 and the wiring film c22 constitute the resistor R and the resistor circuit (that is, the element c5). Each resistor R includes a resistor film line c21A (resistor film c21) and a plurality of wiring films c22 stacked on the resistor film line c21A at regular intervals in the line direction. A resistor film line c21A at a constant interval R where c22 is not laminated constitutes one resistor R. The resistor film line c <b> 21 </ b> A in the portion constituting the resistor R has the same shape and size. Therefore, the multiple resistors R arranged in a matrix on the substrate c2 have equal resistance values.

The wiring film c22 laminated on the resistor film line c21A forms the resistor R and also serves as a conductor film D for connecting a plurality of resistors R to form a resistor circuit. (See FIG. 65).
FIG. 68A is a partially enlarged plan view of a region including a fuse drawn by enlarging a part of the plan view of the chip resistor shown in FIG. 65, and FIG. 68B is a plan view of FIG. It is a figure which shows the cross-sectional structure which follows BB.

  As shown in FIGS. 68A and 68B, the above-described fuse F and conductor film D are also formed by the wiring film c22 laminated on the resistor film c21 forming the resistor R. That is, the fuse F and the conductor film D are formed on the same layer as the wiring film c22 laminated on the resistor film line c21A forming the resistor R by Al or AlCu alloy which is the same metal material as the wiring film c22. Yes. As described above, the wiring film c22 is also used as a conductor film D for electrically connecting a plurality of resistors R in order to form a resistance circuit.

  That is, in the same layer laminated on the resistor film c21, the wiring film for forming the resistor R, the fuse F, the conductor film D, and the element c5 are connected to the first connection electrode c3 and the second connection film c2. A wiring film for connecting to the connection electrode c4 is formed using the same metal material (Al or AlCu alloy) as the wiring film c22. Note that the fuse F is different from (distinguishable from) the wiring film c22 because the fuse F is thinly formed so that it can be easily cut, and there are no other circuit elements around the fuse F. This is because they are arranged in such a manner.

  Here, in the wiring film c22, a region where the fuse F is disposed is referred to as a trimming target region X (see FIGS. 65 and 68A). The trimming target region X is a linear region along the inner side of the second connection electrode c3, and not only the fuse F but also the conductor film D is disposed in the trimming target region X. A resistor film c21 is also formed below the wiring film c22 in the trimming target region X (see FIG. 68B). The fuse F is a wiring having a larger inter-wiring distance (separated from the surroundings) than the portion other than the trimming target region X in the wiring film c22.

The fuse F indicates not only a part of the wiring film c22 but also a group (fuse element) of a part of the resistor R (resistor film c21) and a part of the wiring film c22 on the resistor film c21. It may be.
Further, the fuse F has been described only in the case where the same layer as the conductor film D is used. However, in the conductor film D, another conductor film is further laminated thereon to lower the resistance value of the entire conductor film D. You may do it. Even in this case, if a conductive film is not laminated on the fuse F, the fusing property of the fuse F will not deteriorate.

FIG. 69 is an electric circuit diagram of an element according to the embodiment of the third reference example.
69, element c5 includes a reference resistor circuit R8, resistor circuit R64, two resistor circuits R32, resistor circuit R16, resistor circuit R8, resistor circuit R4, resistor circuit R2, resistor circuit R1, resistor circuit R. / 2, resistor circuit R / 4, resistor circuit R / 8, resistor circuit R / 16, resistor circuit R / 32 are connected in series from the first connection electrode c3 in this order. Each of the reference resistor circuit R8 and the resistor circuits R64 to R2 is configured by connecting in series the same number of resistors R as the last number (“64” in the case of R64). The resistor circuit R1 is composed of one resistor R. Each of the resistance circuits R / 2 to R / 32 is configured by connecting in parallel the same number of resistors R as the last number of itself (“32” in the case of R / 32). The meaning of the number at the end of the resistor circuit is the same in FIGS. 70 and 71 described later.

One fuse F is connected in parallel to each of the resistor circuits R64 to R / 32 other than the reference resistor circuit R8. The fuses F are connected in series either directly or via a conductor film D (see FIG. 68A).
In a state where all the fuses F are not blown as shown in FIG. 69, the element c5 is a reference composed of eight resistors R provided in series between the first connection electrode c3 and the second connection electrode c4. A resistor circuit of the resistor circuit R8 is configured. For example, if the resistance value r of one resistor R is r = 8Ω, the chip resistor in which the first connection electrode c3 and the second connection electrode c4 are connected by a resistance circuit (reference resistance circuit R8) of 8r = 64Ω. A container c1 is configured.

  Further, in a state where all the fuses F are not blown, a plurality of types of resistor circuits other than the reference resistor circuit R8 are short-circuited. That is, 12 types and 13 resistor circuits R64 to R / 32 are connected in series to the reference resistor circuit R8, but each resistor circuit is short-circuited by the fuse F connected in parallel. From an electrical viewpoint, each resistance circuit is not incorporated in the element c5.

  In the chip resistor c1 according to this embodiment, the fuse F is selectively blown by, for example, laser light according to a required resistance value. As a result, the resistance circuit in which the fuse F connected in parallel is blown is incorporated into the element c5. Therefore, the entire resistance value of the element c5 can be set to a resistance value in which resistance circuits corresponding to the blown fuse F are connected in series.

  In particular, a plurality of types of resistor circuits have one, two, four, eight, sixteen, thirty-two, etc. resistors R having the same resistance value in series, and a geometric sequence having a common ratio of two. The number of resistors R is increased, and a plurality of types of series resistor circuits and resistors R having the same resistance value are connected in parallel to 2, 4, 8, 16,. A plurality of types of parallel resistance circuits are provided which are connected by increasing the number of resistors R in a geometric sequence. Therefore, by selectively fusing the fuse F (including the above-described fuse element), the resistance value of the entire element c5 (resistor c56) is adjusted finely and digitally to an arbitrary resistance value. Thus, a resistor having a desired value can be generated in the chip resistor c1.

FIG. 70 is an electric circuit diagram of an element according to another embodiment of the third reference example.
As shown in FIG. 69, instead of configuring the element c5 by connecting the reference resistor circuit R8 and the resistor circuits R64 to R / 32 in series, the element c5 may be configured as shown in FIG. Specifically, between the first connection electrode c3 and the second connection electrode c4, the reference resistance circuit R / 16 and 12 types of resistance circuits R / 16, R / 8, R / 4, R / 2, R1, R2 , R4, R8, R16, R32, R64, and R128 may be configured as a series connection circuit and the element c5 may be configured.

  In this case, a fuse F is connected in series to each of the 12 types of resistor circuits other than the reference resistor circuit R / 16. In a state where all the fuses F are not blown, each resistance circuit is electrically incorporated into the element c5. If the fuse F is selectively blown by, for example, laser light according to the required resistance value, a resistance circuit corresponding to the blown fuse F (a resistance circuit in which the fuse F is connected in series) becomes the element c5. Therefore, the resistance value of the entire chip resistor c1 can be adjusted.

FIG. 71 is an electric circuit diagram of an element according to still another embodiment of the third reference example.
The feature of the element c5 shown in FIG. 71 is that it has a circuit configuration in which a series connection of a plurality of types of resistance circuits and a parallel connection of a plurality of types of resistance circuits are connected in series. As in the previous embodiment, fuses F are connected in parallel to each of the plurality of resistor circuits connected in series, and the plurality of resistor circuits connected in series are all short-circuited by the fuse F. It is in a state. Therefore, when the fuse F is blown, the resistance circuit short-circuited by the blown fuse F is electrically incorporated into the element c5.

On the other hand, a fuse F is connected in series to each of the plurality of types of resistor circuits connected in parallel. Therefore, by blowing the fuse F, the resistor circuit to which the blown fuse F is connected in series can be electrically disconnected from the parallel connection of the resistor circuit.
With this configuration, for example, a small resistance of 1 kΩ or less is made on the parallel connection side, and if a resistance circuit of 1 kΩ or more is made on the series connection side, a wide range from a small resistance of several Ω to a large resistance of several MΩ is obtained. Resistor circuits can be made using a network of resistors constructed with an equal basic design. That is, the chip resistor c1 can easily and quickly cope with a plurality of types of resistance values by selecting and cutting one or a plurality of fuses F. In other words, by combining a plurality of resistors R having different resistance values, chip resistors c1 having various resistance values can be realized with a common design.

As described above, in this chip resistor c1, the connection state of the plurality of resistors R (resistance circuit) can be changed in the trimming target region X.
FIG. 72 is a schematic cross-sectional view of a chip resistor.
Next, the chip resistor c1 will be described in more detail with reference to FIG. For convenience of explanation, in FIG. 72, the element c5 described above is simplified and each element other than the substrate c2 is hatched.

Here, the insulating film c23 and the resin film c24 described above will be described.
The insulating film c23 is made of, for example, SiN (silicon nitride), and has a thickness of 1000 to 5000 mm (here, about 3000 mm). The insulating film c23 is provided over the entire area of the surface c2A and the side surfaces c2C to c2F. The insulating film c23 on the surface c2A covers the resistor film c21 and each wiring film c22 (that is, the element c5) on the resistor film c21 from the surface (the upper side in FIG. 72), and each resistor in the element c5 The upper surface of R is covered. Therefore, the insulating film c23 also covers the wiring film c22 in the trimming target region X described above (see FIG. 68B). The insulating film c23 is in contact with the element c5 (the wiring film c22 and the resistor film c21), and is also in contact with the insulating layer c20 in a region other than the resistor film c21. Thus, the insulating film c23 on the surface c2A functions as a protective film that covers the entire surface c2A and protects the element c5 and the insulating layer c20. On the surface c2A, the insulating film c23 prevents a short circuit between the resistors R other than the wiring film c22 (short circuit between adjacent resistor film lines c21A).

  On the other hand, the insulating film c23 provided on each of the side surfaces c2C to c2F functions as a protective layer that protects each of the side surfaces c2C to c2F. The boundary between each of the side surfaces c2C to c2F and the surface c2A is the edge c85 described above, but the insulating film c23 also covers the boundary (edge c85). In the insulating film c23, a portion covering the edge c85 (a portion overlapping the edge c85) is referred to as an end c23A.

The resin film c24 protects the surface c2A of the chip resistor c1 together with the insulating film c23, and is made of a resin such as polyimide. The thickness of the resin film c24 is about 5 μm.
As described above, the resin film c24 includes the first resin film c24A and the second resin film c24B.
The first resin film c24A covers a part of the side surfaces c2C to c2F that is slightly separated from the edge c85 (end c23A of the insulating film c23) toward the back surface c2B. Specifically, the first resin film c24A is formed in each of the side surfaces c2C to c2F in a region having a gap K from the edge c85 of the surface c2A to the back surface c2B side. However, the first resin film c24A is arranged to be biased toward the front surface c2A rather than the back surface c2B. The first resin films c24A on the side surfaces c2C and 2D extend in a streak shape along the short side c82, and are formed over the entire region in the direction of the short side c82 (see FIG. 64A). The first resin films c24A on the side surfaces c2E and 2F extend in a streak shape along the long side c81, and are formed over the entire region in the direction of the long side c81 (see FIG. 64A). The first resin film c24A on each of the side surfaces c2C to c2F projects outward from the edge (edge c85) of the surface c2A. Specifically, the first resin film c24A bulges outward in an arc shape from the edge c85 in the direction along the surface c2A. Therefore, the first resin film c24A forms the outline of the chip resistor c1 in plan view.

  The second resin film c24B covers substantially the entire surface of the insulating film c23 on the surface c2A (including the resistor film c21 and the wiring film c22 covered with the insulating film c23). Specifically, the second resin film c24B is formed away from the end c23A so as not to cover the end c23A (the edge c85 of the surface c2A) of the insulating film c23. Therefore, the first resin film c24A and the second resin film c24B are not continuous and are interrupted at the end c23A (the entire area of the edge c85). As a result, the end c23A (the entire area of the edge c85) of the insulating film c23 is exposed to the outside.

  In the second resin film c24B, one opening c25 is formed at two positions separated in plan view. Each opening c25 is a through-hole that continuously penetrates the second resin film c24B and the insulating film c23 in the respective thickness directions. Therefore, the opening c25 is formed not only in the second resin film c24B but also in the insulating film c23. A part of the wiring film c22 is exposed from each opening c25. A portion of the wiring film c22 exposed from each opening c25 is a pad region c22A for external connection.

  Of the two openings c25, one opening c25 is filled with the first connection electrode c3, and the other opening c25 is filled with the second connection electrode c4. A part of each of the first connection electrode c3 and the second connection electrode c4 protrudes from the opening c25 on the surface of the second resin film c24B. The first connection electrode c3 is electrically connected to the wiring film c22 in the pad region c22A in the opening c25 through the one opening c25. The second connection electrode c4 is electrically connected to the wiring film c22 in the pad region c22A in the opening c25 through the other opening c25. Thereby, each of the first connection electrode c3 and the second connection electrode c4 is electrically connected to the element c5. Here, the wiring film c22 forms wiring connected to each of the group of resistors R (resistor c56), the first connection electrode c3, and the second connection electrode c4.

  As described above, the second resin film c24B and the insulating film c23 in which the opening c25 is formed cover the surface c2A in a state where the first connection electrode c3 and the second connection electrode c4 are exposed from the opening c25. Therefore, electrical connection between the chip resistor c1 and the mounting substrate c9 can be achieved via the first connection electrode c3 and the second connection electrode c4 that protrude from the opening c25 on the surface of the second resin film c24B. (See FIG. 64 (b)).

  Here, in the second resin film c24B, the portion located between the first connection electrode c3 and the second connection electrode c4 (referred to as “center portion c24C”) is the first connection electrode c3 and the second connection electrode. It is higher than c4 (away from surface c2A). That is, the central portion c24C has a surface c24D that is higher than the first connection electrode c3 and the second connection electrode c4. The surface c24D is convexly curved in a direction away from the surface c2A.

73A to 73G are schematic sectional views showing a method for manufacturing the chip resistor shown in FIG.
First, as shown in FIG. 73A, a substrate c30 as a base of the substrate c2 is prepared. In this case, the surface c30A of the substrate c30 is the surface c2A of the substrate c2, and the back surface c30B of the substrate c30 is the back surface c2B of the substrate c2.

Then, the surface c30A of the substrate c30 is thermally oxidized to form an insulating layer c20 made of SiO ₂ or the like on the surface c30A, and the element c5 (the resistor R and the wiring film c22 connected to the resistor R is formed on the insulating layer c20. ). Specifically, first, a TiN, TiON, or TiSiON resistor film c21 is formed on the entire surface of the insulating layer c20 by sputtering, and aluminum is further formed on the resistor film c21 so as to be in contact with the resistor film c21. A (Al) wiring film c22 is laminated. Thereafter, using a photolithography process, the resistor film c21 and the wiring film c22 are selectively removed and patterned by dry etching such as RIE (Reactive Ion Etching), for example, as shown in FIG. In a plan view, a configuration is obtained in which the resistor film lines c21A having a certain width on which the resistor films c21 are stacked are arranged in the column direction with a certain interval. At this time, a region in which the resistor film line c21A and the wiring film c22 are partially cut is formed, and the fuse F and the conductor film D are formed in the trimming target region X (see FIG. 65). Subsequently, the wiring film c22 stacked on the resistor film line c21A is selectively removed by wet etching, for example. As a result, an element c5 having a configuration in which the wiring film c22 is laminated at a predetermined interval R on the resistor film line c21A is obtained. At this time, in order to ascertain whether or not the resistor film c21 and the wiring film c22 are formed with target dimensions, the resistance value of the entire element c5 may be measured.

  Referring to FIG. 73A, element c5 is formed at a number of locations on surface c30A of substrate c30 according to the number of chip resistors c1 formed on one substrate c30. One region where the element c5 (the resistor c56 described above) is formed on the substrate c30 is referred to as a chip component region Y (or a chip resistor region Y). The component region Y (that is, the element c5) is formed (set). One chip component region Y coincides with a plan view of one completed chip resistor c1 (see FIG. 72). A region between adjacent chip component regions Y on the surface c30A of the substrate c30 is referred to as a boundary region Z. The boundary region Z has a belt shape and extends in a lattice shape in plan view. One chip component region Y is arranged in one lattice defined by the boundary region Z. Since the width of the boundary region Z is as extremely narrow as 1 μm to 60 μm (for example, 20 μm), many chip component regions Y can be secured on the substrate c30, and as a result, mass production of the chip resistors c1 becomes possible.

  Next, as shown in FIG. 73A, an insulating film c45 made of SiN is formed over the entire surface c30A of the substrate c30 by a CVD (Chemical Vapor Deposition) method. The insulating film c45 covers all of the insulating layer c20 and the element c5 (the resistor film c21 and the wiring film c22) on the insulating layer c20 and is in contact with them. Therefore, the insulating film c45 also covers the wiring film c22 in the trimming target area X (see FIG. 65). Further, since the insulating film c45 is formed over the entire area of the surface c30A of the substrate c30, the insulating film c45 is formed to extend to a region other than the trimming target region X on the surface c30A. Thus, the insulating film c45 becomes a protective film that protects the entire surface c30A (including the element c5 on the surface c30A).

Next, as shown in FIG. 73B, a resist pattern c41 is formed over the entire surface c30A of the substrate c30 so as to cover the entire insulating film c45. An opening c42 is formed in the resist pattern c41.
FIG. 74 is a schematic plan view of a part of a resist pattern used for forming a groove in the step of FIG. 73B.

  Referring to FIG. 74, the opening c42 of the resist pattern c41 is a plan view when a large number of chip resistors c1 (in other words, the above-described chip component region Y) are arranged in a matrix (also in a lattice shape). It corresponds to (corresponds to) the region between the outlines of the adjacent chip resistors c1 (the hatched portion in FIG. 74, in other words, the boundary region Z). Therefore, the overall shape of the opening c42 is a lattice shape having a plurality of linear portions c42A and c42B orthogonal to each other.

In the resist pattern c41, the straight portions c42A and c42B that are orthogonal to each other in the opening c42 are connected to each other while being kept orthogonal to each other (without being curved). Therefore, the intersecting portion c43 of the straight portions c42A and c42B is pointed so as to form approximately 90 ° in plan view.
Referring to FIG. 73B, each of insulating film c45, insulating layer c20, and substrate c30 is selectively removed by plasma etching using resist pattern c41 as a mask. As a result, the material of the substrate c30 is removed in the boundary region Z between the adjacent elements c5 (chip component region Y). As a result, a position (boundary region Z) coinciding with the opening c42 of the resist pattern c41 in plan view reaches the middle of the thickness of the substrate c30 from the surface c30A of the substrate c30 through the insulating film c45 and the insulating layer c20. A groove c44 having a predetermined depth is formed. The groove c44 is partitioned by a pair of side walls c44A facing each other and a bottom wall c44B connecting the lower ends of the pair of side walls c44A (the end on the back surface c30B side of the substrate c30). The depth of the groove c44 with respect to the surface c30A of the substrate c30 is about 100 μm, and the width of the groove c44 (the interval between the opposing side walls c44A) is about 20 μm. However, the width of the groove c44 increases as it approaches the bottom wall c44B. Therefore, the side surface (section screen c44C) that partitions the groove c44 in each side wall c44A is inclined with respect to the plane H perpendicular to the surface c30A of the substrate c30.

  The overall shape of the groove c44 in the substrate c30 is a lattice shape that coincides with the opening c42 (see FIG. 74) of the resist pattern c41 in plan view. Then, on the surface c30A of the substrate c30, a rectangular frame portion (boundary region Z) in the groove c44 surrounds the chip component region Y where each element c5 is formed. The portion of the substrate c30 where the element c5 is formed is a semi-finished product c50 of the chip resistor c1. On the surface c30A of the substrate c30, the semi-finished products c50 are located one by one in the chip component region Y surrounded by the groove c44, and these semi-finished products c50 are arranged in a matrix. By forming the groove c44 in this way, the substrate c30 is separated into the substrate c2 (the resistor main body described above) for each of the plurality of chip component regions Y.

  After the groove c44 is formed as shown in FIG. 73B, the resist pattern c41 is removed, and the insulating film c45 is selectively removed by etching using the mask c65 as shown in FIG. 73C. In the mask c65, an opening c66 is formed in a portion of the insulating film c45 that coincides with each pad region c22A (see FIG. 72) in plan view. Thereby, a portion of the insulating film c45 that coincides with the opening c66 is removed by etching, and an opening c25 is formed in the portion. Thus, the insulating film c45 is formed so as to expose each pad region c22A in the opening c25. Two openings c25 are formed for one semi-finished product c50.

  In each semi-finished product c50, after two openings c25 are formed in the insulating film c45, a probe c70 of a resistance measuring device (not shown) is brought into contact with the pad region c22A of each opening c25, so that the entire resistance value of the element c5 is obtained. Is detected. Then, by irradiating the arbitrary fuse F (see FIG. 65) with a laser beam (not shown) through the insulating film c45, the wiring film c22 in the trimming target region X is trimmed with the laser beam, and the fuse F is melted. In this way, by fusing (trimming) the fuse F so as to have a necessary resistance value, the resistance value of the entire semi-finished product c50 (in other words, the chip resistor c1) can be adjusted as described above. At this time, since the insulating film c45 is a cover film that covers the element c5, it is possible to prevent a short circuit from occurring due to debris or the like generated during the fusing, which adheres to the element c5. Further, since the insulating film c45 covers the fuse F (resistor film c21), the energy of the laser beam can be stored in the fuse F and the fuse F can be blown reliably.

  Thereafter, SiN is formed on the insulating film c45 by the CVD method, and the insulating film c45 is thickened. At this time, as shown in FIG. 73D, the insulating film c45 is also formed over the entire inner peripheral surface of the groove c44 (the section screen c44C of the side wall c44A and the upper surface of the bottom wall c44B). The final insulating film c45 (the state shown in FIG. 73D) has a thickness of 1000 to 5000 mm (here, about 3000 mm). At this time, a part of the insulating film c45 enters each opening c25 and closes the opening c25.

  Thereafter, a photosensitive resin liquid made of polyimide is spray-applied onto the substrate c30 from above the insulating film c45 to form a photosensitive resin coating film c46 as shown in FIG. 73D. The liquid photosensitive resin cannot flow and flows at the entrance of the groove c44 (a portion corresponding to the end c23A of the insulating film c23 or the edge c85 of the substrate c2). Therefore, the liquid photosensitive resin is a region on the back surface c30B side (bottom wall c44B side) of the side surface c30A of the substrate c30 on the side wall c44A (section screen c44C) of the groove c44, and the end portion of the insulating film c23 on the surface c30A. It adheres to the area | region remove | deviated from c23A, and becomes a coating film c46 (resin film | membrane) in each area | region. The coating film c46 on the surface c30A has a shape that is convexly curved upward due to surface tension.

Note that the coating film c46 formed on the side wall c44A of the groove c44 only covers a part of the side wall c44A of the groove c44 on the element c5 side (surface c30A side), and the coating film c46 is a bottom wall of the groove c44. It has not reached c44B. Therefore, the groove c44 is not blocked by the coating film c46.
Next, the coating film c46 is subjected to heat treatment (curing treatment). As a result, the thickness of the coating film c46 is thermally contracted, and the coating film c46 is cured to stabilize the film quality.

  Next, as shown in FIG. 73E, the coating film c46 is patterned, and portions of the coating film c46 on the surface c30A that coincide with the pad regions c22A (openings c25) of the wiring film c22 in plan view are selectively removed. Specifically, the coating film c46 is exposed and developed with the pattern using the mask c62 in which the opening c61 having a pattern that matches (matches) with each pad region c22A in plan view. Thereby, the coating film c46 is separated above each pad region c22A. Next, the insulating film c45 on each pad region c22A is removed by RIE using a mask (not shown), whereby each opening c25 is opened and the pad region c22A is exposed.

  Next, a Ni / Pd / Au laminated film formed by laminating Ni, Pd, and Au is formed on the pad region c22A in each opening c25 by electroless plating. At this time, the Ni / Pd / Au laminated film protrudes from the opening c25 to the surface of the coating film c46. Thereby, the Ni / Pd / Au laminated film in each opening c25 becomes the first connection electrode c3 and the second connection electrode c4 shown in FIG. 73F. Note that the upper surfaces of the first connection electrode c3 and the second connection electrode c4 are at positions below the upper end of the coating film c46 that is convexly curved on the surface c30A.

Next, after conducting an energization inspection between the first connection electrode c3 and the second connection electrode c4, the substrate c30 is ground from the back surface c30B.
Specifically, after forming the groove c44, as shown in FIG. 73G, a support tape c71 having a thin plate shape made of PET (polyethylene terephthalate) and having an adhesive surface c72 is formed on each of the semi-finished products c50 on the adhesive surface c72. Are attached to the first connection electrode c3 and the second connection electrode c4 side (that is, the surface c30A). Thereby, each semi-finished product c50 is supported by the support tape c71. Here, as the support tape c71, for example, a laminate tape can be used.

  With each semi-finished product c50 supported by the support tape c71, the substrate c30 is ground from the back surface c30B side. When the substrate c30 is thinned by grinding until it reaches the upper surface of the bottom wall c44B (see FIG. 73F) of the groove c44, there is no connection between the adjacent semi-finished products c50, so the substrate c30 is divided with the groove c44 as a boundary. Then, the semi-finished product c50 is individually separated to be a finished product of the chip resistor c1. That is, the substrate c30 is cut (divided) in the groove c44 (in other words, the boundary region Z), and thereby the individual chip resistors c1 are cut out. Note that the chip resistor c1 may be cut out by etching the substrate c30 from the back surface c30B side to the bottom wall c44B of the groove c44.

  In each completed chip resistor c1, the portion that formed the section screen c44C of the side wall c44A of the groove c44 becomes one of the side surfaces c2C to c2F of the substrate c2, and the back surface c30B becomes the back surface c2B. That is, as described above, the step of forming the groove c44 by etching (see FIG. 73B) is included in the step of forming the side surfaces c2C to c2F. In the step of forming the groove c44, the side surface (section screen c44C) of the substrate c30 in the plurality of chip component regions Y (chip resistors c1) is inclined with respect to the plane H perpendicular to the surface c30A of the substrate c30. Can be shaped at once (see FIG. 73B). In other words, forming the groove c44 shapes the side surfaces c2C to c2F of the substrate c2 of each chip resistor c1 at a time so as to have a portion inclined with respect to the plane H.

  By forming the groove c44 by etching, the side surfaces c2C to c2F in the completed chip resistor c1 are rough surfaces with irregular patterns. Incidentally, when the groove c44 is mechanically formed by a dicing saw (not shown), a large number of streaks forming a grinding mark of the dicing saw remain in a regular pattern on the side surfaces c2C to c2F. Even if the side surfaces c2C to c2F are etched, this streak cannot be completely erased.

Further, the insulating film c45 becomes the insulating film c23, and the separated coating film c46 becomes the resin film c24.
As described above, if the substrate c30 is ground from the back surface c30B side after the groove c44 is formed, a plurality of chip component regions Y formed on the substrate c30 are divided into individual chip resistors c1 (chip components) all at once. (A plurality of chip resistors c1 can be obtained at a time). Therefore, the productivity of the chip resistor c1 can be improved by shortening the manufacturing time of the plurality of chip resistors c1. Incidentally, when a substrate c30 having a diameter of 8 inches is used, about 500,000 chip resistors c1 can be cut out. When the chip resistor c1 is cut out by forming the groove c44 in the substrate c30 using only a dicing saw (not shown), the dicing saw is moved many times to form a large number of grooves c44 in the substrate c30. However, if the groove c44 is formed by etching as in the third reference example, this problem can be solved.

  That is, even if the chip size of the chip resistor c1 is small, the chip resistor c1 is separated at a time by grinding the substrate c30 from the back surface c30B after the groove c44 is formed in this way. be able to. Therefore, as compared with the conventional case where the chip resistor c1 is singulated by dicing the substrate c30 with a dicing saw, the cost reduction and time reduction can be achieved and the yield can be improved by omitting the dicing process.

  Further, since the groove c44 can be formed with high accuracy by etching, the accuracy of the external dimension can be improved in each chip resistor c1 divided by the groove c44. In particular, if plasma etching is used, the groove c44 can be formed with higher accuracy. Specifically, the dimensional tolerance of the chip resistor c1 when the groove c44 is formed using a general dicing saw is ± 20 μm, whereas in the third reference example, the dimensional tolerance of the chip resistor c1 Can be reduced to about ± 5 μm. Further, since the interval between the grooves c44 can be reduced according to the resist pattern c41 (see FIG. 74), the chip resistor c1 formed between the adjacent grooves c44 can be reduced in size. In the case of etching, unlike the case where a dicing saw is used, the chip resistor c1 is not cut out, so that the corner portions c11 (FIG. It is possible to reduce the occurrence of chipping in a) and to improve the appearance of the chip resistor c1.

  When each chip resistor c1 is cut out by grinding the substrate c30 from the back surface c30B side, the chip resistor c1 may be cut out earlier or later. That is, when cutting out the chip resistor c1, a slight time difference may occur between the chip resistors c1. In this case, the chip resistor c1 cut out first may vibrate left and right, and may contact the adjacent chip resistor c1. At this time, in each chip resistor c1, since the resin film c24 (first resin film c24A) functions as a bumper, the chip resistors c1 adjacent to each other while being supported by the support tape c71 prior to singulation. Even if they collide with each other, since the resin films c24 first come into contact with each other in the chip resistors c1, the corner portion c12 on the front surface c2A side and the back surface c2B side of the chip resistor c1 (particularly, the edge portion c85 on the front surface c2A side). ) Can be avoided or suppressed. In particular, since the first resin film c24A projects outward from the edge c85 of the surface c2A of the chip resistor c1, the edge c85 does not come into contact with the surrounding parts, so that the chipping at the edge c85 is prevented. Can be avoided or suppressed.

Note that the back surface c2B may be cleaned by polishing or etching the back surface c2B of the substrate c2 in the completed chip resistor c1.
75A to 75D are schematic sectional views showing the chip resistor recovery process after the process of FIG. 73G.
FIG. 75A shows a state in which a plurality of chip resistors c1 separated into pieces continue to adhere to the support tape c71. In this state, as shown in FIG. 75B, a thermal foam sheet c73 is attached to the back surface c2B of the substrate c2 of each chip resistor c1. The thermally foamed sheet c73 includes a sheet-like sheet main body c74 and a large number of expanded particles c75 kneaded into the sheet main body c74.

  The adhesive strength of the sheet body c74 is stronger than the adhesive strength on the adhesive surface c72 of the support tape c71. Therefore, after sticking the thermal foam sheet c73 on the back surface c2B of the substrate c2 of each chip resistor c1, as shown in FIG. 75C, the support tape c71 is peeled off from each chip resistor c1, and the chip resistors c1 Transfer to the thermal foam sheet c73. At this time, if the support tape c71 is irradiated with ultraviolet rays (see the dotted arrow in FIG. 75B), the adhesiveness of the adhesive surface c72 is reduced, so that the support tape c71 is easily peeled off from each chip resistor c1.

  Next, the thermal foam sheet c73 is heated. Thereby, as shown in FIG. 75D, in the thermally foamed sheet c73, each foamed particle c75 in the sheet main body c74 expands and swells from the surface of the sheet main body c74. As a result, the contact area between the thermal foam sheet c73 and the back surface c2B of the substrate c2 of each chip resistor c1 is reduced, and all the chip resistors c1 are naturally peeled off (dropped off) from the thermal foam sheet c73. The chip resistor c1 collected in this manner is mounted on the mounting substrate c9 (see FIG. 64B) or is accommodated in an accommodation space formed on an embossed carrier tape (not shown). In this case, the processing time can be shortened compared to the case where the chip resistors c1 are peeled off from the support tape c71 or the thermal foam sheet c73 one by one. Of course, with a plurality of chip resistors c1 attached to the support tape c71 (see FIG. 75A), a predetermined number of chip resistors c1 may be directly peeled off from the support tape c71 without using the thermal foam sheet c73. .

76A to 76C are schematic cross-sectional views showing the chip resistor recovery step (modified example) after the step of FIG. 73G.
Each chip resistor c1 can be recovered by another method shown in FIGS. 76A to 76C.
FIG. 76A shows a state where a plurality of singulated chip resistors c1 are still attached to the support tape c71, as in FIG. 75A. In this state, as shown in FIG. 76B, the transfer tape c77 is attached to the back surface c2B of the substrate c2 of each chip resistor c1. The transfer tape c77 has stronger adhesive force than the adhesive surface c72 of the support tape c71. Therefore, as shown in FIG. 76C, after attaching the transfer tape c77 to each chip resistor c1, the support tape c71 is peeled off from each chip resistor c1. At this time, as described above, the support tape c71 may be irradiated with ultraviolet rays (see dotted arrows in FIG. 76B) in order to reduce the adhesiveness of the adhesive surface c72.

  Frames c78 of a collection device (not shown) are attached to both ends of the transfer tape c77. The frames c78 on both sides can move in a direction toward or away from each other. After the support tape c71 is peeled off from each chip resistor c1, when the frames c78 on both sides are moved away from each other, the transfer tape c77 expands and becomes thin. As a result, the adhesive force of the transfer tape c77 is reduced, so that each chip resistor c1 is easily peeled off from the transfer tape c77. In this state, when the suction nozzle c76 of the transport device (not shown) is directed to the surface c2A side of the chip resistor c1, the chip resistor c1 is transferred to the transfer tape by the suction force generated by the transport device (not shown). It is peeled off from c77 and sucked by the suction nozzle c76. At this time, when the chip resistor c1 is pushed up to the suction nozzle c76 side through the transfer tape c77 from the opposite side to the suction nozzle c76 by the protrusion c79 shown in FIG. 76C, the chip resistor c1 is smoothly peeled off from the transfer tape c77. be able to. The chip resistor c1 thus collected is transported by a transport device (not shown) while being attracted to the suction nozzle c76.

  77 to 82 are longitudinal sectional views of the chip resistor according to the embodiment or the modification, and FIGS. 77 and 79 also show plan views. 77 to 82, for convenience of explanation, illustration of the insulating film c23 and the like described above is omitted, and only the substrate c2, the first connection electrode c3, the second connection electrode c4, and the resin film c24 are illustrated. In addition, in FIG. 77 (c) and FIG. 79 (c), the resin film c24 is not shown.

As shown in FIGS. 77 to 82, each of the side surfaces c2C to c2F of the substrate c2 has a portion inclined with respect to the plane H perpendicular to the surface c2A of the substrate c2.
In the chip resistor c1 shown in FIGS. 77 and 78, each of the side surfaces c2C to c2F is a plane along the plane E inclined with respect to the plane H described above. Further, the surface c2A of the substrate c2 and each of the side surfaces c2C to c2F of the substrate c2 form an acute angle. For this reason, the edge c90 of the back surface c2B of the substrate c2 retreats inward of the substrate c2 with respect to the edge c85 of the surface c2A of the substrate c2. Specifically, in plan view, the rectangular edge c90 that outlines the back surface c2B is positioned inside the rectangular edge c85 that outlines the front surface c2A (see FIG. 77C). Therefore, with respect to any of the side surfaces c2C to c2F, the plane E is inclined so as to recede inward of the substrate c2 from the edge c85 of the front surface c2A toward the edge c90 of the back surface c2B. Therefore, each of the side surfaces c2C to c2F in the chip resistor c1 has a trapezoidal shape (substantially isosceles trapezoidal shape) that narrows toward the back surface c2B side.

Here, in the resin film c24, as described above, the first resin film c24A is located in a region away from the boundary (edge c85) between each side surface and the surface c2A toward the back surface c2B side in each of the side surfaces c2C to c2F. The second resin film c24B is formed on the surface c2A.
On the other hand, as shown in FIG. 78, the first resin film c24A on each of the side surfaces c2C to c2F may not be separated from the second resin film c24B at the boundary (edge c85) between each side surface and the surface c2A. Good. In this case, the resin film c24 is continuously formed from each of the side surfaces c2C to c2F to the surface c2A.

  In the chip resistor c1 shown in FIG. 79, each of the side surfaces c2C to c2F is a plane along the plane G inclined with respect to the plane H described above. Further, the surface c2A of the substrate c2 and each of the side surfaces c2C to c2F of the substrate c2 form an obtuse angle. For this reason, the edge c90 of the back surface c2B of the substrate c2 projects outward from the edge c85 of the surface c2A of the substrate c2. Specifically, in plan view, the rectangular edge c90 that outlines the back surface c2B is located outside the rectangular edge c85 that outlines the front surface c2A (see FIG. 79C). Therefore, with respect to any of the side surfaces c2C to c2F, the plane G is inclined so as to project outward from the substrate c2 toward the edge c90 of the back surface c2B from the edge c85 of the front surface c2A. Therefore, each of the side surfaces c2C to c2F in the chip resistor c1 has a trapezoidal shape (substantially isosceles trapezoidal shape) that narrows toward the surface c2A side.

  Further, each of the side surfaces c2C to c2F does not need to be a plane inclined with respect to the plane H described above, and is a curved surface that is convexly curved inward toward the substrate c2 as shown in FIGS. Thus, it is only necessary to have a portion inclined to the plane H (a curved surface portion having the planes E and G described above as tangents). In this case, the surface c2A of the substrate c2 and each of the side surfaces c2C to c2F of the substrate c2 form an acute angle, and the back surface c2B of the substrate c2 and each of the side surfaces c2C to c2F of the substrate c2 form an acute angle. Yes.

  In FIG. 80, the edge c90 of the back surface c2B of the substrate c2 is not shifted to either the outside or the inside of the substrate c2 with respect to the edge c85 of the surface c2A of the substrate c2, and overlaps in plan view. . In FIG. 81, the edge c90 of the back surface c2B of the substrate c2 is retreated inward of the substrate c2 with respect to the edge c85 of the surface c2A of the substrate c2. In FIG. 82, the edge c90 of the back surface c2B of the substrate c2 projects outward from the substrate c2 with respect to the edge c85 of the surface c2A of the substrate c2.

The side surfaces c2C to c2F shown in FIGS. 77 to 82 can be realized by appropriately setting the etching conditions for forming the groove c44 by etching. That is, the shape of the side surfaces c2C to c2F on the substrate c2 can be controlled by the etching technique.
As described above, in the chip resistor c1, one of the edge portion c85 of the front surface c2A and the edge portion c90 of the back surface c2B of the substrate c2 projects outward from the substrate c2 more than the other (the case of FIG. 81). except). Therefore, since the corner part (corner part) 12 in the front surface c2A and the back surface c2B of the chip resistor c1 does not become a right angle, the chipping in the corner part c12 (particularly the obtuse corner part c12) can be reduced.

  In particular, in the chip resistor c1 shown in FIGS. 77 and 78, since the corner portion c12 (the corner portion c12 of the edge portion c90) on the back surface c2B of the substrate c2 becomes an obtuse angle, chipping at the corner portion c12 can be reduced. In the chip resistor c1 shown in FIG. 79, since the corner part c12 (the corner part c12 of the edge part c85) on the surface c2A of the substrate c2 has an obtuse angle, chipping at the corner part c12 can be reduced.

  When the chip resistor c1 is mounted on the mounting substrate c9 (see FIG. 64B), the suction nozzle (not shown) is attached after the back surface c2B of the chip resistor c1 is suctioned to the suction nozzle (not shown) of the automatic mounting machine. ) Is moved to the mounting substrate c9, thereby mounting the chip resistor c1 on the mounting substrate c9. Prior to adsorbing the chip resistor c1 to the adsorption nozzle (not shown), the outline of the chip resistor c1 is image-recognized from the front surface c2A side or the back surface c2B side, and then adsorbed on the back surface c2B of the chip resistor c1. A position to be adsorbed by a nozzle (not shown) is determined. Here, when one of the edge portion c85 and the edge portion c90 protrudes outward from the substrate c2 than the other, the outline of the chip component when the image is recognized from the front surface c2A side or the back surface c2B side of the substrate c2 is as follows. The substrate c2 is clearly constituted by only one of the edge c85 of the front surface c2A and the edge c90 of the back surface c2B (an edge protruding outward of the substrate c2). Therefore, since the outline of the chip resistor c1 can be correctly recognized, a desired portion (for example, the central portion) on the back surface c2B of the chip resistor c1 is accurately attracted to the suction nozzle (not shown), and the chip resistor c1 can be accurately mounted on the mounting substrate c9 (see FIG. 64B). That is, it is possible to improve the mounting position accuracy.

  In particular, in the case of the chip resistor c1 shown in FIGS. 77 and 79 to 82, the second resin film c24B on each of the side surfaces c2C to c2F is spaced from the surface c2A so that the edge c85 of the substrate c2 is exposed. It is formed in the open area. Further, in the case of the chip resistor c1 shown in FIGS. 77 and 80 to 82, the surface c2A of the substrate c2 and each of the side surfaces c2C to c2F form an acute angle. Therefore, since the edge c85 of the surface c2A of the substrate c2 stands out, the outline (edge c85) of the chip resistor c1 becomes clearer and easier to recognize, so that the chip resistor c1 is more accurately attached to the mounting substrate c9. Can be implemented. In other words, the outline of the chip resistor c1 can be easily recognized by the edge c85, and thereby the chip resistor c1 can be attracted to a suction nozzle (not shown) at an accurate position. When the edge c85 or the edge c90 is focused for image recognition, the first resin film c24A is not in focus because the first resin film c24A is not focused. The part c85 or the edge part c90 and the first resin film c24A are not confused.

On the other hand, if priority is given to prevention of chipping at the corner portion c12 over improvement in mounting position accuracy, the corner portion c12 of the substrate c2 (here, the corner portion c12 on the surface c2A side) is placed on the resin film as shown in FIG. It may be covered with c24. In this case, chipping at the corner portion c12 can be reliably avoided or suppressed.
Further, the surface c2A of the substrate c2 is protected by the second resin film c24B. In particular, the surface c24D of the second resin film c24B (center portion c24C) has a height higher than that of the first connection electrode c3 and the second connection electrode c4 (FIGS. 77 (b) and 78 (b), 79 (b), FIG. 80 (b), FIG. 81 (b) and FIG. 82 (b), illustration is omitted). Therefore, as shown in FIG. 64B, when the chip resistor c1 is mounted on the mounting substrate c9, if the substrate c2 receives an impact from the mounting substrate c9 on the surface c2A side, the second resin film c24B (center Since the portion c24C) is initially subjected to an impact, the surface c2A of the substrate c2 can be reliably protected by relaxing the impact with the second resin film c24B.

  The embodiment of the third reference example has been described above, but the third reference example can be implemented in other forms. For example, as an example of the chip component of the third reference example, the chip resistor c1 is disclosed in the above-described embodiment, but the third reference example can also be applied to a chip component such as a chip capacitor, a chip inductor, or a chip diode. Below, a chip capacitor is explained.

FIG. 83 is a plan view of a chip capacitor according to another embodiment of the third reference example. 84 is a cross-sectional view taken along section line LXXXIV-LXXXIV in FIG. 83. FIG. 85 is an exploded perspective view showing a part of the structure of the chip capacitor separately.
In the chip capacitor c101 described below, the same reference numerals are given to the portions corresponding to the portions described in the above-described chip resistor c1, and detailed description thereof will be omitted. In the chip capacitor c101, a portion denoted by the same reference numeral as that described for the chip resistor c1 has the same configuration as the portion described for the chip resistor c1, unless otherwise specified. The same effect as the part demonstrated by c1 can be show | played.

  Referring to FIG. 83, similarly to the chip resistor c1, the chip capacitor c101 includes a substrate c2, a first connection electrode c3 disposed on the substrate c2 (on the surface c2A side of the substrate c2), and the substrate c2. And a second connection electrode c4. In this embodiment, the substrate c2 has a rectangular shape in plan view. A first connection electrode c3 and a second connection electrode c4 are arranged at both ends in the longitudinal direction of the substrate c2. In this embodiment, the first connection electrode c3 and the second connection electrode c4 have a substantially rectangular planar shape extending in the short direction of the substrate c2. On the surface c2A of the substrate c2, a plurality of capacitor elements C1 to C9 are arranged in a capacitor arrangement region c105 between the first connection electrode c3 and the second connection electrode c4. The plurality of capacitor elements C1 to C9 are a plurality of element elements (capacitor elements) constituting the element c5 described above, and each of the second connection electrodes c4 via a plurality of fuse units c107 (corresponding to the above-described fuse F). Is electrically connected.

  As shown in FIGS. 84 and 85, an insulating layer c20 is formed on the surface c2A of the substrate c2, and a lower electrode film c111 is formed on the surface of the insulating layer c20. The lower electrode film c111 extends over almost the entire capacitor arrangement region c105. Further, the lower electrode film c111 is formed to extend to a region immediately below the first connection electrode c3. More specifically, the lower electrode film c111 includes a capacitor electrode region c111A that functions as a common lower electrode of the capacitor elements C1 to C9 in the capacitor arrangement region c105, and an external electrode lead disposed immediately below the first connection electrode c3. And a pad region c111B. The capacitor electrode region c111A is located in the capacitor arrangement region c105, and the pad region c111B is located immediately below the first connection electrode c3 and is in contact with the first connection electrode c3.

  A capacitor film (dielectric film) c112 is formed so as to cover and be in contact with the lower electrode film c111 (capacitor electrode area c111A) in the capacitor arrangement region c105. The capacitive film c112 is formed over the entire capacitor electrode region c111A (capacitor arrangement region c105). In this embodiment, the capacitive film c112 further covers the insulating layer c20 outside the capacitor arrangement region c105.

  An upper electrode film c113 is formed on the capacitance film c112. In FIG. 83, the upper electrode film c113 is colored for the sake of clarity. The upper electrode film c113 includes a capacitor electrode region c113A located in the capacitor arrangement region c105, a pad region c113B located immediately below the second connection electrode c4 and in contact with the second connection electrode c4, and the capacitor electrode region c113A and the pad region. and a fuse region c113C arranged between c113B.

  In the capacitor electrode region c113A, the upper electrode film c113 is divided (separated) into a plurality of electrode film portions (upper electrode film portions) c131 to c139. In this embodiment, each of the electrode film portions c131 to c139 is formed in a rectangular shape, and extends in a band shape from the fuse region c113C toward the first connection electrode c3. The plurality of electrode film portions c131 to c139 are opposed to the lower electrode film c111 with a plurality of types of facing areas with the capacitor film c112 interposed therebetween (while in contact with the capacitor film c112). More specifically, the facing area of the electrode film portions c131 to c139 with respect to the lower electrode film c111 may be determined to be 1: 2: 4: 8: 16: 32: 64: 128: 128. In other words, the plurality of electrode film portions c131 to c139 include a plurality of electrode film portions having different facing areas, and more specifically, a plurality of facing areas set so as to form a geometric sequence with a common ratio of 2. It includes electrode film portions c131 to c138 (or c131 to c137, c139). Accordingly, the plurality of capacitor elements C1 to C9 respectively configured by the electrode film portions c131 to c139 and the lower electrode film c111 facing each other with the capacitance film c112 interposed therebetween include a plurality of capacitor elements having different capacitance values. . When the ratio of the facing areas of the electrode film portions c131 to c139 is as described above, the ratio of the capacitance values of the capacitor elements C1 to C9 is equal to the ratio of the facing areas, and is 1: 2: 4: 8: 16: 32. : 64: 128: 128. That is, the plurality of capacitor elements C1 to C9 include a plurality of capacitor elements C1 to C8 (or C1 to C7, C9) having capacitance values set so as to form a geometric sequence with a common ratio of 2.

  In this embodiment, the electrode film portions c131 to c135 are formed in a strip shape having the same width and a length ratio set to 1: 2: 4: 8: 16. The electrode film portions c135, c136, c137, c138, and c139 are formed in a strip shape having the same length and the width ratio set to 1: 2: 4: 8: 8. The electrode film portions c135 to c139 are formed to extend over a range from the edge on the second connection electrode c4 side of the capacitor arrangement region c105 to the edge on the first connection electrode c3 side. c134 is formed shorter than that.

The pad region c113B is formed substantially similar to the second connection electrode c4, and has a substantially rectangular planar shape. As shown in FIG. 84, the upper electrode film c113 in the pad region c113B is in contact with the second connection electrode c4.
The fuse region c113C is disposed along one long side of the pad region c113B (long side on the inner side with respect to the periphery of the substrate c2). The fuse region c113C includes a plurality of fuse units c107 arranged along the one long side of the pad region c113B.

  The fuse unit c107 is integrally formed of the same material as the pad region c113B of the upper electrode film c113. The plurality of electrode film portions c131 to c139 are formed integrally with one or a plurality of fuse units c107, and are connected to the pad region c113B via the fuse units c107, and the pad region c113B is connected to the electrode film portions c131 to c139. It is electrically connected to the second connection electrode c4. As shown in FIG. 83, the electrode film portions c131 to c136 having a relatively small area are connected to the pad region c113B by one fuse unit c107, and a plurality of electrode film portions c137 to c139 having a relatively large area are provided. It is connected to the pad region c113B through the fuse unit c107. It is not necessary to use all the fuse units c107, and in this embodiment, some of the fuse units c107 are unused.

  The fuse unit c107 includes a first wide portion c107A for connection to the pad region c113B, a second wide portion c107B for connection to the electrode film portions c131 to c139, and first and second wide portions c107A and 7B. And a narrow portion c107C connecting between the two. The narrow portion c107C is configured to be cut (fused) by laser light. Accordingly, unnecessary electrode film portions of the electrode film portions c131 to c139 can be electrically disconnected from the first and second connection electrodes c3 and c4 by cutting the fuse unit c107.

  Although not shown in FIGS. 83 and 85, as shown in FIG. 84, the surface of the chip capacitor c101 including the surface of the upper electrode film c113 is covered with the insulating film c23 described above. The insulating film c23 is made of, for example, a nitride film, and is formed so as to extend not only to the upper surface of the chip capacitor c101 but also to the side surfaces c2C to c2F of the substrate c2 and cover the entire side surfaces c2C to c2F. Furthermore, the above-described resin film c24 is formed on the insulating film c23. In the resin film c24, the first resin film c24A covers the portion on the surface c2A side in the side surfaces c2C to c2F, and the second resin film c24B covers the surface c2A, but the resin film c24 is an edge of the surface c2A. It is interrupted at c85, and the edge c85 is exposed.

  The insulating film c23 and the resin film c24 are protective films that protect the surface of the chip capacitor c101. In these, the above-described opening c25 is formed in a region corresponding to the first connection electrode c3 and the second connection electrode c4. The opening c25 penetrates the insulating film c23 and the resin film c24 so as to expose a part of the pad region c111B of the lower electrode film c111 and a part of the pad region c113B of the upper electrode film c113. Furthermore, in this embodiment, the opening c25 corresponding to the first connection electrode c3 also penetrates the capacitive film c112.

  A first connection electrode c3 and a second connection electrode c4 are embedded in the opening c25. Accordingly, the first connection electrode c3 is bonded to the pad region c111B of the lower electrode film c111, and the second connection electrode c4 is bonded to the pad region c113B of the upper electrode film c113. The first and second external electrodes c3, 4 are formed so as to protrude from the surface of the resin film c24. As a result, the chip capacitor c101 can be flip-chip bonded to the mounting substrate.

  FIG. 86 is a circuit diagram showing an internal electrical configuration of the chip capacitor c101. A plurality of capacitor elements C1 to C9 are connected in parallel between the first connection electrode c3 and the second connection electrode c4. Between the capacitor elements C1 to C9 and the second connection electrode c4, fuses F1 to F9 each composed of one or a plurality of fuse units c107 are interposed in series.

  When all the fuses F1 to F9 are connected, the capacitance value of the chip capacitor c101 is equal to the sum of the capacitance values of the capacitor elements C1 to C9. When one or more fuses selected from the plurality of fuses F1 to F9 are cut, the capacitor element corresponding to the cut fuse is cut, and the capacitance of the chip capacitor c101 is equal to the capacitance value of the cut capacitor element. The value decreases.

  Therefore, the capacitance value between the pad regions c111B and c113B (the total capacitance value of the capacitor elements C1 to C9) is measured, and then one or more appropriately selected from the fuses F1 to F9 according to the desired capacitance value. If the fuse is blown with laser light, adjustment to a desired capacitance value (laser trimming) can be performed. In particular, if the capacitance values of the capacitor elements C1 to C8 are set to form a geometric sequence with a common ratio of 2, the capacitor element C1 having the minimum capacitance value (the value of the first term of the geometric sequence). Fine adjustment is possible to match the target capacitance value with accuracy corresponding to the capacitance value.

For example, the capacitance values of the capacitor elements C1 to C9 may be determined as follows.
C1 = 0.03125pF
C2 = 0.0625pF
C3 = 0.125pF
C4 = 0.25pF
C5 = 0.5pF
C6 = 1pF
C7 = 2pF
C8 = 4pF
C9 = 4pF
In this case, the capacitance of the chip capacitor c101 can be finely adjusted with a minimum fitting accuracy of 0.03125 pF. Further, by appropriately selecting a fuse to be cut from the fuses F1 to F9, it is possible to provide a chip capacitor c101 having an arbitrary capacitance value between 10 pF and 18 pF.

  As described above, according to this embodiment, the plurality of capacitor elements C1 to C9 that can be separated by the fuses F1 to F9 are provided between the first connection electrode c3 and the second connection electrode c4. Capacitor elements C1 to C9 include a plurality of capacitor elements having different capacitance values, more specifically, a plurality of capacitor elements having capacitance values set so as to form a geometric sequence. As a result, by selecting one or more fuses from the fuses F1 to F9 and fusing them with laser light, it is possible to cope with a plurality of types of capacitance values without changing the design and accurately match the desired capacitance values. The chip capacitor c101 that can be embedded can be realized with a common design.

Details of each part of the chip capacitor c101 will be described below.
Referring to FIG. 83, substrate c2 has a rectangular shape such as 0.3 mm × 0.15 mm and 0.4 mm × 0.2 mm in plan view (preferably, a size of 0.4 mm × 0.2 mm or less). You may have. Capacitor arrangement region c105 is generally a square region having one side corresponding to the length of the short side of substrate c2. The thickness of the substrate c2 may be about 150 μm. Referring to FIG. 84, substrate c2 may be, for example, a substrate that has been thinned by grinding or polishing from the back side (the surface on which capacitor elements C1 to C9 are not formed). As a material of the substrate c2, a semiconductor substrate typified by a silicon substrate, a glass substrate, or a resin film may be used.

The insulating layer c20 may be an oxide film such as a silicon oxide film. The film thickness may be about 500 to 2000 mm.
The lower electrode film c111 is preferably a conductive film, particularly a metal film, and may be, for example, an aluminum film. The lower electrode film c111 made of an aluminum film can be formed by a sputtering method. Similarly, the upper electrode film c113 is preferably composed of a conductive film, particularly a metal film, and may be an aluminum film. The upper electrode film c113 made of an aluminum film can be formed by sputtering. Patterning for dividing the capacitor electrode region c113A of the upper electrode film c113 into electrode film portions c131 to c139 and further shaping the fuse region c113C into a plurality of fuse units c107 can be performed by photolithography and etching processes.

The capacitor film c112 can be made of, for example, a silicon nitride film, and the film thickness can be 500 to 2000 mm (for example, 1000 mm). The capacitor film c112 may be a silicon nitride film formed by plasma CVD (chemical vapor deposition).
The insulating film c23 can be made of, for example, a silicon nitride film, and can be formed by, for example, a plasma CVD method. The film thickness may be about 8000 mm. As described above, the resin film c24 can be formed of a polyimide film or other resin film.

  The first and second connection electrodes c3 and 4 include, for example, a nickel layer in contact with the lower electrode film c111 or the upper electrode film c113, a palladium layer stacked on the nickel layer, and a gold layer stacked on the palladium layer. For example, it can be formed by a plating method (more specifically, an electroless plating method). The nickel layer contributes to improving the adhesion to the lower electrode film c111 or the upper electrode film c113, and the palladium layer is formed from the material of the upper electrode film or the lower electrode film and the gold of the uppermost layer of the first and second connection electrodes c3 and c4. It functions as a diffusion preventing layer that suppresses mutual diffusion.

The manufacturing process of such a chip capacitor c101 is the same as the manufacturing process of the chip resistor c1 after forming the element c5.
When the element c5 (capacitor element) is formed in the chip capacitor c101, first, an oxide film (for example, a silicon oxide film) is formed on the surface of the substrate c30 (substrate c2) by the thermal oxidation method and / or the CVD method. An insulating layer c20 is formed. Next, a lower electrode film c111 made of an aluminum film is formed over the entire surface of the insulating layer c20, for example, by sputtering. The film thickness of the lower electrode film c111 may be about 8000 mm. Next, a resist pattern corresponding to the final shape of the lower electrode film c111 is formed on the surface of the lower electrode film by photolithography. Using this resist pattern as a mask, the lower electrode film is etched to obtain the lower electrode film c111 having the pattern shown in FIG. The etching of the lower electrode film c111 can be performed by, for example, reactive ion etching.

  Next, a capacitor film c112 made of a silicon nitride film or the like is formed on the lower electrode film c111 by, for example, plasma CVD. In the region where the lower electrode film c111 is not formed, the capacitor film c112 is formed on the surface of the insulating layer c20. Next, the upper electrode film c113 is formed on the capacitor film c112. The upper electrode film c113 is made of, for example, an aluminum film and can be formed by a sputtering method. The film thickness may be about 8000 mm. Next, a resist pattern corresponding to the final shape of the upper electrode film c113 is formed on the surface of the upper electrode film c113 by photolithography. By etching using this resist pattern as a mask, the upper electrode film c113 is patterned into a final shape (see FIG. 83 and the like). Thereby, the upper electrode film c113 has a portion divided into a plurality of electrode film portions c131 to c139 in the capacitor electrode region c113A, and has a plurality of fuse units c107 in the fuse region c113C. It is shaped into a pattern having a connected pad region c113B. Etching for patterning the upper electrode film c113 may be performed by wet etching using an etchant such as phosphoric acid or by reactive ion etching.

  Thus, the element c5 (capacitor elements C1 to C9 and the fuse unit c107) in the chip capacitor c101 is formed. After the element c5 is formed, an insulating film c45 is formed by plasma CVD so as to cover all the element c5 (the upper electrode film c113 and the capacitor film c112 in the region where the upper electrode film c113 is not formed) (FIG. 73A). Thereafter, after the groove c44 is formed (see FIG. 73B), the opening c25 is formed (see FIG. 73C). Then, the probe c70 is pressed against the pad region c113B of the upper electrode film c113 and the pad region c111B of the lower electrode film c111 exposed from the opening c25, and the total capacitance values of the plurality of capacitor elements C0 to C9 are measured ( (See FIG. 73C). Based on the measured total capacitance value, the capacitor element to be disconnected, that is, the fuse to be disconnected, is selected according to the target capacitance value of the chip capacitor c101.

  From this state, laser trimming for fusing the fuse unit c107 is performed. That is, laser light is applied to the fuse unit c107 constituting the fuse selected according to the measurement result of the total capacity value, and the narrow portion c107C (see FIG. 83) of the fuse unit c107 is melted. As a result, the corresponding capacitor element is separated from the pad region c113B. When the laser light is applied to the fuse unit c107, the energy of the laser light is accumulated in the vicinity of the fuse unit c107 by the action of the insulating film c45 that is a cover film, and the fuse unit c107 is thus blown out. Thereby, the capacitance value of the chip capacitor c101 can be surely set to the target capacitance value.

  Next, a silicon nitride film is deposited on the cover film (insulating film c45) by plasma CVD, for example, and an insulating film c23 is formed. In the final form, the above-described cover film is integrated with the insulating film c23 and constitutes a part of the insulating film c23. The insulating film c23 formed after the fuse is cut enters the opening of the cover film destroyed at the same time when the fuse is blown, and covers and protects the cut surface of the fuse unit c107. Therefore, the insulating film c23 prevents foreign matter from entering the cut portion of the fuse unit c107 and moisture from entering. Thereby, a highly reliable chip capacitor c101 can be manufactured. The insulating film c23 may be formed so as to have a film thickness of about 8000 mm as a whole.

Next, the coating film c46 described above is formed (see FIG. 73D). Thereafter, the opening c25 closed by the coating film c46 and the insulating film c23 is opened (see FIG. 73E), and the first connection electrode c3 and the second connection electrode c4 are formed in the opening c25 by, for example, electroless plating. Grown (see FIG. 73F).
Thereafter, as in the case of the chip resistor c1, when the substrate c30 is ground from the back surface c30B (see FIG. 73G), the piece of the chip capacitor c101 can be cut out.

  In the patterning of the upper electrode film c113 using the photolithography process, the electrode film portions c131 to 149 having a very small area can be formed with high accuracy, and the fuse unit c107 having a fine pattern can be formed. Then, after patterning the upper electrode film c113, the fuse to be cut is determined through measurement of the total capacitance value. By cutting the determined fuse, it is possible to obtain a chip capacitor c101 that is accurately adjusted to a desired capacitance value.

Although the chip parts (chip resistor c1 and chip capacitor c101) of the third reference example have been described above, the third reference example can be implemented in other forms.
For example, in the above-described embodiment, in the case of the chip resistor c1, the plurality of resistor circuits have a plurality of resistor circuits having resistance values forming a series of geometric ratios with a common ratio r (0 <r, r ≠ 1) = 2. However, the common ratio of the geometric sequence may be a number other than two. Also in the case of the chip capacitor c101, an example is shown in which the capacitor element has a plurality of capacitor elements having capacitance values forming a geometric sequence with a common ratio r (0 <r, r ≠ 1) = 2. However, the common ratio of the geometric sequence may be a number other than two.

In the chip resistor c1 and the chip capacitor c101, the insulating layer c20 is formed on the surface of the substrate c2. However, if the substrate c2 is an insulating substrate, the insulating layer c20 can be omitted.
In the chip capacitor c101, only the upper electrode film c113 is divided into a plurality of electrode film parts. However, only the lower electrode film c111 is divided into a plurality of electrode film parts, or the upper electrode film c113 is divided. The lower electrode film c111 may be divided into a plurality of electrode film portions. Furthermore, in the above-described embodiment, an example in which the upper electrode film or the lower electrode film and the fuse unit are integrated is shown. However, the fuse unit is formed of a conductor film different from the upper electrode film or the lower electrode film. May be. Further, in the above-described chip capacitor c101, a one-layer capacitor structure having the upper electrode film c113 and the lower electrode film c111 is formed, but another electrode film is laminated on the upper electrode film c113 via a capacitive film. Thus, a plurality of capacitor structures may be stacked.

In the chip capacitor c101, a conductive substrate may be used as the substrate c2, the conductive substrate may be used as a lower electrode, and the capacitor film c112 may be formed so as to be in contact with the surface of the conductive substrate. In this case, one external electrode may be drawn from the back surface of the conductive substrate.
<Invention According to Fourth Reference Example>
(1) Features of Invention According to Fourth Reference Example For example, the features of the invention according to the fourth reference example are the following D1 to D15.
(D1) a substrate, an element circuit network including a plurality of element elements formed on the substrate, an electrode provided on the substrate and externally connecting the element circuit network, and the plurality of element elements A plurality of fuses each connected to the electrodes in a detachable manner, and the plurality of element elements and the plurality of fuses are covered in a state where the electrodes are exposed, and inward of the substrate from the edge of the substrate A chip part including a protective resin film having a retreated edge.

According to this configuration, since the protective resin film is made of resin, there is little risk of cracking due to impact. Therefore, since the protective resin film can reliably protect the substrate surface (particularly, the element circuit network and the fuse) from impact, a chip component having excellent impact resistance can be provided. Further, in this chip component, by selecting and cutting one or a plurality of fuses, a combination pattern of a plurality of element elements in the element circuit network can be changed to an arbitrary pattern. Chip parts with various characteristics can be realized with a common design.
(D2) a substrate, an element circuit network including a plurality of element elements formed on the substrate, an electrode provided on the substrate and externally connecting the element circuit network, and the plurality of element elements A plurality of fuses each connected to the electrode in a detachable manner, a passivation film having a surface covering portion covering the surface of the substrate and a side surface covering portion covering the side surface of the substrate, and the electrode exposed in the state A chip component comprising: a protective resin film formed on the passivation film and having an edge aligned with a side surface covering portion of the passivation film in a plan view.

According to this configuration, since the protective resin film is made of resin, there is little risk of cracking due to impact. Therefore, since the protective resin film can reliably protect the substrate surface (particularly, the element circuit network and the fuse) and the edge of the substrate surface from impact, a chip component having excellent impact resistance can be provided. Further, in this chip component, by selecting and cutting one or a plurality of fuses, a combination pattern of a plurality of element elements in the element circuit network can be changed to an arbitrary pattern. Chip parts with various characteristics can be realized with a common design.
(D3) a substrate, an element circuit network including a plurality of element elements formed on the substrate, an electrode provided on the substrate for externally connecting the element circuit network, and the plurality of element elements. A plurality of fuses each connected to the electrode in a detachable manner, a passivation film having a surface covering portion covering the surface of the substrate and a side surface covering portion covering the side surface of the substrate, and the electrode exposed in the state A chip component including a protective resin film formed on the passivation film and covering both the surface covering portion and the side surface covering portion of the passivation film.

According to this configuration, since the protective resin film is made of resin, there is little risk of cracking due to impact. Therefore, since the protective resin film can reliably protect the substrate surface (particularly, the element circuit network and the fuse) and the side surface of the substrate from impact, a chip component having excellent impact resistance can be provided. Further, in this chip component, by selecting and cutting one or a plurality of fuses, a combination pattern of a plurality of element elements in the element circuit network can be changed to an arbitrary pattern. Chip parts with various characteristics can be realized with a common design.
(D4) The chip according to any one of D1 to D3, wherein the element circuit network includes a resistor circuit network including a plurality of resistors formed on the substrate, and the chip component is a chip resistor. parts.

According to this configuration, this chip component (chip resistor) can easily and quickly cope with a plurality of types of resistance values by selecting and cutting one or a plurality of fuses. In other words, chip resistors having various resistance values can be realized with a common design by combining a plurality of resistors having different resistance values.
(D5) The chip component according to D4, wherein the resistor includes a resistor film formed on the substrate and a wiring film laminated on the resistor film.

According to this configuration, since the portion between the adjacent wiring films in the resistor film becomes a resistor, the resistor can be configured simply by simply laminating the wiring film on the resistor film.
(D6) The chip component according to any one of D1 to D3, wherein the element circuit network includes a capacitor circuit network including a plurality of capacitor elements formed on the substrate, and the chip component is a chip capacitor. .

According to this configuration, this chip component (chip capacitor) can easily and quickly cope with a plurality of types of capacitance values by selecting and cutting one or a plurality of fuses. In other words, chip capacitors having various capacitance values can be realized by a common design by combining a plurality of capacitor elements having different capacitance values.
(D7) The capacitor element includes a capacitive film formed on the substrate, and a lower electrode film and an upper electrode film facing each other with the capacitive film interposed therebetween, and the lower electrode film and the upper electrode film are separated from each other. The chip component according to D6, including the plurality of electrode film portions, wherein the plurality of electrode film portions are respectively connected to the plurality of fuses.

According to this configuration, a plurality of capacitor elements corresponding to the number of electrode film portions can be formed.
(D8) The chip component according to any one of D1 to D3, wherein the element circuit network includes an inductor circuit network including a plurality of inductor elements formed on the substrate, and the chip component is a chip inductor. .

According to this configuration, in this chip component (chip inductor), a combination pattern of a plurality of inductor elements in the inductor network can be changed to an arbitrary pattern by selecting and cutting one or a plurality of fuses. Therefore, chip inductors having various electrical characteristics of the inductor network can be realized with a common design.
(D9) The chip component according to any one of D1 to D3, wherein the element circuit network includes a diode circuit network including a plurality of diode elements formed on the substrate, and the chip component is a chip diode. .

According to this configuration, in this chip component (chip diode), the combination pattern of a plurality of diode elements in the diode network can be changed to an arbitrary pattern by selecting and cutting one or a plurality of fuses. Therefore, chip diodes with various electrical characteristics of the diode network can be realized with a common design.
(D10) The protective resin film is preferably made of polyimide.
(D11) The chip component according to any one of D1 to D10, wherein the protective resin film has an opening that penetrates the protective resin film in a thickness direction and in which the electrode is disposed.

In this case, in the protective resin film, the electrode can be exposed from the opening.
(D12) The opening may be widened toward the surface of the protective resin film.
(D13) On the surface of the electrode, the end is curved toward the surface of the substrate.
(D14) The chip component according to any one of D1 to D13, wherein the electrode includes a Ni layer and an Au layer, and the Au layer is exposed on an outermost surface.

In this case, in the electrode, since the surface of the Ni layer is covered with the Au layer, the Ni layer can be prevented from being oxidized.
(D15) The chip part according to D14, wherein the electrode further includes a Pd layer interposed between the Ni layer and the Au layer.
In this case, in the electrode, even if a through hole (pin hole) is formed in the Au layer by thinning the Au layer, the Pd layer interposed between the Ni layer and the Au layer blocks the through hole. Therefore, the Ni layer can be prevented from being exposed to the outside through the through hole and being oxidized.
(2) Embodiment of Invention According to Fourth Reference Example Hereinafter, an embodiment of the fourth reference example will be described in detail with reference to the accompanying drawings. Note that the reference numerals shown in FIGS. 87 to 110 are valid only in these drawings, and even if they are used in other embodiments, they do not indicate the same elements as those in the other embodiments.

FIG. 87A is a schematic perspective view for explaining the configuration of the chip resistor according to the embodiment of the fourth reference example, and FIG. 87B is a diagram illustrating the chip resistor mounted on the mounting substrate. It is typical sectional drawing which shows the state made.
The chip resistor d1 is a minute chip part and has a rectangular parallelepiped shape as shown in FIG. 87 (a). The planar shape of the chip resistor d1 is a rectangle. Regarding the dimensions of the chip resistor d1, for example, the length L (the length of the long side d81) is about 0.6 mm, the width W (the length of the short side d82) is about 0.3 mm, and the thickness T Is about 0.2 mm.

The chip resistor d1 is formed by forming a large number of chip resistors d1 on a substrate in a lattice pattern, forming grooves in the substrate, and then polishing the back surface (or dividing the substrate by the grooves) to obtain individual chips. It is obtained by separating the resistor d1.
The chip resistor d1 includes a substrate d2 constituting the main body of the chip resistor d1, a first connection electrode d3 and a second connection electrode d4 that are a pair of external connection electrodes, a first connection electrode d3, and a second connection electrode d4. And an element d5 connected externally.

  The substrate d2 has a substantially rectangular parallelepiped chip shape. In the substrate d2, the upper surface in FIG. 87 (a) is the surface d2A. The surface d2A is a surface (element formation surface) on which the element d5 is formed on the substrate d2, and has a substantially rectangular shape. The surface opposite to the front surface d2A in the thickness direction of the substrate d2 is a back surface d2B. The front surface d2A and the back surface d2B have substantially the same shape and are parallel to each other. However, the back surface d2B is larger than the front surface d2A. Therefore, the front surface d2A fits inside the back surface d2B in a plan view viewed from the direction orthogonal to the front surface d2A. The rectangular edge defined by the pair of long sides d81 and short sides d82 on the front surface d2A is referred to as an edge portion d85, and the rectangular end defined by the pair of long sides d81 and short sides d82 on the back surface d2B. The edge is referred to as edge d90.

The substrate d2 has a plurality of side surfaces (a side surface d2C, a side surface d2D, a side surface d2E, and a side surface d2F) in addition to the front surface d2A and the back surface d2B. The plurality of side surfaces extend so as to intersect (specifically, orthogonally cross) each of the front surface d2A and the back surface d2B, and connect the front surface d2A and the back surface d2B.
The side surface d2C is constructed between the short sides d82 on one side in the longitudinal direction on the front surface d2A and the back surface d2B (left front side in FIG. 87A), and the side surface d2D is on the other side in the longitudinal direction on the front surface d2A and the back surface d2B ( It is constructed between the short sides d82 on the right back side in FIG. 87 (a). The side surface d2C and the side surface d2D are both end surfaces of the substrate d2 in the longitudinal direction. The side surface d2E is constructed between the long sides d81 on one side in the short direction of the front surface d2A and the back surface d2B (the left back side in FIG. 87A), and the side surface d2F is the short direction of the front surface d2A and the back surface d2B. It is installed between the long sides d81 on the other side (the right front side in FIG. 87 (a)). The side surface d2E and the side surface d2F are both end surfaces of the substrate d2 in the lateral direction. Each of the side surface d2C and the side surface d2D intersects (specifically, orthogonal) with each of the side surface d2E and the side surface d2F.

As described above, adjacent ones on the surface d2A to the side surface d2F form a substantially right angle.
Each of the side surface d2C, the side surface d2D, the side surface d2E, and the side surface d2F (hereinafter referred to as “each side surface”) has a rough surface region S on the front surface d2A side and a streak pattern region P on the back surface d2B side. doing. In the rough surface region S, each side surface is a rough surface having a rough irregular pattern as shown by fine dots in FIG. On each side surface, in the streak pattern region P, a large number of streaks (saw marks) V forming a grinding trace of a dicing saw described later remain in a regular pattern. The reason why the rough surface region S and the streak pattern region P are present on each side surface is due to the manufacturing process of the chip resistor d1, and will be described in detail later.

  In each side surface, the rough surface region S occupies approximately half of the front surface d2A side, and the streak pattern region P occupies approximately half of the back surface d2B side. On each side surface, the streak pattern region P protrudes outward of the substrate d2 from the rough surface region S (outside the substrate d2 in a plan view). A step N is formed between them. The level difference N extends between the lower end edge of the rough surface region S and the upper end edge of the streak pattern region P and extends in parallel with the front surface d2A and the back surface d2B. The steps N on each side surface are connected to each other and form a rectangular frame body located between the edge d85 of the front surface d2A and the edge d90 of the back surface d2B in plan view.

Thus, since the level | step difference N is provided in each side surface, as above-mentioned, the back surface d2B is larger than the surface d2A.
In the substrate d2, the entire region of the surface d2A and the side surfaces d2C to d2F (both the rough surface region S and the streak pattern region P on each side surface) is covered with the passivation film d23. Therefore, strictly speaking, in FIG. 87 (a), the entire areas of the surface d2A and the side surfaces d2C to d2F are located inside (back side) of the passivation film d23 and are not exposed to the outside. Here, in the passivation film d23, a portion covering the surface d2A is referred to as a surface covering portion d23A, and a portion covering each of the side surfaces d2C to d2F is referred to as a side surface covering portion d23B.

Further, the chip resistor d1 has a resin film d24. The resin film d24 is a protective film (protective resin film) that is formed on the passivation film d23 and covers at least the entire surface d2A.
The passivation film d23 and the resin film d24 will be described in detail later.
The first connection electrode d3 and the second connection electrode d4 are formed in a region inside the edge portion d85 on the surface d2A of the substrate d2, and are partially exposed from the resin film d24 on the surface d2A. In other words, the resin film d24 covers the surface d2A (strictly, the passivation film d23 on the surface d2A) so as to expose the first connection electrode d3 and the second connection electrode d4. Each of the first connection electrode d3 and the second connection electrode d4 is configured by, for example, stacking Ni (nickel), Pd (palladium), and Au (gold) on the surface d2A in this order. The first connection electrode d3 and the second connection electrode d4 are spaced apart in the longitudinal direction of the surface d2A and are long in the short direction of the surface d2A. In FIG. 87A, on the surface d2A, the first connection electrode d3 is provided near the side surface d2C, and the second connection electrode d4 is provided near the side surface d2D.

  The element d5 is an element circuit network, and is formed on the substrate d2 (on the surface d2A), specifically, in a region between the first connection electrode d3 and the second connection electrode d4 on the surface d2A of the substrate d2. Further, it is covered from above with a passivation film d23 (surface covering portion d23A) and a resin film d24. The element d5 in this embodiment is a resistor d56. The resistor d56 is configured by a resistor network in which a plurality of (unit) resistors R having equal resistance values are arranged in a matrix on the surface d2A. Each resistor R is made of TiN (titanium nitride), TiON (titanium oxynitride) or TiSiON. The element d5 is electrically connected to a wiring film d22 described later, and is electrically connected to the first connection electrode d3 and the second connection electrode d4 via the wiring film d22.

  As shown in FIG. 87 (b), the first connection electrode d3 and the second connection electrode d4 are opposed to the mounting substrate d9, and are electrically connected to the pair of connection terminals d88 on the mounting substrate d9 by the solder d13. Connect mechanically. Thereby, the chip resistor d1 can be mounted on the mounting substrate d9 (flip chip connection). The first connection electrode d3 and the second connection electrode d4 that function as external connection electrodes are formed of gold (Au) or gold-plated on the surface in order to improve solder wettability and reliability. It is desirable.

FIG. 88 is a plan view of the chip resistor, showing the arrangement relationship between the first connection electrode, the second connection electrode and the element, and the configuration (layout pattern) of the element in plan view.
Referring to FIG. 88, element d5, which is a resistor network, includes eight resistors R arranged along the row direction (longitudinal direction of substrate d2) and along the column direction (width direction of substrate d2). A total of 352 resistors R composed of 44 resistors R arranged in this manner. These resistors R are a plurality of element elements that constitute a resistance network of the element d5.

  A plurality of types of resistor circuits R are formed by grouping and electrically connecting a large number of these resistors R every predetermined number of 1 to 64. The formed plurality of types of resistance circuits are connected in a predetermined manner by a conductor film D (a wiring film formed of a conductor). Furthermore, a plurality of fuses (fuses) that can be cut (fused) on the surface d2A of the substrate d2 in order to electrically incorporate a resistance circuit with respect to the element d5 or to electrically separate it from the element d5. F is provided. The plurality of fuses F and the conductor film D are arranged along the inner side of the second connection electrode d3 so that the arrangement region is linear. More specifically, the plurality of fuses F and the conductor film D are arranged so as to be adjacent to each other, and the arrangement direction thereof is linear. The plurality of fuses F respectively connect a plurality of types of resistor circuits (a plurality of resistors R for each resistor circuit) to the second connection electrode d3 so as to be cut (separable).

89A is a plan view illustrating a part of the element shown in FIG. 88 in an enlarged manner. FIG. 89B is a longitudinal sectional view in the length direction taken along the line BB of FIG. 89A drawn to explain the configuration of the resistor in the element. FIG. 89C is a longitudinal sectional view in the width direction along CC of FIG. 89A drawn to explain the configuration of the resistor in the element.
The configuration of the resistor R will be described with reference to FIGS. 89A, 89B, and 89C.

The chip resistor d1 further includes an insulating layer d20 and a resistor film d21 in addition to the wiring film d22, the passivation film d23, and the resin film d24 described above (see FIGS. 89B and 89C). The insulating layer d20, the resistor film d21, the wiring film d22, the passivation film d23, and the resin film d24 are formed on the substrate d2 (surface d2A).
The insulating layer d20 is made of SiO ₂ (silicon oxide). The insulating layer d20 covers the entire surface d2A of the substrate d2. The insulating layer d20 has a thickness of about 10,000 mm.

  The resistor film d21 is formed on the insulating layer d20. The resistor film d21 is formed of TiN, TiON, or TiSiON. The thickness of the resistor film d21 is about 2000 mm. The resistor film d21 constitutes a plurality of resistor films (hereinafter referred to as “resistor film line d21A”) extending linearly in parallel between the first connection electrode d3 and the second connection electrode d4. The resistor film line d21A may be cut at a predetermined position in the line direction (see FIG. 89A).

  A wiring film d22 is laminated on the resistor film line d21A. The wiring film d22 is made of Al (aluminum) or an alloy of aluminum and Cu (copper) (AlCu alloy). The thickness of the wiring film d22 is about 8000 mm. The wiring film d22 is laminated on the resistor film line d21A with a constant interval R in the line direction, and is in contact with the resistor film line d21A.

The electrical characteristics of the resistor film line d21A and the wiring film d22 having this configuration are shown by circuit symbols as shown in FIG. That is, as shown in FIG. 90A, each portion of the resistor film line d21A in the region of the predetermined interval R forms one resistor R having a certain resistance value r.
In the region where the wiring film d22 is laminated, the resistor film line d21A is short-circuited by the wiring film d22 by electrically connecting the resistors R adjacent to each other. Therefore, a resistance circuit is formed which is formed by connecting in series the resistor R of the resistor r shown in FIG. 90 (b).

  Further, since the adjacent resistor film lines d21A are connected by the resistor film d21 and the wiring film d22, the resistor network of the element d5 shown in FIG. 89A is shown in FIG. A resistor circuit (consisting of R unit resistors) is formed. As described above, the resistor film d21 and the wiring film d22 constitute the resistor R and the resistor circuit (that is, the element d5). Each resistor R includes a resistor film line d21A (resistor film d21) and a plurality of wiring films d22 stacked on the resistor film line d21A at regular intervals in the line direction. A resistor film line d21A at a constant interval R where d22 is not laminated constitutes one resistor R. The resistor film line d21A in the portion constituting the resistor R has the same shape and size. Therefore, the multiple resistors R arranged in a matrix on the substrate d2 have the same resistance value.

The wiring film d22 laminated on the resistor film line d21A forms the resistor R and also serves as a conductor film D for connecting a plurality of resistors R to form a resistor circuit. (See FIG. 88).
FIG. 91A is a partially enlarged plan view of a region including a fuse drawn by enlarging a part of the plan view of the chip resistor shown in FIG. 88, and FIG. 91B is a plan view of FIG. 91A. It is a figure which shows the cross-sectional structure which follows BB.

  As shown in FIGS. 91A and 91B, the above-described fuse F and conductor film D are also formed by the wiring film d22 laminated on the resistor film d21 forming the resistor R. That is, the fuse F and the conductor film D are formed on the same layer as the wiring film d22 laminated on the resistor film line d21A forming the resistor R by Al or AlCu alloy which is the same metal material as the wiring film d22. Yes. As described above, the wiring film d22 is also used as a conductor film D for electrically connecting a plurality of resistors R in order to form a resistance circuit.

  That is, in the same layer laminated on the resistor film d21, the wiring film for forming the resistor R, the fuse F, the conductor film D, and the element d5 are connected to the first connection electrode d3 and the second connection electrode d3. A wiring film for connection to the connection electrode d4 is formed using the same metal material (Al or AlCu alloy) as the wiring film d22. Note that the fuse F is made different from (differentiated from) the wiring film d22 because the fuse F is thinly formed so that it can be easily cut, and there are no other circuit elements around the fuse F. This is because they are arranged in such a manner.

  Here, in the wiring film d22, a region where the fuse F is arranged is referred to as a trimming target region X (see FIGS. 88 and 91A). The trimming target region X is a linear region along the inner side of the second connection electrode d3, and not only the fuse F but also the conductor film D is disposed in the trimming target region X. A resistor film d21 is also formed below the wiring film d22 in the trimming target region X (see FIG. 91B). The fuse F is a wiring having a larger inter-wiring distance (separated from the surroundings) than the portion other than the trimming target region X in the wiring film d22.

The fuse F indicates not only a part of the wiring film d22 but also a group (fuse element) of a part of the resistor R (resistor film d21) and a part of the wiring film d22 on the resistor film d21. It may be.
Further, the fuse F has been described only in the case where the same layer as the conductor film D is used. However, in the conductor film D, another conductor film is further laminated thereon to lower the resistance value of the entire conductor film D. You may do it. Even in this case, if a conductive film is not laminated on the fuse F, the fusing property of the fuse F will not deteriorate.

FIG. 92 is an electric circuit diagram of an element according to the embodiment of the fourth reference example.
Referring to FIG. 92, element d5 includes reference resistor circuit R8, resistor circuit R64, two resistor circuits R32, resistor circuit R16, resistor circuit R8, resistor circuit R4, resistor circuit R2, resistor circuit R1, resistor circuit R. / 2, resistor circuit R / 4, resistor circuit R / 8, resistor circuit R / 16, resistor circuit R / 32 are connected in series in this order from the first connection electrode d3. Each of the reference resistor circuit R8 and the resistor circuits R64 to R2 is configured by connecting in series the same number of resistors R as the last number (“64” in the case of R64). The resistor circuit R1 is composed of one resistor R. Each of the resistance circuits R / 2 to R / 32 is configured by connecting in parallel the same number of resistors R as the last number of itself (“32” in the case of R / 32). The meaning of the number at the end of the resistor circuit is the same in FIGS. 93 and 94 described later.

One fuse F is connected in parallel to each of the resistor circuits R64 to R / 32 other than the reference resistor circuit R8. The fuses F are connected in series either directly or via a conductor film D (see FIG. 91A).
In a state where all the fuses F are not blown as shown in FIG. 92, the element d5 is a reference composed of eight resistors R provided in series between the first connection electrode d3 and the second connection electrode d4. A resistor circuit of the resistor circuit R8 is configured. For example, if the resistance value r of one resistor R is r = 8Ω, the chip resistor in which the first connection electrode d3 and the second connection electrode d4 are connected by a resistance circuit (reference resistance circuit R8) of 8r = 64Ω. A container d1 is configured.

  Further, in a state where all the fuses F are not blown, a plurality of types of resistor circuits other than the reference resistor circuit R8 are short-circuited. That is, 12 types and 13 resistor circuits R64 to R / 32 are connected in series to the reference resistor circuit R8, but each resistor circuit is short-circuited by the fuse F connected in parallel. From an electrical viewpoint, each resistance circuit is not incorporated in the element d5.

  In the chip resistor d1 according to this embodiment, the fuse F is selectively blown by, for example, laser light according to a required resistance value. Thereby, the resistance circuit in which the fuse F connected in parallel is blown is incorporated in the element d5. Therefore, the entire resistance value of the element d5 can be set to a resistance value in which resistance circuits corresponding to the blown fuse F are connected in series.

  In particular, a plurality of types of resistor circuits have one, two, four, eight, sixteen, thirty-two, etc. resistors R having the same resistance value in series, and a geometric sequence having a common ratio of two. The number of resistors R is increased, and a plurality of types of series resistor circuits and resistors R having the same resistance value are connected in parallel to 2, 4, 8, 16,. A plurality of types of parallel resistance circuits are provided which are connected by increasing the number of resistors R in a geometric sequence. Therefore, by selectively blowing the fuse F (including the above-described fuse element), the resistance value of the entire element d5 (resistor d56) is adjusted finely and digitally to an arbitrary resistance value. Thus, a resistor having a desired value can be generated in the chip resistor d1.

FIG. 93 is an electric circuit diagram of an element according to another embodiment of the fourth reference example.
Instead of configuring the element d5 by connecting the reference resistor circuit R8 and the resistor circuit R64 to the resistor circuit R / 32 in series as illustrated in FIG. 92, the element d5 may be configured as illustrated in FIG. Specifically, between the first connection electrode d3 and the second connection electrode d4, a reference resistance circuit R / 16 and 12 types of resistance circuits R / 16, R / 8, R / 4, R / 2, R1, R2 , R4, R8, R16, R32, R64, and R128, the element d5 may be configured by a series connection circuit with a parallel connection circuit.

  In this case, a fuse F is connected in series to each of the 12 types of resistor circuits other than the reference resistor circuit R / 16. In a state where all the fuses F are not blown, each resistance circuit is electrically incorporated into the element d5. If the fuse F is selectively blown by, for example, laser light according to the required resistance value, the resistance circuit corresponding to the blown fuse F (the resistance circuit in which the fuse F is connected in series) becomes the element d5. Therefore, the resistance value of the entire chip resistor d1 can be adjusted.

FIG. 94 is an electric circuit diagram of an element according to still another embodiment of the fourth reference example.
The feature of the element d5 shown in FIG. 94 is that the circuit configuration is such that a plurality of types of resistor circuits connected in series and a plurality of types of resistor circuits connected in series are connected in series. As in the previous embodiment, fuses F are connected in parallel to each of the plurality of resistor circuits connected in series, and the plurality of resistor circuits connected in series are all short-circuited by the fuse F. It is in a state. Therefore, when the fuse F is blown, the resistance circuit short-circuited by the blown fuse F is electrically incorporated into the element d5.

On the other hand, a fuse F is connected in series to each of the plurality of types of resistor circuits connected in parallel. Therefore, by blowing the fuse F, the resistor circuit to which the blown fuse F is connected in series can be electrically disconnected from the parallel connection of the resistor circuit.
With this configuration, for example, a small resistance of 1 kΩ or less is made on the parallel connection side, and if a resistance circuit of 1 kΩ or more is made on the series connection side, a wide range from a small resistance of several Ω to a large resistance of several MΩ is obtained. Resistor circuits can be made using a network of resistors constructed with an equal basic design. That is, the chip resistor d1 can easily and quickly cope with a plurality of types of resistance values by selecting and cutting one or a plurality of fuses F. In other words, by combining a plurality of resistors R having different resistance values, chip resistors d1 having various resistance values can be realized with a common design.

As described above, in this chip resistor d1, the connection state of the plurality of resistors R (resistance circuit) can be changed in the trimming target region X.
FIG. 95 is a schematic cross-sectional view of a chip resistor.
Next, the chip resistor d1 will be described in more detail with reference to FIG. For convenience of explanation, in FIG. 95, the element d5 described above is simplified and each element other than the substrate d2 is hatched.

Here, the passivation film d23 and the resin film d24 described above will be described.
The passivation film d23 is made of, for example, SiN (silicon nitride), and has a thickness of 1000 to 5000 mm (here, about 3000 mm). As described above, the passivation film d23 includes the surface covering portion d23A provided over the entire area of the surface d2A and the side surface covering portion d23B provided over the entire area of each of the side surfaces d2C to d2F. The surface covering portion d23A covers the resistor film d21 and each wiring film d22 on the resistor film d21 (that is, the element d5) from the surface (upper side in FIG. 95), and the upper surface of each resistor R in the element d5. Covering. Therefore, the surface covering portion d23A also covers the wiring film d22 in the trimming target region X described above (see FIG. 91B). The surface covering portion d23A is in contact with the element d5 (the wiring film d22 and the resistor film d21), and is also in contact with the insulating layer d20 in a region other than the resistor film d21. Thus, the surface covering portion d23A functions as a protective film that covers the entire surface d2A and protects the element d5 and the insulating layer d20. Further, on the surface d2A, the surface covering portion d23A prevents a short circuit other than the wiring film d22 between the resistors R (short circuit between adjacent resistor film lines d21A).

On the other hand, the side surface covering portion d23B provided on each of the side surfaces d2C to d2F functions as a protective layer that protects each of the side surfaces d2C to d2F. The side surface covering portion d23B covers all of the rough surface region S and the streak pattern region P in each of the side surfaces d2C to d2F, and also covers the step N between the rough surface region S and the streak pattern region P without leakage. ing.
Further, the boundary between each of the side surfaces d2C to d2F and the surface d2A is the edge d85 described above, but the passivation film d23 also covers the boundary (edge d85). In the passivation film d23, a portion covering the edge d85 (a portion overlapping the edge d85) is referred to as an end d23C.

  The resin film d24 protects the surface d2A of the chip resistor d1 together with the passivation film d23, and is made of a resin such as polyimide. The resin film d24 is on the surface coating portion d23A (including the above-described end portion d23C) of the passivation film d23 so as to cover all regions other than the first connection electrode d3 and the second connection electrode d4 on the surface d2A in plan view. Is formed. Therefore, the resin film d24 covers the entire surface of the surface covering portion d23A (including the element d5 and the fuse F covered by the surface covering portion d23A) on the surface d2A. On the other hand, the resin film d24 does not cover the side surfaces d2C to d2F. Therefore, the edge 24A on the outer periphery of the resin film d24 is aligned with the side surface covering portion d23B in a plan view, and the side end surface d24B of the resin film d24 at the edge 24A is the side surface covering portion d23B (strictly speaking, the rough surface of each side surface). It is flush with the side surface covering portion d23B) in the surface area S and extends in the thickness direction of the substrate d2. The surface d24C of the resin film d24 extends flat so as to be parallel to the surface d2A of the substrate d2. When stress is applied to the surface d2A side of the substrate d2 in the chip resistor d1, the surface d24C of the resin film d24 (particularly, the surface d24C in the region between the first connection electrode d3 and the second connection electrode d4) Functions as a stress dispersion surface and disperses the stress.

  In the resin film d24, one opening d25 is formed at two positions separated from each other in plan view. Each opening d25 is a through-hole that continuously penetrates the resin film d24 and the passivation film d23 (surface covering portion d23A) in each thickness direction. Therefore, the opening d25 is formed not only in the resin film d24 but also in the passivation film d23. A part of the wiring film d22 is exposed from each opening d25. A portion exposed from each opening d25 in the wiring film d22 is a pad region d22A (pad) for external connection. Each opening d25 extends along the thickness direction of the surface covering portion d23A (same as the thickness direction of the substrate d2) in the surface covering portion d23A, and in the resin film d24, the resin film d24 from the surface covering portion d23A side. The surface gradually spreads in the longitudinal direction of the substrate d2 (left and right direction in FIG. 95) toward the surface d24C. Therefore, the section screen d24D that partitions the opening d25 in the resin film d24 is an inclined surface that intersects the thickness direction of the substrate d2. In the resin film d24, a portion bordering each opening d25 has a pair of partition screens d24D that partitions the opening d25 from the longitudinal direction. The interval between the partition screens d24D is on the surface covering portion d23A side. Gradually spreads from the surface toward the surface d24C of the resin film d24. Further, in the resin film d24, there is another pair of section screens d24D that divides the openings d25 from the short direction of the substrate d2 (not shown in FIG. 95). The interval between these section screens d24D may also gradually increase from the surface covering portion d23A side toward the surface d24C of the resin film d24.

  Of the two openings d25, one opening d25 is filled with the first connection electrode d3, and the other opening d25 is filled with the second connection electrode d4. Each of the first connection electrode d3 and the second connection electrode d4 extends toward the surface d24C of the resin film d24 according to the opening d25 that extends toward the surface d24C of the resin film d24. Therefore, each longitudinal section (cut surface when cut along a plane along the longitudinal direction and the thickness direction of the substrate d2) of the first connection electrode d3 and the second connection electrode d4 is an upper base on the surface d2A side of the substrate d2. And has a trapezoidal shape having a lower base on the surface d24C side of the resin film d24. In addition, the lower bottoms are the surfaces d3A and 4A in the first connection electrode d3 and the second connection electrode d4, respectively. In each of the surfaces d3A and d4A, the end on the opening d25 side is the surface d2A side of the substrate d2 Curved to When the opening d25 does not expand toward the surface d24C of the resin film d24 (the section screen d24D that defines the opening d25 extends in the thickness direction of the substrate d2), each of the surfaces d3A and d4A is In all the regions including the end on the opening d25 side, the surface becomes a flat surface along the surface d2A of the substrate d2.

  Further, as described above, each of the first connection electrode d3 and the second connection electrode d4 is configured by stacking Ni, Pd, and Au on the surface d2A in this order, so that the Ni layer d33, Pd The layer d34 and the Au layer d35 are provided in this order from the surface d2A side. Therefore, a Pd layer d34 is interposed between the Ni layer d33 and the Au layer d35 in each of the first connection electrode d3 and the second connection electrode d4. In each of the first connection electrode d3 and the second connection electrode d4, the Ni layer d33 occupies most of each connection electrode, and the Pd layer d34 and the Au layer d35 are formed much thinner than the Ni layer d33. ing. When the chip resistor d1 is mounted on the mounting substrate d9 (see FIG. 87 (b)), the Ni layer d33 relays the Al of the wiring film d22 in the pad region d22A of each opening d25 and the solder d13 described above. Have a role to play.

  In the first connection electrode d3 and the second connection electrode d4, since the surface of the Ni layer d33 is covered with the Au layer d35 via the Pd layer d34, the Ni layer d33 can be prevented from being oxidized. Even if the Au layer d35 is thinned to form a through hole (pinhole) in the Au layer d35, the Pd layer d34 interposed between the Ni layer d33 and the Au layer d35 has the through hole formed therein. Since it is plugged, it is possible to prevent the Ni layer d33 from being exposed to the outside through the through hole and being oxidized.

  In each of the first connection electrode d3 and the second connection electrode d4, the Au layer d35 is exposed on the outermost surface as the surfaces d3A and d4A, and faces the outside from the opening d25 on the surface d24A of the resin film d24. Yes. The first connection electrode d3 is electrically connected to the wiring film d22 in the pad region d22A in the opening d25 through one opening d25. The second connection electrode d4 is electrically connected to the wiring film d22 in the pad region d22A in the opening d25 through the other opening d25. In each of the first connection electrode d3 and the second connection electrode d4, the Ni layer d33 is connected to the pad region d22A. Thereby, each of the first connection electrode d3 and the second connection electrode d4 is electrically connected to the element d5. Here, the wiring film d22 forms a wiring connected to each of the group of resistors R (resistor d56), the first connection electrode d3, and the second connection electrode d4.

  Thus, the resin film d24 and the passivation film d23 in which the opening d25 is formed cover the surface d2A in a state where the first connection electrode d3 and the second connection electrode d4 are exposed from the opening d25. Therefore, electrical connection between the chip resistor d1 and the mounting substrate d9 can be achieved via the first connection electrode d3 and the second connection electrode d4 exposed in the opening d25 on the surface d24C of the resin film d24. (See FIG. 87 (b)).

  Here, the thickness H of the resin film d24, that is, the height H from the surface d2A of the substrate d2 to the surface d24C of the resin film d24 is (from the surface d2A of each of the first connection electrode d3 and the second connection electrode d4). ) Height J or more. In FIG. 95, as the first embodiment, the height H and the height J are the same, and the surface d24C of the resin film d24 and the respective surfaces d3A of the first connection electrode d3 and the second connection electrode d4. , D4A are flush with each other.

96A to 96H are schematic sectional views showing a method for manufacturing the chip resistor shown in FIG.
First, as shown in FIG. 96A, a substrate d30 as a base of the substrate d2 is prepared. In this case, the surface d30A of the substrate d30 is the surface d2A of the substrate d2, and the back surface d30B of the substrate d30 is the back surface d2B of the substrate d2.

Then, the surface d30A of the substrate d30 is thermally oxidized to form an insulating layer d20 made of SiO ₂ or the like on the surface d30A, and the element d5 (the resistor R and the wiring film d22 connected to the resistor R is formed on the insulating layer d20. ). Specifically, first, a resistor film d21 of TiN, TiON, or TiSiON is formed on the entire surface of the insulating layer d20 by sputtering, and further, aluminum is formed on the resistor film d21 so as to be in contact with the resistor film d21. A wiring film d22 of (Al) is laminated. Thereafter, using a photolithography process, the resistor film d21 and the wiring film d22 are selectively removed and patterned by dry etching such as RIE (Reactive Ion Etching), for example, as shown in FIG. In a plan view, a configuration is obtained in which resistor film lines d21A having a certain width on which the resistor films d21 are stacked are arranged in the column direction with a certain interval. At this time, a region in which the resistor film line d21A and the wiring film d22 are partially cut is also formed, and the fuse F and the conductor film D are formed in the above-described trimming target region X (see FIG. 88). Subsequently, the wiring film d22 laminated on the resistor film line d21A is selectively removed by, for example, wet etching and patterned. As a result, an element d5 (in other words, a plurality of resistors R) having a configuration in which the wiring film d22 is laminated at a predetermined interval R on the resistor film line d21A is obtained. In this way, the fuses F can be easily formed together with the plurality of resistors R by simply laminating the wiring film d22 on the resistor film d21 and patterning the resistor film d21 and the wiring film d22. In order to confirm whether or not the resistor film d21 and the wiring film d22 are formed with target dimensions, the resistance value of the entire element d5 may be measured.

  Referring to FIG. 96A, elements d5 are formed at a number of locations on surface d30A of substrate d30 according to the number of chip resistors d1 formed on one substrate d30. One region where the element d5 (the resistor d56 described above) is formed on the substrate d30 is referred to as a chip component region Y. On the surface d30A of the substrate d30, a plurality of chip component regions Y each having a resistor d56 are provided. (That is, element d5) is formed (set). One chip component region Y coincides with a plan view of one completed chip resistor d1 (see FIG. 95). A region between adjacent chip component regions Y on the surface d30A of the substrate d30 is referred to as a boundary region Z. The boundary region Z has a belt shape and extends in a lattice shape in plan view. One chip component region Y is arranged in one lattice defined by the boundary region Z. Since the width of the boundary region Z is as very narrow as 1 μm to 60 μm (for example, 20 μm), a large number of chip component regions Y can be secured on the substrate d30, and as a result, mass production of the chip resistors d1 becomes possible.

  Next, as shown in FIG. 96A, an insulating film d45 made of SiN is formed over the entire surface d30A of the substrate d30 by a CVD (Chemical Vapor Deposition) method. The insulating film d45 covers and covers all of the insulating layer d20 and the element d5 (resistor film d21 and wiring film d22) on the insulating layer d20. Therefore, the insulating film d45 also covers the wiring film d22 in the trimming target region X (see FIG. 88). Further, since the insulating film d45 is formed over the entire area of the surface d30A of the substrate d30, the insulating film d45 is formed to extend to a region other than the trimming target region X on the surface d30A. Thereby, the insulating film d45 becomes a protective film for protecting the entire surface d30A (including the element d5 on the surface d30A).

Next, as shown in FIG. 96B, a resist pattern d41 is formed over the entire surface d30A of the substrate d30 so as to cover the entire insulating film d45. An opening d42 is formed in the resist pattern d41.
FIG. 97 is a schematic plan view of a part of the resist pattern used for forming the first groove in the step of FIG. 96B.

  Referring to FIG. 97, the opening d42 of the resist pattern d41 is a plan view when a large number of chip resistors d1 (in other words, the above-described chip component region Y) are arranged in a matrix (also in a lattice shape). It corresponds (corresponds) to the area between the outlines of the adjacent chip resistors d1 (the hatched part in FIG. 97, in other words, the boundary area Z). Therefore, the overall shape of the opening d42 is a lattice shape having a plurality of linear portions d42A and d42B orthogonal to each other.

In the resist pattern d41, the straight portions d42A and d42B orthogonal to each other in the opening d42 are connected to each other while maintaining a state orthogonal to each other (without bending). Therefore, the intersecting portion d43 of the straight portions d42A and d42B is pointed so as to form approximately 90 ° in plan view.
Referring to FIG. 96B, each of insulating film d45, insulating layer d20, and substrate d30 is selectively removed by plasma etching using resist pattern d41 as a mask. Thereby, the material of the substrate d30 is etched (removed) in the boundary region Z between the adjacent elements d5 (chip component region Y). As a result, the position (boundary region Z) that coincides with the opening d42 of the resist pattern d41 in plan view passes through the insulating film d45 and the insulating layer d20 and reaches the middle of the thickness of the substrate d30 from the surface d30A of the substrate d30. A first groove d44 having a predetermined depth is formed. The first groove d44 is partitioned by a pair of side surfaces d44A facing each other and a bottom surface d44B connecting the lower ends of the pair of side surfaces d44A (the end on the back surface d30B side of the substrate d30). The depth of the first groove d44 with reference to the surface d30A of the substrate d30 is about half of the thickness T (see FIG. 87A) of the completed chip resistor d1, and the width of the first groove d44 (opposing) M) is about 20 μm, and is constant over the entire depth direction. Among the etching, the first groove d44 can be formed with high accuracy by using plasma etching in particular.

  The overall shape of the first groove d44 in the substrate d30 is a lattice shape that coincides with the opening d42 (see FIG. 97) of the resist pattern d41 in plan view. On the surface d30A of the substrate d30, a rectangular frame portion (boundary region Z) in the first groove d44 surrounds the chip component region Y where each element d5 is formed. The part where the element d5 is formed on the substrate d30 is a semi-finished product d50 of the chip resistor d1. On the surface d30A of the substrate d30, the semi-finished products d50 are located one by one in the chip component region Y surrounded by the first groove d44, and these semi-finished products d50 are arranged in a matrix.

  After the first groove d44 is formed as shown in FIG. 96B, the resist pattern d41 is removed, and as shown in FIG. 96C, a dicing machine (not shown) having a dicing saw d47 is operated. The dicing saw d47 is a disc-shaped grindstone, and a cutting tooth portion is formed on the peripheral end surface thereof. The width Q (thickness) of the dicing saw d47 is smaller than the width M of the first groove d44. Here, the dicing line U is set at the central position of the first groove d44 (position equidistant from the pair of side surfaces d44A facing each other). The dicing saw d47 moves along the dicing line U in the first groove d44 in a state where the central position 47A in the thickness direction coincides with the dicing line U in plan view, and at this time, the bottom surface of the first groove d44 The substrate d30 is scraped from d44B. When the movement of the dicing saw d47 is completed, a second groove d48 having a predetermined depth dug down from the bottom surface d44B of the first groove d44 is formed on the substrate d30.

  The second groove d48 is continuous from the bottom surface d44B of the first groove d44 and is recessed toward the back surface d30B side of the substrate d30 at a predetermined depth. The second groove d48 is partitioned by a pair of side surfaces d48A facing each other and a bottom surface d48B connecting the lower ends of the pair of side surfaces d48A (the end on the back surface d30B side of the substrate d30). The depth of the second groove d48 with respect to the bottom surface d44B of the first groove d44 is about half of the thickness T of the completed chip resistor d1, and the width of the second groove d48 (the distance between the opposing side surfaces d48A). Is the same as the width Q of the dicing saw d47, and is constant over the entire region in the depth direction. In the first groove d44 and the second groove d48, between the side surface d44A and the side surface d48A adjacent to each other in the thickness direction of the substrate d30, the direction perpendicular to the thickness direction (the direction along the surface d30A of the substrate d30). An extending step d49 is formed. Therefore, a group of continuous first grooves d44 and second grooves d48 has a convex shape that becomes narrower toward the back surface d30B. The side surface d44A becomes the rough surface region S of each side surface (each of the side surfaces d2C to d2F) in the completed chip resistor d1, the side surface d48A becomes the streak pattern region P of each side surface in the chip resistor d1, and the step d49 is formed. The level difference N on each side surface of the chip resistor d1.

  Here, by forming the first groove d44 by etching, each of the side surfaces d44A and the bottom surface d44B has a rough surface with an irregular pattern. On the other hand, by forming the second groove d48 with the dicing saw d47, a large number of streaks forming a grinding mark of the dicing saw d47 remain in a regular pattern on each side surface d48A. Even if the side surface d48A is etched, this streak cannot be completely erased, and the finished chip resistor d1 becomes the streak V described above (see FIG. 87A).

  Next, as shown in FIG. 96D, the insulating film d45 is selectively removed by etching using the mask d65. In the mask d65, an opening d66 is formed in a portion of the insulating film d45 that coincides with each pad region d22A (see FIG. 95) in plan view. Thereby, a portion of the insulating film d45 that coincides with the opening d66 is removed by etching, and an opening d25 is formed in the portion. Thus, the insulating film d45 is formed so as to expose each pad region d22A in the opening d25. Two openings d25 are formed for one semi-finished product d50.

  In each semi-finished product d50, after the two openings d25 are formed in the insulating film d45, the probe d70 of the resistance measuring device (not shown) is brought into contact with the pad region d22A of each opening d25, so that the entire resistance value of the element d5 is obtained. Is detected. Then, by irradiating an arbitrary fuse F (see FIG. 88) with a laser beam (not shown) through the insulating film d45, the wiring film d22 in the trimming target region X is trimmed with the laser beam, and the fuse F is melted. In this way, by fusing (trimming) the fuse F so as to have a necessary resistance value, the resistance value of the entire semi-finished product d50 (in other words, the chip resistor d1) can be adjusted as described above. At this time, since the insulating film d45 is a cover film that covers the element d5, it is possible to prevent a short circuit from occurring due to debris or the like generated at the time of fusing attached to the element d5. Further, since the insulating film d45 covers the fuse F (resistor film d21), the energy of the laser beam can be stored in the fuse F and the fuse F can be blown reliably.

  Thereafter, SiN is formed on the insulating film d45 by the CVD method, and the insulating film d45 is thickened. At this time, as shown in FIG. 96E, the insulating film d45 is also formed over the entire inner peripheral surfaces (the above-described side surface d44A, bottom surface d44B, side surface d48A, and bottom surface d48B) of the first groove d44 and the second groove d48. Therefore, the insulating film d45 is also formed on the step d49 described above. The insulating film d45 (the insulating film d45 in the state shown in FIG. 96E) on the inner peripheral surfaces of the first groove d44 and the second groove d48 has a thickness of 1000 to 5000 mm (here, about 3000 mm). ing. At this time, a part of the insulating film d45 enters each opening d25 and closes the opening d25.

  Thereafter, a photosensitive resin liquid made of polyimide is spray-applied onto the substrate d30 from above the insulating film d45 to form a photosensitive resin film d46 as shown in FIG. 96E. At this time, the liquid is passed through a mask (not shown) having a pattern covering only the first groove d44 and the second groove d48 in a plan view so that the liquid does not enter the first groove d44 and the second groove d48. A liquid is applied to the substrate d30. As a result, the liquid photosensitive resin is formed only on the substrate d30, and becomes a resin film d46 (resin film) on the substrate d30. The surface d46A of the resin film d46 on the surface d30A is flat along the surface d30A.

  Since the liquid does not enter the first groove d44 and the second groove d48, the resin film d46 is not formed in the first groove d44 and the second groove d48. In addition to spraying the photosensitive resin liquid, the resin film d46 may be formed by spin-coating the liquid or by attaching a sheet made of the photosensitive resin to the surface d30A of the substrate d30. Good.

Next, heat treatment (curing treatment) is performed on the resin film d46. As a result, the thickness of the resin film d46 is thermally contracted, and the resin film d46 is cured to stabilize the film quality.
Next, as shown in FIG. 96F, the resin film d46 is patterned, and portions of the resin film d46 on the surface d30A that coincide with the pad regions d22A (openings d25) of the wiring film d22 in plan view are selectively removed. Specifically, the resin film d46 is exposed and developed with the pattern using a mask d62 in which an opening d61 having a pattern that matches (matches) with each pad region d22A in plan view. Thereby, the resin film d46 is separated above each pad region d22A to form an opening d25. At this time, the portion of the resin film d46 that borders the opening d25 is thermally contracted, and the section screen d46B that partitions the opening d25 in the portion becomes an inclined surface that intersects the thickness direction of the substrate d30. As a result, as described above, the opening d25 is in a state of being widened toward the surface d46A of the resin film d46 (which becomes the surface d24C of the resin film d24).

Next, the insulating film d45 on each pad region d22A is removed by RIE using a mask (not shown), thereby opening each opening d25 and exposing the pad region d22A.
Next, by forming an Ni / Pd / Au laminated film formed by laminating Ni, Pd and Au on the pad region d22A in each opening d25 by electroless plating, as shown in FIG. A first connection electrode d3 and a second connection electrode d4 are formed on the region d22A.

FIG. 98 is a diagram for explaining a manufacturing process of the first connection electrode and the second connection electrode.
Specifically, referring to FIG. 98, first, the surface of pad region d22A is purified to remove (degrease) organic matter (including smut such as carbon stains and oily dirt) on the surface. (Step S1). Next, the oxide film on the surface is removed (step S2). Next, a zincate process is performed on the surface, and Al (of the wiring film d22) on the surface is replaced with Zn (step S3). Next, Zn on the surface is peeled off with nitric acid or the like, and new Al is exposed in the pad region d22A (step S4).

Next, Ni plating is performed on the surface of new Al in the pad region d22A by immersing the pad region d22A in a plating solution. Thereby, Ni in the plating solution is chemically reduced and deposited, and a Ni layer d33 is formed on the surface (step S5).
Next, Pd plating is performed on the surface of the Ni layer d33 by immersing the Ni layer d33 in another plating solution. Thereby, Pd in the plating solution is chemically reduced and deposited, and a Pd layer d34 is formed on the surface of the Ni layer d33 (step S6).

  Next, by immersing the Pd layer d34 in another plating solution, Au plating is performed on the surface of the Pd layer d34. Thereby, Au in the plating solution is chemically reduced and deposited, and an Au layer d35 is formed on the surface of the Pd layer d34 (step S7). Thereby, the first connection electrode d3 and the second connection electrode d4 are formed, and when the first connection electrode d3 and the second connection electrode d4 after the formation are dried (step S8), the first connection electrode d3 and the second connection electrode The manufacturing process of the electrode d4 is completed. In addition, the process of wash | cleaning the semi-finished product d50 with water is implemented suitably between the steps which follow. In addition, the zincate process may be performed a plurality of times.

  FIG. 96G shows a state after the first connection electrode d3 and the second connection electrode d4 are formed in each semi-finished product d50. In each of the first connection electrode d3 and the second connection electrode d4, the surfaces d3A and d4A are flush with the surface d46A of the resin film d46. In addition, according to the fact that the section screen d46B that partitions the opening d25 in the resin film d46 is inclined as described above, the opening d25 is formed on the surfaces d3A and d4A in the first connection electrode d3 and the second connection electrode d4, respectively. The edge on the edge side of the substrate is curved toward the back surface d30B side of the substrate d30. Therefore, in each of the first connection electrode d3 and the second connection electrode d4, the edge part on the edge side of the opening d25 in each of the Ni layer d33, the Pd layer d34, and the Au layer d35 is curved toward the back surface d30B side of the substrate d30. Yes.

  As described above, since the first connection electrode d3 and the second connection electrode d4 are formed by electroless plating, the first connection is compared with the case where the first connection electrode d3 and the second connection electrode d4 are formed by electrolytic plating. It is possible to improve the productivity of the chip resistor d1 by reducing the number of steps of forming the electrode d3 and the second connection electrode d4 (for example, a lithography step necessary for electrolytic plating, a resist mask peeling step, etc.). Furthermore, in the case of electroless plating, since a resist mask required for electrolytic plating is not required, the formation positions of the first connection electrode d3 and the second connection electrode d4 are displaced due to the displacement of the resist mask. Since it does not occur, the formation position accuracy of the first connection electrode d3 and the second connection electrode d4 can be improved, and the yield can be improved. Also, the first connection electrode d3 and the second connection electrode d4 can be formed only on the pad region d22A by performing electroless plating on the pad region d22A exposed from the resin film d24.

  In the case of electrolytic plating, the plating solution generally contains Ni or Sn. Therefore, Sn remaining on the surfaces d3A and d4A of the first connection electrode d3 and the second connection electrode d4 is oxidized, thereby connecting the first connection electrode d3, the second connection electrode d4, and the connection terminal d88 (see FIG. 87 (b)) may occur, but there is no such problem in the fourth reference example using electroless plating.

After the first connection electrode d3 and the second connection electrode d4 are formed in this way, a current inspection between the first connection electrode d3 and the second connection electrode d4 is performed, and then the substrate d30 is ground from the back surface d30B. The
Specifically, as shown in FIG. 96H, a support tape d71 having a thin plate shape made of PET (polyethylene terephthalate) and having an adhesive surface d72 is formed on the adhesive surface d72 by the first connection electrode d3 and the semi-finished product d50. It is attached to the second connection electrode d4 side (that is, the surface d30A). Thereby, each semi-finished product d50 is supported by the support tape d71. Here, as the support tape d71, for example, a laminate tape can be used.

  In a state where each semi-finished product d50 is supported by the support tape d71, the substrate d30 is ground from the back surface d30B side. When the substrate d30 is thinned until the back surface d30B reaches the bottom surface d48B (see FIG. 96G) of the second groove d48 by grinding, there is no connection between the adjacent semi-finished products d50. The substrate d30 is divided with the two grooves d48 as a boundary, and the semi-finished product d50 is individually separated to be a finished product of the chip resistor d1. That is, the substrate d30 is cut (divided) in the first groove d44 and the second groove d48 (in other words, the boundary region Z), and thereby the individual chip resistors d1 are cut out. The thickness of the substrate d30 (substrate d2) after grinding the back surface d30B is 150 μm to 400 μm (150 μm to 400 μm).

  In each completed chip resistor d1, the portion that formed the side surface d44A of the first groove d44 becomes the rough surface region S of any of the side surfaces d2C to d2F of the substrate d2, and forms the side surface d48A of the second groove d48. This portion becomes the streak pattern region P on any one of the side surfaces d2C to d2F of the substrate d2, and the step d49 between the side surface d44A and the side surface d48A becomes the above-described step N. In each completed chip resistor d1, the back surface d30B becomes the back surface d2B. That is, as described above, the step of forming the first groove d44 and the second groove d48 (see FIGS. 96B and 96C) is included in the step of forming the side surfaces d2C to d2F. Further, the insulating film d45 becomes the passivation film d23, and the resin film d46 becomes the resin film d24.

  For example, even if the depth of the first groove d44 (see FIG. 96B) formed by etching is not uniform, if the second groove d48 is formed by the dicing saw d47 (see FIG. 96C), the first groove d44 and the first groove d44 The entire depth of the two grooves d48 (the depth from the surface d30A of the substrate d30 to the bottom of the second groove d48) is uniform. Therefore, when the chip resistor d1 is separated into pieces by grinding the back surface d30B of the substrate d30, the time difference between the chip resistors d1 until they are separated from the substrate d30 is reduced, and the chip resistors d1 are made almost simultaneously. It can be separated from the substrate d30. As a result, it is possible to suppress a problem that chipping occurs in the chip resistor d1 due to the previously separated chip resistor d1 repeatedly colliding with the substrate d30. Further, since the corner (corner portion d11) on the surface d2A side of the chip resistor d1 is partitioned by the first groove d44 formed by etching, the corner portion d11 is partitioned by the dicing saw d47. In comparison, chipping is less likely to occur. As a result, chipping can be suppressed when the chip resistor d1 is singulated, and occurrence of defective singulation can be avoided. That is, the shape of the corner d11 (see FIG. 87A) on the surface d2A side of the chip resistor d1 can be controlled. In addition, compared with the case where both the first groove d44 and the second groove d48 are formed by etching, the time required for separating the chip resistor d1 is shortened, and the productivity of the chip resistor d1 is improved. You can also.

  In particular, when the thickness of the substrate d2 in the separated chip resistor d1 is as relatively large as 150 μm to 400 μm, a groove (from the surface d30A of the substrate d30 to the bottom surface d48B of the second groove d48 only by etching) (See FIG. 96C) is difficult and time consuming. However, even in such a case, the chip resistor is formed by grinding the back surface d30B of the substrate d30 after forming the first groove d44 and the second groove d48 using etching and dicing by the dicing saw d47 in combination. It is possible to shorten the time required for dividing d1. Therefore, the productivity of the chip resistor d1 can be improved.

  Further, if the second groove d48 reaches the back surface d30B of the substrate d30 by dicing (if the second groove d48 penetrates the substrate d30), the completed chip resistor d1 has a back surface d2B and side surfaces d2C˜. Chipping may occur at the corner with d2F. However, if half dicing is performed so that the second groove d48 does not reach the back surface d30B as in the fourth reference example (see FIG. 96C), and the back surface d30B is polished, the corner portion between the back surface d2B and the side surfaces d2C to d2F. Chipping hardly occurs.

  Further, when a groove reaching only the surface d30A of the substrate d30 to the bottom surface d48B of the second groove d48 is formed by etching alone, the side surface of the completed groove does not follow the thickness direction of the substrate d2 due to variations in the etching rate. The cross section of is difficult to be rectangular. That is, the side surface of the groove varies. However, by using etching and dicing together as in the fourth reference example, the entire groove side surfaces (side surface d44A and side surface d48A) of the first groove d44 and the second groove d48 are compared with the case of only etching. The variation can be reduced, and the side surface of the groove can be along the thickness direction of the substrate d2.

  Further, since the width Q of the dicing saw d47 is smaller than the width M of the first groove d44, the width Q of the second groove d48 formed by the dicing saw d47 is smaller than the width M of the first groove d44. The second groove d48 is located inside the first groove d44 (see FIG. 96C). Therefore, when the second groove d48 is formed by the dicing saw d47, the dicing saw d47 does not increase the width of the first groove d44. Therefore, it is possible to reliably prevent the corner d11 on the surface d2A side of the chip resistor d1 that should be partitioned by the first groove d44 from being partitioned by the dicing saw d47 and causing chipping at the corner d11.

  The chip resistor d1 is separated into pieces by grinding the back surface d30B after forming the second groove d48, but the back surface d30B is ground first before forming the second groove d48. Therefore, the second groove d48 may be formed by dicing. It is also assumed that the chip resistor d1 is cut out by etching the substrate d30 from the back surface d30B side to the bottom surface d48B of the second groove d48.

  As described above, if the substrate d30 is ground from the back surface d30B side after the first groove d44 and the second groove d48 are formed, a plurality of chip component regions Y formed on the substrate d30 are collectively separated into individual chip resistors. It can be divided into d1 (chip parts) (a plurality of pieces of chip resistors d1 can be obtained at one time). Therefore, the productivity of the chip resistor d1 can be improved by shortening the manufacturing time of the plurality of chip resistors d1. Incidentally, when a substrate d30 having a diameter of 8 inches is used, about 500,000 chip resistors d1 can be cut out.

That is, even if the chip size of the chip resistor d1 is small, the chip resistor d1 is formed by grinding the substrate d30 from the back surface d30B after the first groove d44 and the second groove d48 are formed in this way. Can be singulated at once.
Further, since the first groove d44 can be formed with high accuracy by etching, the external dimension accuracy is improved on the rough surface region S side of the side surfaces d2C to d2F partitioned by the first groove d44 in each chip resistor d1. be able to. In particular, if plasma etching is used, the first groove d44 can be formed with higher accuracy. Further, since the interval between the first grooves d44 can be reduced according to the resist pattern d41 (see FIG. 97), the chip resistor d1 formed between the adjacent first grooves d44 can be reduced in size. . In the case of etching, chipping can be reduced in the corner portion d11 (see FIG. 87 (a)) between adjacent ones in the rough surface region S of the side surfaces d2C to d2F of the chip resistor d1, and the chip resistance can be reduced. The appearance of the container d1 can be improved.

Note that the back surface d2B may be cleaned by polishing or etching the back surface d2B of the substrate d2 in the completed chip resistor d1.
As shown in FIG. 96H, the completed chip resistor d1 is peeled off from the support tape d71, and then conveyed to a predetermined space and stored in the space.
When the chip resistor d1 is mounted on the mounting substrate d9 (see FIG. 87 (b)), the back surface d2B of the chip resistor d1 is attracted to the suction nozzle d91 (see FIG. 87 (b)) of the automatic mounting machine. The chip resistor d1 is transported by moving the nozzle d91. At this time, the suction nozzle d91 is sucked to a substantially central portion in the longitudinal direction of the back surface d2B. Then, referring to FIG. 87 (b), the suction nozzle d91 that sucks the chip resistor d1 is moved to the mounting substrate d9. The mounting substrate d9 is provided with the pair of connection terminals d88 described above according to the first connection electrode d3 and the second connection electrode d4 of the chip resistor d1. The connection terminal d88 is made of Cu, for example. Solder d13 is provided on the surface of each connection terminal d88 so as to protrude from the surface.

  Therefore, by moving the suction nozzle d91 and pressing it against the mounting substrate d9, in the chip resistor d1, the first connection electrode d3 is brought into contact with the solder d13 of one connection terminal d88, and the second connection electrode d4 is contacted with the other connection. Contact with the solder d13 of the terminal d88. When the solder d13 is heated in this state, the solder d13 is melted. After that, when the solder d13 is cooled and solidified, the first connection electrode d3 and the one connection terminal d88 are joined via the solder d13, and the second connection electrode d4 and the other connection terminal d88 join the solder d13. And the mounting of the chip resistor d1 on the mounting substrate d9 is completed.

FIG. 99 is a schematic diagram for explaining how the completed chip resistor is accommodated in the embossed carrier tape.
On the other hand, the completed chip resistor d1 as shown in FIG. 96H may be accommodated in the embossed carrier tape d92 shown in FIG.
The embossed carrier tape d92 is, for example, a tape (strip-shaped body) formed of polycarbonate resin or the like. In the embossed carrier tape d92, a large number of pockets d93 are formed so as to be aligned in the longitudinal direction of the embossed carrier tape d92. Each pocket d93 is partitioned as a concave space that is recessed toward one surface (back surface) of the embossed carrier tape d92.

  When the completed chip resistor d1 (see FIG. 96H) is accommodated in the embossed carrier tape d92, the suction nozzle d91 (see FIG. 87 (b)) of the transport device is connected to the back surface d2B (substantially central portion in the longitudinal direction) of the chip resistor d1. ) And then the suction nozzle d91 is moved to peel off the chip resistor d1 from the support tape d71. Then, the suction nozzle d91 is moved to a position facing the pocket d93 of the embossed carrier tape d92. At this time, in the chip resistor d1 sucked by the suction nozzle d91, the first connection electrode d3, the second connection electrode d4, and the resin film d24 on the surface d2A side face the pocket d93.

  Here, when the chip resistor d1 is accommodated in the embossed carrier tape d92, the embossed carrier tape d92 is placed on a flat support base d95. The suction nozzle d91 is moved to the pocket d93 side (see the thick line arrow), and the chip resistor d1 in which the surface d2A side faces the pocket d93 is accommodated in the pocket d93. When the surface d2A side of the chip resistor d1 comes into contact with the bottom d93A of the pocket d93, the accommodation of the chip resistor d1 into the embossed carrier tape d92 is completed. When the surface d2A side of the chip resistor d1 is brought into contact with the bottom d93A of the pocket d93 by moving the suction nozzle d91, the first connection electrode d3, the second connection electrode d4, and the resin film d24 on the surface d2A side are It is pressed against the bottom d93A supported by d95.

  After the housing of the chip resistor d1 with respect to the embossed carrier tape d92 is completed, a release cover d94 is attached to the surface of the embossed carrier tape d92, and the inside of each pocket d93 is sealed by the release cover d94. This prevents foreign matter from entering each pocket d93. When taking out the chip resistor d1 from the embossed carrier tape d92, the peeling cover d94 is peeled off from the embossed carrier tape d92 and the pocket d93 is opened. Thereafter, the chip resistor d1 is taken out from the pocket d93 by the automatic mounting machine and mounted as described above.

  When the chip resistor d1 is mounted in this way, when the chip resistor d1 is accommodated in the embossed carrier tape d92, or when a stress test is performed on the chip resistor d1, the back surface of the chip resistor d1 When a force is applied to d2B (substantially central portion in the longitudinal direction) to press the first connection electrode d3 and the second connection electrode d4 against something (referred to as “contacted portion”), the surface d2A of the substrate d2 Stress acts on The contacted part is a mounting substrate d9 when the chip resistor d1 is mounted. When the chip resistor d1 is accommodated in the embossed carrier tape d92, the contacted portion of the pocket d93 supported by the support base d95 is used. The bottom d93A is a support surface that supports the chip resistor d1 that receives stress during a stress test.

  In this case, the height H (see FIG. 95) of the resin film d24 on the surface d2A of the substrate d2 is less than the height J (see FIG. 95) of each of the first connection electrode d3 and the second connection electrode d4. A chip resistor d1 in which the surfaces d3A and 4A of the first connection electrode d3 and the second connection electrode d4 protrude most from the surface d2A of the substrate d2 (that is, the resin film d24 is thin) is conceivable (see FIG. 100 described later). ). Since such a chip resistor d1 is in contact (two-point contact) only with the first connection electrode d3 and the second connection electrode d4 on the surface d2A side, the chip resistor d1 is applied. The stress is concentrated at the junction between each of the first connection electrode d3 and the second connection electrode d4 and the substrate d2. As a result, the electrical characteristics of the chip resistor d1 may be deteriorated. Further, the stress causes distortion in the chip resistor d1 (particularly, the substantially central portion in the longitudinal direction of the substrate d2), and in a severe case, the substrate d2 may be cracked starting from the approximately central portion. .

  However, in the fourth reference example, as described above, the resin film d24 is thick so that the height H of the resin film d24 is not less than the height J of each of the first connection electrode d3 and the second connection electrode d4. (See FIG. 95). Therefore, the stress applied to the chip resistor d1 is received not only by the first connection electrode d3 and the second connection electrode d4 but also by the resin film d24. That is, since the area of the portion that receives stress in the chip resistor d1 can be increased, the stress applied to the chip resistor d1 can be dispersed. Thereby, concentration of stress on the first connection electrode d3 and the second connection electrode d4 can be suppressed in the chip resistor d1. In particular, the stress applied to the chip resistor d1 can be more effectively dispersed by the surface d24C of the resin film d24. Thereby, since concentration of stress on the chip resistor d1 can be further suppressed, the strength of the chip resistor d1 can be improved. As a result, it is possible to suppress the chip resistor d1 from being broken during mounting, during a durability test, or during storage in the emboss carrier tape d92. As a result, it is possible to improve the yield in mounting and accommodation in the embossed carrier tape d92, and furthermore, the chip resistor d1 is not easily broken, so that the handleability of the chip resistor d1 can be improved.

Next, a modified example of the chip resistor d1 will be described. 100 to 104 are schematic cross-sectional views of chip resistors according to first to fifth modifications. In the first to fifth modified examples, the same reference numerals are assigned to the portions corresponding to the portions described above for the chip resistor d1, and detailed description thereof is omitted.
With respect to the first connection electrode d3 and the second connection electrode d4, in FIG. 95, the surface d3A of the first connection electrode d3 and the surface d4A of the second connection electrode d4 are flush with the surface d24C of the resin film d24. If it is not considered to disperse the stress applied to the chip resistor d1 during mounting or the like, the surface d3A of the first connection electrode d3 and the surface of the second connection electrode d4 as in the first modification shown in FIG. d4A may protrude from the surface d24C of the resin film d24 in a direction away from the surface d2A of the substrate d2 (upward in FIG. 100). At this time, the height H of the resin film d24 is lower than the respective heights J of the first connection electrode d3 and the second connection electrode d4.

  Conversely, if it is desired to disperse the stress applied to the chip resistor d1 during mounting or the like, as compared with the case of FIG. 95, the height H of the resin film d24 is set to the first value as in the second modification shown in FIG. The height may be higher than the height J of each of the connection electrode d3 and the second connection electrode d4. As a result, the resin film d24 becomes thick, and the surface d3A of the first connection electrode d3 and the surface d4A of the second connection electrode d4 are closer to the surface d2A side of the substrate d2 than the surface d24C of the resin film d24 (downward in FIG. 100). ) In this case, the first connection electrode d3 and the second connection electrode d4 are buried in the substrate d2 side with respect to the surface d24C of the resin film d24. The two-point contact itself at the electrode d4 does not occur. Therefore, the concentration of stress on the chip resistor d1 can be further suppressed. However, when the chip resistor d1 of the second modification is mounted on the mounting substrate d9, the solder d13 on each connection terminal d88 of the mounting substrate d9 is replaced with the surface d3A of the first connection electrode d3 and the second connection electrode d4. It is necessary to prevent the connection failure between the first connection electrode d3 and the second connection electrode d4 and the solder d13 so as to reach the surface d4A (see FIG. 87B).

  Further, in the insulating layer d20 on the surface d2A of the substrate d2, the end surface d20A (portion that coincides with the edge d85 of the surface d2A in plan view) is in the thickness direction of the substrate d2 (in FIGS. 95, 100, and 101). It extends in the vertical direction), but may be inclined as shown in FIGS. Specifically, the end surface d20A of the insulating layer d20 is inclined so as to go inward of the substrate d2 as it approaches the surface of the insulating layer d20 from the surface d2A of the substrate d2. In accordance with the end surface d20A, the portion of the passivation film d23 that covers the end surface d20A (the end d23C described above) is also inclined along the end surface d20A.

In the chip resistor d1 of the third to fifth modifications shown in FIGS. 102 to 104, the position of the edge 24A of the resin film d24 is different.
First, the chip resistor d1 of the third modification shown in FIG. 102 is the same as the chip resistor d1 of FIG. 95 except that the end surface d20A of the insulating layer d20 and the end d23C of the passivation film d23 are inclined. is there. Therefore, in plan view, the edge 24A of the resin film d24 is aligned with the side surface covering portion d23B of the passivation film d23, and the edge portion d85 (the surface of the substrate d2) of the surface d2A of the substrate d2 is equal to the thickness of the side surface covering portion d23B. The outer edge of the surface d2A side). If it is desired to align the edge 24A with the side surface covering portion d23B in this way, when the photosensitive resin liquid is spray-applied to form the resin film d46 described above (see FIG. 96E), the mask 24 is used. It is necessary to prevent the liquid from entering the first groove d44 and the second groove d48. Alternatively, even if the liquid enters the first groove d44 and the second groove d48, when the resin film d46 is subsequently patterned (see FIG. 96F), the first groove d44 and the second groove in the plan view in the mask d62. It is preferable to form an opening d61 in a portion coinciding with the groove d48. Then, the resin film d46 in the first groove d44 and the second groove d48 can be removed by patterning the resin film d46, and the edge 24A of the resin film d24 can be aligned with the side surface covering portion d23B.

Here, since the resin film d24 is made of a resin, there is little possibility that a crack will occur due to an impact. Therefore, since the resin film d24 can reliably protect the surface d2A (particularly, the element d5 and the fuse F) of the substrate d2 and the edge d85 of the surface d2A of the substrate d2 from impact, the chip resistor having excellent impact resistance. A container d1 can be provided.
On the other hand, in the chip resistor d1 of the fourth modification shown in FIG. 103, the edge 24A of the resin film d24 is not aligned with the side surface covering portion d23B of the passivation film d23 in plan view, and is more than the side surface covering portion d23B. Inward, more specifically, the substrate d2 recedes inward from the edge d85 of the surface d2A of the substrate d2. Also in this case, since the resin film d24 can reliably protect the surface d2A (particularly, the element d5 and the fuse F) of the substrate d2 from impact, it is possible to provide the chip resistor d1 having excellent impact resistance. In order to retract the edge 24A of the resin film d24 inward of the substrate d2, when patterning the resin film d46, an opening is also formed in a portion of the mask d62 that overlaps the edge d85 of the substrate d2 (substrate d30) in plan view. It is preferable to form d61 (see FIG. 96F). Then, by patterning the resin film d46, the resin film d46 in a region overlapping with the edge d85 of the substrate d2 (substrate d30) in plan view is removed, and as a result, the edge 24A of the resin film d24 is moved inward of the substrate d2. Can be retreated.

  In the chip resistor d1 of the fifth modification shown in FIG. 104, the edge 24A of the resin film d24 is not aligned with the side surface covering portion d23B of the passivation film d23 in plan view. Specifically, the resin film d24 protrudes outward from the side surface covering portion d23B and covers the entire side surface covering portion d23B from the outside. That is, in the fifth modification, the resin film d24 covers both the surface covering portion d23A and the side surface covering portion d23B of the passivation film d23. In this case, since the resin film d24 can reliably protect the surface d2A (particularly, the element d5 and the fuse F) of the substrate d2 and the side surfaces d2C to d2F of the substrate d2 from impact, the chip resistor having excellent impact resistance. d1 can be provided. If the resin film d24 wants to cover both the surface covering portion d23A and the side surface covering portion d23B, when the photosensitive resin liquid is sprayed to form the resin film d46 described above (see FIG. 96E), The liquid may enter the first groove d44 and the second groove d48 and adhere to the side surface covering portion d23B. As described above, when the liquid is spin-coated, it is not preferable because the liquid does not form a film and completely fills the first groove d44 and the second groove d48. On the other hand, when the resin film d46 is formed by attaching a sheet made of a photosensitive resin to the surface d30A of the substrate d30, the sheet cannot enter the first groove d44 and the second groove d48. Since the whole area of the side surface covering portion d23B cannot be covered, it is not preferable. Therefore, in order for the resin film d24 to cover both the surface covering portion d23A and the side surface covering portion d23B, it is effective to spray the photosensitive resin liquid.

  Although the embodiment of the fourth reference example has been described above, the fourth reference example can be implemented in other forms. For example, as an example of the chip component of the fourth reference example, the chip resistor d1 is disclosed in the above-described embodiment, but the fourth reference example can also be applied to a chip component such as a chip capacitor, a chip inductor, or a chip diode. Below, a chip capacitor is explained.

FIG. 105 is a plan view of a chip capacitor according to another embodiment of the fourth reference example. 106 is a cross-sectional view taken along section line CVI-CVI of FIG. FIG. 107 is an exploded perspective view showing a part of the structure of the chip capacitor separately.
In the chip capacitor d101 to be described below, the same reference numerals are given to the portions corresponding to the portions described in the above-described chip resistor d1, and detailed description thereof will be omitted. In the chip capacitor d101, a part denoted by the same reference numeral as that described for the chip resistor d1 has the same configuration as the part described for the chip resistor d1, unless otherwise specified. The same effect as the part demonstrated by d1 can be show | played.

  Referring to FIG. 105, similarly to the chip resistor d1, the chip capacitor d101 includes the substrate d2, the first connection electrode d3 disposed on the substrate d2 (the surface d2A side of the substrate d2), and the substrate d2. And a second connection electrode d4. In this embodiment, the substrate d2 has a rectangular shape in plan view. A first connection electrode d3 and a second connection electrode d4 are arranged at both ends in the longitudinal direction of the substrate d2. In this embodiment, the first connection electrode d3 and the second connection electrode d4 have a substantially rectangular planar shape extending in the short direction of the substrate d2. On the surface d2A of the substrate d2, a plurality of capacitor elements C1 to C9 are arranged in a capacitor arrangement region d105 between the first connection electrode d3 and the second connection electrode d4. The plurality of capacitor elements C1 to C9 are a plurality of element elements (capacitor elements) constituting the element d5 described above, and each of the second connection electrodes d4 via a plurality of fuse units d107 (corresponding to the fuse F described above). Are electrically connected so as to be separable from each other. An element d5 constituted by these capacitor elements C1 to C9 forms a capacitor network.

  As shown in FIGS. 106 and 107, an insulating layer d20 is formed on the surface d2A of the substrate d2, and a lower electrode film d111 is formed on the surface of the insulating layer d20. The lower electrode film d111 extends over almost the entire capacitor arrangement region d105. Further, the lower electrode film d111 is formed to extend to a region immediately below the first connection electrode d3. More specifically, the lower electrode film d111 includes a capacitor electrode region d111A that functions as a common lower electrode of the capacitor elements C1 to C9 in the capacitor arrangement region d105, and an external electrode lead that is disposed immediately below the first connection electrode d3. And a pad region d111B (pad). The capacitor electrode region d111A is located in the capacitor arrangement region d105, and the pad region d111B is located immediately below the first connection electrode d3 and is in contact with the first connection electrode d3.

  A capacitor film (dielectric film) d112 is formed so as to cover and be in contact with the lower electrode film d111 (capacitor electrode area d111A) in the capacitor arrangement region d105. The capacitive film d112 is formed over the entire capacitor electrode region d111A (capacitor placement region d105). In this embodiment, the capacitive film d112 further covers the insulating layer d20 outside the capacitor arrangement region d105.

  An upper electrode film d113 is formed on the capacitive film d112 so as to be in contact with the capacitive film d112. In FIG. 105, for clarity, the upper electrode film d113 is colored. The upper electrode film d113 includes a capacitor electrode region d113A located in the capacitor arrangement region d105, a pad region d113B (pad) located immediately below the second connection electrode d4 and in contact with the second connection electrode d4, and a capacitor electrode region d113A. And a fuse region d113C disposed between the pad region d113B and the pad region d113B.

  In the capacitor electrode region d113A, the upper electrode film d113 is divided (separated) into a plurality of electrode film parts (upper electrode film parts) d131 to d139. In this embodiment, each of the electrode film portions d131 to d139 is formed in a rectangular shape, and extends in a strip shape from the fuse region d113C toward the first connection electrode d3. The plurality of electrode film portions d131 to d139 are opposed to the lower electrode film d111 with a plurality of types of facing areas with the capacitor film d112 interposed therebetween (while in contact with the capacitor film d112). More specifically, the facing area of the electrode film portions d131 to d139 with respect to the lower electrode film d111 may be determined to be 1: 2: 4: 8: 16: 32: 64: 128: 128. That is, the plurality of electrode film portions d131 to d139 include a plurality of electrode film portions having different facing areas, and more specifically, a plurality of facing areas set so as to form a geometric sequence with a common ratio of 2. The electrode film portions d131 to d138 (or d131 to d137, d139) are included. As a result, the plurality of capacitor elements C1 to C9 respectively configured by the electrode film portions d131 to d139 and the lower electrode film d111 and the capacitor film d112 facing each other with the capacitor film d112 interposed therebetween have a plurality of capacitance values different from each other. Including capacitor elements. When the ratio of the facing areas of the electrode film portions d131 to d139 is as described above, the ratio of the capacitance values of the capacitor elements C1 to C9 is equal to the ratio of the facing areas, and is 1: 2: 4: 8: 16: 32. : 64: 128: 128. That is, the plurality of capacitor elements C1 to C9 include a plurality of capacitor elements C1 to C8 (or C1 to C7, C9) having capacitance values set so as to form a geometric sequence with a common ratio of 2.

  In this embodiment, the electrode film portions d131 to d135 are formed in a strip shape having the same width and the length ratio set to 1: 2: 4: 8: 16. The electrode film portions d135, d136, d137, d138, and d139 are formed in a strip shape having the same length and the width ratio set to 1: 2: 4: 8: 8. The electrode film portions d135 to d139 are formed to extend over a range from the edge on the second connection electrode d4 side of the capacitor arrangement region d105 to the edge on the first connection electrode d3 side. d134 is formed shorter than that.

The pad region d113B is formed in a substantially similar shape to the second connection electrode d4, and has a substantially rectangular planar shape. As shown in FIG. 106, the upper electrode film d113 in the pad region d113B is in contact with the second connection electrode d4.
The fuse region d113C is arranged along one long side of the pad region d113B (long side on the inner side with respect to the periphery of the substrate d2). The fuse region d113C includes a plurality of fuse units d107 arranged along the one long side of the pad region d113B.

  The fuse unit d107 is integrally formed of the same material as the pad region d113B of the upper electrode film d113. The plurality of electrode film portions d131 to d139 are formed integrally with one or a plurality of fuse units d107, and are connected to the pad region d113B via the fuse units d107, and are connected via the pad region d113B. It is electrically connected to the second connection electrode d4. As shown in FIG. 105, the electrode film portions d131 to d136 having a relatively small area are connected to the pad region d113B by one fuse unit d107, and a plurality of electrode film portions d137 to d139 having a relatively large area are provided. It is connected to the pad region d113B through the fuse unit d107. It is not necessary to use all the fuse units d107, and in this embodiment, some of the fuse units d107 are unused.

  The fuse unit d107 includes a first wide portion d107A for connection to the pad region d113B, a second wide portion d107B for connection to the electrode film portions d131 to d139, and first and second wide portions d107A and 7B. And a narrow portion d107C connecting between the two. The narrow portion d107C is configured to be cut (melted) by laser light. Accordingly, unnecessary electrode film portions of the electrode film portions d131 to d139 can be electrically separated from the first and second connection electrodes d3 and d4 by cutting the fuse unit d107.

  Although not shown in FIGS. 105 and 107, as shown in FIG. 106, the surface of the chip capacitor d101 including the surface of the upper electrode film d113 is covered with the passivation film d23 described above. The passivation film d23 is made of, for example, a nitride film, and is formed so as to extend not only to the upper surface of the chip capacitor d101 but also to the side surfaces d2C to d2F of the substrate d2, and to cover the entire side surfaces d2C to d2F. Further, the above-described resin film d24 is formed on the passivation film d23.

  The passivation film d23 and the resin film d24 are protective films that protect the surface of the chip capacitor d101. In these, the openings d25 described above are formed in regions corresponding to the first connection electrode d3 and the second connection electrode d4, respectively. The opening d25 penetrates the passivation film d23 and the resin film d24 so as to expose a part of the pad region d111B of the lower electrode film d111 and a part of the pad region d113B of the upper electrode film d113. Furthermore, in this embodiment, the opening d25 corresponding to the first connection electrode d3 also penetrates the capacitive film d112.

  A first connection electrode d3 and a second connection electrode d4 are embedded in the opening d25, respectively. Accordingly, the first connection electrode d3 is bonded to the pad region d111B of the lower electrode film d111, and the second connection electrode d4 is bonded to the pad region d113B of the upper electrode film d113. In this embodiment, the first and second external electrodes d3 and d4 are formed so that the surfaces d3A and 4A are substantially flush with the surface d24A of the resin film d24. Similar to the chip resistor d1, the chip capacitor d101 can be flip-chip bonded to the mounting substrate d9.

  FIG. 108 is a circuit diagram showing an internal electrical configuration of the chip capacitor. A plurality of capacitor elements C1 to C9 are connected in parallel between the first connection electrode d3 and the second connection electrode d4. Between each capacitor element C1 to C9 and the second connection electrode d4, fuses F1 to F9 each composed of one or a plurality of fuse units d107 are interposed in series.

  When all the fuses F1 to F9 are connected, the capacitance value of the chip capacitor d101 is equal to the sum of the capacitance values of the capacitor elements C1 to C9. When one or more fuses selected from the plurality of fuses F1 to F9 are disconnected, the capacitor element corresponding to the disconnected fuse is disconnected, and the capacitance of the chip capacitor d101 is equal to the capacitance value of the disconnected capacitor element. The value decreases.

  Therefore, the capacitance value between the pad regions d111B and d113B (total capacitance value of the capacitor elements C1 to C9) is measured, and then one or more appropriately selected from the fuses F1 to F9 according to the desired capacitance value. If the fuse is blown with a laser beam, adjustment to a desired capacitance value (laser trimming) can be performed. In particular, if the capacitance values of the capacitor elements C1 to C8 are set to form a geometric sequence with a common ratio of 2, the capacitor element C1 having the minimum capacitance value (the value of the first term of the geometric sequence). Fine adjustment is possible to match the target capacitance value with accuracy corresponding to the capacitance value.

For example, the capacitance values of the capacitor elements C1 to C9 may be determined as follows.
C1 = 0.03125pF
C2 = 0.0625pF
C3 = 0.125pF
C4 = 0.25pF
C5 = 0.5pF
C6 = 1pF
C7 = 2pF
C8 = 4pF
C9 = 4pF
In this case, the capacitance of the chip capacitor d101 can be finely adjusted with a minimum fitting accuracy of 0.03125 pF. Further, by appropriately selecting a fuse to be cut from the fuses F1 to F9, a chip capacitor d101 having an arbitrary capacitance value between 10 pF and 18 pF can be provided.

  As described above, according to this embodiment, a plurality of capacitor elements C1 to C9 that can be separated by the fuses F1 to F9 are provided between the first connection electrode d3 and the second connection electrode d4. Capacitor elements C1 to C9 include a plurality of capacitor elements having different capacitance values, more specifically, a plurality of capacitor elements having capacitance values set so as to form a geometric sequence. As a result, by selecting one or more fuses from the fuses F1 to F9 and fusing them with laser light, it is possible to cope with a plurality of types of capacitance values without changing the design and accurately match the desired capacitance values. The chip capacitor d101 that can be embedded can be realized with a common design.

Details of each part of the chip capacitor d101 will be described below.
Referring to FIG. 105, substrate d2 has a rectangular shape such as 0.3 mm × 0.15 mm or 0.4 mm × 0.2 mm in plan view (preferably, a size of 0.4 mm × 0.2 mm or less). You may have. Capacitor arrangement region d105 is generally a square region having one side corresponding to the length of the short side of substrate d2. The thickness of the substrate d2 may be about 150 μm. Referring to FIG. 106, substrate d2 may be, for example, a substrate that has been thinned by grinding or polishing from the back surface side (the surface on which capacitor elements C1 to C9 are not formed). As a material of the substrate d2, a semiconductor substrate typified by a silicon substrate may be used, a glass substrate may be used, or a resin film may be used.

The insulating layer d20 may be an oxide film such as a silicon oxide film. The film thickness may be about 500 to 2000 mm.
The lower electrode film d111 is preferably a conductive film, particularly a metal film, and may be, for example, an aluminum film. The lower electrode film d111 made of an aluminum film can be formed by sputtering. Similarly, the upper electrode film d113 is preferably composed of a conductive film, particularly a metal film, and may be an aluminum film. The upper electrode film d113 made of an aluminum film can be formed by a sputtering method. Patterning for dividing the capacitor electrode region d113A of the upper electrode film d113 into electrode film portions d131 to d139 and further shaping the fuse region d113C into a plurality of fuse units d107 can be performed by photolithography and etching processes.

The capacitor film d112 can be made of, for example, a silicon nitride film, and the film thickness can be 500 to 2000 mm (for example, 1000 mm). The capacitive film d112 may be a silicon nitride film formed by plasma CVD (chemical vapor deposition).
The passivation film d23 can be composed of, for example, a silicon nitride film, and can be formed by, for example, a plasma CVD method. The film thickness may be about 8000 mm. As described above, the resin film d24 can be composed of a polyimide film or other resin film.

  The first and second connection electrodes d3, 4 are, for example, a Ni layer d33 in contact with the lower electrode film d111 or the upper electrode film d113, a Pd layer d34 laminated on the Ni layer d33, and a laminate on the Pd layer d34. For example, it may be formed by an electroless plating method. The Ni layer d33 contributes to improving the adhesion to the lower electrode film d111 or the upper electrode film d113, and the Pd layer d34 is formed of the material of the upper electrode film or the lower electrode film and the uppermost layer of the first and second connection electrodes d3 and d4. It functions as a diffusion prevention layer that suppresses mutual diffusion with gold.

The manufacturing process of such a chip capacitor d101 is the same as the manufacturing process of the chip resistor d1 after forming the element d5.
When the element d5 (capacitor element) is formed in the chip capacitor d101, first, an oxide film (for example, a silicon oxide film) is formed on the surface of the substrate d30 (substrate d2) by the thermal oxidation method and / or the CVD method. An insulating layer d20 is formed. Next, a lower electrode film d111 made of an aluminum film is formed over the entire surface of the insulating layer d20 by sputtering, for example. The thickness of the lower electrode film d111 may be about 8000 mm. Next, a resist pattern corresponding to the final shape of the lower electrode film d111 is formed on the surface of the lower electrode film by photolithography. Using this resist pattern as a mask, the lower electrode film is etched to obtain the lower electrode film d111 having the pattern shown in FIG. The etching of the lower electrode film d111 can be performed by, for example, reactive ion etching.

  Next, a capacitor film d112 made of a silicon nitride film or the like is formed on the lower electrode film d111 by, for example, plasma CVD. In the region where the lower electrode film d111 is not formed, the capacitor film d112 is formed on the surface of the insulating layer d20. Next, the upper electrode film d113 is formed on the capacitor film d112. The upper electrode film d113 is made of, for example, an aluminum film and can be formed by a sputtering method. The film thickness may be about 8000 mm. Next, a resist pattern corresponding to the final shape of the upper electrode film d113 is formed on the surface of the upper electrode film d113 by photolithography. By etching using the resist pattern as a mask, the upper electrode film d113 is patterned into a final shape (see FIG. 105 and the like). Accordingly, the upper electrode film d113 has a portion divided into a plurality of electrode film portions d131 to d139 in the capacitor electrode region d113A, and has a plurality of fuse units d107 in the fuse region d113C. It is shaped into a pattern having a connected pad region d113B. By dividing the upper electrode film d113, a plurality of capacitor elements C1 to C9 corresponding to the number of electrode film portions d131 to d139 can be formed. Etching for patterning the upper electrode film d113 may be performed by wet etching using an etchant such as phosphoric acid or by reactive ion etching.

  Thus, the element d5 (capacitor elements C1 to C9 and the fuse unit d107) in the chip capacitor d101 is formed. After the element d5 is formed, the insulating film d45 is formed by plasma CVD so as to cover the element d5 (the upper electrode film d113 and the capacitor film d112 in the region where the upper electrode film d113 is not formed) (FIG. 96A). Thereafter, after the first groove d44 and the second groove d48 are formed (see FIGS. 96B and 96C), the opening d25 is formed (see FIG. 96D). Then, the probe d70 is pressed against the pad region d113B of the upper electrode film d113 and the pad region d111B of the lower electrode film d111 exposed from the opening d25, and the total capacitance values of the plurality of capacitor elements C0 to C9 are measured ( (See FIG. 96D). Based on the measured total capacitance value, the capacitor element to be disconnected, that is, the fuse to be disconnected, is selected according to the target capacitance value of the chip capacitor d101.

  From this state, laser trimming for fusing the fuse unit d107 is performed. That is, a laser beam is applied to the fuse unit d107 constituting the fuse selected according to the measurement result of the total capacitance value, and the narrow portion d107C (see FIG. 105) of the fuse unit d107 is blown. As a result, the corresponding capacitor element is separated from the pad region d113B. When the laser light is applied to the fuse unit d107, the energy of the laser light is accumulated in the vicinity of the fuse unit d107 by the action of the insulating film d45 which is a cover film, and the fuse unit d107 is thus blown out. Thereby, the capacitance value of the chip capacitor d101 can be surely set to the target capacitance value.

  Next, a silicon nitride film is deposited on the cover film (insulating film d45) by, for example, plasma CVD to form a passivation film d23. In the final form, the above-described cover film is integrated with the passivation film d23 and constitutes a part of the passivation film d23. The passivation film d23 formed after the fuse is cut enters the opening of the cover film destroyed at the same time when the fuse is blown, and covers and protects the cut surface of the fuse unit d107. Therefore, the passivation film d23 prevents foreign matter from entering the cut portion of the fuse unit d107 and moisture from entering. Thereby, a highly reliable chip capacitor d101 can be manufactured. The passivation film d23 may be formed so as to have a film thickness of, for example, about 8000 mm as a whole.

  Next, the resin film d46 described above is formed (see FIG. 96E). Thereafter, the opening d25 closed by the resin film d46 and the passivation film d23 is opened (see FIG. 96F), and the pad region d111B and the pad region d113B are exposed from the resin film d46 (resin film d24) through the opening d25. Is done. Thereafter, the first connection electrode d3 and the second connection electrode d4 are formed on the pad region d111B and the pad region d113B exposed from the resin film d46 in the opening d25 by, for example, electroless plating (see FIG. 96G). .

Thereafter, as in the case of the chip resistor d1, when the substrate d30 is ground from the back surface d30B (see FIG. 96H), the chip capacitor d101 can be cut out.
In the patterning of the upper electrode film d113 using the photolithography process, the electrode film portions d131 to d139 having a small area can be formed with high accuracy, and the fuse unit d107 having a fine pattern can be formed. Then, after patterning the upper electrode film d113, a fuse to be cut is determined through measurement of the total capacitance value. By cutting the determined fuse, it is possible to obtain a chip capacitor d101 that is accurately adjusted to a desired capacitance value. In other words, the chip capacitor d101 can easily and quickly cope with a plurality of types of capacitance values by selecting and cutting one or a plurality of fuses. In other words, chip capacitors d101 having various capacitance values can be realized with a common design by combining a plurality of capacitor elements C1 to C9 having different capacitance values.

Although the chip parts (chip resistor d1 and chip capacitor d101) of the fourth reference example have been described above, the fourth reference example can be implemented in other forms.
For example, in the above-described embodiment, in the case of the chip resistor d1, the plurality of resistor circuits have a plurality of resistor circuits having resistance values forming a series of geometric ratios with a common ratio r (0 <r, r ≠ 1) = 2. However, the common ratio of the geometric sequence may be a number other than two. Also, in the case of the chip capacitor d101, an example is shown in which the capacitor element has a plurality of capacitor elements having capacitance values forming a geometric sequence with a common ratio r (0 <r, r ≠ 1) = 2. However, the common ratio of the geometric sequence may be a number other than two.

In the chip resistor d1 and the chip capacitor d101, the insulating layer d20 is formed on the surface of the substrate d2. However, if the substrate d2 is an insulating substrate, the insulating layer d20 can be omitted.
In the chip capacitor d101, only the upper electrode film d113 is divided into a plurality of electrode film parts. However, only the lower electrode film d111 is divided into a plurality of electrode film parts, or the upper electrode film d113 is divided. Both the lower electrode film d111 and the lower electrode film d111 may be divided into a plurality of electrode film portions. Furthermore, in the above-described embodiment, an example in which the upper electrode film or the lower electrode film and the fuse unit are integrated is shown. However, the fuse unit is formed of a conductor film different from the upper electrode film or the lower electrode film. May be. In the above-described chip capacitor d101, a single-layer capacitor structure having an upper electrode film d113 and a lower electrode film d111 is formed. Another electrode film is laminated on the upper electrode film d113 via a capacitive film. Thus, a plurality of capacitor structures may be stacked.

In the chip capacitor d101, a conductive substrate may be used as the substrate d2, the conductive substrate may be used as a lower electrode, and the capacitor film d112 may be formed so as to be in contact with the surface of the conductive substrate. In this case, one external electrode may be drawn from the back surface of the conductive substrate.
When the fourth reference example is applied to a chip inductor, the element d5 formed on the substrate d2 in the chip inductor is an inductor circuit network (inductor element) including a plurality of inductor elements (element elements). including. In this case, the element d5 is provided in the multilayer wiring formed on the surface d2A of the substrate d2, and is formed by the wiring film d22. In this chip inductor, the combination pattern of a plurality of inductor elements in the inductor network can be changed to an arbitrary pattern by selecting and cutting one or a plurality of fuses F. However, various chip inductors can be realized with a common design.

  When the fourth reference example is applied to a chip diode, the element d5 formed on the substrate d2 in the chip diode is a diode network (diode element) including a plurality of diode elements (element elements). including. The diode element is formed on the substrate d2. In this chip diode, by selecting and cutting one or a plurality of fuses F, a combination pattern of a plurality of diode elements in the diode network can be changed to an arbitrary pattern. However, various chip diodes can be realized with a common design.

In any of the chip inductor and the chip diode, the same effects as those of the chip resistor d1 and the chip capacitor d101 can be obtained.
Further, in the above-described first connection electrode d3 and second connection electrode d4, the Pd layer d34 interposed between the Ni layer d33 and the Au layer d35 can be omitted. Since the adhesion between the Ni layer d33 and the Au layer d35 is good, the Pd layer d34 may be omitted if the above-described pinhole cannot be formed in the Au layer d35.

Further, as described above, if the intersecting portion 43 (see FIG. 97) of the opening d42 of the resist pattern d41 used when forming the first groove d44 by etching is made round, the completed chip component has the substrate d2. The corner portion (corner portion in the rough surface region S) 11 on the surface d2A side can be formed in a round shape.
Further, the configurations of the modifications 1 to 5 (FIGS. 100 to 104) described in the chip resistor d1 are applicable to any of the chip capacitor d101, the chip inductor, and the chip diode.

  FIG. 109 is a perspective view illustrating an appearance of a smartphone that is an example of an electronic device in which the chip component of the fourth reference example is used. The smartphone d201 is configured by housing electronic components inside a flat rectangular parallelepiped housing d202. The casing d202 has a pair of rectangular main surfaces on the front side and the back side, and the pair of main surfaces are joined by four side surfaces. On one main surface of the housing d202, the display surface of the display panel d203 configured by a liquid crystal panel, an organic EL panel, or the like is exposed. The display surface of the display panel d203 constitutes a touch panel and provides an input interface for the user.

  The display panel d203 is formed in a rectangular shape that occupies most of one main surface of the housing d202. An operation button d204 is arranged along one short side of the display panel d203. In this embodiment, a plurality (three) of operation buttons d204 are arranged along the short side of the display panel d203. The user can operate the smartphone d201 by operating the operation button d204 and the touch panel to call and execute a necessary function.

  A speaker d205 is arranged in the vicinity of another short side of the display panel d203. The speaker d205 provides an earpiece for a telephone function and is also used as an acoustic unit for reproducing music data and the like. On the other hand, a microphone d206 is disposed on one side surface of the housing d202 near the operation button d204. The microphone d206 can be used as a recording microphone in addition to providing a mouthpiece for a telephone function.

  FIG. 110 is a schematic plan view showing the configuration of the electronic circuit assembly d210 accommodated in the housing d202. The electronic circuit assembly d210 includes a wiring board d211 and circuit components mounted on the mounting surface of the wiring board d211. The plurality of circuit components include a plurality of integrated circuit elements (ICs) d212 to d220 and a plurality of chip components. The plurality of ICs include a transmission processing ICd212, a one-segment TV reception ICd213, a GPS reception ICd214, an FM tuner ICd215, a power supply ICd216, a flash memory d217, a microcomputer d218, a power supply ICd219, and a baseband ICd220. A plurality of chip components (corresponding to the chip components of the fourth reference example) include chip inductors d221, d225, d235, chip resistors d222, d224, d233, chip capacitors d227, d230, d234, and chip diodes d228, d231. Including.

The transmission processing IC d212 includes an electronic circuit for generating a display control signal for the display panel d203 and receiving an input signal from the touch panel on the surface of the display panel d203. A flexible wiring 209 is connected to the transmission processing IC d212 for connection with the display panel d203.
The one-seg TV reception ICd 213 incorporates an electronic circuit that constitutes a receiver for receiving radio waves of one-seg broadcasting (terrestrial digital television broadcasting intended for receiving portable devices). A plurality of chip inductors d221 and a plurality of chip resistors d222 are arranged in the vicinity of the one-segment TV reception IC d213. The one-segment TV reception IC d213, the chip inductor d221, and the chip resistor d222 constitute a one-segment broadcast reception circuit d223. The chip inductor d221 and the chip resistor d222 respectively have an inductance and a resistance that are accurately matched, and give a highly accurate circuit constant to the one-segment broadcasting reception circuit d223.

The GPS receiving IC d214 includes an electronic circuit that receives radio waves from GPS satellites and outputs position information of the smartphone d201.
The FM tuner ICd215 constitutes an FM broadcast receiving circuit d226 together with a plurality of chip resistors d224 and a plurality of chip inductors d225 mounted on the wiring board d211 in the vicinity thereof. The chip resistor d224 and the chip inductor d225 each have a resistance value and an inductance that are precisely matched, and give a highly accurate circuit constant to the FM broadcast receiving circuit d226.

In the vicinity of the power supply IC d216, a plurality of chip capacitors d227 and a plurality of chip diodes d228 are mounted on the mounting surface of the wiring board d211. The power supply IC d216 forms a power supply circuit d229 together with the chip capacitor d227 and the chip diode d228.
The flash memory d217 is a storage device for recording an operating system program, data generated inside the smartphone d201, data and programs acquired from the outside by a communication function, and the like.

The microcomputer d218 includes a CPU, a ROM, and a RAM, and is an arithmetic processing circuit that realizes a plurality of functions of the smartphone d201 by executing various arithmetic processes. More specifically, image processing and arithmetic processing for various application programs are realized by the action of the microcomputer d218.
Near the power supply IC d219, a plurality of chip capacitors d230 and a plurality of chip diodes d231 are mounted on the mounting surface of the wiring board d211. The power supply IC d219 forms a power supply circuit d232 together with the chip capacitor d230 and the chip diode d231.

  Near the baseband IC d220, a plurality of chip resistors d233, a plurality of chip capacitors d234, and a plurality of chip inductors d235 are mounted on the mounting surface of the wiring board d211. The baseband IC d220 constitutes a baseband communication circuit d236 together with the chip resistor d233, the chip capacitor d234, and the chip inductor d235. The baseband communication circuit d236 provides a communication function for telephone communication and data communication.

  With such a configuration, the power appropriately adjusted by the power supply circuits d229 and d232 is transmitted to the transmission processing IC d212, the GPS receiving IC d214, the one-segment broadcasting receiving circuit d223, the FM broadcasting receiving circuit d226, the baseband communication circuit d236, the flash memory d217, and It is supplied to the microcomputer d218. The microcomputer d218 performs arithmetic processing in response to an input signal input via the transmission processing IC d212, outputs a display control signal from the transmission processing IC d212 to the display panel d203, and causes the display panel d203 to perform various displays. .

When reception of the one-segment broadcasting is instructed by operating the touch panel or the operation button d204, the one-segment broadcasting is received by the function of the one-segment broadcasting receiving circuit d223. Then, the microcomputer d218 executes a calculation process for outputting the received image to the display panel d203 and causing the received sound to be audible from the speaker d205.
Further, when the position information of the smartphone d201 is required, the microcomputer d218 acquires the position information output from the GPS reception IC d214, and executes a calculation process using the position information.

Further, when an FM broadcast reception command is input by operating the touch panel or the operation button d204, the microcomputer d218 activates the FM broadcast reception circuit d226 and executes arithmetic processing for outputting the received sound from the speaker d205. To do.
The flash memory d217 is used to store data acquired by communication, to store data created by calculation of the microcomputer d218 and input from the touch panel. The microcomputer d218 writes data to the flash memory d217 and reads data from the flash memory d217 as necessary.

The function of telephone communication or data communication is realized by the baseband communication circuit d236. The microcomputer d218 controls the baseband communication circuit d236 to perform processing for transmitting and receiving voice or data.
<Invention according to fifth reference example>
(1) Features of the invention according to the fifth reference example For example, the features of the invention according to the fifth reference example are the following E1 to E16.
(E1) A step of forming elements in a plurality of chip component regions set on the surface of the substrate, and etching a boundary region of the plurality of chip component regions, thereby forming a first depth of a predetermined depth from the surface of the substrate. A step of forming one groove, a step of forming a second groove having a predetermined depth from the bottom surface of the first groove by a dicing saw, and grinding the back surface of the substrate until reaching the second groove, And a step of dividing the substrate into a plurality of chip components.

According to this method, even if the depth of the first groove formed by etching is not uniform, if the second groove is formed by a dicing saw, the entire depth of the first groove and the second groove (of the substrate) The depth from the surface to the bottom of the second groove is uniform. Therefore, when the back surface of the substrate is ground to separate the chip components, the time difference between the chip components until they are separated from the substrate can be reduced, and each chip component can be separated from the substrate almost simultaneously. As a result, it is possible to suppress the problem that chipping occurs in the chip component due to the chip component previously separated repeatedly colliding with the substrate. Further, since the corner portion on the surface side of the chip part is partitioned by the first groove formed by etching, chipping is less likely to occur at the corner portion than in the case where the corner portion is partitioned by the dicing saw. As a result, chipping can be suppressed when chip parts are separated, and occurrence of defective pieces can be avoided. In addition, compared with the case where both the first groove and the second groove are formed by etching, the time required for separating the chip parts can be shortened and the productivity of the chip parts can be improved.
(E2) The chip part manufacturing method according to E1, wherein the dicing saw has a width smaller than a width of the first groove.

According to this method, the width of the second groove formed by the dicing saw is smaller than the width of the first groove, and the second groove is located inside the first groove. Therefore, when the second groove is formed by the dicing saw, the dicing saw does not increase the width of the first groove. Therefore, it is possible to reliably suppress the occurrence of chipping in the corner portion due to the corner portion on the surface side of the chip component that should be partitioned by the first groove being partitioned by the dicing saw.
(E3) The chip component manufacturing method according to E1 or 2, wherein the etching is plasma etching.

According to this method, the first groove can be formed with high accuracy.
(E4) The method of manufacturing a chip component according to any one of E1 to E3, wherein the step of forming the element includes a step of forming a resistor, and the chip component is a chip resistor.
According to this method, it is possible to manufacture a chip resistor that can suppress chipping during singulation and avoid occurrence of defective singulation.
(E5) The step of forming the resistor includes a step of forming a resistor film on a surface of the substrate, a step of forming a wiring film in contact with the resistor film, the resistor film, and the wiring Forming a plurality of the resistors by patterning a film, forming an external connection electrode for externally connecting the element on the substrate, and forming the plurality of resistors on the external connection electrode. And a step of forming a plurality of fuses that are detachably connected to the substrate on the substrate.

According to this method, a chip component (chip resistor) can easily and quickly cope with a plurality of types of resistance values by selecting and cutting one or a plurality of fuses. In other words, chip resistors having various resistance values can be realized with a common design by combining a plurality of resistors having different resistance values.
(E6) The method of manufacturing a chip component according to any one of E1 to E3, wherein the step of forming the element includes a step of forming a capacitor element, and the chip component is a chip capacitor.

According to this method, it is possible to manufacture a chip capacitor that can suppress chipping during singulation and can avoid occurrence of defective singulation.
(E7) The step of forming the capacitor element includes a step of forming a capacitive film on the surface of the substrate, a step of forming an electrode film in contact with the capacitive film, and dividing the electrode film into a plurality of electrode film portions. Forming a plurality of capacitor elements corresponding to the plurality of electrode film portions, forming an external connection electrode for externally connecting the elements, and the plurality of capacitor elements. And a step of forming a plurality of fuses respectively connected to the external connection electrodes in a detachable manner on the substrate.

According to this method, a chip component (chip capacitor) can easily and quickly respond to a plurality of types of capacitance values by selecting and cutting one or a plurality of fuses. In other words, chip capacitors having various capacitance values can be realized by a common design by combining a plurality of capacitor elements having different capacitance values.
(E8) The method of manufacturing a chip component according to any one of E1 to E3, wherein the step of forming the element includes a step of forming an inductor element, and the chip component is a chip inductor.

According to this method, it is possible to manufacture a chip inductor that can suppress chipping during singulation and can avoid occurrence of defective singulation.
(E9) The method of manufacturing a chip component according to any one of E1 to E3, wherein the step of forming the element includes a step of forming a diode element, and the chip component is a chip diode.

According to this method, it is possible to manufacture a chip diode that can suppress chipping during singulation and can avoid occurrence of defective singulation.
(E10) The method for manufacturing a chip component according to any one of E1 to E9, wherein the thickness of the substrate after grinding the back surface of the substrate is 150 μm to 400 μm.
According to this method, the first groove is formed by etching and the second groove is formed by a dicing saw even when the thickness of the substrate in the separated chip component is relatively large, 150 μm to 400 μm. By grinding the back surface of the substrate after that, it is possible to shorten the time required for separating the chip parts and improve the productivity of the chip parts.
(E11) A substrate having a front surface and a back surface, a plurality of element elements formed on the surface of the substrate, an external connection electrode formed on the surface of the substrate, and the plurality of elements formed on the surface of the substrate A plurality of fuses severably connected to the external connection electrodes, and the side surface of the substrate has a rough surface region of an irregular pattern on the surface side, and a streak pattern region is formed on the substrate. Chip parts on the back side of

  With respect to this configuration, after forming the first groove from the surface of the substrate by etching using a resist pattern, the second groove is formed from the bottom surface of the first groove by a dicing saw and the back surface of the substrate is ground. The groove (first groove and second groove) is divided into a plurality of chip parts. Then, on the side surface of the substrate of each divided chip component, the surface side formed by the first groove is a rough surface region of an irregular pattern, and the back surface side formed by the second groove is a streak pattern region.

  When the first groove is formed by etching and then the second groove is formed by the dicing saw, the second groove is formed by the dicing saw even if the depth of the first groove formed by etching is not uniform. Is formed, the entire depth of the first groove and the second groove (depth from the surface of the substrate to the bottom of the second groove) becomes uniform. Therefore, when the back surface of the substrate is ground to separate the chip components, the time difference between the chip components until they are separated from the substrate can be reduced, and each chip component can be separated from the substrate almost simultaneously. As a result, it is possible to suppress the problem that chipping occurs in the chip component due to the chip component previously separated repeatedly colliding with the substrate. Further, since the corner portion on the surface side of the chip part is partitioned by the first groove formed by etching, chipping is less likely to occur at the corner portion than in the case where the corner portion is partitioned by the dicing saw. As a result, chipping can be suppressed when chip parts are separated, and occurrence of defective pieces can be avoided. In addition, compared with the case where both the first groove and the second groove are formed by etching, the time required for separating the chip parts can be shortened and the productivity of the chip parts can be improved.

Further, in this chip component, by selecting and cutting one or a plurality of fuses, a combination pattern of a plurality of element elements in the element can be changed to an arbitrary pattern, so that the electrical characteristics of the element vary. Chip components can be realized with a common design.
(E12) The linear pattern region according to E11, wherein the streak pattern region protrudes outward of the substrate from the rough surface region, and a step is formed between the rough surface region and the streak pattern region. Chip parts.

In this case, in order to form the step, the dicing saw for forming the second groove described above has a width smaller than the width of the first groove, so that the second groove formed by the dicing saw The width is smaller than the width of the first groove, and the second groove is located inside the first groove. Therefore, when the second groove is formed by the dicing saw, the dicing saw does not increase the width of the first groove. Therefore, it is possible to reliably suppress the occurrence of chipping in the corner portion due to the corner portion on the surface side of the chip component that should be partitioned by the first groove being partitioned by the dicing saw.
(E13) The element element is a resistor including a resistor film formed on a surface of the substrate and a wiring film laminated in contact with the resistor film, and the chip component is a chip resistor. A chip component according to E11 or E12.

According to this configuration, this chip component (chip resistor) can easily and quickly cope with a plurality of types of resistance values by selecting and cutting one or a plurality of fuses. In other words, chip resistors having various resistance values can be realized with a common design by combining a plurality of resistors having different resistance values.
(E14) The element element is a capacitor element including a capacitive film formed on the surface of the substrate and an electrode film formed in contact with the capacitive film, and the chip component is a chip capacitor. E11 Or the chip component as described in E12.

According to this configuration, this chip component (chip capacitor) can easily and quickly cope with a plurality of types of capacitance values by selecting and cutting one or a plurality of fuses. In other words, chip capacitors having various capacitance values can be realized by a common design by combining a plurality of capacitor elements having different capacitance values.
(E15) The chip component according to E11 or 12, wherein the element element includes an inductor element provided in a multilayer wiring formed on the surface of the substrate, and the chip component is a chip inductor.

According to this configuration, in this chip component (chip inductor), the combination pattern of a plurality of inductor elements can be changed to an arbitrary pattern by selecting and cutting one or a plurality of fuses. Chip inductors with various characteristics can be realized with a common design.
(E16) The chip component according to E11 or E12, wherein the element element is a diode element, and the chip component is a chip diode.

According to this configuration, in this chip component (chip diode), a combination pattern of a plurality of diode elements can be changed to an arbitrary pattern by selecting and cutting one or a plurality of fuses. Chip diodes with various characteristics can be realized with a common design.
(2) Embodiment of Invention According to Fifth Reference Example Hereinafter, an embodiment of a fifth reference example will be described in detail with reference to the accompanying drawings. In addition, the code | symbol shown in FIGS. 111-134 is effective only in these drawings, and even if it is used for other embodiment, it does not show the same element as the code | symbol of the said other embodiment.

FIG. 111A is a schematic perspective view for explaining the configuration of the chip resistor according to the embodiment of the fifth reference example, and FIG. 111B is a diagram illustrating the chip resistor mounted on the mounting substrate. It is typical sectional drawing which shows the state made.
The chip resistor e1 is a minute chip component and has a rectangular parallelepiped shape as shown in FIG. The planar shape of the chip resistor e1 is a rectangle. Regarding the dimensions of the chip resistor e1, for example, the length L (length of the long side e81) is about 0.6 mm, the width W (length of the short side e82) is about 0.3 mm, and the thickness T Is about 0.2 mm.

The chip resistor e1 is formed by forming a large number of chip resistors e1 on a substrate in a lattice pattern, forming grooves in the substrate, and then polishing the back surface (or dividing the substrate by the grooves) to obtain individual chips. It is obtained by separating the resistor e1.
The chip resistor e1 includes a substrate e2 constituting the main body of the chip resistor e1, a first connection electrode e3 and a second connection electrode e4 that form a pair of external connection electrodes, a first connection electrode e3, and a second connection electrode e4. Is mainly provided with an element e5 connected externally.

  The substrate e2 has a substantially rectangular parallelepiped chip shape. In the substrate e2, the upper surface in FIG. 111 (a) is the surface e2A. The front surface e2A is a surface (element formation surface) on which the element e5 is formed on the substrate e2, and has a substantially rectangular shape. The surface opposite to the front surface e2A in the thickness direction of the substrate e2 is a back surface e2B. The front surface e2A and the back surface e2B have substantially the same shape and are parallel to each other. However, the back surface e2B is larger than the front surface e2A. Therefore, in the plan view seen from the direction orthogonal to the front surface e2A, the front surface e2A fits inside the back surface e2B. The rectangular edge defined by the pair of long sides e81 and short sides e82 on the front surface e2A is referred to as an edge portion e85, and the rectangular end defined by the pair of long sides e81 and short sides e82 on the back surface e2B. The edge is referred to as edge e90.

The substrate e2 has a plurality of side surfaces (side surface e2C, side surface e2D, side surface e2E, and side surface e2F) in addition to the front surface e2A and the back surface e2B. The plurality of side surfaces extend so as to intersect (specifically, orthogonally cross) each of the front surface e2A and the back surface e2B, and connect the front surface e2A and the back surface e2B.
The side surface e2C is constructed between the short sides e82 on one side in the longitudinal direction on the front surface e2A and the back surface e2B (the left front side in FIG. 111 (a)), and the side surface e2D is on the other side in the longitudinal direction on the front surface e2A and the back surface e2B ( It is constructed between the short sides e82 on the right back side in FIG. 111 (a). The side surface e2C and the side surface e2D are both end surfaces of the substrate e2 in the longitudinal direction. The side surface e2E is constructed between the long sides e81 on one side in the short direction of the front surface e2A and the back surface e2B (the left back side in FIG. 111 (a)), and the side surface e2F is the short direction of the front surface e2A and the back surface e2B It is installed between the long sides e81 on the other side (the right front side in FIG. 111 (a)). The side surface e2E and the side surface e2F are both end surfaces of the substrate e2 in the lateral direction. Each of the side surface e2C and the side surface e2D intersects (specifically, orthogonal) with each of the side surface e2E and the side surface e2F.

As described above, the adjacent ones on the surface e2A to the side surface e2F form a substantially right angle.
Each of the side surface e2C, the side surface e2D, the side surface e2E, and the side surface e2F (hereinafter referred to as “each side surface”) has a rough surface region S on the front surface e2A side and a streak pattern region P on the back surface e2B side. doing. In the rough surface region S, each side surface is a rough surface having a rough irregular pattern as shown by fine dots in FIG. On each side surface, in the streak pattern region P, a large number of streaks (saw marks) V forming a grinding trace of a dicing saw described later remain in a regular pattern. The reason why the rough surface region S and the streak pattern region P are present on each side surface is due to the manufacturing process of the chip resistor e1, and will be described in detail later.

  In each side surface, the rough surface region S occupies approximately half of the front surface e2A side, and the streak pattern region P occupies approximately half of the back surface e2B side. On each side surface, the streak pattern region P protrudes outward of the substrate e2 from the rough surface region S (outside the substrate e2 in plan view), whereby the rough surface region S and the streak pattern region P A step N is formed between them. The step N extends between the lower end edge of the rough surface region S and the upper end edge of the streak pattern region P and extends in parallel with the front surface e2A and the back surface e2B. The steps N on the side surfaces are connected to each other, and as a whole, have a rectangular frame shape located between the edge e85 of the front surface e2A and the edge e90 of the back surface e2B in plan view.

Thus, since the level | step difference N is provided in each side surface, as above-mentioned, the back surface e2B is larger than the surface e2A.
In the substrate e2, the entire region of the surface e2A and the side surfaces e2C to e2F (both the rough surface region S and the streak pattern region P on each side surface) is covered with the passivation film e23. Therefore, strictly speaking, in FIG. 111 (a), the entire regions of the surface e2A and the side surfaces e2C to e2F are located on the inner side (back side) of the passivation film e23 and are not exposed to the outside. Here, in the passivation film e23, a portion covering the surface e2A is referred to as a surface covering portion e23A, and a portion covering each of the side surfaces e2C to e2F is referred to as a side surface covering portion e23B.

Further, the chip resistor e1 has a resin film e24. The resin film e24 is a protective film (protective resin film) that is formed on the passivation film e23 and covers at least the entire surface e2A.
The passivation film e23 and the resin film e24 will be described in detail later.
The first connection electrode e3 and the second connection electrode e4 are formed in a region inside the edge portion e85 on the surface e2A of the substrate e2, and are partially exposed from the resin film e24 on the surface e2A. In other words, the resin film e24 covers the surface e2A (strictly, the passivation film e23 on the surface e2A) so as to expose the first connection electrode e3 and the second connection electrode e4. Each of the first connection electrode e3 and the second connection electrode e4 is configured, for example, by stacking Ni (nickel), Pd (palladium), and Au (gold) on the surface e2A in this order. The first connection electrode e3 and the second connection electrode e4 are spaced apart in the longitudinal direction of the surface e2A and are long in the short direction of the surface e2A. In FIG. 111A, on the surface e2A, the first connection electrode e3 is provided near the side surface e2C, and the second connection electrode e4 is provided near the side surface e2D.

  The element e5 is an element circuit network, and is formed on the substrate e2 (on the surface e2A), specifically, in a region between the first connection electrode e3 and the second connection electrode e4 on the surface e2A of the substrate e2. Further, it is covered from above with a passivation film e23 (surface covering portion e23A) and a resin film e24. The element e5 of this embodiment is a resistor e56. The resistor e56 is configured by a resistor network in which a plurality of (unit) resistors R having equal resistance values are arranged in a matrix on the surface e2A. Each resistor R is made of TiN (titanium nitride), TiON (titanium oxynitride) or TiSiON. The element e5 is electrically connected to a wiring film e22 to be described later, and is electrically connected to the first connection electrode e3 and the second connection electrode e4 via the wiring film e22.

  As shown in FIG. 111 (b), the first connection electrode e3 and the second connection electrode e4 are opposed to the mounting substrate e9, and the solder e13 is electrically connected to the pair of connection terminals e88 on the mounting substrate e9. Connect mechanically. As a result, the chip resistor e1 can be mounted on the mounting substrate e9 (flip chip connection). The first connection electrode e3 and the second connection electrode e4 functioning as external connection electrodes are made of gold (Au) or plated with gold in order to improve solder wettability and reliability. It is desirable.

FIG. 112 is a plan view of the chip resistor, showing the arrangement relationship between the first connection electrode, the second connection electrode and the element, and the configuration (layout pattern) of the element in plan view.
Referring to FIG. 112, element e5, which is a resistance network, includes eight resistors R arranged in the row direction (longitudinal direction of substrate e2) and the column direction (width direction of substrate e2). A total of 352 resistors R composed of 44 resistors R arranged in this manner. These resistors R are a plurality of element elements constituting a resistance network of the element e5.

  A plurality of types of resistor circuits R are formed by grouping and electrically connecting a large number of these resistors R every predetermined number of 1 to 64. The formed plurality of types of resistance circuits are connected in a predetermined manner by a conductor film D (a wiring film formed of a conductor). Furthermore, a plurality of fuses (fuses) that can be cut (fused) on the surface e2A of the substrate e2 in order to electrically incorporate a resistance circuit with respect to the element e5 or to electrically separate it from the element e5. F is provided. The plurality of fuses F and conductor films D are arranged along the inner side of the second connection electrode e3 so that the arrangement region is linear. More specifically, the plurality of fuses F and the conductor film D are arranged so as to be adjacent to each other, and the arrangement direction thereof is linear. The plurality of fuses F respectively connect a plurality of types of resistor circuits (a plurality of resistors R for each resistor circuit) to the second connection electrode e3 so as to be cut (separable).

FIG. 113A is a plan view illustrating a part of the element shown in FIG. 112 in an enlarged manner. FIG. 113B is a longitudinal sectional view in the length direction along BB of FIG. 113A drawn to explain the configuration of the resistor in the element. FIG. 113C is a longitudinal sectional view in the width direction along CC of FIG. 113A drawn to explain the structure of the resistor in the element.
The structure of the resistor R will be described with reference to FIGS. 113A, 113B, and 113C.

The chip resistor e1 further includes an insulating layer e20 and a resistor film e21 in addition to the wiring film e22, the passivation film e23, and the resin film e24 described above (see FIGS. 113B and 113C). The insulating layer e20, the resistor film e21, the wiring film e22, the passivation film e23, and the resin film e24 are formed on the substrate e2 (surface e2A).
The insulating layer e20 is made of SiO ₂ (silicon oxide). The insulating layer e20 covers the entire surface e2A of the substrate e2. The insulating layer e20 has a thickness of about 10,000 mm.

  The resistor film e21 is formed on the insulating layer e20. The resistor film e21 is formed of TiN, TiON, or TiSiON. The thickness of the resistor film e21 is about 2000 mm. The resistor film e21 constitutes a plurality of resistor films (hereinafter referred to as “resistor film line e21A”) extending linearly in parallel between the first connection electrode e3 and the second connection electrode e4. The resistor film line e21A may be cut at a predetermined position in the line direction (see FIG. 113A).

  A wiring film e22 is stacked on the resistor film line e21A. The wiring film e22 is made of Al (aluminum) or an alloy of aluminum and Cu (copper) (AlCu alloy). The thickness of the wiring film e22 is about 8000 mm. The wiring film e22 is laminated on the resistor film line e21A at a predetermined interval R in the line direction, and is in contact with the resistor film line e21A.

FIG. 114 shows the electrical characteristics of the resistor film line e21A and the wiring film e22 having this configuration by circuit symbols. That is, as shown in FIG. 114 (a), each portion of the resistor film line e21A in the region of the predetermined interval R forms one resistor R having a certain resistance value r.
And in the area | region where the wiring film e22 was laminated | stacked, the resistor film line e21A is short-circuited by the said wiring film e22 by electrically connecting the resistors R with which the wiring film e22 adjoins. Therefore, a resistance circuit is formed which is formed by connecting in series the resistor R of the resistor r shown in FIG. 114 (b).

  Further, since the adjacent resistor film lines e21A are connected by the resistor film e21 and the wiring film e22, the resistor network of the element e5 shown in FIG. 113A is shown in FIG. A resistor circuit (consisting of R unit resistors) is formed. As described above, the resistor film e21 and the wiring film e22 constitute the resistor R and the resistor circuit (that is, the element e5). Each resistor R includes a resistor film line e21A (resistor film e21) and a plurality of wiring films e22 stacked on the resistor film line e21A at regular intervals in the line direction. The resistor film line e21A at a constant interval R where the e22 is not laminated constitutes one resistor R. The resistor film lines e <b> 21 </ b> A in the portion constituting the resistor R are all equal in shape and size. Therefore, the multiple resistors R arranged in a matrix on the substrate e2 have the same resistance value.

Further, the wiring film e22 laminated on the resistor film line e21A forms the resistor R and also plays a role of the conductor film D for connecting a plurality of resistors R to form a resistor circuit. (See FIG. 112).
FIG. 115 (a) is a partially enlarged plan view of a region including a fuse drawn by enlarging a part of the plan view of the chip resistor shown in FIG. 112, and FIG. 115 (b) is a plan view of FIG. 115 (a). It is a figure which shows the cross-sectional structure which follows BB.

  As shown in FIGS. 115A and 115B, the above-described fuse F and conductor film D are also formed by the wiring film e22 laminated on the resistor film e21 forming the resistor R. That is, the fuse F and the conductor film D are formed in the same layer as the wiring film e22 laminated on the resistor film line e21A forming the resistor R by Al or AlCu alloy which is the same metal material as the wiring film e22. Yes. As described above, the wiring film e22 is also used as a conductor film D for electrically connecting a plurality of resistors R in order to form a resistance circuit.

  That is, in the same layer laminated on the resistor film e21, the wiring film for forming the resistor R, the fuse F, the conductor film D, and the element e5 are connected to the first connection electrode e3 and the second electrode e2. A wiring film for connecting to the connection electrode e4 is formed as the wiring film e22 using the same metal material (Al or AlCu alloy). Note that the fuse F is different from the wiring film e22 (differentiated) because the fuse F is formed so as to be easily cut and no other circuit elements exist around the fuse F. This is because they are arranged in such a manner.

  Here, in the wiring film e22, a region where the fuse F is arranged is referred to as a trimming target region X (see FIGS. 112 and 115A). The trimming target region X is a linear region along the inner side of the second connection electrode e3, and not only the fuse F but also the conductor film D is disposed in the trimming target region X. A resistor film e21 is also formed below the wiring film e22 in the trimming target region X (see FIG. 115B). The fuse F is a wiring having a larger inter-wiring distance (separated from the surroundings) than the portion other than the trimming target region X in the wiring film e22.

The fuse F indicates not only a part of the wiring film e22 but also a group (fuse element) of a part of the resistor R (resistor film e21) and a part of the wiring film e22 on the resistor film e21. It may be.
Further, the fuse F has been described only in the case where the same layer as the conductor film D is used. However, in the conductor film D, another conductor film is further laminated thereon to lower the resistance value of the entire conductor film D. You may do it. Even in this case, if a conductive film is not laminated on the fuse F, the fusing property of the fuse F will not deteriorate.

FIG. 116 is an electric circuit diagram of an element according to the embodiment of the fifth reference example.
Referring to FIG. 116, element e5 includes reference resistor circuit R8, resistor circuit R64, two resistor circuits R32, resistor circuit R16, resistor circuit R8, resistor circuit R4, resistor circuit R2, resistor circuit R1, resistor circuit R. / 2, resistor circuit R / 4, resistor circuit R / 8, resistor circuit R / 16, resistor circuit R / 32 are connected in series from the first connection electrode e3 in this order. Each of the reference resistor circuit R8 and the resistor circuits R64 to R2 is configured by connecting in series the same number of resistors R as the last number (“64” in the case of R64). The resistor circuit R1 is composed of one resistor R. Each of the resistance circuits R / 2 to R / 32 is configured by connecting in parallel the same number of resistors R as the last number of itself (“32” in the case of R / 32). The meaning of the number at the end of the resistor circuit is the same in FIGS. 117 and 118 described later.

One fuse F is connected in parallel to each of the resistor circuits R64 to R / 32 other than the reference resistor circuit R8. The fuses F are connected in series either directly or via a conductor film D (see FIG. 115 (a)).
In a state where all the fuses F are not blown as shown in FIG. 116, the element e5 is a reference composed of eight resistors R provided in series between the first connection electrode e3 and the second connection electrode e4. A resistor circuit of the resistor circuit R8 is configured. For example, if the resistance value r of one resistor R is r = 8Ω, the chip resistor in which the first connection electrode e3 and the second connection electrode e4 are connected by a resistance circuit (reference resistance circuit R8) of 8r = 64Ω. A device e1 is configured.

  Further, in a state where all the fuses F are not blown, a plurality of types of resistor circuits other than the reference resistor circuit R8 are short-circuited. That is, 12 types of 13 resistor circuits R64 to R / 32 are connected in series to the reference resistor circuit R8, but each resistor circuit is short-circuited by a fuse F connected in parallel. From an electrical viewpoint, each resistance circuit is not incorporated in the element e5.

  In the chip resistor e1 according to this embodiment, the fuse F is selectively blown by, for example, laser light according to a required resistance value. Thereby, the resistance circuit in which the fuse F connected in parallel is blown is incorporated in the element e5. Therefore, the entire resistance value of the element e5 can be set to a resistance value in which a resistance circuit corresponding to the blown fuse F is connected in series.

  In particular, a plurality of types of resistor circuits have one, two, four, eight, sixteen, thirty-two, etc. resistors R having the same resistance value in series, and a geometric sequence having a common ratio of two. The number of resistors R is increased, and a plurality of types of series resistor circuits and resistors R having the same resistance value are connected in parallel to 2, 4, 8, 16,. A plurality of types of parallel resistance circuits are provided which are connected by increasing the number of resistors R in a geometric sequence. Therefore, by selectively fusing the fuse F (including the above-described fuse element), the resistance value of the entire element e5 (resistor e56) is adjusted finely and digitally to an arbitrary resistance value. Thus, a resistor having a desired value can be generated in the chip resistor e1.

FIG. 117 is an electric circuit diagram of an element according to another embodiment of the fifth reference example.
116, instead of configuring the element e5 by connecting the reference resistance circuit R8 and the resistance circuit R64 to the resistance circuit R / 32 in series, the element e5 may be configured as illustrated in FIG. Specifically, between the first connection electrode e3 and the second connection electrode e4, the reference resistance circuit R / 16 and 12 types of resistance circuits R / 16, R / 8, R / 4, R / 2, R1, R2 , R4, R8, R16, R32, R64, and R128 may be configured as a series connection circuit and the element e5 may be configured.

  In this case, a fuse F is connected in series to each of the 12 types of resistor circuits other than the reference resistor circuit R / 16. In a state where all the fuses F are not blown, each resistance circuit is electrically incorporated into the element e5. If the fuse F is selectively blown by a laser beam, for example, according to a required resistance value, a resistance circuit corresponding to the blown fuse F (a resistance circuit in which the fuse F is connected in series) is connected to the element e5. Therefore, the resistance value of the entire chip resistor e1 can be adjusted.

FIG. 118 is an electric circuit diagram of an element according to still another embodiment of the fifth reference example.
A feature of the element e5 shown in FIG. 118 is that a circuit configuration in which a plurality of types of resistor circuits are connected in series and a plurality of types of resistor circuits in parallel is connected in series. As in the previous embodiment, fuses F are connected in parallel to each of the plurality of resistor circuits connected in series, and the plurality of resistor circuits connected in series are all short-circuited by the fuse F. It is in a state. Therefore, when the fuse F is blown, the resistance circuit short-circuited by the blown fuse F is electrically incorporated into the element e5.

On the other hand, a fuse F is connected in series to each of the plurality of types of resistor circuits connected in parallel. Therefore, by blowing the fuse F, the resistor circuit to which the blown fuse F is connected in series can be electrically disconnected from the parallel connection of the resistor circuit.
With this configuration, for example, a small resistance of 1 kΩ or less is made on the parallel connection side, and if a resistance circuit of 1 kΩ or more is made on the series connection side, a wide range from a small resistance of several Ω to a large resistance of several MΩ is obtained. Resistor circuits can be made using a network of resistors constructed with an equal basic design. That is, the chip resistor e1 can easily and quickly cope with a plurality of types of resistance values by selecting and cutting one or more fuses F. In other words, chip resistors e1 having various resistance values can be realized with a common design by combining a plurality of resistors R having different resistance values.

As described above, in the chip resistor e1, the connection state of the plurality of resistors R (resistor circuits) can be changed in the trimming target region X.
FIG. 119 is a schematic cross-sectional view of the chip resistor.
Next, the chip resistor e1 will be described in more detail with reference to FIG. For convenience of explanation, in FIG. 119, the element e5 described above is simplified and each element other than the substrate e2 is hatched.

Here, the passivation film e23 and the resin film e24 described above will be described.
The passivation film e23 is made of, for example, SiN (silicon nitride), and has a thickness of 1000 to 5000 mm (here, about 3000 mm). As described above, the passivation film e23 includes the surface covering portion e23A provided over the entire area of the surface e2A and the side surface covering portion e23B provided over the entire area of each of the side surfaces e2C to e2F. The surface covering portion e23A covers the resistor film e21 and each wiring film e22 (that is, the element e5) on the resistor film e21 from the surface (the upper side of FIG. 119), and the upper surface of each resistor R in the element e5. Covering. Therefore, the surface covering portion e23A also covers the wiring film e22 in the trimming target region X described above (see FIG. 115 (b)). The surface covering portion e23A is in contact with the element e5 (the wiring film e22 and the resistor film e21), and is also in contact with the insulating layer e20 in a region other than the resistor film e21. Thus, the surface covering portion e23A functions as a protective film that covers the entire surface e2A and protects the element e5 and the insulating layer e20. Further, on the surface e2A, the surface covering portion e23A prevents a short circuit between the resistors R other than the wiring film e22 (short circuit between adjacent resistor film lines e21A).

On the other hand, the side surface covering portion e23B provided on each of the side surfaces e2C to e2F functions as a protective layer that protects each of the side surfaces e2C to e2F. The side surface covering portion e23B covers all of the rough surface region S and the streak pattern region P in each of the side surfaces e2C to e2F, and also covers the step N between the rough surface region S and the streak pattern region P without leakage. ing.
The boundary between each of the side surfaces e2C to e2F and the surface e2A is the edge e85 described above, but the passivation film e23 also covers the boundary (edge e85). In the passivation film e23, a portion covering the edge portion e85 (a portion overlapping the edge portion e85) is referred to as an end portion e23C.

  The resin film e24 protects the surface e2A of the chip resistor e1 together with the passivation film e23, and is made of a resin such as polyimide. The resin film e24 is on the surface coating portion e23A (including the above-described end portion e23C) of the passivation film e23 so as to cover all regions other than the first connection electrode e3 and the second connection electrode e4 on the surface e2A in plan view. Is formed. Therefore, the resin film e24 covers the entire surface of the surface covering portion e23A (including the element e5 and the fuse F covered by the surface covering portion e23A) on the surface e2A. On the other hand, the resin film e24 does not cover the side surfaces e2C to e2F. Therefore, the edge 24A on the outer periphery of the resin film e24 is aligned with the side surface covering portion e23B in a plan view, and the side end surface e24B of the resin film e24 on the edge 24A is the side surface covering portion e23B (strictly speaking, the rough surface of each side surface It is flush with the side surface covering portion e23B) in the surface region S and extends in the thickness direction of the substrate e2. The surface e24C of the resin film e24 extends flat so as to be parallel to the surface e2A of the substrate e2. When stress is applied to the surface e2A side of the substrate e2 in the chip resistor e1, the surface e24C of the resin film e24 (particularly, the surface e24C in the region between the first connection electrode e3 and the second connection electrode e4) Functions as a stress dispersion surface and disperses the stress.

  Further, in the resin film e24, one opening e25 is formed at two positions separated in plan view. Each opening e25 is a through-hole that continuously penetrates the resin film e24 and the passivation film e23 (surface covering portion e23A) in the respective thickness directions. Therefore, the opening e25 is formed not only in the resin film e24 but also in the passivation film e23. A part of the wiring film e22 is exposed from each opening e25. A portion exposed from each opening e25 in the wiring film e22 is a pad region e22A (pad) for external connection. Each opening e25 extends along the thickness direction of the surface covering portion e23A (same as the thickness direction of the substrate e2) in the surface covering portion e23A, and in the resin film e24, the resin film e24 from the surface covering portion e23A side. The substrate e2 gradually spreads in the longitudinal direction (left and right direction in FIG. 119) toward the surface e24C. Therefore, the section screen e24D that partitions the opening e25 in the resin film e24 is an inclined surface that intersects the thickness direction of the substrate e2. In the resin film e24, a portion bordering each opening e25 has a pair of section screens e24D that partitions the opening e25 from the longitudinal direction. The interval between the section screens e24D is on the surface covering portion e23A side. Gradually expands toward the surface e24C of the resin film e24. Further, in the resin film e24, there is another pair of section screens e24D for partitioning the openings e25 from the short direction of the substrate e2 (not shown in FIG. 119). The interval between the partition screens e24D may also gradually increase from the surface covering portion e23A side toward the surface e24C of the resin film e24.

  Of the two openings e25, one opening e25 is filled with the first connection electrode e3, and the other opening e25 is filled with the second connection electrode e4. Each of the first connection electrode e3 and the second connection electrode e4 extends toward the surface e24C of the resin film e24 according to the opening e25 that extends toward the surface e24C of the resin film e24. Therefore, each longitudinal section (cut surface when cut along a plane along the longitudinal direction and the thickness direction of the substrate e2) of each of the first connection electrode e3 and the second connection electrode e4 is an upper base on the surface e2A side of the substrate e2. And has a trapezoidal shape with a lower base on the surface e24C side of the resin film e24. In addition, the lower bottoms are the surfaces e3A and e4A in the first connection electrode e3 and the second connection electrode e4, respectively. In each of the surfaces e3A and e4A, the end on the opening e25 side is the surface e2A side of the substrate e2 Curved to When the opening e25 does not expand toward the surface e24C of the resin film e24 (the section screen e24D that defines the opening e25 extends in the thickness direction of the substrate e2), each of the surfaces e3A and e4A is In all the regions including the end on the opening e25 side, the surface becomes a flat surface along the surface e2A of the substrate e2.

  Further, as described above, each of the first connection electrode e3 and the second connection electrode e4 is configured by stacking Ni, Pd, and Au on the surface e2A in this order, so that the Ni layer e33, Pd The layer e34 and the Au layer e35 are provided in this order from the surface e2A side. Therefore, the Pd layer e34 is interposed between the Ni layer e33 and the Au layer e35 in each of the first connection electrode e3 and the second connection electrode e4. In each of the first connection electrode e3 and the second connection electrode e4, the Ni layer e33 occupies most of each connection electrode, and the Pd layer e34 and the Au layer e35 are formed much thinner than the Ni layer e33. ing. When the chip resistor e1 is mounted on the mounting substrate e9 (see FIG. 111B), the Ni layer e33 relays the Al of the wiring film e22 in the pad region e22A of each opening e25 and the above-described solder e13. Have a role to play.

  In the first connection electrode e3 and the second connection electrode e4, since the surface of the Ni layer e33 is covered with the Au layer e35 via the Pd layer e34, the Ni layer e33 can be prevented from being oxidized. Even if the Au layer e35 is thinned to form a through hole (pin hole) in the Au layer e35, the Pd layer e34 interposed between the Ni layer e33 and the Au layer e35 has the through hole. Since it is plugged, it is possible to prevent the Ni layer e33 from being exposed to the outside through the through hole and being oxidized.

  In each of the first connection electrode e3 and the second connection electrode e4, the Au layer e35 is exposed on the outermost surface as the surfaces e3A and e4A, and faces the outside from the opening e25 on the surface e24A of the resin film e24. Yes. The first connection electrode e3 is electrically connected to the wiring film e22 in the pad region e22A in the opening e25 through one opening e25. The second connection electrode e4 is electrically connected to the wiring film e22 in the pad region e22A in the opening e25 via the other opening e25. In each of the first connection electrode e3 and the second connection electrode e4, the Ni layer e33 is connected to the pad region e22A. Thereby, each of the first connection electrode e3 and the second connection electrode e4 is electrically connected to the element e5. Here, the wiring film e22 forms a wiring connected to each of the group of resistors R (resistor e56), the first connection electrode e3, and the second connection electrode e4.

  Thus, the resin film e24 and the passivation film e23 in which the opening e25 is formed cover the surface e2A in a state where the first connection electrode e3 and the second connection electrode e4 are exposed from the opening e25. Therefore, electrical connection between the chip resistor e1 and the mounting substrate e9 can be achieved through the first connection electrode e3 and the second connection electrode e4 exposed in the opening e25 on the surface e24C of the resin film e24. (See FIG. 111 (b)).

  Here, the thickness H of the resin film e24, that is, the height H from the surface e2A of the substrate e2 to the surface e24C of the resin film e24, is determined from each of the first connection electrode e3 and the second connection electrode e4 (from the surface e2A). ) Height J or more. In FIG. 119, as the first embodiment, the height H and the height J are the same, and the surface e24C of the resin film e24 and the respective surfaces e3A of the first connection electrode e3 and the second connection electrode e4. , E4A are flush with each other.

120A to 120H are schematic sectional views showing a method for manufacturing the chip resistor shown in FIG. 119.
First, as shown in FIG. 120A, a substrate e30 that is a base of the substrate e2 is prepared. In this case, the front surface e30A of the substrate e30 is the front surface e2A of the substrate e2, and the back surface e30B of the substrate e30 is the back surface e2B of the substrate e2.

Then, the surface e30A of the substrate e30 is thermally oxidized to form an insulating layer e20 made of SiO ₂ or the like on the surface e30A, and the element e5 (the resistor R and the wiring film e22 connected to the resistor R is formed on the insulating layer e20. ). Specifically, first, a resistor film e21 of TiN, TiON, or TiSiON is formed on the entire surface of the insulating layer e20 by sputtering, and further, aluminum is formed on the resistor film e21 so as to be in contact with the resistor film e21. A (Al) wiring film e22 is laminated. Thereafter, using a photolithography process, the resistor film e21 and the wiring film e22 are selectively removed and patterned by dry etching such as RIE (Reactive Ion Etching), for example, as shown in FIG. In a plan view, a configuration is obtained in which resistor film lines e21A having a certain width on which the resistor films e21 are laminated are arranged in the column direction with a certain interval. At this time, a region in which the resistor film line e21A and the wiring film e22 are partially cut is formed, and the fuse F and the conductor film D are formed in the trimming target region X (see FIG. 112). Subsequently, the wiring film e22 laminated on the resistor film line e21A is selectively removed by, for example, wet etching and patterned. As a result, an element e5 (in other words, a plurality of resistors R) having a configuration in which the wiring film e22 is laminated at a predetermined interval R on the resistor film line e21A is obtained. In this way, the fuse F can be easily formed together with the plurality of resistors R by simply laminating the wiring film e22 on the resistor film e21 and patterning the resistor film e21 and the wiring film e22. In order to confirm whether or not the resistor film e21 and the wiring film e22 are formed with target dimensions, the resistance value of the entire element e5 may be measured.

  Referring to FIG. 120A, elements e5 are formed at a number of locations on surface e30A of substrate e30 according to the number of chip resistors e1 formed on one substrate e30. One region where the element e5 (the resistor e56 described above) is formed on the substrate e30 is referred to as a chip component region Y. On the surface e30A of the substrate e30, a plurality of chip component regions Y each having a resistor e56 are provided. That is, the element e5 is formed (set). One chip component region Y coincides with a plan view of one completed chip resistor e1 (see FIG. 119). A region between adjacent chip component regions Y on the surface e30A of the substrate e30 is referred to as a boundary region Z. The boundary region Z has a belt shape and extends in a lattice shape in plan view. One chip component region Y is arranged in one lattice defined by the boundary region Z. Since the width of the boundary region Z is as very narrow as 1 μm to 60 μm (for example, 20 μm), a large number of chip component regions Y can be secured on the substrate e30, and as a result, mass production of the chip resistors e1 becomes possible.

  Next, as shown in FIG. 120A, an insulating film e45 made of SiN is formed over the entire surface e30A of the substrate e30 by a CVD (Chemical Vapor Deposition) method. The insulating film e45 covers all of the insulating layer e20 and the element e5 (resistor film e21 and wiring film e22) on the insulating layer e20 and is in contact with them. Therefore, the insulating film e45 also covers the wiring film e22 in the above-described trimming target region X (see FIG. 112). In addition, since the insulating film e45 is formed over the entire surface e30A of the substrate e30, the insulating film e45 is formed to extend to a region other than the trimming target region X on the surface e30A. Thus, the insulating film e45 becomes a protective film that protects the entire surface e30A (including the element e5 on the surface e30A).

Next, as shown in FIG. 120B, a resist pattern e41 is formed over the entire surface e30A of the substrate e30 so as to cover the entire insulating film e45. An opening e42 is formed in the resist pattern e41.
FIG. 121 is a schematic plan view of a part of a resist pattern used for forming the first groove in the step of FIG. 120B.

  Referring to FIG. 121, the opening e42 of the resist pattern e41 is a plan view when a large number of chip resistors e1 (in other words, the above-described chip component region Y) are arranged in a matrix (also in a lattice shape). It corresponds to (corresponds to) the region between the outlines of the adjacent chip resistors e1 (the hatched portion in FIG. 121, in other words, the boundary region Z). Therefore, the entire shape of the opening e42 is a lattice shape having a plurality of linear portions e42A and e42B orthogonal to each other.

In the resist pattern e41, the straight portions e42A and e42B orthogonal to each other in the opening e42 are connected to each other while maintaining a state orthogonal to each other (without bending). Therefore, the intersecting portion e43 of the straight portions e42A and e42B is pointed so as to form approximately 90 ° in plan view.
Referring to FIG. 120B, each of insulating film e45, insulating layer e20, and substrate e30 is selectively removed by plasma etching using resist pattern e41 as a mask. As a result, the material of the substrate e30 is etched (removed) in the boundary region Z between the adjacent elements e5 (chip component region Y). As a result, a position (boundary region Z) coinciding with the opening e42 of the resist pattern e41 in plan view passes through the insulating film e45 and the insulating layer e20 and reaches the middle of the thickness of the substrate e30 from the surface e30A of the substrate e30. A first groove e44 having a predetermined depth is formed. The first groove e44 is partitioned by a pair of side surfaces e44A facing each other and a bottom surface e44B connecting the lower ends of the pair of side surfaces e44A (the end on the back surface e30B side of the substrate e30). The depth of the first groove e44 with respect to the surface e30A of the substrate e30 is about half the thickness T (see FIG. 111A) of the completed chip resistor e1, and the width of the first groove e44 (opposing M) is about 20 μm and is constant over the entire depth direction. Among the etching, the first groove e44 can be formed with high accuracy by using plasma etching in particular.

  The overall shape of the first groove e44 in the substrate e30 is a lattice shape that coincides with the opening e42 (see FIG. 121) of the resist pattern e41 in plan view. On the surface e30A of the substrate e30, a rectangular frame part (boundary region Z) in the first groove e44 surrounds the chip component region Y where each element e5 is formed. A portion of the substrate e30 where the element e5 is formed is a semi-finished product e50 of the chip resistor e1. On the surface e30A of the substrate e30, the semi-finished products e50 are located one by one in the chip component region Y surrounded by the first groove e44, and these semi-finished products e50 are arranged in a matrix.

  After the first groove e44 is formed as shown in FIG. 120B, the resist pattern e41 is removed, and as shown in FIG. 120C, a dicing machine (not shown) having a dicing saw e47 is operated. The dicing saw e47 is a disc-shaped grindstone, and a cutting tooth portion is formed on the peripheral end surface thereof. The width Q (thickness) of the dicing saw e47 is smaller than the width M of the first groove e44. Here, the dicing line U is set at the center position of the first groove e44 (position equidistant from the pair of side surfaces e44A facing each other). The dicing saw e47 moves in the first groove e44 along the dicing line U in a state where the central position 47A in the thickness direction coincides with the dicing line U in plan view, and at this time, the bottom surface of the first groove e44 The substrate e30 is shaved from e44B. When the movement of the dicing saw e47 is completed, a second groove e48 having a predetermined depth dug down from the bottom surface e44B of the first groove e44 is formed in the substrate e30.

  The second groove e48 is continuously recessed from the bottom surface e44B of the first groove e44 to the back surface e30B side of the substrate e30 at a predetermined depth. The second groove e48 is defined by a pair of side surfaces e48A facing each other and a bottom surface e48B connecting the lower ends of the pair of side surfaces e48A (ends on the back surface e30B side of the substrate e30). The depth of the second groove e48 relative to the bottom surface e44B of the first groove e44 is about half of the thickness T of the completed chip resistor e1, and the width of the second groove e48 (the distance between the opposing side surfaces e48A). Is the same as the width Q of the dicing saw e47 and is constant over the entire region in the depth direction. In the first groove e44 and the second groove e48, between the side surface e44A and the side surface e48A adjacent to each other in the thickness direction of the substrate e30, in a direction orthogonal to the thickness direction (a direction along the surface e30A of the substrate e30). An extending step e49 is formed. Therefore, a group of continuous first grooves e44 and second grooves e48 has a convex shape that becomes narrower toward the back surface e30B side. The side surface e44A becomes the rough surface region S of each side surface (each of the side surfaces e2C to e2F) of the completed chip resistor e1, the side surface e48A becomes the streak pattern region P of each side surface of the chip resistor e1, and the step e49 The level difference N on each side surface of the chip resistor e1.

  Here, by forming the first groove e44 by etching, the side surface e44A and the bottom surface e44B are rough surfaces with irregular patterns. On the other hand, by forming the second groove e48 with the dicing saw e47, a large number of lines forming a grinding mark of the dicing saw e47 remain in a regular pattern on each side surface e48A. Even if the side surface e48A is etched, this streak cannot be completely erased, and the finished chip resistor e1 becomes the streak V described above (see FIG. 111A).

  Next, as shown in FIG. 120D, the insulating film e45 is selectively removed by etching using the mask e65. In the mask e65, an opening e66 is formed in a portion of the insulating film e45 that coincides with each pad region e22A (see FIG. 119) in plan view. Thereby, a portion of the insulating film e45 that coincides with the opening e66 is removed by etching, and an opening e25 is formed in the portion. Thus, the insulating film e45 is formed so as to expose each pad region e22A in the opening e25. Two openings e25 are formed for one semi-finished product e50.

  In each semi-finished product e50, after the two openings e25 are formed in the insulating film e45, the probe e70 of the resistance measuring device (not shown) is brought into contact with the pad region e22A of each opening e25, so that the entire resistance value of the element e5 is obtained. Is detected. Then, by irradiating a laser beam (not shown) to an arbitrary fuse F (see FIG. 112) through the insulating film e45, the wiring film e22 in the trimming target region X is trimmed with the laser beam, and the fuse F is melted. In this way, by fusing (trimming) the fuse F so as to have a necessary resistance value, the resistance value of the entire semi-finished product e50 (in other words, the chip resistor e1) can be adjusted as described above. At this time, since the insulating film e45 is a cover film that covers the element e5, it is possible to prevent a short circuit from occurring due to debris or the like generated at the time of fusing attached to the element e5. Further, since the insulating film e45 covers the fuse F (resistor film e21), the energy of the laser beam can be stored in the fuse F and the fuse F can be blown surely.

  Thereafter, SiN is formed on the insulating film e45 by a CVD method to thicken the insulating film e45. At this time, as shown in FIG. 120E, the insulating film e45 is also formed over the entire inner peripheral surfaces (the side surface e44A, the bottom surface e44B, the side surface e48A, and the bottom surface e48B described above) of the first groove e44 and the second groove e48. Therefore, the insulating film e45 is also formed on the above-described step e49. The insulating film e45 (insulating film e45 in the state shown in FIG. 120E) on the inner peripheral surfaces of the first groove e44 and the second groove e48 has a thickness of 1000 to 5000 mm (here, about 3000 mm). ing. At this time, a part of the insulating film e45 enters each opening e25 and closes the opening e25.

  Thereafter, a photosensitive resin liquid made of polyimide is spray-applied onto the substrate e30 from above the insulating film e45 to form a photosensitive resin film e46 as shown in FIG. 120E. At this time, in order to prevent the liquid from entering the first groove e44 and the second groove e48, it passes through a mask (not shown) having a pattern that covers only the first groove e44 and the second groove e48 in plan view. The liquid is applied to the substrate e30. As a result, the liquid photosensitive resin is formed only on the substrate e30, and becomes a resin film e46 (resin film) on the substrate e30. The surface e46A of the resin film e46 on the surface e30A is flat along the surface e30A.

  Since the liquid does not enter the first groove e44 and the second groove e48, the resin film e46 is not formed in the first groove e44 and the second groove e48. In addition to spraying the photosensitive resin liquid, the resin film e46 may be formed by spin-coating the liquid or by attaching a sheet made of the photosensitive resin to the surface e30A of the substrate e30. Good.

Next, heat treatment (curing treatment) is performed on the resin film e46. As a result, the thickness of the resin film e46 is thermally contracted, and the resin film e46 is cured to stabilize the film quality.
Next, as shown in FIG. 120F, the resin film e46 is patterned, and portions of the resin film e46 on the surface e30A that coincide with the pad regions e22A (openings e25) of the wiring film e22 in plan view are selectively removed. Specifically, the resin film e46 is exposed and developed with the pattern e using a mask e62 in which an opening e61 having a pattern that matches (matches) with each pad region e22A in plan view. Thereby, the resin film e46 is separated above each pad region e22A to form an opening e25. At this time, a portion of the resin film e46 that borders the opening e25 is thermally contracted, and a section screen e46B that partitions the opening e25 in the portion becomes an inclined surface that intersects the thickness direction of the substrate e30. As a result, as described above, the opening e25 is in a state of being widened toward the surface e46A of the resin film e46 (which becomes the surface e24C of the resin film e24).

Next, the insulating film e45 on each pad region e22A is removed by RIE using a mask (not shown), whereby each opening e25 is opened and the pad region e22A is exposed.
Next, a Ni / Pd / Au laminated film formed by laminating Ni, Pd, and Au is formed on the pad region e22A in each opening e25 by electroless plating, as shown in FIG. 120G. A first connection electrode e3 and a second connection electrode e4 are formed on the region e22A.

FIG. 122 is a diagram for explaining a manufacturing process of the first connection electrode and the second connection electrode.
Specifically, referring to FIG. 122, first, the surface of pad region e22A is purified to remove (degrease) organic matter (including smut such as carbon stains and oily dirt) on the surface. (Step S1). Next, the oxide film on the surface is removed (step S2). Next, a zincate process is performed on the surface, and Al (of the wiring film e22) on the surface is replaced with Zn (step S3). Next, Zn on the surface is peeled off with nitric acid or the like, and new Al is exposed in the pad region e22A (step S4).

Next, Ni plating is performed on the surface of new Al in the pad region e22A by immersing the pad region e22A in a plating solution. Thereby, Ni in the plating solution is chemically reduced and deposited, and a Ni layer e33 is formed on the surface (step S5).
Next, Pd plating is performed on the surface of the Ni layer e33 by immersing the Ni layer e33 in another plating solution. Thereby, Pd in the plating solution is chemically reduced and deposited, and a Pd layer e34 is formed on the surface of the Ni layer e33 (step S6).

  Next, by immersing the Pd layer e34 in another plating solution, Au plating is performed on the surface of the Pd layer e34. Thereby, Au in the plating solution is chemically reduced and deposited, and an Au layer e35 is formed on the surface of the Pd layer e34 (step S7). Thereby, the first connection electrode e3 and the second connection electrode e4 are formed. When the first connection electrode e3 and the second connection electrode e4 after the formation are dried (step S8), the first connection electrode e3 and the second connection electrode The manufacturing process of the electrode e4 is completed. In addition, the process of wash | cleaning the semi-finished product e50 with water is suitably implemented between the steps which follow. In addition, the zincate process may be performed a plurality of times.

  FIG. 120G shows a state after the first connection electrode e3 and the second connection electrode e4 are formed in each semi-finished product e50. In each of the first connection electrode e3 and the second connection electrode e4, the surfaces e3A and e4A are flush with the surface e46A of the resin film e46. In addition, in accordance with the section screen e46B that partitions the opening e25 in the resin film e46, as described above, the first connection electrode e3 and the second connection electrode e4 have the opening e25 on the surfaces e3A and e4A, respectively. The edge on the edge side of the substrate is curved toward the back surface e30B side of the substrate e30. Therefore, in each of the first connection electrode e3 and the second connection electrode e4, the edge portion of the edge e of the opening e25 in each of the Ni layer e33, the Pd layer e34, and the Au layer e35 is curved toward the back surface e30B side of the substrate e30. Yes.

  As described above, since the first connection electrode e3 and the second connection electrode e4 are formed by electroless plating, the first connection electrode e3 and the second connection electrode e4 are compared with the case where the first connection electrode e3 and the second connection electrode e4 are formed by electrolytic plating. It is possible to improve the productivity of the chip resistor e1 by reducing the number of process steps (for example, a lithography process and a resist mask peeling process required for electrolytic plating) for the electrode e3 and the second connection electrode e4. Furthermore, in the case of electroless plating, since a resist mask required for electrolytic plating is unnecessary, there is a shift in the formation positions of the first connection electrode e3 and the second connection electrode e4 due to the position shift of the resist mask. Since it does not occur, the formation position accuracy of the first connection electrode e3 and the second connection electrode e4 can be improved, and the yield can be improved. Also, the first connection electrode e3 and the second connection electrode e4 can be formed only on the pad region e22A by performing electroless plating on the pad region e22A exposed from the resin film e24.

  In the case of electrolytic plating, the plating solution generally contains Ni or Sn. Therefore, Sn remaining on the surfaces e3A and e4A of the first connection electrode e3 and the second connection electrode e4 is oxidized, thereby connecting the first connection electrode e3 and the second connection electrode e4 to the connection terminal e88 of the mounting substrate e9 (FIG. 111 (b)) may occur, but there is no such problem in the fifth reference example using electroless plating.

After the first connection electrode e3 and the second connection electrode e4 are formed in this manner and then the energization inspection is performed between the first connection electrode e3 and the second connection electrode e4, the substrate e30 is ground from the back surface e30B. The
Specifically, as shown in FIG. 120H, a support tape e71 having a thin plate shape made of PET (polyethylene terephthalate) and having an adhesive surface e72 is formed on the adhesive surface e72 by the first connection electrode e3 in each semi-finished product e50 and It is attached to the second connection electrode e4 side (that is, the surface e30A). Thereby, each semi-finished product e50 is supported by the support tape e71. Here, as the support tape e71, for example, a laminate tape can be used.

  In a state where each semi-finished product e50 is supported by the support tape e71, the substrate e30 is ground from the back surface e30B side. When the substrate e30 is thinned until the back surface e30B reaches the bottom surface e48B (see FIG. 120G) of the second groove e48 by grinding, there is no connection between the adjacent semi-finished products e50. The substrate e30 is divided with the two grooves e48 as a boundary, and the semi-finished product e50 is individually separated to be a finished product of the chip resistor e1. That is, the substrate e30 is cut (divided) in the first groove e44 and the second groove e48 (in other words, the boundary region Z), and thereby the individual chip resistors e1 are cut out. The thickness of the substrate e30 (substrate e2) after grinding the back surface e30B is 150 μm to 400 μm (150 μm or more and 400 μm or less).

  In each completed chip resistor e1, the portion that formed the side surface e44A of the first groove e44 becomes the rough surface region S of any of the side surfaces e2C to e2F of the substrate e2, and forms the side surface e48A of the second groove e48. This portion becomes the streak pattern region P of any one of the side surfaces e2C to e2F of the substrate e2, and the step e49 between the side surface e44A and the side surface e48A becomes the above-described step N. In each completed chip resistor e1, the back surface e30B becomes the back surface e2B. That is, as described above, the step of forming the first groove e44 and the second groove e48 (see FIGS. 120B and 120C) is included in the step of forming the side surfaces e2C to e2F. Further, the insulating film e45 becomes the passivation film e23, and the resin film e46 becomes the resin film e24.

  For example, even if the depth of the first groove e44 (see FIG. 120B) formed by etching is not uniform, if the second groove e48 is formed by the dicing saw e47 (see FIG. 120C), the first groove e44 and the first groove e44 The entire depth of the second groove e48 (the depth from the surface e30A of the substrate e30 to the bottom of the second groove e48) is uniform. Therefore, when the back surface e30B of the substrate e30 is ground to separate the chip resistor e1, the time difference between the chip resistors e1 until the chip resistor e1 is separated from the substrate e30 is reduced, and the chip resistors e1 are made almost simultaneously. It can be separated from the substrate e30. As a result, it is possible to suppress a problem that chipping occurs in the chip resistor e1 due to the previously separated chip resistor e1 repeatedly colliding with the substrate e30. Further, since the corner (corner portion e11) on the surface e2A side of the chip resistor e1 is partitioned by the first groove e44 formed by etching, the corner portion e11 is partitioned by the dicing saw e47. In comparison, chipping is less likely to occur. As a result, chipping can be suppressed when the chip resistor e1 is singulated, and occurrence of singulation failure can be avoided. That is, the shape of the corner e11 (see FIG. 111A) on the surface e2A side of the chip resistor e1 can be controlled. In addition, compared with the case where both the first groove e44 and the second groove e48 are formed by etching, the time required for separating the chip resistor e1 is shortened, and the productivity of the chip resistor e1 is improved. You can also.

  In particular, when the thickness of the substrate e2 in the singulated chip resistor e1 is relatively large, 150 μm to 400 μm, a groove (from the surface e30A of the substrate e30 to the bottom surface e48B of the second groove e48 only by etching) 120C) is difficult and time consuming. However, even in such a case, the chip resistor is formed by grinding the back surface e30B of the substrate e30 after forming the first groove e44 and the second groove e48 by using etching and dicing by the dicing saw e47 in combination. The time required for separating e1 can be shortened. Therefore, the productivity of the chip resistor e1 can be improved.

  Further, if the second groove e48 reaches the back surface e30B of the substrate e30 by dicing (if the second groove e48 penetrates the substrate e30), the completed chip resistor e1 has a back surface e2B and side surfaces e2C˜ Chipping may occur at the corners with e2F. However, if the back surface e30B is polished after half dicing so that the second groove e48 does not reach the back surface e30B as in the fifth reference example (see FIG. 120C), the corner portion between the back surface e2B and the side surfaces e2C to e2F Chipping hardly occurs.

  Further, when a groove reaching only the surface e30A of the substrate e30 to the bottom surface e48B of the second groove e48 is formed by etching alone, the side surface of the completed groove does not follow the thickness direction of the substrate e2 due to variations in the etching rate. The cross section of is difficult to be rectangular. That is, the side surface of the groove varies. However, by using etching and dicing together as in the fifth reference example, compared to the case of only etching, the entire groove side surfaces of the first groove e44 and the second groove e48 (each of the side surface e44A and the side surface e48A). The variation can be reduced, and the side surface of the groove can be along the thickness direction of the substrate e2.

  Further, since the width Q of the dicing saw e47 is smaller than the width M of the first groove e44, the width Q of the second groove e48 formed by the dicing saw e47 is smaller than the width M of the first groove e44. The second groove e48 is located inside the first groove e44 (see FIG. 120C). Therefore, when the second groove e48 is formed by the dicing saw e47, the dicing saw e47 does not increase the width of the first groove e44. Therefore, it is possible to reliably prevent the corner e11 on the surface e2A side of the chip resistor e1 that should be partitioned by the first groove e44 from being partitioned by the dicing saw e47 and causing chipping at the corner e11.

  The chip resistor e1 is separated into pieces by grinding the back surface e30B after forming the second groove e48. However, before forming the second groove e48, the back surface e30B is ground first. Therefore, the second groove e48 may be formed by dicing. It is also assumed that the chip resistor e1 is cut out by etching the substrate e30 from the back surface e30B side to the bottom surface e48B of the second groove e48.

  As described above, if the substrate e30 is ground from the back surface e30B side after the first groove e44 and the second groove e48 are formed, a plurality of chip component regions Y formed on the substrate e30 are collectively separated into individual chip resistors. The chip can be divided into e1 (chip parts) (a plurality of chip resistors e1 can be obtained at a time). Therefore, the productivity of the chip resistor e1 can be improved by shortening the manufacturing time of the plurality of chip resistors e1. Incidentally, when a substrate e30 having a diameter of 8 inches is used, about 500,000 chip resistors e1 can be cut out.

That is, even if the chip size of the chip resistor e1 is small, the chip resistor e1 is formed by grinding the substrate e30 from the back surface e30B after first forming the first groove e44 and the second groove e48 in this way. Can be singulated at once.
Further, since the first groove e44 can be formed with high accuracy by etching, on the rough surface region S side of the side surfaces e2C to e2F defined by the first groove e44 in each chip resistor e1, the external dimension accuracy is improved. be able to. In particular, if plasma etching is used, the first groove e44 can be formed with higher accuracy. Further, since the interval between the first grooves e44 can be reduced according to the resist pattern e41 (see FIG. 121), the chip resistor e1 formed between the adjacent first grooves e44 can be reduced in size. . In the case of etching, chipping can be reduced in the corner portion e11 (see FIG. 111 (a)) between adjacent ones in the rough surface region S of the side surfaces e2C to e2F of the chip resistor e1, and the chip resistance can be reduced. The appearance of the container e1 can be improved.

Note that the back surface e2B of the completed chip resistor e1 may be mirror-finished by polishing or etching the back surface e2B of the substrate e2 to clean the back surface e2B.
As shown in FIG. 120H, the completed chip resistor e1 is peeled off from the support tape e71, and then conveyed to a predetermined space and stored in the space.
When the chip resistor e1 is mounted on the mounting board e9 (see FIG. 111B), the back surface e2B of the chip resistor e1 is attracted to the suction nozzle e91 (see FIG. 111B) of the automatic mounting machine. The chip resistor e1 is conveyed by moving the nozzle e91. At this time, the suction nozzle e91 is sucked to a substantially central portion in the longitudinal direction of the back surface e2B. Then, referring to FIG. 111 (b), the suction nozzle e91 that sucks the chip resistor e1 is moved to the mounting substrate e9. The mounting substrate e9 is provided with the pair of connection terminals e88 described above according to the first connection electrode e3 and the second connection electrode e4 of the chip resistor e1. The connection terminal e88 is made of Cu, for example. The solder e13 is provided on the surface of each connection terminal e88 so as to protrude from the surface.

  Therefore, by moving the suction nozzle e91 and pressing it against the mounting substrate e9, in the chip resistor e1, the first connection electrode e3 is brought into contact with the solder e13 of one connection terminal e88, and the second connection electrode e4 is connected to the other connection. Contact with the solder e13 of the terminal e88. When the solder e13 is heated in this state, the solder e13 is melted. After that, when the solder e13 is cooled and solidified, the first connection electrode e3 and the one connection terminal e88 are joined via the solder e13, and the second connection electrode e4 and the other connection terminal e88 join the solder e13. The chip resistor e1 is mounted on the mounting substrate e9.

FIG. 123 is a schematic diagram for explaining how the completed chip resistor is accommodated in the embossed carrier tape.
On the other hand, the completed chip resistor e1 as shown in FIG. 120H may be accommodated in the embossed carrier tape e92 shown in FIG.
The embossed carrier tape e92 is a tape (strip-shaped body) formed of, for example, polycarbonate resin. In the embossed carrier tape e92, a large number of pockets e93 are formed so as to be aligned in the longitudinal direction of the embossed carrier tape e92. Each pocket e93 is partitioned as a concave space that is recessed toward one surface (back surface) of the embossed carrier tape e92.

  When the completed chip resistor e1 (see FIG. 120H) is accommodated in the embossed carrier tape e92, the suction nozzle e91 (see FIG. 111 (b)) of the transport device is connected to the back surface e2B (substantially central portion in the longitudinal direction) of the chip resistor e1. ) And then the suction nozzle e91 is moved to peel off the chip resistor e1 from the support tape e71. Then, the suction nozzle e91 is moved to a position facing the pocket e93 of the embossed carrier tape e92. At this time, in the chip resistor e1 sucked by the suction nozzle e91, the first connection electrode e3, the second connection electrode e4, and the resin film e24 on the surface e2A side face the pocket e93.

  Here, when the chip resistor e1 is accommodated in the embossed carrier tape e92, the embossed carrier tape e92 is placed on a flat support base e95. The suction nozzle e91 is moved to the pocket e93 side (see the thick arrow), and the chip resistor e1 in the posture where the surface e2A side faces the pocket e93 is accommodated in the pocket e93. When the surface e2A side of the chip resistor e1 comes into contact with the bottom e93A of the pocket e93, the accommodation of the chip resistor e1 into the embossed carrier tape e92 is completed. When the surface e2A side of the chip resistor e1 is brought into contact with the bottom e93A of the pocket e93 by moving the suction nozzle e91, the first connection electrode e3, the second connection electrode e4, and the resin film e24 on the surface e2A side are It is pressed against the bottom e93A supported by e95.

  After the housing of the chip resistor e1 with respect to the embossed carrier tape e92 is completed, a release cover e94 is attached to the surface of the embossed carrier tape e92, and the inside of each pocket e93 is sealed by the release cover e94. This prevents foreign matter from entering each pocket e93. When taking out the chip resistor e1 from the embossed carrier tape e92, the peeling cover e94 is peeled off from the embossed carrier tape e92 and the pocket e93 is opened. Thereafter, the chip resistor e1 is taken out from the pocket e93 by the automatic mounting machine and mounted as described above.

  When the chip resistor e1 is mounted in this way, when the chip resistor e1 is accommodated in the embossed carrier tape e92, or when a stress test is performed on the chip resistor e1, the back surface of the chip resistor e1 When a force is applied to e2B (substantially central portion in the longitudinal direction) to press the first connection electrode e3 and the second connection electrode e4 against something (referred to as a “contacted portion”), the surface e2A of the substrate e2 Stress acts on The contacted part is a mounting substrate e9 when the chip resistor e1 is mounted. When the chip resistor e1 is accommodated in the embossed carrier tape e92, the contacted portion of the pocket e93 supported by the support base e95. The bottom e93A is a support surface that supports the chip resistor e1 that receives stress during a stress test.

  In this case, the height H (see FIG. 119) of the resin film e24 on the surface e2A of the substrate e2 is less than the respective heights J (see FIG. 119) of the first connection electrode e3 and the second connection electrode e4. A chip resistor e1 in which the surfaces e3A and 4A of the first connection electrode e3 and the second connection electrode e4 protrude most from the surface e2A of the substrate e2 (that is, the resin film e24 is thin) is conceivable (see FIG. 124 described later). ). Since such a chip resistor e1 is in contact (two-point contact) with only the first connection electrode e3 and the second connection electrode e4 on the surface e2A side, the chip resistor e1 is applied. The stress is concentrated at the junction between each of the first connection electrode e3 and the second connection electrode e4 and the substrate e2. As a result, the electrical characteristics of the chip resistor e1 may be deteriorated. Further, the stress causes distortion in the chip resistor e1 (particularly, the substantially central portion in the longitudinal direction of the substrate e2), and in a severe case, the substrate e2 may be cracked starting from the approximately central portion. .

  However, in the fifth reference example, as described above, the resin film e24 is thick so that the height H of the resin film e24 is not less than the height J of each of the first connection electrode e3 and the second connection electrode e4. (See FIG. 119). Therefore, the stress applied to the chip resistor e1 is received not only by the first connection electrode e3 and the second connection electrode e4 but also by the resin film e24. That is, since the area of the portion that receives stress in the chip resistor e1 can be increased, the stress applied to the chip resistor e1 can be dispersed. Thereby, concentration of stress on the first connection electrode e3 and the second connection electrode e4 can be suppressed in the chip resistor e1. In particular, the stress applied to the chip resistor e1 can be more effectively dispersed by the surface e24C of the resin film e24. Thereby, since the concentration of stress on the chip resistor e1 can be further suppressed, the strength of the chip resistor e1 can be improved. As a result, it is possible to suppress the breakage of the chip resistor e1 during mounting, during a durability test, or during storage in the embossed carrier tape e92. As a result, it is possible to improve the yield in mounting and accommodation in the embossed carrier tape e92. Further, since the chip resistor e1 is not easily broken, the handling property of the chip resistor e1 can be improved.

Next, a modified example of the chip resistor e1 will be described. 124 to 128 are schematic cross-sectional views of chip resistors according to first to fifth modifications. In the first to fifth modified examples, the same reference numerals are assigned to the portions corresponding to the portions described above for the chip resistor e1, and detailed description thereof is omitted.
Regarding the first connection electrode e3 and the second connection electrode e4, in FIG. 119, the surface e3A of the first connection electrode e3 and the surface e4A of the second connection electrode e4 are flush with the surface e24C of the resin film e24. If it is not considered to disperse the stress applied to the chip resistor e1 during mounting or the like, the surface e3A of the first connection electrode e3 and the surface of the second connection electrode e4 as in the first modification shown in FIG. e4A may protrude from the surface e24C of the resin film e24 in a direction away from the surface e2A of the substrate e2 (upward in FIG. 124). At this time, the height H of the resin film e24 is lower than the respective heights J of the first connection electrode e3 and the second connection electrode e4.

  Conversely, if it is desired to disperse the stress applied to the chip resistor e1 at the time of mounting or the like rather than the case of FIG. 119, the height H of the resin film e24 is set to the first value as in the second modification shown in FIG. The height may be higher than the height J of each of the connection electrode e3 and the second connection electrode e4. Thereby, the resin film e24 becomes thick, and the surface e3A of the first connection electrode e3 and the surface e4A of the second connection electrode e4 are closer to the surface e2A side of the substrate e2 than the surface e24C of the resin film e24 (lower in FIG. 124) ) In this case, since the first connection electrode e3 and the second connection electrode e4 are buried in the substrate e2 side with respect to the surface e24C of the resin film e24, the first connection electrode e3 and the second connection described above. The two-point contact itself at the electrode e4 does not occur. Therefore, the concentration of stress on the chip resistor e1 can be further suppressed. However, when the chip resistor e1 of the second modified example is mounted on the mounting board e9, the solder e13 on each connection terminal e88 of the mounting board e9 is replaced with the surface e3A of the first connection electrode e3 and the second connection electrode e4. It is necessary to prevent the connection failure between the first connection electrode e3 and the second connection electrode e4 and the solder e13 so as to reach the surface e4A (see FIG. 111B).

  Further, in the insulating layer e20 on the surface e2A of the substrate e2, the end surface e20A (portion that coincides with the edge e85 of the surface e2A in plan view) is the thickness direction of the substrate e2 (in FIGS. 119, 124, and 125). It extends in the vertical direction), but may be inclined as shown in FIGS. Specifically, the end surface e20A of the insulating layer e20 is inclined so as to go inward of the substrate e2 as it approaches the surface of the insulating layer e20 from the surface e2A of the substrate e2. In accordance with the end surface e20A, the portion of the passivation film e23 that covers the end surface e20A (the above-described end portion e23C) is also inclined along the end surface e20A.

In the chip resistor e1 of the third to fifth modifications shown in FIGS. 126 to 128, there is a difference in the position of the edge 24A of the resin film e24.
First, the chip resistor e1 of the third modification shown in FIG. 126 is the same as the chip resistor e1 of FIG. 119 except that the end surface e20A of the insulating layer e20 and the end portion e23C of the passivation film e23 are inclined. is there. Therefore, in a plan view, the edge 24A of the resin film e24 is aligned with the side surface covering portion e23B of the passivation film e23, and the edge portion e85 (surface of the substrate e2) of the surface e2A of the substrate e2 is equal to the thickness of the side surface covering portion e23B. It is located outside the edge of the surface e2A side). If it is desired to align the edge 24A with the side surface covering portion e23B in this way, when the photosensitive resin liquid is spray-applied to form the resin film e46 described above (see FIG. 120E), the mask 24 (not shown) is used. It is necessary to prevent the liquid from entering the first groove e44 and the second groove e48. Alternatively, even if the liquid enters the first groove e44 and the second groove e48, when the resin film e46 is subsequently patterned (see FIG. 120F), the first groove e44 and the second groove in the mask e62 in plan view. It is preferable to form an opening e61 in a portion that coincides with the groove e48. Then, the resin film e46 in the first groove e44 and the second groove e48 can be removed by patterning the resin film e46, and the edge 24A of the resin film e24 can be aligned with the side surface covering part e23B.

Here, since the resin film e <b> 24 is made of resin, there is little risk of cracking due to impact. Therefore, the resin film e24 can reliably protect the surface e2A (particularly, the element e5 and the fuse F) of the substrate e2 and the edge e85 of the surface e2A of the substrate e2 from the impact, so that the chip resistor having excellent impact resistance. A device e1 can be provided.
On the other hand, in the chip resistor e1 of the fourth modified example shown in FIG. 127, the edge 24A of the resin film e24 is not aligned with the side surface covering portion e23B of the passivation film e23 in plan view, and is more than the side surface covering portion e23B. Inward, more specifically, the substrate e2 recedes inward from the edge e85 of the surface e2A of the substrate e2. Also in this case, since the resin film e24 can reliably protect the surface e2A (particularly, the element e5 and the fuse F) of the substrate e2 from impact, it is possible to provide the chip resistor e1 having excellent impact resistance. In order to recede the edge 24A of the resin film e24 inward of the substrate e2, when patterning the resin film e46, an opening is also formed in a portion of the mask e62 that overlaps the edge e85 of the substrate e2 (substrate e30) in plan view. e61 may be formed (see FIG. 120F). Then, by patterning the resin film e46, the resin film e46 in a region overlapping with the edge e85 of the substrate e2 (substrate e30) in plan view is removed, and as a result, the edge 24A of the resin film e24 is moved inward of the substrate e2. Can be retreated.

  In the chip resistor e1 of the fifth modified example shown in FIG. 128, the edge 24A of the resin film e24 is not aligned with the side surface covering portion e23B of the passivation film e23 in plan view. Specifically, the resin film e24 projects outward from the side surface covering portion e23B and covers the entire side surface covering portion e23B from the outside. That is, in the fifth modification, the resin film e24 covers both the surface covering portion e23A and the side surface covering portion e23B of the passivation film e23. In this case, since the resin film e24 can reliably protect the surface e2A (particularly, the element e5 and the fuse F) of the substrate e2 and the side surfaces e2C to e2F of the substrate e2 from impact, the chip resistor having excellent impact resistance. e1 can be provided. If the resin film e24 wants to cover both the surface covering portion e23A and the side surface covering portion e23B, when the photosensitive resin liquid is spray applied to form the resin film e46 described above (see FIG. 120E), The liquid may enter the first groove e44 and the second groove e48 and adhere to the side surface covering portion e23B. As described above, when the liquid is spin-coated, it is not preferable because the liquid does not form a film and completely fills the first groove e44 and the second groove e48. On the other hand, when the resin film e46 is formed by attaching a sheet made of a photosensitive resin to the surface e30A of the substrate e30, the sheet cannot enter the first groove e44 and the second groove e48. Since the whole area of the side surface covering portion e23B cannot be covered, it is not preferable. Therefore, in order for the resin film e24 to cover both the surface covering portion e23A and the side surface covering portion e23B, it is effective to spray the photosensitive resin liquid.

  As mentioned above, although the embodiment of the fifth reference example has been described, the fifth reference example can be implemented in other forms. For example, as an example of the chip component of the fifth reference example, the chip resistor e1 is disclosed in the above-described embodiment, but the fifth reference example can also be applied to a chip component such as a chip capacitor, a chip inductor, or a chip diode. Below, a chip capacitor is explained.

FIG. 129 is a plan view of a chip capacitor according to another embodiment of the fifth reference example. 130 is a cross-sectional view taken along section line CXXX-CXXX in FIG. 129. FIG. 131 is an exploded perspective view showing a part of the structure of the chip capacitor separately.
In the chip capacitor e101 described below, the same reference numerals are given to the portions corresponding to the portions described in the above-described chip resistor e1, and detailed description thereof will be omitted. In the chip capacitor e101, a part denoted by the same reference numeral as that described for the chip resistor e1 has the same configuration as the part described for the chip resistor e1, unless otherwise specified. The same effect as the part demonstrated by e1 can be show | played.

  Referring to FIG. 129, similarly to the chip resistor e1, the chip capacitor e101 includes the substrate e2, the first connection electrode e3 disposed on the substrate e2 (the surface e2A side of the substrate e2), and the substrate e2. And a second connection electrode e4. In this embodiment, the substrate e2 has a rectangular shape in plan view. A first connection electrode e3 and a second connection electrode e4 are arranged at both ends in the longitudinal direction of the substrate e2. In this embodiment, the first connection electrode e3 and the second connection electrode e4 have a substantially rectangular planar shape extending in the short direction of the substrate e2. On the surface e2A of the substrate e2, a plurality of capacitor elements C1 to C9 are arranged in a capacitor arrangement region e105 between the first connection electrode e3 and the second connection electrode e4. The plurality of capacitor elements C1 to C9 are a plurality of element elements (capacitor elements) constituting the element e5 described above, and each of the second connection electrodes e4 via a plurality of fuse units e107 (corresponding to the above-described fuse F). Are electrically connected so as to be separable from each other. The element e5 constituted by these capacitor elements C1 to C9 forms a capacitor network.

  As shown in FIGS. 130 and 131, an insulating layer e20 is formed on the surface e2A of the substrate e2, and a lower electrode film e111 is formed on the surface of the insulating layer e20. The lower electrode film e111 extends over almost the entire capacitor arrangement region e105. Further, the lower electrode film e111 is formed to extend to a region immediately below the first connection electrode e3. More specifically, the lower electrode film e111 includes a capacitor electrode region e111A that functions as a common lower electrode of the capacitor elements C1 to C9 in the capacitor arrangement region e105, and an external electrode lead that is disposed immediately below the first connection electrode e3. And a pad region e111B (pad). The capacitor electrode region e111A is located in the capacitor arrangement region e105, and the pad region e111B is located immediately below the first connection electrode e3 and is in contact with the first connection electrode e3.

  A capacitor film (dielectric film) 112 is formed so as to cover and contact the lower electrode film e111 (capacitor electrode area e111A) in the capacitor arrangement area e105. The capacitive film e112 is formed over the entire capacitor electrode region e111A (capacitor placement region e105). In this embodiment, the capacitive film e112 further covers the insulating layer e20 outside the capacitor arrangement region e105.

  An upper electrode film e113 is formed on the capacitive film e112 so as to be in contact with the capacitive film e112. In FIG. 129, the upper electrode film e113 is colored for the sake of clarity. The upper electrode film e113 includes a capacitor electrode region e113A located in the capacitor arrangement region e105, a pad region e113B (pad) located immediately below the second connection electrode e4 and in contact with the second connection electrode e4, and a capacitor electrode region e113A. And a fuse region e113C disposed between the pad region e113B and the pad region e113B.

  In the capacitor electrode region e113A, the upper electrode film e113 is divided (separated) into a plurality of electrode film parts (upper electrode film parts) e131 to e139. In this embodiment, each of the electrode film portions e131 to e139 is formed in a rectangular shape, and extends in a band shape from the fuse region e113C toward the first connection electrode e3. The plurality of electrode film portions e131 to e139 are opposed to the lower electrode film e111 with a plurality of types of facing areas with the capacitor film e112 interposed therebetween (in contact with the capacitor film e112). More specifically, the facing area of the electrode film portions e131 to e139 with respect to the lower electrode film e111 may be determined to be 1: 2: 4: 8: 16: 32: 64: 128: 128. That is, the plurality of electrode film portions e131 to e139 include a plurality of electrode film portions having different facing areas, and more specifically, a plurality of facing areas set so as to form a geometric sequence with a common ratio of 2. It includes electrode film portions e131 to 138 (or e131 to e137, e139). Thereby, the plurality of capacitor elements C1 to C9 respectively constituted by the lower electrode film e111 and the capacitance film e112 opposed to each other with the electrode film portions e131 to e139 and the capacitance film e112 interposed therebetween have a plurality of capacitance values different from each other. Including capacitor elements. When the ratio of the opposing areas of the electrode film portions e131 to e139 is as described above, the ratio of the capacitance values of the capacitor elements C1 to C9 is equal to the ratio of the opposing areas, and is 1: 2: 4: 8: 16: 32. : 64: 128: 128. That is, the plurality of capacitor elements C1 to C9 include a plurality of capacitor elements C1 to C8 (or C1 to C7, C9) having capacitance values set so as to form a geometric sequence with a common ratio of 2.

  In this embodiment, the electrode film portions e131 to e135 are formed in a strip shape having the same width and a length ratio set to 1: 2: 4: 8: 16. Further, the electrode film portions e135, e136, e137, e138, e139 are formed in a strip shape having the same length and the width ratio set to 1: 2: 4: 8: 8. The electrode film portions e135 to e139 are formed to extend over a range from the edge on the second connection electrode e4 side of the capacitor arrangement region e105 to the edge on the first connection electrode e3 side. e134 is formed shorter than that.

The pad region e113B is formed substantially similar to the second connection electrode e4 and has a substantially rectangular planar shape. As shown in FIG. 130, the upper electrode film e113 in the pad region e113B is in contact with the second connection electrode e4.
The fuse region e113C is disposed along one long side of the pad region e113B (long side on the inner side with respect to the periphery of the substrate e2). The fuse region e113C includes a plurality of fuse units e107 arranged along the one long side of the pad region e113B.

  The fuse unit e107 is integrally formed of the same material as the pad region e113B of the upper electrode film e113. The plurality of electrode film portions e131 to e139 are integrally formed with one or a plurality of fuse units e107, and are connected to the pad region e113B via the fuse units e107, and the pad region e113B is connected to the electrode film portions e131 to e139. It is electrically connected to the second connection electrode e4. As shown in FIG. 129, the electrode film portions e131 to e136 having a relatively small area are connected to the pad region e113B by one fuse unit e107, and a plurality of electrode film portions e137 to e139 having a relatively large area are provided. It is connected to the pad region e113B through the fuse unit e107. Not all the fuse units e107 need be used, and in this embodiment, some of the fuse units e107 are unused.

  The fuse unit e107 includes a first wide portion e107A for connection to the pad region e113B, a second wide portion e107B for connection to the electrode film portions e131 to e139, and first and second wide portions e107A and 7B. And a narrow portion e107C that connects the two. The narrow portion e <b> 107 </ b> C is configured to be cut (melted) by laser light. Accordingly, unnecessary electrode film portions of the electrode film portions e131 to e139 can be electrically separated from the first and second connection electrodes e3 and e4 by cutting the fuse unit e107.

  Although not shown in FIGS. 129 and 131, as shown in FIG. 130, the surface of the chip capacitor e101 including the surface of the upper electrode film e113 is covered with the above-described passivation film e23. The passivation film e23 is made of, for example, a nitride film, and is formed so as to extend not only to the upper surface of the chip capacitor e101 but also to the side surfaces e2C to e2F of the substrate e2 and cover the entire side surfaces e2C to e2F. Further, the above-described resin film e24 is formed on the passivation film e23.

  The passivation film e23 and the resin film e24 are protective films that protect the surface of the chip capacitor e101. In these, the aforementioned openings e25 are formed in regions corresponding to the first connection electrode e3 and the second connection electrode e4, respectively. The opening e25 penetrates the passivation film e23 and the resin film e24 so as to expose a part of the pad region e111B of the lower electrode film e111 and a part of the pad region e113B of the upper electrode film e113. Furthermore, in this embodiment, the opening e25 corresponding to the first connection electrode e3 also penetrates the capacitive film e112.

  A first connection electrode e3 and a second connection electrode e4 are embedded in the opening e25. Thereby, the first connection electrode e3 is bonded to the pad region e111B of the lower electrode film e111, and the second connection electrode e4 is bonded to the pad region e113B of the upper electrode film e113. In this embodiment, the first and second external electrodes e3 and e4 are formed such that the respective surfaces e3A and e4A are substantially flush with the surface e24A of the resin film e24. Similarly to the chip resistor e1, the chip capacitor e101 can be flip-chip bonded to the mounting substrate e9.

  FIG. 132 is a circuit diagram showing an internal electrical configuration of the chip capacitor. A plurality of capacitor elements C1 to C9 are connected in parallel between the first connection electrode e3 and the second connection electrode e4. Between the capacitor elements C1 to C9 and the second connection electrode e4, fuses F1 to F9 each composed of one or a plurality of fuse units e107 are interposed in series.

  When all the fuses F1 to F9 are connected, the capacitance value of the chip capacitor e101 is equal to the sum of the capacitance values of the capacitor elements C1 to C9. When one or more fuses selected from the plurality of fuses F1 to F9 are disconnected, the capacitor element corresponding to the disconnected fuse is disconnected, and the capacitance of the chip capacitor e101 is equal to the capacitance value of the disconnected capacitor element. The value decreases.

  Therefore, the capacitance value between the pad regions e111B and e113B (total capacitance value of the capacitor elements C1 to C9) is measured, and then one or more appropriately selected from the fuses F1 to F9 according to the desired capacitance value. If the fuse is blown with a laser beam, adjustment to a desired capacitance value (laser trimming) can be performed. In particular, if the capacitance values of the capacitor elements C1 to C8 are set to form a geometric sequence with a common ratio of 2, the capacitor element C1 having the minimum capacitance value (the value of the first term of the geometric sequence). Fine adjustment is possible to match the target capacitance value with accuracy corresponding to the capacitance value.

For example, the capacitance values of the capacitor elements C1 to C9 may be determined as follows.
C1 = 0.03125pF
C2 = 0.0625pF
C3 = 0.125pF
C4 = 0.25pF
C5 = 0.5pF
C6 = 1pF
C7 = 2pF
C8 = 4pF
C9 = 4pF
In this case, the capacitance of the chip capacitor e101 can be finely adjusted with a minimum fitting accuracy of 0.03125 pF. Further, by appropriately selecting a fuse to be cut from the fuses F1 to F9, it is possible to provide a chip capacitor e101 having an arbitrary capacitance value between 10 pF and 18 pF.

  As described above, according to this embodiment, a plurality of capacitor elements C1 to C9 that can be separated by the fuses F1 to F9 are provided between the first connection electrode e3 and the second connection electrode e4. Capacitor elements C1 to C9 include a plurality of capacitor elements having different capacitance values, more specifically, a plurality of capacitor elements having capacitance values set so as to form a geometric sequence. As a result, by selecting one or more fuses from the fuses F1 to F9 and fusing them with laser light, it is possible to cope with a plurality of types of capacitance values without changing the design and accurately match the desired capacitance values. The chip capacitor e101 that can be embedded can be realized with a common design.

Details of each part of the chip capacitor e101 will be described below.
Referring to FIG. 129, substrate e2 has a rectangular shape such as 0.3 mm × 0.15 mm and 0.4 mm × 0.2 mm in plan view (preferably, a size of 0.4 mm × 0.2 mm or less). You may have. Capacitor arrangement region e105 is generally a square region having one side corresponding to the length of the short side of substrate e2. The thickness of the substrate e2 may be about 150 μm. Referring to FIG. 130, substrate e2 may be, for example, a substrate that has been thinned by grinding or polishing from the back side (the surface on which capacitor elements C1 to C9 are not formed). As a material of the substrate e2, a semiconductor substrate typified by a silicon substrate may be used, a glass substrate may be used, or a resin film may be used.

The insulating layer e20 may be an oxide film such as a silicon oxide film. The film thickness may be about 500 to 2000 mm.
The lower electrode film e111 is preferably a conductive film, particularly a metal film, and may be, for example, an aluminum film. The lower electrode film e111 made of an aluminum film can be formed by sputtering. Similarly, the upper electrode film e113 is preferably composed of a conductive film, particularly a metal film, and may be an aluminum film. The upper electrode film e113 made of an aluminum film can be formed by sputtering. Patterning for dividing the capacitor electrode region e113A of the upper electrode film e113 into electrode film portions e131 to e139 and further shaping the fuse region e113C into a plurality of fuse units e107 can be performed by photolithography and etching processes.

The capacitor film e112 can be made of, for example, a silicon nitride film, and the film thickness can be 500 to 2000 mm (for example, 1000 mm). The capacitive film e112 may be a silicon nitride film formed by plasma CVD (chemical vapor deposition).
The passivation film e23 can be made of, for example, a silicon nitride film, and can be formed by, for example, a plasma CVD method. The film thickness may be about 8000 mm. As described above, the resin film e24 can be formed of a polyimide film or other resin film.

  The first and second connection electrodes e3 and e4 are, for example, a Ni layer e33 in contact with the lower electrode film e111 or the upper electrode film e113, a Pd layer e34 stacked on the Ni layer e33, and a stack on the Pd layer e34. For example, it may be formed by an electroless plating method. The Ni layer e33 contributes to improving the adhesion to the lower electrode film e111 or the upper electrode film e113, and the Pd layer e34 is formed of the material of the upper electrode film or the lower electrode film and the uppermost layer of the first and second connection electrodes e3 and e4. It functions as a diffusion preventing layer that suppresses interdiffusion with gold.

The manufacturing process of such a chip capacitor e101 is the same as the manufacturing process of the chip resistor e1 after the element e5 is formed.
When the element e5 (capacitor element) is formed in the chip capacitor e101, first, an oxide film (for example, a silicon oxide film) is formed on the surface of the substrate e30 (substrate e2) by the thermal oxidation method and / or the CVD method. An insulating layer e20 is formed. Next, a lower electrode film e111 made of an aluminum film is formed over the entire surface of the insulating layer e20 by sputtering, for example. The film thickness of the lower electrode film e111 may be about 8000 mm. Next, a resist pattern corresponding to the final shape of the lower electrode film e111 is formed on the surface of the lower electrode film by photolithography. The lower electrode film e111 having the pattern shown in FIG. 129 or the like is obtained by etching the lower electrode film using the resist pattern as a mask. The etching of the lower electrode film e111 can be performed by, for example, reactive ion etching.

  Next, a capacitor film e112 made of a silicon nitride film or the like is formed on the lower electrode film e111 by, for example, plasma CVD. In the region where the lower electrode film e111 is not formed, the capacitor film e112 is formed on the surface of the insulating layer e20. Next, the upper electrode film e113 is formed on the capacitor film e112. The upper electrode film e113 is made of, for example, an aluminum film and can be formed by a sputtering method. The film thickness may be about 8000 mm. Next, a resist pattern corresponding to the final shape of the upper electrode film e113 is formed on the surface of the upper electrode film e113 by photolithography. By etching using the resist pattern as a mask, the upper electrode film e113 is patterned into a final shape (see FIG. 129 and the like). Accordingly, the upper electrode film e113 has a portion divided into a plurality of electrode film portions e131 to e139 in the capacitor electrode region e113A, and has a plurality of fuse units e107 in the fuse region e113C. It is shaped into a pattern having a connected pad region e113B. By dividing the upper electrode film e113, a plurality of capacitor elements C1 to C9 corresponding to the number of electrode film portions e131 to e139 can be formed. Etching for patterning the upper electrode film e113 may be performed by wet etching using an etchant such as phosphoric acid or by reactive ion etching.

  Thus, the element e5 (capacitor elements C1 to C9 and the fuse unit e107) in the chip capacitor e101 is formed. After the element e5 is formed, an insulating film e45 is formed by plasma CVD so as to cover all the elements e5 (the upper electrode film e113 and the capacitor film e112 in the region where the upper electrode film e113 is not formed) (FIG. 120A). Thereafter, after the first groove e44 and the second groove e48 are formed (see FIGS. 120B and 120C), the opening e25 is formed (see FIG. 120D). Then, the probe e70 is pressed against the pad region e113B of the upper electrode film e113 and the pad region e111B of the lower electrode film e111 exposed from the opening e25, and the total capacitance values of the plurality of capacitor elements C0 to C9 are measured ( (See FIG. 120D). Based on the measured total capacitance value, the capacitor element to be disconnected, that is, the fuse to be disconnected, is selected according to the target capacitance value of the chip capacitor e101.

  From this state, laser trimming for fusing the fuse unit e107 is performed. That is, a laser beam is applied to the fuse unit e107 constituting the fuse selected according to the measurement result of the total capacitance value, and the narrow portion e107C (see FIG. 129) of the fuse unit e107 is melted. As a result, the corresponding capacitor element is separated from the pad region e113B. When the laser light is applied to the fuse unit e107, the energy of the laser light is accumulated in the vicinity of the fuse unit e107 by the action of the insulating film e45 that is a cover film, and thereby the fuse unit e107 is melted. Thereby, the capacitance value of the chip capacitor e101 can be reliably set to the target capacitance value.

  Next, a silicon nitride film is deposited on the cover film (insulating film e45) by, for example, plasma CVD to form a passivation film e23. In the final form, the aforementioned cover film is integrated with the passivation film e23 and constitutes a part of this passivation film e23. The passivation film e23 formed after the fuse is cut enters into the opening of the cover film destroyed at the same time when the fuse is blown, and covers and protects the cut surface of the fuse unit e107. Therefore, the passivation film e <b> 23 prevents foreign matter from entering the cut portion of the fuse unit e <b> 107 and moisture from entering. Thereby, a highly reliable chip capacitor e101 can be manufactured. The passivation film e23 may be formed so as to have a film thickness of, for example, about 8000 mm as a whole.

  Next, the above-described resin film e46 is formed (see FIG. 120E). Thereafter, the opening e25 closed by the resin film e46 and the passivation film e23 is opened (see FIG. 120F), and the pad region e111B and the pad region e113B are exposed from the resin film e46 (resin film e24) through the opening e25. Is done. Thereafter, the first connection electrode e3 and the second connection electrode e4 are formed on the pad region e111B and the pad region e113B exposed from the resin film e46 in the opening e25, for example, by electroless plating (see FIG. 120G). .

Thereafter, as in the case of the chip resistor e1, when the substrate e30 is ground from the back surface e30B (see FIG. 120H), the piece of the chip capacitor e101 can be cut out.
In the patterning of the upper electrode film e113 using the photolithography process, the electrode film portions e131 to e139 having a small area can be formed with high accuracy, and the fuse unit e107 having a fine pattern can be formed. Then, after the patterning of the upper electrode film e113, the fuse to be cut is determined through measurement of the total capacitance value. By cutting the determined fuse, it is possible to obtain a chip capacitor e101 that is accurately adjusted to a desired capacitance value. That is, the chip capacitor e101 can easily and quickly cope with a plurality of types of capacitance values by selecting and cutting one or a plurality of fuses. In other words, chip capacitors e101 having various capacitance values can be realized with a common design by combining a plurality of capacitor elements C1 to C9 having different capacitance values.

Although the chip parts (chip resistor e1 and chip capacitor e101) of the fifth reference example have been described above, the fifth reference example can be implemented in still other forms.
For example, in the above-described embodiment, in the case of the chip resistor e1, the plurality of resistor circuits have a plurality of resistor circuits having resistance values forming a series of geometric ratios with a common ratio r (0 <r, r ≠ 1) = 2. However, the common ratio of the geometric sequence may be a number other than two. Also in the case of the chip capacitor e101, an example is shown in which the capacitor element has a plurality of capacitor elements having capacitance values forming a geometric sequence with a common ratio r (0 <r, r ≠ 1) = 2. However, the common ratio of the geometric sequence may be a number other than two.

In the chip resistor e1 and the chip capacitor e101, the insulating layer e20 is formed on the surface of the substrate e2. However, if the substrate e2 is an insulating substrate, the insulating layer e20 can be omitted.
Further, in the chip capacitor e101, only the upper electrode film e113 is divided into a plurality of electrode film parts, but only the lower electrode film e111 is divided into a plurality of electrode film parts, or the upper electrode film e113. Both the lower electrode film e111 may be divided into a plurality of electrode film portions. Furthermore, in the above-described embodiment, an example in which the upper electrode film or the lower electrode film and the fuse unit are integrated is shown. However, the fuse unit is formed of a conductor film different from the upper electrode film or the lower electrode film. May be. Further, in the above-described chip capacitor e101, a single-layer capacitor structure having the upper electrode film e113 and the lower electrode film e111 is formed, but another electrode film is laminated on the upper electrode film e113 via a capacitive film. Thus, a plurality of capacitor structures may be stacked.

In the chip capacitor e101, a capacitive substrate e112 may be formed so as to be in contact with the surface of the conductive substrate using a conductive substrate as the substrate e2, using the conductive substrate as a lower electrode. In this case, one external electrode may be drawn from the back surface of the conductive substrate.
When the fifth reference example is applied to a chip inductor, the element e5 formed on the substrate e2 in the chip inductor includes an inductor circuit network (inductor element) including a plurality of inductor elements (element elements). including. In this case, the element e5 is provided in the multilayer wiring formed on the surface e2A of the substrate e2, and is formed by the wiring film e22. In this chip inductor, the combination pattern of a plurality of inductor elements in the inductor network can be changed to an arbitrary pattern by selecting and cutting one or a plurality of fuses F. However, various chip inductors can be realized with a common design.

  When the fifth reference example is applied to a chip diode, the element e5 formed on the substrate e2 in the chip diode is a diode network (diode element) including a plurality of diode elements (element elements). including. The diode element is formed on the substrate e2. In this chip diode, by selecting and cutting one or a plurality of fuses F, a combination pattern of a plurality of diode elements in the diode network can be changed to an arbitrary pattern. However, various chip diodes can be realized with a common design.

In both the chip inductor and the chip diode, the same effects as those of the chip resistor e1 and the chip capacitor e101 can be obtained.
In addition, in the first connection electrode e3 and the second connection electrode e4 described above, the Pd layer e34 interposed between the Ni layer e33 and the Au layer e35 can be omitted. Since the adhesion between the Ni layer e33 and the Au layer e35 is good, the Pd layer e34 may be omitted if the above-described pinhole cannot be formed in the Au layer e35.

Further, as described above, if the intersecting portion e43 (see FIG. 121) of the opening e42 of the resist pattern e41 used when forming the first groove e44 by etching is rounded, in the completed chip component, the substrate e2 A corner portion (corner portion in the rough surface region S) e11 on the surface e2A side can be formed in a round shape.
Further, the configurations of the modifications 1 to 5 (FIGS. 124 to 128) described in the chip resistor e1 can be applied to any of the chip capacitor e101, the chip inductor, and the chip diode.

  FIG. 133 is a perspective view illustrating an appearance of a smartphone that is an example of an electronic device in which the chip component of the fifth reference example is used. The smartphone e201 is configured by housing electronic components inside a flat rectangular parallelepiped housing e202. The housing e202 has a pair of rectangular main surfaces on the front side and the back side, and the pair of main surfaces are joined by four side surfaces. On one main surface of the housing e202, the display surface of the display panel e203 formed of a liquid crystal panel, an organic EL panel, or the like is exposed. The display surface of the display panel e203 constitutes a touch panel and provides an input interface for the user.

  The display panel e203 is formed in a rectangular shape that occupies most of one main surface of the housing e202. An operation button e204 is arranged along one short side of the display panel e203. In this embodiment, a plurality (three) of operation buttons e204 are arranged along the short side of the display panel e203. The user can operate the smartphone e201 by operating the operation button e204 and the touch panel to call and execute necessary functions.

  A speaker e205 is disposed in the vicinity of another short side of the display panel e203. The speaker e205 provides an earpiece for a telephone function and is also used as an acoustic unit for reproducing music data and the like. On the other hand, a microphone e206 is disposed on one side surface of the housing e202 near the operation button e204. The microphone e206 provides a mouthpiece for a telephone function and can also be used as a recording microphone.

  FIG. 134 is a schematic plan view showing the configuration of the electronic circuit assembly e210 accommodated in the housing e202. The electronic circuit assembly e210 includes a wiring board e211 and circuit components mounted on the mounting surface of the wiring board e211. The plurality of circuit components include a plurality of integrated circuit elements (ICs) e212 to e220 and a plurality of chip components. The plurality of ICs include a transmission processing ICe 212, a one-segment TV receiving ICe 213, a GPS receiving ICe 214, an FM tuner ICe 215, a power source IC 216, a flash memory e 217, a microcomputer e 218, a power source IC 219, and a baseband ICe 220. A plurality of chip components (corresponding to the chip components of the fifth reference example) include chip inductors e221, e225, e235, chip resistors e222, e224, e233, chip capacitors e227, e230, e234, and chip diodes e228, e231. Including.

The transmission processing ICe 212 includes an electronic circuit that generates a display control signal for the display panel e203 and receives an input signal from the touch panel on the surface of the display panel e203. A flexible wiring 209 is connected to the transmission processing ICe 212 for connection with the display panel e203.
The one-seg TV reception ICe 213 incorporates an electronic circuit that constitutes a receiver for receiving radio waves of one-seg broadcasting (terrestrial digital television broadcasting intended for receiving portable devices). In the vicinity of the one-segment TV reception ICe 213, a plurality of chip inductors e221 and a plurality of chip resistors e222 are arranged. The one-segment TV reception ICe 213, the chip inductor e221, and the chip resistor e222 constitute a one-segment broadcast reception circuit e223. The chip inductor e221 and the chip resistor e222 respectively have an inductance and a resistance that are accurately matched, and give a highly accurate circuit constant to the one-segment broadcasting reception circuit e223.

The GPS receiving ICe 214 includes an electronic circuit that receives radio waves from GPS satellites and outputs position information of the smartphone e201.
The FM tuner ICe215 forms an FM broadcast receiving circuit e226 together with a plurality of chip resistors e224 and a plurality of chip inductors e225 mounted on the wiring board e211 in the vicinity thereof. The chip resistor e224 and the chip inductor e225 each have a resistance value and an inductance that are accurately matched, and give a highly accurate circuit constant to the FM broadcast receiving circuit e226.

A plurality of chip capacitors e227 and a plurality of chip diodes e228 are mounted on the mounting surface of the wiring board e211 in the vicinity of the power supply ICe216. The power supply ICe 216 constitutes a power supply circuit e229 together with the chip capacitor e227 and the chip diode e228.
The flash memory e217 is a storage device for recording an operating system program, data generated inside the smartphone e201, data and a program acquired from the outside by a communication function, and the like.

The microcomputer e218 includes a CPU, a ROM, and a RAM, and is an arithmetic processing circuit that realizes a plurality of functions of the smartphone e201 by executing various arithmetic processes. More specifically, image processing and arithmetic processing for various application programs are realized by the operation of the microcomputer e218.
Near the power supply ICe 219, a plurality of chip capacitors e230 and a plurality of chip diodes e231 are mounted on the mounting surface of the wiring board e211. The power supply ICe 219 constitutes a power supply circuit e232 together with the chip capacitor e230 and the chip diode e231.

  Near the baseband ICe220, a plurality of chip resistors e233, a plurality of chip capacitors e234, and a plurality of chip inductors e235 are mounted on the mounting surface of the wiring board e211. The baseband ICe220 constitutes a baseband communication circuit e236 together with the chip resistor e233, the chip capacitor e234, and the chip inductor e235. The baseband communication circuit e236 provides a communication function for telephone communication and data communication.

  With such a configuration, the power appropriately adjusted by the power supply circuits e229 and e232 is transmitted to the transmission processing ICe212, the GPS reception ICe214, the one-segment broadcast reception circuit e223, the FM broadcast reception circuit e226, the baseband communication circuit e236, the flash memory e217, and It is supplied to the microcomputer e218. The microcomputer e218 performs arithmetic processing in response to an input signal input via the transmission processing ICe212, outputs a display control signal from the transmission processing ICe212 to the display panel e203, and causes the display panel e203 to perform various displays. .

When reception of one-segment broadcasting is instructed by operating the touch panel or the operation button e204, the one-segment broadcasting is received by the function of the one-segment broadcasting receiving circuit e223. Then, the microcomputer e218 executes arithmetic processing for outputting the received image to the display panel e203 and causing the received sound to be audible from the speaker e205.
When the position information of the smartphone e201 is required, the microcomputer e218 acquires the position information output from the GPS reception ICe 214, and executes a calculation process using the position information.

Further, when an FM broadcast reception command is input by operating the touch panel or the operation button e204, the microcomputer e218 activates the FM broadcast reception circuit e226 and executes arithmetic processing for outputting the received sound from the speaker e205. To do.
The flash memory e <b> 217 is used for storing data acquired by communication, calculation of the microcomputer e <b> 218, and data created by input from the touch panel. The microcomputer e218 writes data to the flash memory e217 and reads data from the flash memory e217 as necessary.

  The function of telephone communication or data communication is realized by the baseband communication circuit e236. The microcomputer e218 controls the baseband communication circuit e236 to perform processing for transmitting and receiving voice or data.

DESCRIPTION OF SYMBOLS 1 Chip resistor 2 Board | substrate 2A Element formation surface 2B Back surface 2C Side surface 2D Side surface 2E Side surface 2F Side surface 3 1st connection electrode 4 2nd connection electrode 11 Crossing part 20 Insulating layer 22 Wiring film 23 Insulating film 24 Resin film 27 Crossing part 30 Substrate 30B Back surface 44 Groove 56 Resistance 71 Support base material R Resistor X Trimming target area Y Chip resistor area Z Boundary area

Claims (16)

Forming each element in a plurality of chip component regions set on the surface of the substrate;
Forming a groove having a predetermined depth from the surface of the substrate in a boundary region of the plurality of chip component regions;
Grinding the back surface of the substrate until it reaches the groove, and dividing the substrate into a plurality of chip components.   The manufacturing method of the chip component of Claim 1 including the process of forming a protective film in the side wall of the said groove | channel. Forming the groove includes forming a resist pattern corresponding to the boundary region;
The method of manufacturing a chip component according to claim 1, further comprising: forming the groove by etching using the resist pattern as a mask.   The method for manufacturing a chip part according to claim 3, wherein the etching is plasma etching. Forming the element includes forming a resistor;
The chip component manufacturing method according to claim 1, wherein the chip component is a chip resistor. Forming the resistor includes forming a resistor film on the surface of the substrate; forming a wiring film in contact with the resistor film; and patterning the resistor film and the wiring film. Forming a plurality of the resistors by:
Forming an external connection electrode on the substrate for externally connecting the element;
The method of manufacturing a chip component according to claim 5, further comprising: forming a plurality of fuses on the substrate to detachably connect the plurality of resistors to the external connection electrode. Forming the element includes forming a capacitor element;
The chip component manufacturing method according to claim 1, wherein the chip component is a chip capacitor. The step of forming the capacitor element includes a step of forming a capacitive film on the surface of the substrate, a step of forming an electrode film in contact with the capacitive film, and dividing the electrode film into a plurality of electrode film portions. Forming a plurality of capacitor elements corresponding to the plurality of electrode film portions;
Forming an external connection electrode on the substrate for externally connecting the element;
The method of manufacturing a chip component according to claim 7, further comprising: forming a plurality of fuses on the substrate to detachably connect the plurality of capacitor elements to the external connection electrode.   The chip part manufacturing method according to any one of claims 1 to 8, wherein a planar shape of each chip part region is a rectangle having two orthogonal sides of 0.4 mm or less and 0.2 mm or less, respectively.   The manufacturing method of the chip component according to any one of claims 1 to 9, wherein a strip-shaped boundary region having a width of 1 µm to 60 µm is provided between the plurality of chip component regions. A substrate,
A plurality of element elements formed on the surface of the substrate;
An external connection electrode formed on the surface of the substrate;
A plurality of fuses formed on the surface of the substrate and severably connecting the plurality of element elements to the external connection electrodes,
A chip component, wherein a side surface of the substrate is a rough surface having an irregular pattern.   The chip component according to claim 11, comprising a protective film formed on the side surface. The element element is a resistor including a resistor film formed on a surface of the substrate and a wiring film laminated in contact with the resistor film,
The chip component according to claim 11 or 12, wherein the chip component is a chip resistor. The element element is a capacitor element including a capacitive film formed on a surface of the substrate and an electrode film formed in contact with the capacitive film;
The chip component according to claim 11 or 12, wherein the chip component is a chip capacitor.   The chip component according to claim 11 or 12, wherein the chip component is a chip inductor.   The chip component according to claim 11 or 12, wherein the chip component is a chip diode.

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