JP3432749B2 - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereofInfo
- Publication number
- JP3432749B2 JP3432749B2 JP20825898A JP20825898A JP3432749B2 JP 3432749 B2 JP3432749 B2 JP 3432749B2 JP 20825898 A JP20825898 A JP 20825898A JP 20825898 A JP20825898 A JP 20825898A JP 3432749 B2 JP3432749 B2 JP 3432749B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- semiconductor device
- semiconductor
- sealing resin
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 267
- 238000004519 manufacturing process Methods 0.000 title description 15
- 229920005989 resin Polymers 0.000 claims description 83
- 239000011347 resin Substances 0.000 claims description 83
- 238000007789 sealing Methods 0.000 claims description 65
- 239000000758 substrate Substances 0.000 claims description 36
- 230000015572 biosynthetic process Effects 0.000 claims description 20
- 238000010586 diagram Methods 0.000 description 15
- 230000035882 stress Effects 0.000 description 13
- 238000000034 method Methods 0.000 description 12
- 230000000694 effects Effects 0.000 description 8
- 229910000679 solder Inorganic materials 0.000 description 8
- 230000002093 peripheral effect Effects 0.000 description 7
- 230000002950 deficient Effects 0.000 description 6
- 238000002347 injection Methods 0.000 description 6
- 239000007924 injection Substances 0.000 description 6
- 230000007547 defect Effects 0.000 description 5
- 230000017525 heat dissipation Effects 0.000 description 5
- 238000010521 absorption reaction Methods 0.000 description 4
- 230000000052 comparative effect Effects 0.000 description 4
- 238000004382 potting Methods 0.000 description 4
- 238000012360 testing method Methods 0.000 description 3
- 238000001816 cooling Methods 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 230000007257 malfunction Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 229920001971 elastomer Polymers 0.000 description 1
- 239000000806 elastomer Substances 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体装置及びその
製造方法に係り、特に半導体素子の回路形成面を樹脂に
より封止した構成の半導体装置及びその製造方法に関す
る。近年、半導体装置が搭載される電子機器の小型化に
伴い、半導体装置の小型化が図られている。このため、
半導体装置の大きさを半導体素子（チップ）の大きさに
極めて近付けたＣＳＰ(Chip Size Package) が開発さ
れ、また実用されるようになってきている。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a structure in which a circuit forming surface of a semiconductor element is sealed with a resin and a manufacturing method thereof. 2. Description of the Related Art In recent years, semiconductor devices have been downsized along with downsizing of electronic devices in which the semiconductor devices are mounted. For this reason,
A CSP (Chip Size Package), which makes the size of a semiconductor device extremely close to the size of a semiconductor element (chip), has been developed and put into practical use.
【０００２】このＣＳＰは、回路形成面を保護するため
に少なくとも回路形成面を封止樹脂により封止するよう
構成されており、また放熱特性を向上させる面から半導
体素子背面を露出させた構成とされている。また、上記
のようにＣＳＰはその大きさが略半導体素子と同じで小
型化を図ることができるが、半導体装置としての所定の
強度も維持させる必要がある。This CSP is constructed such that at least the circuit forming surface is sealed with a sealing resin in order to protect the circuit forming surface, and the back surface of the semiconductor element is exposed from the surface for improving heat dissipation characteristics. Has been done. Further, as described above, the size of the CSP is substantially the same as that of a semiconductor element and can be miniaturized, but it is necessary to maintain a predetermined strength as a semiconductor device.
【０００３】[0003]
【従来の技術】図１及び図２は、従来の半導体装置の一
例を示している。図１は、従来のＢＧＡ(Ball Grid Arr
ay) タイプの半導体装置１Ａを示している。この半導体
装置１Ａは、その全体形状が半導体素子２と略等しい形
状とされたＣＳＰである。1 and 2 show an example of a conventional semiconductor device. Figure 1 shows the conventional BGA (Ball Grid Arr).
The ay) type semiconductor device 1A is shown. The semiconductor device 1A is a CSP whose overall shape is substantially the same as that of the semiconductor element 2.
【０００４】この半導体装置１Ａは、大略すると半導体
素子２Ａ，基板５，はんだボール６，及び封止樹脂７Ａ
等により構成されている。半導体素子２Ａはベアチップ
であり、その回路形成面３にはバンプ４が配設されてい
る。この半導体素子２Ａは、バンプ４により基板５にフ
ェイスダウンで接合されている。また、放熱特性を向上
させる面より、半導体素子２Ａの背面２ａは、外部に露
出された構成とされている。The semiconductor device 1A is roughly composed of a semiconductor element 2A, a substrate 5, solder balls 6, and a sealing resin 7A.
Etc. The semiconductor element 2A is a bare chip, and bumps 4 are provided on the circuit formation surface 3 thereof. The semiconductor element 2A is joined face down to the substrate 5 by the bumps 4. Further, the back surface 2a of the semiconductor element 2A is configured to be exposed to the outside in order to improve heat dissipation characteristics.
【０００５】基板５は例えばＴＡＢ(Tape Automated Bo
nding)基板であり、その下部には外部接続端子となるは
んだボール６が配設されている。このはんだボール６と
バンプ４は、基板５に形成された配線及びスルーホール
を介して電気的に接続された構成とされている。また、
半導体素子２Ａの回路形成面３は保護を行なわないと、
酸化及び腐食が発生し易いため、半導体素子２Ａと基板
５との間には封止樹脂７Ａが配設されている。この封止
樹脂７Ａを配設することにより、半導体素子２Ａの回路
形成面３は保護され、半導体装置１Ａの信頼性を向上さ
せることができる。従来、この封止樹脂７Ａは、半導体
素子２Ａの回路形成面３のみを覆うよう配設されてい
た。The substrate 5 is, for example, TAB (Tape Automated Board).
soldering ball 6 serving as an external connection terminal is disposed below the substrate. The solder balls 6 and the bumps 4 are electrically connected to each other via the wiring and through holes formed on the substrate 5. Also,
If the circuit formation surface 3 of the semiconductor element 2A is not protected,
A sealing resin 7A is provided between the semiconductor element 2A and the substrate 5 because oxidation and corrosion easily occur. By disposing this sealing resin 7A, the circuit forming surface 3 of the semiconductor element 2A is protected and the reliability of the semiconductor device 1A can be improved. Conventionally, the sealing resin 7A has been disposed so as to cover only the circuit forming surface 3 of the semiconductor element 2A.
【０００６】一方、図２は、従来のリードフレームタイ
プの半導体装置１Ｂを示している。この半導体装置１Ｂ
も、その全体形状が半導体素子２Ｂと略等しい形状とさ
れたＣＳＰである。この半導体装置１Ｂは、大略すると
半導体素子２Ｂ，リード８，及び封止樹脂７Ｂ等により
構成されている。半導体素子２Ｂはベアチップであり、
その回路形成面３には電極パッド１２が形成されてい
る。また本従来例においても、放熱特性を向上させる面
より、半導体素子２Ｂの背面２ａは、外部に露出された
構成とされている。On the other hand, FIG. 2 shows a conventional lead frame type semiconductor device 1B. This semiconductor device 1B
Is a CSP whose overall shape is substantially the same as that of the semiconductor element 2B. The semiconductor device 1B is roughly composed of a semiconductor element 2B, leads 8, sealing resin 7B, and the like. The semiconductor element 2B is a bare chip,
Electrode pads 12 are formed on the circuit formation surface 3. Further, also in this conventional example, the back surface 2a of the semiconductor element 2B is configured to be exposed to the outside in order to improve the heat dissipation characteristics.
【０００７】リード８は、そのインナー側の端部を接着
剤９により半導体素子２Ｂに固定されている。また、リ
ード８のインナー側端部と回路形成面３に形成された電
極パッド１２との間には、ワイヤ１０が配設されてい
る。この半導体装置１Ｂにおいても、半導体素子２Ｂの
回路形成面３を保護する必要があり、よって半導体素子
２Ｂの回路形成面３には封止樹脂７Ｂが形成されてい
る。そして、リード８のアウター部分は封止樹脂７Ｂか
ら外部に延出し、外部接続端子として機能する構成とさ
れている。本従来例においても、封止樹脂７Ｂは、半導
体素子２Ｂの回路形成面３のみを覆うよう配設されてい
た。The inner end of the lead 8 is fixed to the semiconductor element 2B with an adhesive 9. A wire 10 is provided between the inner end of the lead 8 and the electrode pad 12 formed on the circuit forming surface 3. Also in this semiconductor device 1B, it is necessary to protect the circuit forming surface 3 of the semiconductor element 2B, and thus the sealing resin 7B is formed on the circuit forming surface 3 of the semiconductor element 2B. The outer portion of the lead 8 extends from the sealing resin 7B to the outside and functions as an external connection terminal. Also in this conventional example, the sealing resin 7B is disposed so as to cover only the circuit formation surface 3 of the semiconductor element 2B.
【０００８】[0008]
【発明が解決しようとする課題】ところで、図１に示す
ように、半導体装置１Ａを実装基板１３に実装した場
合、半導体素子２Ａと実装基板１３の熱膨張係数の違い
により、例えばリフロー時のように熱の印加時に応力が
発生する。この応力は、半導体素子２Ａと封止樹脂７Ａ
との界面に集中して発生する。By the way, as shown in FIG. 1, when the semiconductor device 1A is mounted on the mounting substrate 13, a difference in thermal expansion coefficient between the semiconductor element 2A and the mounting substrate 13 causes a difference in, for example, reflow. Stress is generated when heat is applied. This stress is due to the semiconductor element 2A and the sealing resin 7A.
Occurs concentrated on the interface with.
【０００９】図３は、半導体素子２Ａと封止樹脂７Ａと
の界面に応力集中が発生した時、半導体装置１Ａに発生
する現象を説明するための図である。前記のように、半
導体素子２Ａと実装基板１３の熱膨張係数の違いにより
発生する応力は、半導体素子２Ａと封止樹脂７Ａとの界
面、換言すれば回路形成面３と封止樹脂７Ａとの界面に
集中して発生する（図３（Ａ）に、回路形成面３と封止
樹脂７Ａとの界面を矢印Ａで示す位置）。FIG. 3 is a diagram for explaining a phenomenon that occurs in the semiconductor device 1A when stress concentration occurs at the interface between the semiconductor element 2A and the sealing resin 7A. As described above, the stress generated by the difference in the thermal expansion coefficient between the semiconductor element 2A and the mounting substrate 13 is the interface between the semiconductor element 2A and the sealing resin 7A, in other words, between the circuit forming surface 3 and the sealing resin 7A. These are concentrated on the interface (in FIG. 3 (A), the interface between the circuit forming surface 3 and the sealing resin 7A is indicated by an arrow A).
【００１０】よって、この回路形成面３（半導体素子２
Ａ）と封止樹脂７Ａとの界面Ａには、図３（Ｂ）に示す
ように、微小クラック１１Ａが発生し易くなる。また、
微小クラック１１Ａが発生すると、その後に熱応力が印
加されることによりクラックは徐々に進行し、やがて図
３（Ｃ）に示すような大きなクラック１１Ｂとなる。そ
して、最終的には半導体素子２Ａの回路形成面３はクラ
ック１１Ｂにより破壊され、半導体素子２Ａが機能しな
い状態となるおそれがある。Therefore, the circuit forming surface 3 (semiconductor element 2
At the interface A between A) and the sealing resin 7A, as shown in FIG. 3B, microcracks 11A are likely to occur. Also,
When the minute cracks 11A are generated, the thermal stress is applied thereafter, and the cracks gradually progress to become large cracks 11B as shown in FIG. 3C. Finally, the circuit forming surface 3 of the semiconductor element 2A may be broken by the crack 11B, and the semiconductor element 2A may be in a non-functioning state.
【００１１】一方、半導体装置１Ａ，１Ｂの耐湿性に注
目すると、図１及び図２に示されるように、回路形成面
３（半導体素子２Ａ）と封止樹脂７Ａとの界面は外気に
晒されているため、耐湿性に対して十分な効果が得られ
ない。よって、この界面から水分が半導体装置１Ａ，１
Ｂ内に侵入し、熱印加時においてはこの水分が蒸発して
体積が増大することによりクラックが発生してしまう。
また、水分が回路形成面３に付着した場合には、回路形
成面３が腐食してしまうおそれもある。On the other hand, focusing attention on the moisture resistance of the semiconductor devices 1A and 1B, as shown in FIGS. 1 and 2, the interface between the circuit forming surface 3 (semiconductor element 2A) and the sealing resin 7A is exposed to the outside air. Therefore, sufficient effect cannot be obtained for the moisture resistance. Therefore, moisture is absorbed from this interface in the semiconductor devices 1A and 1A.
When it enters B and heat is applied, the moisture evaporates and the volume increases, so that cracks occur.
Further, if water adheres to the circuit forming surface 3, the circuit forming surface 3 may be corroded.
【００１２】更に、半導体装置１Ａ，１Ｂは半導体素子
２Ａ，２Ｂの背面２ａが露出した構成であるため、搬送
等により半導体素子２Ａ，２Ｂにいわゆるエッジ欠けが
発生しやすい。このエッジ欠けが発生すると、これに起
因して半導体素子２Ａ，２Ｂにチップクラックが発生
し、半導体素子２Ａ，２Ｂの動作不良の原因となるとい
う問題点も生じる。Further, since the semiconductor devices 1A and 1B have a structure in which the back surfaces 2a of the semiconductor elements 2A and 2B are exposed, so-called edge defects are likely to occur in the semiconductor elements 2A and 2B due to transportation or the like. When this edge chipping occurs, a chip crack occurs in the semiconductor elements 2A and 2B due to this, which causes a problem that the semiconductor elements 2A and 2B malfunction.
【００１３】本発明は上記の点に鑑みてなされたもので
あり、クラックの発生を抑制することにより信頼性の向
上を図った半導体装置及びその製造方法を提供すること
を目的とする。The present invention has been made in view of the above points, and it is an object of the present invention to provide a semiconductor device and a method of manufacturing the same for which reliability is improved by suppressing the occurrence of cracks.
【００１４】[0014]
【課題を解決するための手段】上記課題を解決するため
に本発明では、次に述べる各手段を講じたことを特徴と
するものである。請求項１記載の発明は、半導体素子
と、該半導体素子を搭載する基板と、前記半導体素子が
前記基板に搭載された状態において、前記半導体素子に
形成された回路形成面を封止する封止樹脂と、を具備す
る半導体装置において、前記半導体素子の前記回路形成
面と反対側に位置する背面の辺エッジに面取り部を形成
し、かつ、前記封止樹脂に形成された前記半導体素子の
外周側面を覆う側面被覆部の前記回路形成面からの高さ
をｔとし、前記半導体素子の高さ寸法をＴとした場合、
前記側面被覆部の回路形成面からの高さｔがＴ／４≦ｔ
≦Ｔとなるよう構成したことを特徴とするものである。In order to solve the above-mentioned problems, the present invention is characterized by the following means. According to a first aspect of the present invention, a semiconductor element, a substrate on which the semiconductor element is mounted, and a sealing for sealing a circuit formation surface formed on the semiconductor element in a state where the semiconductor element is mounted on the substrate. In a semiconductor device including a resin, a chamfered portion is formed on a side edge of a back surface of the semiconductor element opposite to the circuit formation surface , and the semiconductor element of the semiconductor element formed on the sealing resin is formed.
Height of the side surface covering portion covering the outer peripheral side surface from the circuit forming surface
And t is the height dimension of the semiconductor element,
The height t of the side surface covering portion from the circuit forming surface is T / 4 ≦ t.
It is characterized in that it is configured such that ≦ T.
【００１５】また、請求項２記載の発明は、請求項１記
載の半導体装置において、更に、前記半導体素子の前記
回路形成面の辺エッジに面取り部を形成したことを特徴
とするものである。According to a second aspect of the present invention, there is provided the semiconductor device according to the first aspect, further comprising:
It is characterized in that a chamfered portion is formed at a side edge of the circuit formation surface .
【００１６】また、請求項３記載の発明は、半導体素子
と、該半導体素子を搭載する基板と、前記半導体素子が
前記基板に搭載された状態において、前記半導体素子に
形成された回路形成面を封止する封止樹脂と、を具備す
る半導体装置において、前記半導体素子の前記回路形成
面と反対側に位置する背面のコーナーエッジに面取り部
を形成し、かつ、前記封止樹脂に形成された前記半導体
素子の外周側面を覆う側面被覆部の前記回路形成面から
の高さをｔとし、前記半導体素子の高さ寸法をＴとした
場合、前記側面被覆部の回路形成面からの高さｔがＴ／
４≦ｔ≦Ｔとなるよう構成したことを特徴とするもので
ある。According to a third aspect of the present invention, a semiconductor element, a substrate on which the semiconductor element is mounted, and a circuit forming surface formed on the semiconductor element in a state where the semiconductor element is mounted on the substrate are provided. In a semiconductor device comprising a sealing resin for sealing, the circuit formation of the semiconductor element
Chamfer on the back corner edge located opposite the face
And the semiconductor formed on the sealing resin.
From the circuit forming surface of the side surface covering portion that covers the outer peripheral side surface of the element
Is defined as t, and the height dimension of the semiconductor element is defined as T.
In this case, the height t of the side surface covering portion from the circuit forming surface is T /
It is characterized in that it is configured such that 4 ≦ t ≦ T.
【００１７】また、請求項４記載の発明は、請求項３記
載の半導体装置において、更に、前記半導体素子の前記
回路形成面のコーナーエッジに面取り部を形成したこと
を特徴とするものである。 The invention according to claim 4 is the semiconductor device according to claim 3, further comprising:
A chamfer is formed on the corner edge of the circuit formation surface.
It is characterized by.
【００１８】[0018]
【００１９】[0019]
【００２０】[0020]
【００２１】[0021]
【００２２】[0022]
【００２３】[0023]
【００２４】[0024]
【００２５】[0025]
【００２６】[0026]
【００２７】[0027]
【００２８】[0028]
【００２９】[0029]
【００３０】[0030]
【００３１】[0031]
【００３２】[0032]
【００３３】[0033]
【発明の実施の形態】次に、本発明の実施の形態につい
て図面と共に説明する。先ず、図４を用いて本発明の第
１実施例である半導体装置２０Ａについて説明する。こ
の半導体装置２０Ａは、その全体形状が半導体素子２２
と略等しい形状とされたＣＳＰであり、よって小型化が
図られている。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings. First, the semiconductor device 20A will be described a first embodiment of the present invention with reference to FIG. This semiconductor device 20A has a semiconductor element 22 having an overall shape.
The CSP has substantially the same shape as that of FIG.
【００３４】半導体装置２０Ａは、大略すると半導体素
子２２Ａ，基板２５，はんだボール２６，及び封止樹脂
２７Ａ等により構成されている。半導体素子２２Ａはベ
アチップであり、その回路形成面２３にはバンプ２４が
配設されている。また、本実施例で用いる半導体素子２
２Ａは、特に面取り加工等は行なわれておらず、よって
矩形状の外形を有したものである。この半導体素子２２
Ａは、バンプ２４により基板２５にフェイスダウンで接
合されている。また、放熱特性を向上させる面より、半
導体素子２２Ａの背面２２ａは外部に露出された構成と
されている。The semiconductor device 20A is generally composed of a semiconductor element 22A, a substrate 25, solder balls 26, a sealing resin 27A and the like. The semiconductor element 22A is a bare chip, and bumps 24 are provided on the circuit forming surface 23 thereof. In addition, the semiconductor element 2 used in this embodiment
2A is not particularly chamfered and therefore has a rectangular outer shape. This semiconductor element 22
A is joined face down to the substrate 25 by bumps 24. Further, the rear surface 22a of the semiconductor element 22A is exposed to the outside in order to improve the heat dissipation characteristics.
【００３５】基板２５は例えばＴＡＢ基板であり、その
下部には外部接続端子となるはんだボール２６が配設さ
れている。このはんだボール２６とバンプ２４は、基板
２５に形成された配線及びスルーホール（図示せず）を
介して電気的に接続された構成とされている。尚、基板
２５はＴＡＢ基板に限定されるものではなく、ガラス−
エポキシ基板等の樹脂基板を用いることも、またセラミ
ック基板を用いることも可能である。また、外部接続端
子ははんだボール２６に限定されるものではなく、銅ボ
ール等の他の金属ボールを用いることも、また鉛レスは
んだを用いたボールを用いることも可能である。The substrate 25 is, for example, a TAB substrate, and solder balls 26, which serve as external connection terminals, are disposed below the TAB substrate. The solder balls 26 and the bumps 24 are electrically connected to each other through wirings and through holes (not shown) formed on the substrate 25. The substrate 25 is not limited to the TAB substrate, but a glass substrate.
It is also possible to use a resin substrate such as an epoxy substrate or a ceramic substrate. Further, the external connection terminals are not limited to the solder balls 26, and other metal balls such as copper balls, or balls using leadless solder can be used.
【００３６】一方、上記したように半導体素子２２Ａの
能動領域となる回路形成面２３は、保護を行なわないと
酸化及び腐食が発生し易い。このため、半導体素子２２
Ａ（具体的には、回路形成面２３）と基板２５との間に
は封止樹脂２７Ａが配設されている。この封止樹脂２７
Ａは後述するように、ポッティングにより形成されるも
のであり、またその材質としては例えばエポキシ系樹
脂、或いはシリコン系樹脂を用いることが考えられる。On the other hand, as described above, the circuit forming surface 23, which is the active region of the semiconductor element 22A, is easily oxidized and corroded unless it is protected. Therefore, the semiconductor element 22
A sealing resin 27A is provided between A (specifically, the circuit forming surface 23) and the substrate 25. This sealing resin 27
As will be described later, A is formed by potting, and as its material, for example, an epoxy resin or a silicon resin can be used.
【００３７】本実施例では、封止樹脂２７Ａを回路形成
面２３を封止する回路面封止部２８Ａと、半導体素子２
２Ａの外周側面２２ｂを覆う側面被覆部２９Ａとを一体
的に設けた構成としたことを特徴とするものである。ま
た、側面被覆部２９Ａの回路形成面２３からの高さをｔ
とし、半導体素子２２Ａの高さ寸法をＴ（図４に、この
各高さｔ，Ｔを矢印で示す）とした場合、側面被覆部２
９Ａの回路形成面２３からの高さｔがＴ／４≦ｔ≦Ｔと
なるよう構成している。In this embodiment, the circuit surface sealing portion 28A for sealing the circuit forming surface 23 with the sealing resin 27A and the semiconductor element 2 are used.
It is characterized in that a side surface covering portion 29A for covering the outer peripheral side surface 22b of 2A is integrally provided. Further, the height of the side surface covering portion 29A from the circuit forming surface 23 is t
When the height dimension of the semiconductor element 22A is T (each height t, T is indicated by an arrow in FIG. 4), the side surface covering portion 2
The height t of the 9A from the circuit forming surface 23 is T / 4 ≦ t ≦ T.
【００３８】また、図５は本発明の第２実施例である半
導体装置２０Ｂを示している。尚、図５において、図４
に示した第１実施例に係る半導体装置２０Ａと同一構成
については同一符号を付してその説明を省略する。ま
た、以下説明する各実施例においても同様とする。半導
体装置２０Ｂにおいても、封止樹脂２７Ｂは回路形成面
２３を封止する回路面封止部２８Ｂと、半導体素子２２
Ａの外周側面２２ｂを覆う側面被覆部２９Ｂとにより構
成されているが、本実施例では側面被覆部２９Ｂの高さ
が半導体素子２２Ａの背面２２ａと同一高さとなるよう
構成したことを特徴とするものである（ｔ＝Ｔ）。FIG. 5 shows a semiconductor device 20B according to the second embodiment of the present invention. In addition, in FIG.
The same components as those of the semiconductor device 20A according to the first embodiment shown in FIG. The same applies to each embodiment described below. Also in the semiconductor device 20B, the sealing resin 27B and the circuit surface sealing portion 28B that seals the circuit forming surface 23 and the semiconductor element 22.
The outer peripheral side surface 22b of A is formed of a side surface covering portion 29B, but in this embodiment, the height of the side surface covering portion 29B is the same as that of the back surface 22a of the semiconductor element 22A. (T = T).
【００３９】上記した第１及び第２実施例に係る半導体
装置２０Ａ，２０Ｂの構成によれば、半導体素子２２Ａ
の側面２２ｂの所定範囲が側面被覆部２９Ａ，２９Ｂに
より覆われた構成となるため、封止樹脂２７Ａ，２７Ｂ
と半導体素子２２Ａとの密着性を向上させることができ
る。よって、耐リフロー性及び耐湿性が向上し、これに
より半導体装置２０Ａ，２０Ｂの信頼性を向上すること
ができる。According to the configurations of the semiconductor devices 20A and 20B according to the first and second embodiments described above, the semiconductor element 22A
Since a predetermined range of the side surface 22b of the sealing resin 27A, 27B is covered with the side surface covering portions 29A, 29B.
The adhesiveness between the semiconductor element 22A and the semiconductor element 22A can be improved. Therefore, the reflow resistance and the moisture resistance are improved, which can improve the reliability of the semiconductor devices 20A and 20B.
【００４０】また、封止樹脂２７Ａ，２７Ｂが半導体素
子２２Ａの側面２２ｂまで配設されていることから、温
度サイクル時において回路形成面２３が破損することを
防止することができる。ここでいう温度サイクルとは信
頼性試験の一つであり、半導体装置２０Ａ，２０Ｂに対
し、例えば−６５℃と１５０℃との間で加熱・冷却を交
番的に印加する試験をいう。Further, since the sealing resins 27A and 27B are provided up to the side surface 22b of the semiconductor element 22A, it is possible to prevent the circuit forming surface 23 from being damaged during the temperature cycle. The temperature cycle mentioned here is one of reliability tests, and is a test in which heating / cooling is alternately applied to the semiconductor devices 20A and 20B, for example, between -65 ° C and 150 ° C.
【００４１】ここで、上記のように封止樹脂２７Ａ，２
７Ｂを半導体素子２２Ａの側面２２ｂに配設することに
より、回路形成面２３の破損が抑制できる理由について
説明する。先に図３を用いて説明したように、応力集中
は半導体素子２２Ａと実装基板（図４及び図５には図示
せず）との熱膨張係数の違いにより発生し、その発生位
置は半導体素子２２Ａと封止樹脂２７Ａ，２７Ｂとの界
面、換言すれば回路形成面２３と封止樹脂２７Ａ，２７
Ｂとの界面に集中する。図４及び図５に、この応力集中
が発生する位置を矢印Ｂ１，Ｂ２で示している。Here, as described above, the sealing resin 27A, 2
The reason why the circuit forming surface 23 can be prevented from being damaged by disposing 7B on the side surface 22b of the semiconductor element 22A will be described. As described above with reference to FIG. 3, the stress concentration occurs due to the difference in the thermal expansion coefficient between the semiconductor element 22A and the mounting substrate (not shown in FIGS. 4 and 5), and the occurrence position is the semiconductor element. 22A and the interface between the sealing resins 27A and 27B, in other words, the circuit forming surface 23 and the sealing resins 27A and 27B.
Focus on the interface with B. 4 and 5, the positions where the stress concentration occurs are indicated by arrows B1 and B2.
【００４２】従って、第１及び第２実施例に係る半導体
装置２０Ａ，２０Ｂにおいても、温度サイクルを実施し
た場合、半導体素子２２Ａと実装基板の熱膨張係数の違
いにより、位置Ｂ１，Ｂ２に応力が集中する。半導体装
置２０Ａにおいては、この応力集中が発生する位置Ｂ１
は、回路形成面２３からＴ／４（Ｔは半導体素子２２Ａ
の厚さ）以上離間した位置である。また、半導体装置２
０Ｂにおいては、この応力集中が発生する位置Ｂ２は、
回路形成面２３から半導体素子２２Ａの厚さＴだけ離間
した位置である。Therefore, also in the semiconductor devices 20A and 20B according to the first and second embodiments, when the temperature cycle is performed, stress is applied to the positions B1 and B2 due to the difference in the thermal expansion coefficient between the semiconductor element 22A and the mounting substrate. concentrate. In the semiconductor device 20A, the position B1 where this stress concentration occurs
From the circuit forming surface 23 to T / 4 (T is the semiconductor element 22A
Thickness)) or more. In addition, the semiconductor device 2
At 0B, the position B2 where this stress concentration occurs is
It is a position separated from the circuit forming surface 23 by the thickness T of the semiconductor element 22A.
【００４３】よって、第１及び第２実施例に係る半導体
装置２０Ａ，２０Ｂでは、応力集中が発生する位置が回
路形成面２３から離間しているため、仮に位置Ｂ１，Ｂ
２にクラックが発生しても、これが回路形成面２３に至
ることはなく、よって温度サイクルを実施しても回路形
成面２３が破損することを防止でき、半導体装置２０
Ａ，２０Ｂの信頼性を向上させることができる。Therefore, in the semiconductor devices 20A and 20B according to the first and second embodiments, the positions where the stress concentration occurs are separated from the circuit forming surface 23, and therefore the positions B1 and B are provisionally set.
Even if a crack is generated in 2, the circuit does not reach the circuit forming surface 23. Therefore, it is possible to prevent the circuit forming surface 23 from being damaged even if a temperature cycle is performed.
The reliability of A and 20B can be improved.
【００４４】また、側面被覆部２９Ａ，２９Ｂが半導体
素子２２Ａの側面２２ｂを覆うことにより、半導体素子
２２Ａはその外部の大なる面積を封止樹脂２７Ａ，２７
Ｂに保持された構成となる。よって、半導体素子２２Ａ
が熱変形しようとしても、封止樹脂２７Ａ，２７Ｂはこ
の変形を阻止する機能を奏し、これにより応力集中を緩
和することができる。従って、位置Ｂ１，Ｂ２において
クラックが発生することを防止でき、これによっても半
導体装置２０Ａ，２０Ｂの信頼性を向上させることがで
きる。Further, since the side surface covering portions 29A and 29B cover the side surface 22b of the semiconductor element 22A, the semiconductor element 22A has a large area outside the sealing resin 27A and 27A.
The configuration is held in B. Therefore, the semiconductor element 22A
However, even if it is about to be thermally deformed, the sealing resins 27A and 27B have a function of preventing this deformation, whereby stress concentration can be relieved. Therefore, it is possible to prevent the occurrence of cracks at the positions B1 and B2, which also improves the reliability of the semiconductor devices 20A and 20B.
【００４５】図６は、本発明者が実施した温度サイクル
の実験結果を示している。同図において、横軸はサイク
ル数（−６５℃と１５０℃との間で加熱・冷却を１回繰
り返すことを１サイクルとする）を示しており、縦軸は
これにより発生した不良品の発生率（総合不良発生率）
を示している。また、比較例としては、先に図１に示し
た半導体装置１Ａを用い、また実施例としては図４に示
した半導体装置２０Ａを用いた。FIG. 6 shows the experimental results of the temperature cycle conducted by the present inventor. In the figure, the horizontal axis represents the number of cycles (one cycle of repeating heating and cooling once between −65 ° C. and 150 ° C. is one cycle), and the vertical axis represents the occurrence of defective products. Rate (total failure rate)
Is shown. Further, as a comparative example, the semiconductor device 1A previously shown in FIG. 1 was used, and as an example, the semiconductor device 20A shown in FIG. 4 was used.
【００４６】同図に示す実験結果を考察すると、比較例
では１００サイクルで約１０パーセントの不良品が発生
し、４００サイクル以上では約４０パーセントの不良品
が発生している。これに対し、側面被覆部２９Ａにより
半導体素子２２Ａの側面２２ｂを覆った半導体装置２０
Ａでは、全てのサイクル数領域において全く不良品は発
生しなかった。この実験結果からも、本実施例の構成に
よれば、半導体装置２０Ａ，２０Ｂの信頼性を向上させ
ることができることが判る。Considering the experimental results shown in the figure, in the comparative example, about 10% of defective products were generated in 100 cycles, and about 400% of defective products were generated in 400 cycles or more. On the other hand, the semiconductor device 20 in which the side surface covering portion 29A covers the side surface 22b of the semiconductor element 22A is used.
In A, no defective product was generated at all in the cycle number region. From this experimental result, it can be seen that the configuration of the present embodiment can improve the reliability of the semiconductor devices 20A and 20B.
【００４７】続いて、図７を用いて本発明の第３実施例
である半導体装置２０Ｃについて説明する。本実施例に
係る半導体装置２０Ｃは、半導体素子２２Ｂの回路形成
面２３と反対側に位置する背面２２ａの辺エッジに背面
側面取り部３０を形成したことを特徴とするものであ
る。この背面側面取り部３０は、背面２２ａの４つの辺
エッジ全てに形成されている。Next, a semiconductor device 20C which is a third embodiment of the present invention will be described with reference to FIG. The semiconductor device 20C according to the present embodiment is characterized in that the back side chamfered portion 30 is formed on the side edge of the back surface 22a located on the side opposite to the circuit forming surface 23 of the semiconductor element 22B. The back side chamfered portion 30 is formed on all four side edges of the back surface 22a.
【００４８】この背面側面取り部３０を形成するには、
例えば半導体素子２２Ｂをウェーハからダイシングによ
り切断し個片化する際、異なる歯圧或いは異なる歯角を
有する２枚のダイシングブレードを用いてダイシングす
ることにより、容易に形成することができる。本実施例
のように、半導体素子２２Ｂの背面２２ａの辺エッジに
背面側面取り部３０を形成することにより、例えば搬送
時等において半導体素子２２Ｂにエッジ欠けが発生する
ことを防止することができる。エッジ欠けが存在する
と、上記した熱サイクルを実施した場合にエッジ欠け部
分からクラックが発生するおそれがあり、このクラック
が回路形成面２３に達すると半導体装置２０Ｃが機能し
なくなってしまう。To form the back side chamfer 30,
For example, when the semiconductor element 22B is cut from a wafer by dicing and divided into individual pieces, it can be easily formed by dicing using two dicing blades having different tooth pressures or different tooth angles. By forming the back surface chamfered portion 30 at the side edge of the back surface 22a of the semiconductor element 22B as in the present embodiment, it is possible to prevent the occurrence of edge chipping in the semiconductor element 22B during transportation, for example. If there is an edge defect, a crack may occur from the edge defect portion when the above-mentioned thermal cycle is performed, and if the crack reaches the circuit formation surface 23, the semiconductor device 20C will not function.
【００４９】しかるに、背面側面取り部３０を形成する
ことにより、このクラックの発生を防止することがで
き、半導体装置２０Ｃの信頼性の向上を図ることができ
る。続いて、図８を用いて本発明の第４実施例である半
導体装置２０Ｄについて説明する。前記した第３実施例
に係る半導体装置２０Ｃでは、半導体素子２２Ｂの背面
２２ａの辺エッジに背面側面取り部３０を形成した構成
としたが、本実施例に係る半導体装置２０Ｄは、背面側
面取り部３０に加えて半導体素子２２Ｃの回路形成面２
３の辺エッジに回路面側面取り部３１を形成したことを
特徴とするものである。この回路面側面取り部３１も、
背面側面取り部３０と同様の形成方法により形成するこ
とができる。However, by forming the back side chamfered portion 30, the occurrence of this crack can be prevented, and the reliability of the semiconductor device 20C can be improved. Subsequently, a semiconductor device 20D according to a fourth embodiment of the present invention will be described with reference to FIG. In the semiconductor device 20C according to the third embodiment described above, the back side chamfered portion 30 is formed at the side edge of the back surface 22a of the semiconductor element 22B, but the semiconductor device 20D according to the present embodiment has a back side chamfered portion. In addition to 30, the circuit forming surface 2 of the semiconductor element 22C
The circuit chamfered portion 31 is formed at the side edge of No. 3. This circuit chamfer 31 is also
It can be formed by the same forming method as the back side chamfered portion 30.
【００５０】本実施例のように、背面側面取り部３０に
加え半導体素子２２Ｃの回路形成面２３の辺エッジに回
路面側面取り部３１を形成したことにより、半導体素子
２２Ｃと封止樹脂２７の接触面積を広くすることができ
る。よって、半導体素子２２Ｃと封止樹脂２７との密着
性及び耐湿性を更に向上することができ、半導体装置２
０Ｄの信頼性を向上させることができる。また、回路面
側面取り部３１は封止樹脂２７により確実に保護される
こととなり、エッジ欠けの発生及びこれに起因したクラ
ックの発生を防止することができ、これによっても半導
体装置２０Ｄの信頼性を向上させることができる。As in this embodiment, the circuit chamfer 31 is formed at the side edge of the circuit forming surface 23 of the semiconductor element 22C in addition to the back chamfer 30, so that the semiconductor element 22C and the sealing resin 27 are separated. The contact area can be increased. Therefore, the adhesiveness and moisture resistance between the semiconductor element 22C and the sealing resin 27 can be further improved, and the semiconductor device 2
The reliability of 0D can be improved. In addition, the circuit surface chamfered portion 31 is reliably protected by the sealing resin 27, and it is possible to prevent the occurrence of edge chipping and the generation of cracks due to this, which also improves the reliability of the semiconductor device 20D. Can be improved.
【００５１】続いて、図９を用いて本発明の第５実施例
である半導体装置２０Ｅについて説明する。本実施例に
係る半導体装置２０Ｅは、半導体素子２２Ｄの回路形成
面２３と反対側に位置する背面２２ａのコーナーエッジ
に背面側角面取り部３２を形成したことを特徴とするも
のである。この背面側面取り部３０は、背面２２ａの４
つのコーナーエッジ全てに形成されている。Next, a semiconductor device 20E which is a fifth embodiment of the present invention will be described with reference to FIG. The semiconductor device 20E according to the present embodiment is characterized in that the back side chamfered portion 32 is formed at the corner edge of the back surface 22a located on the side opposite to the circuit forming surface 23 of the semiconductor element 22D. The rear side chamfered portion 30 is formed on the rear side 22a by
Formed on all four corner edges.
【００５２】この背面側角面取り部３２も、前記した第
３及び第４実施例で説明したと同様に、半導体素子２２
Ｄをウェーハからダイシングにより切断し個片化する
際、異なる歯圧或いは異なる歯角を有する２枚のダイシ
ングブレードを用いてダイシングすることにより形成す
ることができる。本実施例のように、半導体素子２２Ｄ
の背面２２ａのコーナーエッジに背面側角面取り部３２
を形成することによっても、第３及び第４実施例と同様
に、搬送時等において半導体素子２２Ｄにエッジ欠けが
発生することを防止することができる。よって、エッジ
欠けに起因して発生するクラックを抑制することがで
き、半導体装置２０Ｅの信頼性を向上させることができ
る。This rear side chamfer 32 also has the semiconductor element 22 in the same manner as described in the third and fourth embodiments.
When D is cut from the wafer by dicing and individualized, it can be formed by dicing using two dicing blades having different tooth pressures or different tooth angles. As in this embodiment, the semiconductor element 22D
The back side chamfer 32 on the corner edge of the back 22a
Also by forming the above, similarly to the third and fourth embodiments, it is possible to prevent the occurrence of edge chipping in the semiconductor element 22D during transportation or the like. Therefore, it is possible to suppress cracks generated due to the edge chipping and improve the reliability of the semiconductor device 20E.
【００５３】続いて、図１０を用いて本発明の第６実施
例である半導体装置２０Ｆについて説明する。本実施例
に係る半導体装置２０Ｆは、背面側角面取り部３２に加
えて半導体素子２２Ｅの回路形成面２３のコーナーエッ
ジに回路面側角面取り部３３を形成したことを特徴とす
るものである。この回路面側角面取り部３３も、背面側
角面取り部３２と同様の形成方法により形成することが
できる。A semiconductor device 20F according to a sixth embodiment of the present invention will be described next with reference to FIG. The semiconductor device 20F according to the present embodiment is characterized in that, in addition to the back surface side chamfered portion 32, the circuit surface side chamfered portion 33 is formed at the corner edge of the circuit forming surface 23 of the semiconductor element 22E. The circuit surface side chamfered portion 33 can also be formed by the same forming method as the back surface side chamfered portion 32.
【００５４】本実施例のように、背面側角面取り部３２
に加え半導体素子２２Ｅの回路形成面２３のコーナーエ
ッジに回路面側角面取り部３３を形成したことにより、
半導体素子２２Ｅと封止樹脂２７の接触面積を広くする
ことができる。よって、前記した第４実施例と同様に、
半導体素子２２Ｃと封止樹脂２７との密着性及び耐湿性
を更に向上することができ、半導体装置２０Ｆの信頼性
を向上させることができる。また、回路面側角面取り部
３３は封止樹脂２７により確実に保護されることとな
り、エッジ欠けの発生及びこれに起因したクラックの発
生を防止することができ、これによっても半導体装置２
０Ｆの信頼性を向上させることができる。As in this embodiment, the back side chamfer 32
In addition to forming the circuit surface side chamfered portion 33 at the corner edge of the circuit forming surface 23 of the semiconductor element 22E,
The contact area between the semiconductor element 22E and the sealing resin 27 can be increased. Therefore, similar to the fourth embodiment described above,
The adhesiveness and moisture resistance between the semiconductor element 22C and the sealing resin 27 can be further improved, and the reliability of the semiconductor device 20F can be improved. Further, the circuit surface side chamfered portion 33 is surely protected by the sealing resin 27, and it is possible to prevent the occurrence of edge chipping and the generation of cracks due to this, and this also enables the semiconductor device 2 to be protected.
The reliability of 0F can be improved.
【００５５】続いて、図１１を用いて本発明の第７実施
例である半導体装置２０Ｇについて説明する。本実施例
に係る半導体装置２０Ｇは、先に図４を用いて説明した
第１実施例に係る半導体装置２０Ａと、図７を用いて説
明した第３実施例に係る半導体装置２０Ｃを複合させた
構成を有している。A semiconductor device 20G according to the seventh embodiment of the present invention will be described next with reference to FIG. The semiconductor device 20G according to the present embodiment is a combination of the semiconductor device 20A according to the first embodiment described above with reference to FIG. 4 and the semiconductor device 20C according to the third embodiment described with reference to FIG. Have a configuration.
【００５６】具体的には、封止樹脂２７Ａに半導体素子
２２Ｂの外周側面２２ｂを覆う側面被覆部２９Ａとを一
体的に設けると共に、半導体素子２２Ｂの背面２２ａに
背面側面取り部３０を形成した構成とされている。ま
た、本実施例では、側面被覆部２９Ａが背面２２ａの近
傍まで配設され、よって背面側面取り部３０の一部を被
覆した構成とされている。Specifically, the sealing resin 27A is integrally provided with the side surface covering portion 29A for covering the outer peripheral side surface 22b of the semiconductor element 22B, and the rear side chamfered portion 30 is formed on the rear surface 22a of the semiconductor element 22B. It is said that. Further, in the present embodiment, the side surface covering portion 29A is arranged up to the vicinity of the back surface 22a, and thus a part of the back surface side chamfered portion 30 is covered.
【００５７】本実施例の半導体装置２０Ｇによれば、第
１実施例及び第３実施例で実現できる効果を共有するこ
とが可能となり、よって耐リフロー性，耐湿性，及び温
度サイクル性の向上を図ることができると共に、エッジ
欠けの発生を防止することができ、半導体装置２０Ｇの
信頼性をより高めることができる。また、上記のように
側面被覆部２９Ａ（封止樹脂２７Ａ）は背面側面取り部
３０の一部を被覆するため、背面側面取り部３０は側面
被覆部２９Ａにより保護された（封止された）構成とな
る。よって、背面側面取り部３０が奏するチップ欠け防
止効果に加え、封止樹脂２７Ａによる封止効果を実現で
き、半導体装置２０Ｇの信頼性を更に向上させることが
できる。According to the semiconductor device 20G of the present embodiment, it is possible to share the effects that can be realized in the first and third embodiments, thus improving the reflow resistance, moisture resistance and temperature cycle property. It is possible to prevent the occurrence of edge chipping, and further improve the reliability of the semiconductor device 20G. Further, as described above, the side surface covering portion 29A (sealing resin 27A) covers a part of the back surface side chamfered portion 30, so the back surface side chamfered portion 30 is protected (sealed) by the side surface covering portion 29A. It will be composed. Therefore, in addition to the chip chipping prevention effect of the back side chamfered portion 30, the sealing effect of the sealing resin 27A can be realized, and the reliability of the semiconductor device 20G can be further improved.
【００５８】更に、背面側面取り部３０が存在すること
により、素子側面２２ｂが垂直面である場合（図４及び
図５参照）に比べ、封止樹脂２７Ａは半導体素子２２Ｂ
の側面２２ｂに配設しやすくなる。即ち、背面側面取り
部３０は傾斜面であるため、垂直面に比べて側面被覆部
２９Ａは背面側面取り部３０に乗りやすくなる。よっ
て、封止樹脂２７Ａの形成時において、素子側面２２ｂ
からずり落ちる樹脂量を低減でき、側面被覆部２９Ａを
形成するのに必要となる樹脂量を少なくすることができ
る。Further, the presence of the back side chamfered portion 30 causes the sealing resin 27A to cover the semiconductor element 22B as compared with the case where the element side surface 22b is a vertical surface (see FIGS. 4 and 5).
It becomes easy to dispose on the side surface 22b. That is, since the back side chamfered portion 30 is an inclined surface, the side surface covering portion 29A is easier to ride on the back side chamfered portion 30 compared to the vertical surface. Therefore, when the sealing resin 27A is formed, the element side surface 22b is formed.
The amount of resin that slips off can be reduced, and the amount of resin required to form the side surface coating portion 29A can be reduced.
【００５９】続いて、図１２を用いて本発明の第８実施
例である半導体装置２０Ｈについて説明する。本実施例
に係る半導体装置２０Ｈは、先に図４を用いて説明した
第１実施例に係る半導体装置２０Ａと、図８を用いて説
明した第４実施例に係る半導体装置２０Ｄを複合させた
構成を有している。Next, a semiconductor device 20H according to the eighth embodiment of the present invention will be described with reference to FIG. The semiconductor device 20H according to the present embodiment is a combination of the semiconductor device 20A according to the first embodiment described above with reference to FIG. 4 and the semiconductor device 20D according to the fourth embodiment described with reference to FIG. Have a configuration.
【００６０】具体的には、封止樹脂２７Ａに半導体素子
２２Ｃの外周側面２２ｂを覆う側面被覆部２９Ａとを一
体的に設け、半導体素子２２Ｃの背面２２ａに背面側面
取り部３０を形成し、更に半導体素子２２Ｃの回路形成
面２３に回路面側面取り部３１を形成した構成とされて
いる。また、本実施例においても、側面被覆部２９Ａは
背面２２ａの近傍まで配設され、よって背面側面取り部
３０の一部を被覆した構成とされている。Specifically, the sealing resin 27A is integrally provided with the side surface covering portion 29A for covering the outer peripheral side surface 22b of the semiconductor element 22C, and the rear side chamfered portion 30 is formed on the back surface 22a of the semiconductor element 22C. A circuit surface chamfered portion 31 is formed on the circuit formation surface 23 of the semiconductor element 22C. Also in the present embodiment, the side surface covering portion 29A is arranged up to the vicinity of the back surface 22a, so that a part of the back surface side chamfered portion 30 is covered.
【００６１】本実施例の半導体装置２０Ｈによれば、第
１実施例及び第４実施例で実現できる効果を共有するこ
とが可能となり、よって耐リフロー性，耐湿性，及び温
度サイクル性の向上と、エッジ欠けの発生及びこれに起
因したクラックの発生をより確実に防止することができ
る。尚、先に図９及び図１０を用いて説明した第５実施
例及び第６実施例に係る半導体装置２０Ｅ，２０Ｆにお
いて、封止樹脂２７Ａに側面被覆部２９Ａを設け、この
側面被覆部２９Ａがに半導体素子２２Ｃの外周側面２２
ｂを覆うよう構成してもよい。この構成とした場合に
も、図１１及び図１２で説明した第７実施例及び第８実
施例に係る半導体装置２０Ｇ，２０Ｈで得られると同様
の効果を実現することができる。According to the semiconductor device 20H of the present embodiment, it is possible to share the effects that can be realized in the first and fourth embodiments, thus improving the reflow resistance, moisture resistance and temperature cycle resistance. It is possible to more reliably prevent the occurrence of edge chipping and the resulting cracks. In the semiconductor devices 20E and 20F according to the fifth and sixth embodiments described above with reference to FIGS. 9 and 10, the sealing resin 27A is provided with the side surface covering portion 29A. The outer peripheral side surface 22 of the semiconductor element 22C
It may be configured to cover b. Even with this configuration, it is possible to achieve the same effects as those obtained with the semiconductor devices 20G and 20H according to the seventh and eighth embodiments described with reference to FIGS. 11 and 12.
【００６２】続いて、図１３を用いて本発明の第１実施
例である半導体装置の製造方法について説明する。尚、
本実施例では、半導体装置２０Ｉに設けられた半導体素
子２２Ａの背面露出部分に捺印処理を行なう捺印工程に
特徴を有し、他の製造工程は周知であるため、捺印工程
についてのみ説明するものとする。A method of manufacturing the semiconductor device according to the first embodiment of the present invention will be described with reference to FIG. still,
The present embodiment is characterized by a marking process for performing a marking process on the exposed back surface of the semiconductor element 22A provided in the semiconductor device 20I, and since other manufacturing processes are well known, only the marking process will be described. To do.
【００６３】半導体装置２０Ｉの製造工程には、半導体
装置２０Ｉの識別を行なうため、社標，生産国表示，品
名，ロット番号等の捺印３６（図では、捺印３６を簡略
化して示している）を行なう捺印工程が実施される。こ
の際、半導体素子２２Ａの背面２２ａが露出した構成の
半導体素子２２Ａでは、この背面２２ａに捺印３６を実
施する必要がある。In the manufacturing process of the semiconductor device 20I, in order to identify the semiconductor device 20I, a marking 36 such as a company mark, a country of origin, a product name, and a lot number (the marking 36 is simplified in the figure). A marking step is carried out. At this time, in the semiconductor element 22A having a structure in which the back surface 22a of the semiconductor element 22A is exposed, it is necessary to perform the marking 36 on the back surface 22a.
【００６４】しかるに、半導体素子２２Ａは、能動領域
となる回路形成面２３を有しているため、捺印３６を深
く形成した場合には回路形成面２３に影響を与え、動作
不良が発生するおそれがある。このため、捺印３６は、
上記識別標識が確認しうる範囲において、なるべく浅く
形成する必要がある。そこで本実施例では、捺印工程で
捺印処理を行なうのに際し、１００ｎｍ以上でかつ８０
０ｎｍ以下の波長範囲内のレーザー光３５を用いると共
に、半導体素子２２Ａの背面２２ａに対するレーザー光
３５による捺印３６の深さを２μｍ以下となるよう構成
したことを特徴とするものである。However, since the semiconductor element 22A has the circuit forming surface 23 serving as an active region, when the imprint 36 is formed deeply, it may affect the circuit forming surface 23 and cause a malfunction. is there. Therefore, the seal 36 is
It is necessary to form as shallow as possible within the range where the identification mark can be confirmed. Therefore, in the present embodiment, when the marking process is performed in the marking process, the thickness is 100 nm or more and 80 nm or more.
It is characterized in that the laser light 35 in the wavelength range of 0 nm or less is used, and the marking 36 formed by the laser light 35 on the back surface 22a of the semiconductor element 22A has a depth of 2 μm or less.
【００６５】図１３（Ａ）は、レーザー装置３４を用い
て半導体素子２２Ａの背面２２ａに捺印３６形成してい
る様子を示しており、また図１３（Ｂ）は形成された捺
印３６の例を示している。本実施例のように、捺印工程
で捺印処理を行なうのに用いるレーザー装置３４が発生
するレーザ光３５の波長範囲を１００ｎｍ以上でかつ８
００ｎｍ以下の範囲に設定することにより、半導体素子
２２Ａの回路形成面２３に損傷を与えることなく捺印３
６を形成することができる。これについて、図１４を用
いて説明する。FIG. 13A shows a state in which the imprint 36 is formed on the back surface 22a of the semiconductor element 22A using the laser device 34, and FIG. 13B shows an example of the imprint 36 formed. Shows. As in the present embodiment, the wavelength range of the laser beam 35 generated by the laser device 34 used for performing the marking process in the marking step is 100 nm or more and 8
By setting the thickness within the range of 00 nm or less, the marking 3 can be formed without damaging the circuit forming surface 23 of the semiconductor element 22A.
6 can be formed. This will be described with reference to FIG.
【００６６】図１４は、レーザー光３５の波長と、半導
体素子２２Ａのレーザー吸収係数との関係を示してい
る。同図から判るように、レーザー光３５の波長が８０
０ｎｍを越えると、半導体素子２２Ａのレーザー光３５
を吸収する吸収係数が急激に低くなり、よってレーザー
光３５は半導体素子２２Ａ内を容易に通過して回路形成
面２３に達し、回路形成面２３が破壊されるおそれがあ
る。FIG. 14 shows the relationship between the wavelength of the laser beam 35 and the laser absorption coefficient of the semiconductor element 22A. As can be seen from the figure, the wavelength of the laser beam 35 is 80
If it exceeds 0 nm, the laser light 35 of the semiconductor element 22A
The absorption coefficient of absorbing the laser light rapidly decreases, so that the laser light 35 may easily pass through the semiconductor element 22A to reach the circuit forming surface 23, and the circuit forming surface 23 may be destroyed.
【００６７】一方、レーザー光３５の波長が１００ｎｍ
未満であると、半導体素子２２Ａのレーザー光３５の吸
収係数が急激に高くなることが知られており、半導体素
子２２Ａに捺印を形成することができなくなる。よっ
て、レーザー光３５の波長範囲を１００ｎｍ以上でかつ
８００ｎｍ以下とすることにより、半導体素子２２Ａに
回路形成面２３に損傷を与えることなく、半導体素子２
２Ａの背面２２ａに捺印３６を形成することができる。On the other hand, the wavelength of the laser light 35 is 100 nm.
It is known that if it is less than the above, the absorption coefficient of the laser beam 35 of the semiconductor element 22A rapidly increases, and it becomes impossible to form a seal on the semiconductor element 22A. Therefore, by setting the wavelength range of the laser beam 35 to 100 nm or more and 800 nm or less, the semiconductor element 2 can be provided without damaging the semiconductor element 22A on the circuit forming surface 23.
A marking 36 can be formed on the back surface 22a of 2A.
【００６８】また、この捺印３６の形成時に、上記レー
ザー光３５の波長範囲の制御に加え、レーザー光３５の
照射時間及び走査時間を制御することにより、形成され
る捺印２６の深さは２μｍ以下となるよう構成されてい
る。この構成とすることによっても、半導体素子２２Ａ
の回路形成面２３に影響を与えることなく捺印３６を形
成することができる。これについて、図１５を用いて説
明する。When the marking 36 is formed, the depth of the marking 26 formed is 2 μm or less by controlling the irradiation time and scanning time of the laser light 35 in addition to controlling the wavelength range of the laser light 35. Is configured. Even with this configuration, the semiconductor element 22A
It is possible to form the imprint 36 without affecting the circuit forming surface 23. This will be described with reference to FIG.
【００６９】図１５は本発明者が行なった実験結果を示
しており、温度サイクルを実施した時に不良品が発生す
る割合を示している。尚、本実験の実験条件は、先に図
６を用いて説明した実験条件と同一である。また、同図
には、捺印２６の深さを２μｍとした実施例と、レーザ
ー深さを３μｍ以上とした半導体装置の実験結果を比較
例として合わせて記載している。FIG. 15 shows the result of an experiment conducted by the inventor of the present invention, and shows the ratio of defective products when the temperature cycle is carried out. The experimental conditions of this experiment are the same as the experimental conditions described above with reference to FIG. Further, in the figure, an example in which the depth of the marking 26 is 2 μm and an experimental result of a semiconductor device in which the laser depth is 3 μm or more are also shown as a comparative example.
【００７０】同図にから判るように、比較例に係る半導
体装置では、サイクル数の増加に伴い不良率は急激に上
昇し、１０００サイクル以上においては１００パーセン
トの半導体装置に不良が発生する。これに対し、捺印２
６の深さを２μｍ以下とした本実施例に係る半導体装置
２０Ｉでは、全てのサイクル域において不良品の発生は
なかった。よって、同図に示す実験結果から、捺印２６
の深さを２μｍ以下とすることにより、半導体装置２０
Ｉの信頼性の向上を図ることができることが立証され
る。As can be seen from the figure, in the semiconductor device according to the comparative example, the defect rate sharply increases as the number of cycles increases, and 100% of the semiconductor devices have defects after 1000 cycles. On the other hand, seal 2
In the semiconductor device 20I according to this example in which the depth of 6 was 2 μm or less, no defective product was generated in all cycle regions. Therefore, from the experimental results shown in FIG.
By setting the depth of the semiconductor device to 2 μm or less, the semiconductor device 20
It is proved that the reliability of I can be improved.
【００７１】続いて、図１６を用いて本発明の第１実施
例である半導体装置の製造方法について説明する。本実
施例は先に図５を用いて説明した側面被覆部２９Ｂが半
導体素子２２Ａの背面２２ａと同一高さとなるよう構成
された半導体装置２０Ｂを製造する方法である。また、
本実施例に係る製造方法は、封止樹脂２７Ｂを形成する
樹脂注入工程と、この樹脂注入工程において発生する余
剰樹脂３８を除去する除去工程に特徴を有するものであ
り他の製造工程は周知であるため、樹脂注入工程及び除
去工程についてのみ説明するものとする。A method of manufacturing the semiconductor device according to the first embodiment of the present invention will be described with reference to FIG. The present embodiment is a method of manufacturing the semiconductor device 20B configured so that the side surface covering portion 29B described above with reference to FIG. 5 is flush with the back surface 22a of the semiconductor element 22A. Also,
The manufacturing method according to this embodiment is characterized by a resin injection step of forming the sealing resin 27B and a removal step of removing the surplus resin 38 generated in this resin injection step, and other manufacturing steps are well known. Therefore, only the resin injection step and the removal step will be described.
【００７２】図１６（Ａ）は、封止樹脂２７Ｂを形成す
る樹脂注入工程を示している。同図に示すように、樹脂
注入工程では、封止樹脂２７Ｂとなる樹脂をディスペン
サー３７を用いてポッティングすることにより形成す
る。このように、ディスペンサー３７を用いたポッティ
ングにより封止樹脂２７Ｂを形成することにより、半導
体素子２２Ａの側面２２ｂに容易に側面被覆部２９Ｂを
形成することができる。また、トランスファーモールド
法により封止樹脂２７Ｂを形成する方法に比べ、金型を
必要とすることはなく、また設備も簡単化できるため、
容易かつ安価に封止樹脂２７Ｂを形成することができ
る。FIG. 16A shows a resin injection step of forming the sealing resin 27B. As shown in the figure, in the resin injecting step, the resin to be the sealing resin 27B is formed by potting using the dispenser 37. Thus, by forming the sealing resin 27B by potting using the dispenser 37, the side surface covering portion 29B can be easily formed on the side surface 22b of the semiconductor element 22A. Further, as compared with the method of forming the sealing resin 27B by the transfer molding method, a mold is not required and the equipment can be simplified.
The sealing resin 27B can be easily and inexpensively formed.
【００７３】上記の樹脂注入工程が終了すると、続いて
余剰樹脂３８を除去する除去工程が実施される。図１６
（Ｂ）は、除去工程を示してる。樹脂注入工程では、前
記のようにポッティングにより封止樹脂２７Ｂを形成す
るため、図１６（Ａ）に示すように、半導体素子２２Ａ
の背面２２ａに余剰樹脂３８が付着することが考えられ
る。このように、余剰樹脂３８が半導体素子２２Ａの背
面２２ａに存在する場合、半導体装置２０Ｂの高さにバ
ラツキが生じ、また放熱特性の面からも望ましくない。When the above resin injection step is completed, a removal step for removing the excess resin 38 is subsequently performed. FIG.
(B) shows the removing step. In the resin injecting step, the sealing resin 27B is formed by potting as described above, and therefore, as shown in FIG.
It is conceivable that the surplus resin 38 adheres to the back surface 22a of the. As described above, when the surplus resin 38 is present on the back surface 22a of the semiconductor element 22A, the height of the semiconductor device 20B varies, and it is not desirable in terms of heat dissipation characteristics.
【００７４】よって、樹脂注入工程の終了後、除去工程
を実施して余剰樹脂３８を除去する処理が行なわれる。
本実施例では、余剰樹脂３８を除去する方法としてレー
ザ装置３４を用いており、かつレーザ装置３４が発生す
るレーザ光３５の波長範囲を１００ｎｍ以上でかつ８０
０ｎｍ以下としていることを特徴としている。先に図１
３及び図１４を用いて説明したように、レーザ光３５の
波長が８００ｎｍ以下の場合には、半導体素子２２Ａに
損傷が発生することを抑制することができる。また、レ
ーザ光３５の波長範囲が１００ｎｍ未満になると、余剰
樹脂３８を有効に除去することができなくなる。Therefore, after the resin injection step is completed, the removal step is carried out to remove the excess resin 38.
In this embodiment, the laser device 34 is used as a method for removing the excess resin 38, and the wavelength range of the laser light 35 generated by the laser device 34 is 100 nm or more and 80 nm or more.
The feature is that the thickness is 0 nm or less. Figure 1
As described with reference to FIGS. 3 and 14, when the wavelength of the laser light 35 is 800 nm or less, it is possible to prevent the semiconductor element 22A from being damaged. If the wavelength range of the laser light 35 is less than 100 nm, the surplus resin 38 cannot be effectively removed.
【００７５】よって、本実施例のように、１００ｎｍ以
上でかつ８００ｎｍ以下の波長範囲内のレーザー光３５
を用いて余剰樹脂３８を除去する構成とすることによ
り、半導体素子２２Ａに影響を与えることなく、余剰樹
脂３８の除去を容易かつ効率的に行なうことができる。
更に、この除去工程に連続して、前記した捺印工程を実
施することにより、同一のレーザ装置３４を用いて余剰
樹脂３８の除去処理と捺印３６の形成処理を連続して実
施することが可能となり、更に半導体装置２０Ｂの製造
工程の効率化を図ることができる。Therefore, as in this embodiment, the laser light 35 within the wavelength range of 100 nm or more and 800 nm or less is used.
By using the configuration to remove the excess resin 38, the excess resin 38 can be removed easily and efficiently without affecting the semiconductor element 22A.
Further, by performing the marking step described above following this removal step, it becomes possible to continuously perform the removal processing of the excess resin 38 and the formation processing of the marking 36 using the same laser device 34. Further, the efficiency of the manufacturing process of the semiconductor device 20B can be improved.
【００７６】尚、半導体素子の実装形態としては、上記
した各実施例のように半導体装置内に搭載される形態の
他に、図１７に示すようにマザーボード３９に半導体素
子２２Ａを実装する、いわゆるＭＣＭ（マルチチップモ
ジュール）の搭載形態もある。このようなマザーボード
３９に半導体素子２２Ａを実装する構成において、封止
樹脂２７Ａに側面被覆部２９Ａを設けると共にこの側面
被覆部２９Ａを半導体素子２２Ａの側面２２ｂを被覆す
るよう配設した構成としてもよい。この構成によって
も、上記した各実施例で説明したと同様の効果を実現す
ることができる。As for the mounting form of the semiconductor element, in addition to the mounting form in the semiconductor device as in each of the above-described embodiments, the so-called semiconductor element 22A is mounted on the motherboard 39 as shown in FIG. There is also a mounting form of MCM (multi-chip module). In such a configuration in which the semiconductor element 22A is mounted on the mother board 39, the side surface covering portion 29A may be provided on the sealing resin 27A and the side surface covering portion 29A may be disposed so as to cover the side surface 22b of the semiconductor element 22A. . Also with this configuration, the same effect as that described in each of the above-described embodiments can be realized.
【００７７】続いて、本発明の第９実施例及び第１０実
施例について説明する。図１８は第９実施例に係る半導
体装置２０Ｊを示しており、また図１９は第１０実施例
に係る半導体装置２０Ｋを示している。上記した各実施
例においては、半導体素子２２Ａ〜２２Ｅを基板２５に
実装するのに、バンプ２４を用いた構成とされていた。
しかるに、半導体素子を基板２５に実装する構造は、バ
ンプ２４を用いた構造に限定されるものではない。Next, the ninth and tenth embodiments of the present invention will be described. 18 shows a semiconductor device 20J according to the ninth embodiment, and FIG. 19 shows a semiconductor device 20K according to the tenth embodiment. In each of the above-described embodiments, the bumps 24 are used to mount the semiconductor elements 22A to 22E on the substrate 25.
However, the structure for mounting the semiconductor element on the substrate 25 is not limited to the structure using the bumps 24.
【００７８】図１８に示す半導体装置２０Ｊは、半導体
素子２２Ｆと基板２５をリード４０を用いて電気的に接
続したことを特徴とするものである、また、図１９に示
す半導体装置２０Ｋは、半導体素子２２Ｆと回路基板２
５をワイヤ４１を用いて電気的に接続したことを特徴と
するものである。また、各実施例では、半導体素子２２
Ｆと回路基板２５との間に応力吸収用のエラストマー４
２が配設されている。The semiconductor device 20J shown in FIG. 18 is characterized in that the semiconductor element 22F and the substrate 25 are electrically connected by using the leads 40. Further, the semiconductor device 20K shown in FIG. Element 22F and circuit board 2
5 is electrically connected using a wire 41. In each embodiment, the semiconductor element 22
Elastomer 4 for absorbing stress between F and the circuit board 25
2 are provided.
【００７９】このように、半導体素子２２Ｆ（２２Ａ〜
２２Ｅ）を基板２５に実装する構造はバンプ２４に限定
されるものではなく、リード４０，ワイヤ４１等の他の
接続手段を用いて実装する構造としてもよい。In this way, the semiconductor element 22F (22A ...
22E) is not limited to the bumps 24, but may be mounted using other connecting means such as the leads 40 and the wires 41.
【００８０】[0080]
【発明の効果】上述の如く本発明によれば、耐リフロー
性及び耐湿性が向上し、これにより半導体装置の信頼性
を向上することができる。また、温度サイクル時におい
て応力集中が回路形成面近傍に発生することを抑制で
き、半導体装置の破損を防止することができる。 As described above, according to the present invention, reflow resistance is high.
Property and moisture resistance are improved, and thereby reliability of the semiconductor device can be improved. In addition, it is possible to prevent stress concentration from being generated in the vicinity of the circuit formation surface during the temperature cycle, and prevent damage to the semiconductor device.
【００８１】[0081]
【００８２】[0082]
【００８３】[0083]
【図１】従来の一例である半導体装置を示す図である
（その１）。FIG. 1 is a diagram showing a conventional semiconductor device (No. 1).
【図２】従来の一例である半導体装置を示す図である
（その２）。FIG. 2 is a diagram showing a conventional semiconductor device (No. 2).
【図３】従来の半導体装置で発生する問題点を説明する
ための図である。FIG. 3 is a diagram for explaining a problem that occurs in a conventional semiconductor device.
【図４】本発明の第１実施例である半導体装置を説明す
るための図である。FIG. 4 is a diagram for explaining the semiconductor device according to the first embodiment of the present invention.
【図５】本発明の第２実施例である半導体装置を説明す
るための図である。FIG. 5 is a diagram for explaining a semiconductor device which is a second embodiment of the present invention.
【図６】第１実施例である半導体装置の効果を説明する
めたの図である。FIG. 6 is a diagram for explaining effects of the semiconductor device according to the first embodiment.
【図７】本発明の第３実施例である半導体装置を説明す
るための図である。FIG. 7 is a diagram for explaining a semiconductor device which is a third embodiment of the present invention.
【図８】本発明の第４実施例である半導体装置を説明す
るための図である。FIG. 8 is a diagram for explaining a semiconductor device according to a fourth embodiment of the present invention.
【図９】本発明の第５実施例である半導体装置を説明す
るための図である。FIG. 9 is a diagram for explaining a semiconductor device which is a fifth embodiment of the present invention.
【図１０】本発明の第６実施例である半導体装置を説明
するための図である。FIG. 10 is a drawing for explaining a semiconductor device which is a sixth embodiment of the present invention.
【図１１】本発明の第７実施例である半導体装置を説明
するための図である。FIG. 11 is a drawing for explaining a semiconductor device which is a seventh embodiment of the present invention.
【図１２】本発明の第８実施例である半導体装置を説明
するための図である。FIG. 12 is a diagram for explaining a semiconductor device according to an eighth embodiment of the present invention.
【図１３】本発明の第１実施例である半導体装置の製造
方法を説明するための図である。FIG. 13 is a diagram illustrating the method for manufacturing the semiconductor device according to the first embodiment of the invention.
【図１４】レーザーの波長と吸収係数との関係を示す図
である。FIG. 14 is a diagram showing a relationship between a laser wavelength and an absorption coefficient.
【図１５】第１実施例である製造方法により製造された
半導体装置の信頼性試験の結果を示す図である。FIG. 15 is a diagram showing a result of a reliability test of a semiconductor device manufactured by the manufacturing method according to the first embodiment.
【図１６】本発明の第２実施例である半導体装置の製造
方法を説明するための図である。FIG. 16 is a drawing for explaining the manufacturing method of the semiconductor device which is the second embodiment of the present invention.
【図１７】本発明を半導体素子を実装基板に実装する実
装構造に適用した例を示す図である。FIG. 17 is a diagram showing an example in which the present invention is applied to a mounting structure in which a semiconductor element is mounted on a mounting board.
【図１８】本発明の第９実施例である半導体装置を説明
するための図である。FIG. 18 is a drawing for explaining a semiconductor device which is a ninth embodiment of the present invention.
【図１９】本発明の第１０実施例である半導体装置を説
明するための図である。FIG. 19 is a drawing for explaining a semiconductor device which is a tenth embodiment of the present invention.
２０Ａ〜２０Ｋ 半導体装置 ２２Ａ〜２２Ｆ 半導体素子 ２２ａ 背面 ２３ 回路形成面 ２４ バンプ ２５ 基板 ２６ はんだボール ２７，２７Ａ〜２７Ｄ 封止樹脂 ２８Ａ，２８Ｂ 回路面封止部 ２９Ａ〜２９Ｄ 側面被覆部 ３０ 背面側面取り部 ３１ 回路面側面取り部 ３２ 背面側角面取り部 ３３ 回路面側角面取り部 ３４ レーザー装置 ３５ レーザー光 ３６ 捺印 ３７ ディスペンサー ３８ 余剰樹脂 ３９ マザーボード ４０ リード ４１ ワイヤ 20A to 20K Semiconductor device 22A-22F Semiconductor element 22a back side 23 Circuit formation surface 24 bumps 25 substrates 26 Solder balls 27, 27A to 27D sealing resin 28A, 28B Circuit surface sealing part 29A to 29D Side cover part 30 Back chamfer 31 Circuit chamfer 32 Back side chamfer 33 Circuit surface side chamfer 34 Laser equipment 35 laser light 36 seal 37 dispenser 38 Surplus resin 39 Motherboard 40 leads 41 wire
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ Ｈ０１Ｌ 23/00 Ｈ０１Ｌ 23/30 Ｂ 23/12 23/12 Ｌ 23/31 (72)発明者 関 正明 神奈川県川崎市中原区上小田中４丁目１ 番１号 富士通株式会社内 (72)発明者 浜野 寿夫 神奈川県川崎市中原区上小田中４丁目１ 番１号 富士通株式会社内 (56)参考文献 特開 平９−22968（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 23/29 B23K 26/00 H01L 21/56 H01L 21/60 311 H01L 23/00 H01L 23/12 H01L 23/31 ─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. 7 Identification code FI H01L 23/00 H01L 23/30 B 23/12 23/12 L 23/31 (72) Inventor Masaaki Seki Nakahara-ku, Kawasaki-shi, Kanagawa 4-1-11 Kamiodanaka, Fujitsu Limited (72) Inventor Toshio Hamano 4-1-1 1-1 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture (56) Reference: JP-A-9-22968 (JP) , A) (58) Fields investigated (Int.Cl. 7 , DB name) H01L 23/29 B23K 26/00 H01L 21/56 H01L 21/60 311 H01L 23/00 H01L 23/12 H01L 23/31
Claims (4)
前記半導体素子に形成された回路形成面を封止する封止
樹脂と、を具備する半導体装置において、 前記半導体素子の前記回路形成面と反対側に位置する背
面の辺エッジに面取り部を形成し、 かつ、前記封止樹脂に形成された前記半導体素子の外周
側面を覆う側面被覆部の前記回路形成面からの高さをｔ
とし、前記半導体素子の高さ寸法をＴとした場合、前記
側面被覆部の回路形成面からの高さｔがＴ／４≦ｔ≦Ｔ
となるよう構成したこと を特徴とする半導体装置。1. A semiconductor element, a substrate on which the semiconductor element is mounted, and a state in which the semiconductor element is mounted on the substrate,
In a semiconductor device comprising a sealing resin that seals a circuit formation surface formed on the semiconductor element, a chamfered portion is formed on a side edge of a back surface of the semiconductor element that is opposite to the circuit formation surface. And the outer periphery of the semiconductor element formed in the sealing resin
The height of the side surface covering portion that covers the side surface from the circuit forming surface is t
And the height dimension of the semiconductor element is T,
The height t of the side surface covering portion from the circuit forming surface is T / 4 ≦ t ≦ T
A semiconductor device characterized by being configured as follows .
取り部を形成したこと を特徴とする半導体装置。2. The semiconductor device according to claim 1, further comprising a surface at a side edge of the circuit formation surface of the semiconductor element.
A semiconductor device characterized in that a take-off portion is formed .
前記半導体素子に形成された回路形成面を封止する封止
樹脂と、を具備する半導体装置において、前記半導体素子の前記回路形成面と反対側に位置する背
面のコーナーエッジに面取り部を形成し、 かつ、前記封止樹脂に形成された前記半導体素子の外周
側面を覆う側面被覆部の前記回路形成面からの高さをｔ
とし、前記半導体素子の高さ寸法をＴとした場合、前記
側面被覆部の回路形成面からの高さｔがＴ／４≦ｔ≦Ｔ
となるよう構成したこと を特徴とする半導体装置。3. A semiconductor element, a substrate on which the semiconductor element is mounted, and a state in which the semiconductor element is mounted on the substrate,
In a semiconductor device comprising a sealing resin that seals a circuit formation surface formed on the semiconductor element, a spine located on the opposite side of the semiconductor element from the circuit formation surface.
A chamfer is formed at the corner edge of the surface, and the outer periphery of the semiconductor element formed in the sealing resin.
The height of the side surface covering portion that covers the side surface from the circuit forming surface is t
And the height dimension of the semiconductor element is T,
The height t of the side surface covering portion from the circuit forming surface is T / 4 ≦ t ≦ T
A semiconductor device characterized by being configured as follows .
ジに面取り部を形成したこと を特徴とする半導体装置。4. The semiconductor device according to claim 3, further comprising a corner edge of the circuit formation surface of the semiconductor element.
A semiconductor device characterized in that a chamfered portion is formed on the groove .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20825898A JP3432749B2 (en) | 1998-07-23 | 1998-07-23 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20825898A JP3432749B2 (en) | 1998-07-23 | 1998-07-23 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2000040775A JP2000040775A (en) | 2000-02-08 |
| JP3432749B2 true JP3432749B2 (en) | 2003-08-04 |
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| Application Number | Title | Priority Date | Filing Date |
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| JP20825898A Expired - Fee Related JP3432749B2 (en) | 1998-07-23 | 1998-07-23 | Semiconductor device and manufacturing method thereof |
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| JP (1) | JP3432749B2 (en) |
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| JP2002009096A (en) * | 2000-06-20 | 2002-01-11 | Apic Yamada Corp | Method and apparatus for resin sealing |
| JP4934900B2 (en) * | 2000-12-15 | 2012-05-23 | イビデン株式会社 | Manufacturing method of multilayer printed wiring board |
| JP3929250B2 (en) | 2001-03-08 | 2007-06-13 | 株式会社ルネサステクノロジ | Semiconductor device |
| JP3878430B2 (en) * | 2001-04-06 | 2007-02-07 | 株式会社ルネサステクノロジ | Semiconductor device |
| JP3530158B2 (en) * | 2001-08-21 | 2004-05-24 | 沖電気工業株式会社 | Semiconductor device and manufacturing method thereof |
| JP2004022870A (en) * | 2002-06-18 | 2004-01-22 | Fujitsu Ltd | Flip-chip electronic device and chip module electronic device equipment |
| JP4495916B2 (en) * | 2003-03-31 | 2010-07-07 | 富士通マイクロエレクトロニクス株式会社 | Manufacturing method of semiconductor chip |
| US20060046321A1 (en) * | 2004-08-27 | 2006-03-02 | Hewlett-Packard Development Company, L.P. | Underfill injection mold |
| JP2007173273A (en) | 2005-12-19 | 2007-07-05 | Fujitsu Ltd | Peeling strength simulator, peeling strength simulating program, and peeling strength simulating method |
| JP4852310B2 (en) * | 2006-01-06 | 2012-01-11 | 日本オプネクスト株式会社 | Optical transmission module |
| JP5054943B2 (en) * | 2006-08-04 | 2012-10-24 | Ｔｏｗａ株式会社 | Cutting apparatus and cutting method |
| JP5592820B2 (en) * | 2011-03-15 | 2014-09-17 | 積水化学工業株式会社 | Semiconductor chip mounting method, laminated sheet, and semiconductor chip mounting body |
| JP2017157849A (en) * | 2011-12-28 | 2017-09-07 | ローム株式会社 | Method of producing chip component and chip component |
| JP6282589B2 (en) * | 2012-07-26 | 2018-02-21 | 株式会社村田製作所 | Module and manufacturing method thereof |
| GB2504343A (en) | 2012-07-27 | 2014-01-29 | Ibm | Manufacturing an semiconductor chip underfill using air vent |
| JP5646021B2 (en) * | 2012-12-18 | 2014-12-24 | 積水化学工業株式会社 | Semiconductor package |
| WO2014181766A1 (en) * | 2013-05-07 | 2014-11-13 | ピーエスフォー ルクスコ エスエイアールエル | Semiconductor device and semiconductor device manufacturing method |
| JP2015169597A (en) * | 2014-03-10 | 2015-09-28 | 株式会社日本自動車部品総合研究所 | Pressure sensor and manufacturing method thereof |
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1998
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| JP2000040775A (en) | 2000-02-08 |
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