JP2017130671A - Chip component - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide chip components which are hardly tightly-affixed to each other even if aggregated to one place.SOLUTION: A chip resistor 1 includes: a substrate 2; an element 5 containing a plurality of resistors R formed on the substrate 2; and a first connection electrode 3 and a second connection electrode 4 for externally connecting the element 5. On side surfaces 2C to 2F of the substrate 2, unevenness 12 is formed which is obtained by alternately arranging a recess 10 notched in a thickness direction of the substrate 2 and a protrusion 11 neighboring to the recess 10. The unevenness 12 may be formed over the whole circumference of the side surfaces 2C to 2F of the substrate 2.SELECTED DRAWING: Figure 1C

Description

  The present invention relates to a chip component.

  Patent Document 1 discloses a chip resistor in which a resistive film formed on an insulating substrate is laser trimmed and then a glass cover coat is formed.

Japanese Patent Laid-Open No. 2001-76912

  Similar to the chip resistor disclosed in Patent Document 1, the conventional chip component has a flat side surface over the entire circumference. For this reason, when a large number of diced chips are aligned by a bulk feeder or the like after the chips are cut out from the wafer, the chips may be aggregated due to static electricity or the like and closely adhered to each other. As a result, there is a problem that chip mounting efficiency is lowered.

  An object of the present invention is to provide a chip component that hardly adheres even if it aggregates at one place.

  The chip component of the present invention has a rectangular central region and a peripheral edge around the central region, a substrate having one surface and the other surface opposite to the one surface, and the central region of the substrate. An element circuit network including a plurality of element elements formed on one surface, and an electrode provided on the one surface of the central region of the substrate and externally connecting the element circuit network; On the side surface that intersects the one surface and the other surface, there are formed recesses and recesses that are formed by alternately arranging recesses cut out in the thickness direction of the substrate and protrusions adjacent to the recesses, The concave portion and the convex portion are provided on each side from the peripheral portion of one surface of the substrate to the peripheral portion of the other surface of the substrate.

According to this configuration, even if a large number of chip components are aggregated in one place, the contact area between the chip components can be reduced by the unevenness on the side surface of the substrate. As a result, it is possible to prevent close contact between the chip components, thereby improving the mounting efficiency.
The convex portions may be formed with the same width as each other and arranged at a constant pitch in the circumferential direction of the side surface of the substrate.

The convex portion may include a convex portion that is wider than the width of the concave portion.
According to this configuration, it is difficult for the convex portion to be caught by the concave portion, and the unevenness of the chip component is difficult to mesh with the unevenness of the chip component in the vicinity thereof.
It is preferable that the unevenness is formed over the entire circumference of the side surface of the substrate.
According to this configuration, even if another chip component comes into contact with the side surface of the substrate from any direction, the chip components can be reliably prevented from coming into close contact with each other.

The convex portion may be formed in any of a quadrangular shape, a triangular shape, and an arc shape in a plan view as viewed from the normal direction of the one surface of the substrate.
The chip component preferably includes a plurality of fuses for connecting the plurality of element elements to the electrodes in a detachable manner.
According to this configuration, by selecting and cutting one or a plurality of fuses, a combination pattern of a plurality of element elements in the element circuit network can be changed to an arbitrary pattern, so that the electrical characteristics of the element circuit network However, various chip parts can be realized with a common design.

The element circuit network may include a resistor circuit network including a plurality of resistors formed on the substrate, and the chip component may be a chip resistor.
According to this configuration, this chip component (chip resistor) can easily and quickly cope with a plurality of types of resistance values by selecting and cutting one or a plurality of fuses. In other words, chip resistors having various resistance values can be realized with a common design by combining a plurality of resistors having different resistance values.

The resistor preferably includes a resistor film formed on the substrate and a wiring film laminated on the resistor film.
According to this configuration, since the portion between the adjacent wiring films in the resistor film becomes a resistor, the resistor can be configured simply by simply laminating the wiring film on the resistor film.
The element circuit network may include a capacitor circuit network including a plurality of capacitor elements formed on the substrate, and the chip component may be a chip capacitor.

According to this configuration, this chip component (chip capacitor) can easily and quickly cope with a plurality of types of capacitance values by selecting and cutting one or a plurality of fuses. In other words, chip capacitors having various capacitance values can be realized by a common design by combining a plurality of capacitor elements having different capacitance values.
The capacitor element includes a capacitor film formed on the substrate, and a lower electrode film and an upper electrode film facing each other with the capacitor film interposed therebetween, and the lower electrode film and the upper electrode film are separated from each other. It is preferable that the plurality of electrode film portions are respectively connected to the plurality of fuses.

According to this configuration, a plurality of capacitor elements corresponding to the number of electrode film portions can be formed.
The element circuit network may include an inductor circuit network including a plurality of inductor elements formed on the substrate, and the chip component may be a chip inductor.
According to this configuration, in this chip component (chip inductor), a combination pattern of a plurality of inductor elements in the inductor network can be changed to an arbitrary pattern by selecting and cutting one or a plurality of fuses. Therefore, chip inductors having various electrical characteristics of the inductor network can be realized with a common design.

The element circuit network may include a diode circuit network including a plurality of diode elements formed on the substrate, and the chip component may be a chip diode.
According to this configuration, in this chip component (chip diode), the combination pattern of a plurality of diode elements in the diode network can be changed to an arbitrary pattern by selecting and cutting one or a plurality of fuses. Therefore, chip diodes with various electrical characteristics of the diode network can be realized with a common design.

The electrode preferably includes a Ni layer and an Au layer, and the Au layer is exposed on the outermost surface.
According to this configuration, in the electrode, since the surface of the Ni layer is covered with the Au layer, the Ni layer can be prevented from being oxidized.
Preferably, the electrode further includes a Pd layer interposed between the Ni layer and the Au layer.

  According to this configuration, in the electrode, even if a through hole (pinhole) is formed in the Au layer by thinning the Au layer, the Pd layer interposed between the Ni layer and the Au layer is penetrated. Since the hole is closed, the Ni layer can be prevented from being exposed to the outside through the through hole and being oxidized.

FIG. 1A is a schematic perspective view for explaining a configuration of a chip resistor according to an embodiment of the present invention. FIG. 1B is a schematic cross-sectional view of the circuit assembly in a state where the chip resistor is mounted on the mounting substrate, cut along the longitudinal direction of the chip resistor. FIG. 1C is a schematic plan view of the chip resistor. FIG. 1D is a schematic plan view of the chip resistor and is a diagram illustrating a modification of the unevenness. FIG. 1E is a schematic plan view of the chip resistor and is a diagram showing a modification of the unevenness. FIG. 1F is a schematic plan view of the chip resistor and is a diagram illustrating a modification of the unevenness. FIG. 1G is a schematic plan view of the chip resistor and is a diagram showing a modification of the unevenness. FIG. 1H is a schematic plan view of the chip resistor and is a diagram illustrating a modification of the unevenness. FIG. 1I is a schematic plan view of the chip resistor and is a diagram illustrating a modification of the unevenness. FIG. 2 is a plan view of the chip resistor, showing the arrangement relationship of the first connection electrode, the second connection electrode and the element, and the configuration of the element in plan view. FIG. 3A is a plan view illustrating a part of the element shown in FIG. 2 in an enlarged manner. FIG. 3B is a longitudinal sectional view in the length direction along BB of FIG. 3A drawn to explain the configuration of the resistor in the element. FIG. 3C is a longitudinal sectional view in the width direction along CC of FIG. 3A drawn to explain the configuration of the resistor in the element. FIG. 4 is a diagram showing the electrical characteristics of the resistor film line and the wiring film with circuit symbols and electrical circuit diagrams. FIG. 5A is a partial enlarged plan view of a region including a fuse drawn by enlarging a part of the plan view of the chip resistor shown in FIG. 2, and FIG. 5B is a plan view of FIG. It is a figure which shows the cross-sectional structure which follows BB. FIG. 6 is an electric circuit diagram of the element according to the embodiment of the present invention. FIG. 7 is an electric circuit diagram of an element according to another embodiment of the present invention. FIG. 8 is an electric circuit diagram of an element according to still another embodiment of the present invention. FIG. 9 is a schematic cross-sectional view of a chip resistor. FIG. 10A is a schematic cross-sectional view showing a method of manufacturing the chip resistor shown in FIG. FIG. 10B is a schematic sectional view showing a step subsequent to FIG. 10A. FIG. 10C is an illustrative sectional view showing a step subsequent to FIG. 10B. FIG. 10D is an illustrative sectional view showing a step subsequent to FIG. 10C. FIG. 10E is an illustrative sectional view showing a step subsequent to FIG. 10D. FIG. 10F is an illustrative sectional view showing a step subsequent to FIG. 10E. FIG. 10G is an illustrative sectional view showing a step subsequent to FIG. 10F. FIG. 11 is a schematic plan view of a part of a resist pattern used for forming a groove in the process of FIG. 10B. FIG. 12 is a diagram for explaining a manufacturing process of the first connection electrode and the second connection electrode. FIG. 13 is a plan view of a chip capacitor according to another embodiment of the present invention. FIG. 14 is a cross-sectional view taken along section line XIV-XIV in FIG. FIG. 15 is an exploded perspective view showing a part of the structure of the chip capacitor separately. FIG. 16 is a circuit diagram showing an internal electrical configuration of the chip capacitor. FIG. 17 is a perspective view showing an appearance of a smartphone which is an example of an electronic device in which the chip component of the present invention is used. FIG. 18 is a schematic plan view showing the configuration of the circuit assembly housed in the housing of the smartphone.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1A is a schematic perspective view for explaining a configuration of a chip resistor according to an embodiment of the present invention.
The chip resistor 1 is a minute chip component and has a rectangular parallelepiped shape as shown in FIG. 1A. The planar shape of the chip resistor 1 is a rectangle having two orthogonal sides (long side 81 and short side 82) of 0.4 mm or less and 0.2 mm or less, respectively. Preferably, with respect to the dimensions of the chip resistor 1, the length L (length of the long side 81) is about 0.3 mm, the width W (length of the short side 82) is about 0.15 mm, and the thickness T is about 0.1 mm.

The chip resistor 1 is formed by forming a plurality of chip resistors 1 in a lattice shape on a substrate, forming grooves in the substrate, and then polishing the back surface (or dividing the substrate by the grooves) to obtain individual chips. It is obtained by separating the resistor 1.
The chip resistor 1 is externally provided by a substrate 2 constituting the main body of the chip resistor 1, a first connection electrode 3 and a second connection electrode 4 that are external connection electrodes, and a first connection electrode 3 and a second connection electrode 4. It mainly includes an element 5 to be connected.

  The substrate 2 has a substantially rectangular parallelepiped chip shape. One surface forming the upper surface in FIG. 1A of the substrate 2 is an element formation surface 2A. The element formation surface 2A is a surface on which the element 5 is formed on the substrate 2 and has a substantially rectangular shape. The surface opposite to the element formation surface 2A in the thickness direction of the substrate 2 is a back surface 2B. The element formation surface 2A and the back surface 2B have substantially the same size and shape, and are parallel to each other. The rectangular edge defined by the pair of long sides 81 and short sides 82 on the element forming surface 2A is referred to as a peripheral edge 85, and the rectangular shape defined by the pair of long sides 81 and short sides 82 on the back surface 2B. The edge is referred to as the peripheral edge 90. When viewed from the normal direction perpendicular to the element formation surface 2A (back surface 2B), the peripheral edge portion 85 and the peripheral edge portion 90 overlap each other.

The substrate 2 has a plurality of side surfaces (side surface 2C, side surface 2D, side surface 2E, and side surface 2F) as surfaces other than the element formation surface 2A and the back surface 2B. The plurality of side surfaces extend so as to intersect (specifically, orthogonally cross) each of the element formation surface 2A and the back surface 2B, and connect the element formation surface 2A and the back surface 2B.
The side surface 2C is constructed between the short sides 82 on one side in the longitudinal direction on the element formation surface 2A and the back surface 2B (left front side in FIG. 1A), and the side surface 2D is on the other side in the longitudinal direction on the element formation surface 2A and the back surface 2B. It is constructed between the short sides 82 (on the right back side in FIG. 1A). The side surface 2C and the side surface 2D are both end surfaces of the substrate 2 in the longitudinal direction. The side surface 2E is constructed between the long sides 81 on one side in the short side direction (left rear side in FIG. 1A) of the element forming surface 2A and the back surface 2B, and the side surface 2F is short on the element forming surface 2A and the back surface 2B. It extends between the long sides 81 on the other side in the direction (the right front side in FIG. 1A). The side surface 2E and the side surface 2F are both end surfaces of the substrate 2 in the lateral direction. Each of the side surface 2C and the side surface 2D intersects (specifically, orthogonal) with each of the side surface 2E and the side surface 2F. For this reason, adjacent elements forming surface 2A to side surface 2F form a right angle.

  In the substrate 2, the entire area of the element formation surface 2 </ b> A and the side surfaces 2 </ b> C to 2 </ b> F is covered with the passivation film 23. Therefore, strictly speaking, in FIG. 1A, the entire area of each of the element formation surface 2A and the side surfaces 2C to 2F is located on the inner side (back side) of the passivation film 23 and is not exposed to the outside. Further, the chip resistor 1 has a resin film 24. The resin film 24 covers the entire region of the passivation film 23 on the element formation surface 2A (peripheral portion 85 and its inner region). The passivation film 23 and the resin film 24 will be described in detail later.

  The first connection electrode 3 and the second connection electrode 4 are formed on the element formation surface 2A of the substrate 2 in a region inside the peripheral edge portion 85 (position spaced from the peripheral edge portion 85). It is partially exposed from the resin film 24 on 2A. In other words, the resin film 24 covers the element formation surface 2A (strictly, the passivation film 23 on the element formation surface 2A) so as to expose the first connection electrode 3 and the second connection electrode 4. Each of the first connection electrode 3 and the second connection electrode 4 is configured, for example, by stacking Ni (nickel), Pd (palladium), and Au (gold) on the element formation surface 2A in this order. The first connection electrode 3 and the second connection electrode 4 are spaced apart from each other in the longitudinal direction of the element formation surface 2A and have a rectangular shape that is long in the short direction of the element formation surface 2A. In FIG. 1A, on the element formation surface 2A, the first connection electrode 3 is provided near the side surface 2C, and the second connection electrode 4 is provided near the side surface 2D.

  The first connection electrode 3 and the second connection electrode 4 have substantially the same size and the same shape in a plan view viewed from the normal direction described above. The first connection electrode 3 has a pair of long sides 3A and short sides 3B that form four sides in a plan view. The long side 3A and the short side 3B are orthogonal to each other in plan view. The second connection electrode 4 has a pair of long sides 4A and short sides 4B that form four sides in plan view. The long side 4A and the short side 4B are orthogonal to each other in plan view. The long side 3A and the long side 4A extend in parallel with the short side 82 of the substrate 2, and the short side 3B and the short side 4B extend in parallel with the long side 81 of the substrate 2. The surface of the first connection electrode 3 is curved toward the substrate 2 at both end portions on the long side 3A side. The surface of the second connection electrode 4 is also curved toward the substrate 2 at both ends on the long side 4A side.

  Of the pair of long sides 3A in the first connection electrode 3 in plan view, the entire area of the long side 3A closest to the peripheral edge 85 of the element formation surface 2A of the substrate 2 (the long side 3A on the left front side in FIG. 1A) is , Away from the nearest peripheral edge 85 (short side 82) to the inside of the substrate 2. Of the pair of long sides 4A in the second connection electrode 4, the entire region of the long side 4A closest to the peripheral edge 85 of the element formation surface 2A of the substrate 2 (the long side 4A on the right back side in FIG. 1A) is also viewed in plan view. In FIG. 2, the distance from the nearest peripheral edge 85 (short side 82) is inward of the substrate 2.

In plan view, the entire area of each short side 3B of the first connection electrode 3 is away from the nearest peripheral edge 85 (long side 81) inward of the substrate 2. The entire area of each short side 4B of the second connection electrode 4 is also away from the nearest peripheral edge 85 (long side 81) inward of the substrate 2 in plan view.
The chip resistor 1 does not have electrodes on the surface (that is, the back surface 2B and the side surfaces 2C to 2F) other than the element formation surface 2A on which the first connection electrode 3 and the second connection electrode 4 are formed.

  The element 5 is a circuit element, and is formed in a region between the first connection electrode 3 and the second connection electrode 4 on the element formation surface 2A of the substrate 2, and from above by the passivation film 23 and the resin film 24. It is covered. The element 5 of this embodiment is a resistor 56. The resistor 56 is constituted by a circuit network in which a plurality of (unit) resistors R having equal resistance values are arranged in a matrix on the element formation surface 2A. The resistor R is made of TiN (titanium nitride), TiON (titanium oxynitride) or TiSiON. The element 5 is electrically connected to a wiring film 22 described later, and is electrically connected to the first connection electrode 3 and the second connection electrode 4 via the wiring film 22. That is, the element 5 is formed on the substrate 2 and connected between the first connection electrode 3 and the second connection electrode 4.

FIG. 1B is a schematic cross-sectional view of the circuit assembly in a state where the chip resistor is mounted on the mounting substrate, cut along the longitudinal direction of the chip resistor. In addition, in FIG. 1B, only the principal part is shown with the cross section.
As shown in FIG. 1B, the chip resistor 1 is mounted on the mounting substrate 9. The chip resistor 1 and the mounting substrate 9 in this state constitute a circuit assembly 100. The upper surface of the mounting substrate 9 in FIG. 1B is a mounting surface 9A. A pair of (two) lands 88 connected to an internal circuit (not shown) of the mounting substrate 9 are formed on the mounting surface 9A. Each land 88 is made of Cu, for example. Solder 13 is provided on the surface of each land 88 so as to protrude from the surface.

  When the chip resistor 1 is mounted on the mounting substrate 9, the chip resistor 1 is moved by moving the suction nozzle 91 after the suction nozzle 91 of the automatic mounting machine (not shown) is attracted to the back surface 2B of the chip resistor 1. Transport. At this time, the suction nozzle 91 is sucked to a substantially central portion in the longitudinal direction of the back surface 2B. As described above, since the first connection electrode 3 and the second connection electrode 4 are provided only on one surface (element formation surface 2A) of the chip resistor 1, the back surface 2B of the chip resistor 1 is formed of electrodes ( It becomes a flat surface without unevenness. Therefore, when the suction nozzle 91 is attracted to the chip resistor 1 and moved, the suction nozzle 91 can be attracted to the flat back surface 2B. In other words, if the back surface 2B is flat, the margin of the portion that can be sucked by the suction nozzle 91 can be increased. Thus, the suction nozzle 91 can be reliably attracted to the chip resistor 1, and the chip resistor 1 can be reliably transported without dropping from the suction nozzle 91 in the middle.

  Then, the suction nozzle 91 that sucks the chip resistor 1 is moved to the mounting substrate 9. At this time, the element formation surface 2A of the chip resistor 1 and the mounting surface 9A of the mounting substrate 9 face each other. In this state, the suction nozzle 91 is moved and pressed against the mounting substrate 9. In the chip resistor 1, the first connection electrode 3 is brought into contact with the solder 13 of one land 88, and the second connection electrode 4 is brought into contact with the other land 88. The solder 13 is contacted. Next, when the solder 13 is heated, the solder 13 is melted. Thereafter, when the solder 13 is cooled and solidified, the first connection electrode 3 and the one land 88 are joined via the solder 13, and the second connection electrode 4 and the other land 88 are joined via the solder 13. Join. That is, each of the two lands 88 is soldered to the corresponding electrode in the first connection electrode 3 and the second connection electrode 4. Thereby, mounting of the chip resistor 1 on the mounting substrate 9 (flip chip connection) is completed, and the circuit assembly 100 is completed. Note that the first connection electrode 3 and the second connection electrode 4 that function as external connection electrodes are formed of gold (Au) in order to improve solder wettability and reliability, or as described later. It is desirable to apply gold plating to the surface.

In the completed circuit assembly 100, the element formation surface 2A of the chip resistor 1 and the mounting surface 9A of the mounting substrate 9 extend in parallel while facing each other with a gap. The dimension of the gap corresponds to the sum of the thickness of the portion protruding from the element formation surface 2 </ b> A in the first connection electrode 3 or the second connection electrode 4 and the thickness of the solder 13.
FIG. 1C to FIG. 1I are schematic plan views of the chip resistor 1 and are diagrams for explaining variations of the unevenness of the substrate 2.

The chip resistor 1 is characterized in that, on the side surfaces 2C to 2F of the substrate 2, the recesses 10 notched in the thickness direction of the substrate 2 and the protrusions 11 adjacent to the recesses 10 are alternately arranged. Is formed.
As shown in FIG. 1C, the unevenness 12 may be formed over the entire circumference of the side surfaces 2 </ b> C to 2 </ b> F of the substrate 2. That is, in all the side surfaces 2C to 2F, the concave portions 10 and the convex portions 11 that extend perpendicularly to the element forming surface 2A may be alternately formed from the peripheral edge portion 85 to the peripheral edge portion 90. In this case, the plurality of convex portions 11 are formed with the same width W ₂ (= W ₁ ) by forming the concave portions 10 with a constant width W ₁ (for example, about 5 μm) at a constant pitch P _1. it is preferably formed at a pitch _P 2 of the constant in the circumferential direction side 2C~2F (= _{P 1).} Further, the concave portion 10 and the convex portion 11 may have a quadrangular shape in plan view.

  The unevenness 12 on the side surfaces 2C to 2F of the substrate 2 can reduce the contact area between the chip resistors 1 due to the unevenness 12 of the substrate 2 even if a large number of chip resistors 1 are aggregated in one place. it can. Since at least the recess 10 does not contribute to contact, the area of the recess 10 can be reduced. As a result, adhesion between the chip resistors 1 can be prevented, so that mounting efficiency can be improved. Moreover, if the unevenness | corrugation 12 is formed over the perimeter of the board | substrate 2, even if another chip resistor 1 contacts the side surfaces 2C-2F of the board | substrate 2 from which direction, the chip resistors 1 will be contact | adhered reliably. Can be prevented.

Further, as shown in FIG. 1D, the convex portion 11 may selectively include a wide convex portion 11A having a width W ₄ wider than the width W _{3 of the} concave portion 10. That is, all the convex portions 11 may be wide convex portions 11A, or only some of the convex portions 11 may be wide convex portions 11A. This makes it difficult for the wide convex portion 11 </ b> A to be caught by the concave portion 10, so that the unevenness 12 of the chip resistor 1 becomes difficult to engage with the unevenness 12 of the chip resistor 1 in the vicinity thereof.

Moreover, as shown to FIG. 1E, the board | substrate 2 may have the side surface in which the unevenness | corrugation 12 is not formed. For example, in FIG. 1E, the side surface 2E is a flat surface on which the irregularities 12 are not formed.
Moreover, as shown to FIG. 1F and FIG. 1G, the convex part 11 may be triangular shape in planar view. In this case, the recess 10 may have a triangular shape in a plan view as shown in FIG. 1F, or may have a trapezoidal shape in a plan view as shown in FIG. 1G.

Moreover, as shown in FIG. 1H and FIG. 1I, the convex part 11 may be circular arc shape in planar view. In this case, the concave portion 10 may have an arc shape in a plan view as shown in FIG. 1H or a substantially trapezoidal shape in a plan view as shown in FIG. 1I.
In addition, the shape of the unevenness | corrugation 12 represented to FIG. 1C-FIG. 1I is only an example of the unevenness | corrugation of this invention, Furthermore, another form can also be employ | adopted.

Next, another configuration of the chip resistor 1 will be mainly described.
FIG. 2 is a plan view of the chip resistor, showing the arrangement relationship between the first connection electrode, the second connection electrode and the element, and the configuration (layout pattern) of the element in plan view.
Referring to FIG. 2, element 5 is a resistor network. Specifically, the element 5 includes eight resistors R arranged along the row direction (longitudinal direction of the substrate 2) and 44 resistors arranged along the column direction (width direction of the substrate 2). It has a total of 352 resistors R composed of the body R. These resistors R are a plurality of element elements constituting a resistance network of the element 5.

  A plurality of types of resistor circuits R are formed by grouping and electrically connecting a large number of these resistors R every predetermined number of 1 to 64. The formed plurality of types of resistance circuits are connected in a predetermined manner by a conductor film D (a wiring film formed of a conductor). Furthermore, a plurality of fuses F that can be cut (blown) in order to electrically incorporate a resistance circuit with respect to the element 5 or to electrically separate it from the element 5 are formed on the element forming surface 2A of the substrate 2. Is provided. The plurality of fuses F and the conductor film D are arranged along the inner side of the first connection electrode 3 so that the arrangement region is linear. More specifically, the plurality of fuses F and the conductor film D are arranged so as to be adjacent to each other, and the arrangement direction thereof is linear. The plurality of fuses F connect a plurality of types of resistor circuits (a plurality of resistors R for each resistor circuit) to the first connection electrode 3 so as to be cut (separable).

FIG. 3A is a plan view illustrating a part of the element shown in FIG. 2 in an enlarged manner. FIG. 3B is a longitudinal sectional view in the length direction along BB of FIG. 3A drawn to explain the configuration of the resistor in the element. FIG. 3C is a longitudinal sectional view in the width direction along CC of FIG. 3A drawn to explain the configuration of the resistor in the element.
The configuration of the resistor R will be described with reference to FIGS. 3A, 3B, and 3C.

The chip resistor 1 further includes an insulating layer 20 and a resistor film 21 in addition to the wiring film 22, the passivation film 23, and the resin film 24 described above (see FIGS. 3B and 3C). The insulating layer 20, the resistor film 21, the wiring film 22, the passivation film 23, and the resin film 24 are formed on the substrate 2 (element formation surface 2A).
The insulating layer 20 is made of SiO ₂ (silicon oxide). The insulating layer 20 covers the entire area of the element formation surface 2A of the substrate 2. The insulating layer 20 has a thickness of about 10,000 mm.

  The resistor film 21 is formed on the insulating layer 20. The resistor film 21 is made of TiN, TiON, or TiSiON. The thickness of the resistor film 21 is about 2000 mm. The resistor film 21 constitutes a plurality of resistor films (hereinafter referred to as “resistor film line 21 </ b> A”) extending linearly in parallel between the first connection electrode 3 and the second connection electrode 4. The resistor film line 21A may be cut at a predetermined position in the line direction (see FIG. 3A).

A wiring film 22 is laminated on the resistor film line 21A. The wiring film 22 is made of Al (aluminum) or an alloy of aluminum and Cu (copper) (AlCu alloy). The thickness of the wiring film 22 is about 8000 mm. The wiring film 22 is laminated on the resistor film line 21A at a predetermined interval R in the line direction, and is in contact with the resistor film line 21A.
FIG. 4 shows the electrical characteristics of the resistor film line 21A and the wiring film 22 of this configuration as circuit symbols. That is, as shown in FIG. 4A, each of the resistor film lines 21A in the region of the predetermined interval R forms one resistor R having a certain resistance value r.

In the region where the wiring film 22 is laminated, the resistor film lines 21 </ b> A are short-circuited by the wiring film 22 by electrically connecting the resistors R adjacent to each other. Therefore, a resistance circuit is formed which is formed by connecting in series the resistor R of the resistor r shown in FIG.
Further, since the adjacent resistor film lines 21A are connected to each other by the resistor film 21 and the wiring film 22, the resistor network of the element 5 shown in FIG. 3A is shown in FIG. A resistor circuit (consisting of R unit resistors) is formed. Thus, the resistor film 21 and the wiring film 22 constitute the resistor R and the resistor circuit (that is, the element 5). Each resistor R includes a resistor film line 21A (resistor film 21) and a plurality of wiring films 22 stacked on the resistor film line 21A at a predetermined interval in the line direction. A resistor film line 21A at a constant interval R where 22 is not laminated constitutes one resistor R. The resistor film lines 21A in the portion constituting the resistor R are all equal in shape and size. Therefore, the multiple resistors R arranged in a matrix on the substrate 2 have equal resistance values.

Further, the wiring film 22 laminated on the resistor film line 21A forms the resistor R and also plays a role of the conductor film D for connecting a plurality of resistors R to form a resistor circuit. (See FIG. 2).
FIG. 5A is a partial enlarged plan view of a region including a fuse drawn by enlarging a part of the plan view of the chip resistor shown in FIG. 2, and FIG. 5B is a plan view of FIG. It is a figure which shows the cross-sectional structure which follows BB.

  As shown in FIGS. 5A and 5B, the above-described fuse F and conductor film D are also formed by the wiring film 22 laminated on the resistor film 21 forming the resistor R. That is, the fuse F and the conductor film D are formed on the same layer as the wiring film 22 laminated on the resistor film line 21A forming the resistor R by Al or AlCu alloy which is the same metal material as the wiring film 22. Yes. As described above, the wiring film 22 is also used as a conductor film D for electrically connecting a plurality of resistors R in order to form a resistance circuit.

  That is, in the same layer stacked on the resistor film 21, the wiring film for forming the resistor R, the fuse F, the conductor film D, and the element 5 are connected to the first connection electrode 3 and the second film. A wiring film for connecting to the connection electrode 4 is formed as the wiring film 22 using the same metal material (Al or AlCu alloy). Note that the fuse F is different from the wiring film 22 (differentiated) because the fuse F is thinly formed so that it can be easily cut, and there are no other circuit elements around the fuse F. This is because they are arranged in such a manner.

  Here, a region where the fuse F is arranged in the wiring film 22 is referred to as a trimming target region X (see FIGS. 2 and 5A). The trimming target region X is a linear region along the inner side of the first connection electrode 3, and not only the fuse F but also the conductor film D is disposed in the trimming target region X. A resistor film 21 is also formed below the wiring film 22 in the trimming target region X (see FIG. 5B). The fuse F is a wiring having a larger inter-wiring distance (separated from the surroundings) than the portion other than the trimming target region X in the wiring film 22.

The fuse F indicates not only a part of the wiring film 22 but also a group (fuse element) of a part of the resistor R (resistor film 21) and a part of the wiring film 22 on the resistor film 21. It may be.
Further, the fuse F has been described only in the case where the same layer as the conductor film D is used. However, in the conductor film D, another conductor film is further laminated thereon to lower the resistance value of the entire conductor film D. You may do it. Even in this case, if a conductive film is not laminated on the fuse F, the fusing property of the fuse F will not deteriorate.

FIG. 6 is an electric circuit diagram of the element according to the embodiment of the present invention.
Referring to FIG. 6, element 5 includes reference resistance circuit R8, resistance circuit R64, two resistance circuits R32, resistance circuit R16, resistance circuit R8, resistance circuit R4, resistance circuit R2, resistance circuit R1, and resistance circuit R. / 2, resistor circuit R / 4, resistor circuit R / 8, resistor circuit R / 16, resistor circuit R / 32 are connected in series from the first connection electrode 3 in this order. Each of the reference resistor circuit R8 and the resistor circuits R64 to R2 is configured by connecting in series the same number of resistors R as the last number (“64” in the case of R64). The resistor circuit R1 is composed of one resistor R. Each of the resistance circuits R / 2 to R / 32 is configured by connecting in parallel the same number of resistors R as the last number of itself (“32” in the case of R / 32). The meaning of the number at the end of the resistor circuit is the same in FIGS. 7 and 8 described later.

One fuse F is connected in parallel to each of the resistor circuits R64 to R / 32 other than the reference resistor circuit R8. The fuses F are connected in series directly or via a conductor film D (see FIG. 5A).
In a state where all the fuses F are not blown as shown in FIG. 6, the element 5 is a reference composed of eight resistors R provided in series between the first connection electrode 3 and the second connection electrode 4. A resistor circuit of the resistor circuit R8 is configured. For example, if the resistance value r of one resistor R is r = 8Ω, the chip resistor in which the first connection electrode 3 and the second connection electrode 4 are connected by a resistance circuit (reference resistance circuit R8) of 8r = 64Ω. A container 1 is configured.

  Further, in a state where all the fuses F are not blown, a plurality of types of resistor circuits other than the reference resistor circuit R8 are short-circuited. That is, 12 types and 13 resistor circuits R64 to R / 32 are connected in series to the reference resistor circuit R8, but each resistor circuit is short-circuited by the fuse F connected in parallel. From an electrical viewpoint, each resistance circuit is not incorporated in the element 5.

  In the chip resistor 1 according to this embodiment, the fuse F is selectively blown by, for example, laser light according to a required resistance value. As a result, the resistance circuit in which the fuse F connected in parallel is blown is incorporated in the element 5. Therefore, the entire resistance value of the element 5 can be set to a resistance value in which resistance circuits corresponding to the blown fuse F are connected in series.

  In particular, a plurality of types of resistor circuits have one, two, four, eight, sixteen, thirty-two, etc. resistors R having the same resistance value in series, and a geometric sequence having a common ratio of two. The number of resistors R is increased, and a plurality of types of series resistor circuits and resistors R having the same resistance value are connected in parallel to 2, 4, 8, 16,. A plurality of types of parallel resistance circuits connected to each other by increasing the number of resistors R in a geometric sequence. Therefore, by selectively fusing the fuse F (including the above-described fuse element), the resistance value of the entire element 5 (resistor 56) is adjusted finely and digitally to an arbitrary resistance value. Thus, the chip resistor 1 can generate a desired value of resistance.

FIG. 7 is an electric circuit diagram of an element according to another embodiment of the present invention.
Instead of configuring the element 5 by connecting the reference resistance circuit R8 and the resistance circuit R64 to the resistance circuit R / 32 in series as illustrated in FIG. 6, the element 5 may be configured as illustrated in FIG. Specifically, between the first connection electrode 3 and the second connection electrode 4, the reference resistance circuit R / 16 and the 12 types of resistance circuits R / 16, R / 8, R / 4, R / 2, R1, R2 , R4, R8, R16, R32, R64, and R128 may be used to form the element 5 by a series connection circuit.

  In this case, a fuse F is connected in series to each of the 12 types of resistor circuits other than the reference resistor circuit R / 16. In a state where all the fuses F are not blown, each resistance circuit is electrically incorporated into the element 5. If the fuse F is selectively blown by a laser beam, for example, according to the required resistance value, the resistance circuit corresponding to the blown fuse F (resistance circuit in which the fuse F is connected in series) Therefore, the resistance value of the entire chip resistor 1 can be adjusted.

FIG. 8 is an electric circuit diagram of an element according to still another embodiment of the present invention.
The feature of the element 5 shown in FIG. 8 is that it has a circuit configuration in which a series connection of a plurality of types of resistance circuits and a parallel connection of a plurality of types of resistance circuits are connected in series. As in the previous embodiment, fuses F are connected in parallel to the plurality of types of resistor circuits connected in series, and the plurality of types of resistor circuits connected in series are all short-circuited by fuses F. It is in a state. Therefore, when the fuse F is blown, the resistance circuit short-circuited by the blown fuse F is electrically incorporated into the element 5.

On the other hand, a fuse F is connected in series to each of the plurality of types of resistor circuits connected in parallel. Therefore, by blowing the fuse F, the resistor circuit to which the blown fuse F is connected in series can be electrically disconnected from the parallel connection of the resistor circuit.
With this configuration, for example, a small resistance of 1 kΩ or less is made on the parallel connection side, and if a resistance circuit of 1 kΩ or more is made on the series connection side, a wide range from a small resistance of several Ω to a large resistance of several MΩ is obtained. Resistor circuits can be made using a network of resistors constructed with an equal basic design. In other words, the chip resistor 1 can easily and quickly cope with a plurality of types of resistance values by selecting and cutting one or a plurality of fuses F. In other words, by combining a plurality of resistors R having different resistance values, chip resistors 1 having various resistance values can be realized with a common design.

As described above, in the chip resistor 1, the connection state of the plurality of resistors R (resistance circuit) can be changed in the trimming target region X.
FIG. 9 is a schematic cross-sectional view of a chip resistor.
Next, the chip resistor 1 will be described in more detail with reference to FIG. For convenience of explanation, in FIG. 9, the element 5 described above is shown in a simplified manner, and each element other than the substrate 2 is hatched.

Here, the passivation film 23 and the resin film 24 described above will be described.
The passivation film 23 is made of, for example, SiN (silicon nitride), and has a thickness of 1000 to 5000 mm (here, about 3000 mm). The passivation film 23 is provided over the entire area of each of the element formation surface 2A and the side surfaces 2C to 2F. The passivation film 23 on the element formation surface 2A covers the resistor film 21 and each wiring film 22 (that is, the element 5) on the resistor film 21 from the surface (upper side in FIG. 9). The upper surface of the resistor R is covered. For this reason, the passivation film 23 also covers the wiring film 22 in the trimming target area X described above (see FIG. 5B). Further, the passivation film 23 is in contact with the element 5 (the wiring film 22 and the resistor film 21), and in contact with the insulating layer 20 in a region other than the resistor film 21. Thereby, the passivation film 23 on the element formation surface 2A functions as a protective film that covers the entire element formation surface 2A and protects the element 5 and the insulating layer 20. On the element formation surface 2A, the passivation film 23 prevents a short circuit between the resistors R other than the wiring film 22 (short circuit between adjacent resistor film lines 21A).

  On the other hand, the passivation film 23 provided on each of the side surfaces 2C to 2F functions as a protective layer that protects each of the side surfaces 2C to 2F. The boundary between each of the side surfaces 2C to 2F and the element formation surface 2A is the peripheral edge 85 described above, but the passivation film 23 also covers the boundary (the peripheral edge 85). In the passivation film 23, a portion covering the peripheral edge portion 85 (a portion overlapping the peripheral edge portion 85) is referred to as an end portion 23A. Since the passivation film 23 is an extremely thin film, in this embodiment, the passivation film 23 covering each of the side surfaces 2C to 2F is regarded as a part of the substrate 2. Therefore, the passivation film 23 covering each of the side surfaces 2C to 2F is regarded as the side surfaces 2C to 2F itself.

The resin film 24 protects the element formation surface 2A of the chip resistor 1 together with the passivation film 23, and is made of a resin such as polyimide. The thickness of the resin film 24 is about 5 μm.
The resin film 24 covers the entire surface of the passivation film 23 (including the resistor film 21 and the wiring film 22 covered with the passivation film 23) on the element formation surface 2A. Therefore, the peripheral portion of the resin film 24 coincides with the end portion 23A (the peripheral portion 85 of the element forming surface 2A) of the passivation film 23 in plan view.

  In the resin film 24, one opening 25 is formed at two positions apart in plan view. Each opening 25 is a through hole that continuously penetrates the resin film 24 and the passivation film 23 in the respective thickness directions. Therefore, the opening 25 is formed not only in the resin film 24 but also in the passivation film 23. A part of the wiring film 22 is exposed from each opening 25. A portion of the wiring film 22 exposed from each opening 25 is a pad region 22A for external connection.

Of the two openings 25, one opening 25 is filled with the first connection electrode 3, and the other opening 25 is filled with the second connection electrode 4.
Here, each of the first connection electrode 3 and the second connection electrode 4 has a Ni layer 33, a Pd layer 34, and an Au layer 35 in this order from the element forming surface 2A side. Therefore, the Pd layer 34 is interposed between the Ni layer 33 and the Au layer 35 in each of the first connection electrode 3 and the second connection electrode 4. In each of the first connection electrode 3 and the second connection electrode 4, the Ni layer 33 occupies most of each connection electrode, and the Pd layer 34 and the Au layer 35 are formed much thinner than the Ni layer 33. ing. When the chip resistor 1 is mounted on the mounting substrate 9 (see FIG. 1B), the Ni layer 33 serves to relay the Al of the wiring film 22 in the pad region 22A of each opening 25 and the solder 13 described above. Have.

  Thus, in the 1st connection electrode 3 and the 2nd connection electrode 4, since the surface of the Ni layer 33 is covered with the Au layer 35, it can prevent that the Ni layer 33 is oxidized. In the first connection electrode 3 and the second connection electrode 4, even if a through hole (pinhole) is formed in the Au layer 35 by thinning the Au layer 35, the gap between the Ni layer 33 and the Au layer 35 can be reduced. Since the Pd layer 34 interposed between the two closes the through hole, the Ni layer 33 can be prevented from being exposed to the outside through the through hole and being oxidized.

  In each of the first connection electrode 3 and the second connection electrode 4, the Au layer 35 is exposed on the outermost surface and faces the outside from the opening 25 of the resin film 24. The first connection electrode 3 is electrically connected to the wiring film 22 in the pad region 22 </ b> A in the opening 25 through one opening 25. The second connection electrode 4 is electrically connected to the wiring film 22 in the pad region 22 </ b> A in the opening 25 through the other opening 25. In each of the first connection electrode 3 and the second connection electrode 4, the Ni layer 33 is connected to the pad region 22A. Thereby, each of the first connection electrode 3 and the second connection electrode 4 is electrically connected to the element 5. Here, the wiring film 22 forms wiring connected to each of the group of resistors R (resistor 56), the first connection electrode 3, and the second connection electrode 4.

  As described above, the resin film 24 and the passivation film 23 in which the opening 25 is formed cover the element forming surface 2 </ b> A in a state where the first connection electrode 3 and the second connection electrode 4 are exposed from the opening 25. Therefore, electrical connection between the chip resistor 1 and the mounting substrate 9 can be achieved via the first connection electrode 3 and the second connection electrode 4 protruding from the opening 25 on the surface of the resin film 24 ( (See FIG. 1B).

10A to 10G are schematic sectional views showing a method for manufacturing the chip resistor shown in FIG.
First, as shown in FIG. 10A, a substrate 30 as a base of the substrate 2 is prepared. In this case, the front surface 30A of the substrate 30 is the element formation surface 2A of the substrate 2, and the back surface 30B of the substrate 30 is the back surface 2B of the substrate 2.

Then, the surface 30A of the substrate 30 is thermally oxidized to form the insulating layer 20 made of SiO ₂ or the like on the surface 30A, and the element 5 (the resistor R and the wiring film 22 connected to the resistor R is formed on the insulating layer 20. ). Specifically, first, a resistor film 21 of TiN, TiON, or TiSiON is formed on the entire surface of the insulating layer 20 by sputtering, and further on the resistor film 21 so as to be in contact with the resistor film 21. A wiring film 22 of aluminum (Al) is laminated. Thereafter, using a photolithography process, the resistor film 21 and the wiring film 22 are selectively removed and patterned by dry etching such as RIE (Reactive Ion Etching), for example, as shown in FIG. In a plan view, a configuration is obtained in which the resistor film lines 21A having a certain width on which the resistor films 21 are stacked are arranged in the column direction at regular intervals. At this time, a region in which the resistor film line 21A and the wiring film 22 are partially cut is also formed, and the fuse F and the conductor film D are formed in the above-described trimming target region X (see FIG. 2). Subsequently, the wiring film 22 laminated on the resistor film line 21A is selectively removed by wet etching, for example. As a result, the element 5 having a configuration in which the wiring film 22 is laminated on the resistor film line 21A with a predetermined interval R is obtained. At this time, the resistance value of the entire element 5 may be measured in order to ascertain whether or not the resistor film 21 and the wiring film 22 are formed with target dimensions.

  Referring to FIG. 10A, the elements 5 are formed at a number of locations on the surface 30 </ b> A of the substrate 30 according to the number of chip resistors 1 formed on one substrate 30. When one region where the element 5 (the resistor 56 described above) is formed on the substrate 30 is referred to as a chip component region Y, a plurality of chip component regions Y (that is, the element 5) each having the resistor 56 are formed on the surface 30A of the substrate 30. ) Is formed (set). One chip component region Y coincides with a plan view of one completed chip resistor 1 (see FIG. 9). A region between adjacent chip component regions Y on the surface 30A of the substrate 30 is referred to as a boundary region Z. The boundary region Z has a belt shape and extends in a lattice shape in plan view. One chip component region Y is arranged in one lattice defined by the boundary region Z. Since the width of the boundary region Z is as extremely narrow as 1 μm to 60 μm (for example, 20 μm), a large number of chip component regions Y can be secured on the substrate 30 and, as a result, mass production of the chip resistors 1 becomes possible.

Next, as shown in FIG. 10A, an insulating film 45 made of SiN is formed over the entire surface 30 </ b> A of the substrate 30 by a CVD (Chemical Vapor Deposition) method. The insulating film 45 covers all of the insulating layer 20 and the element 5 (the resistor film 21 and the wiring film 22) on the insulating layer 20, and is in contact with them. Therefore, the insulating film 45 also covers the wiring film 22 in the aforementioned trimming target region X (see FIG. 2). Further, since the insulating film 45 is formed over the entire area of the surface 30A of the substrate 30, it is formed to extend to a region other than the trimming target region X on the surface 30A. Thereby, the insulating film 45 becomes a protective film for protecting the entire surface 30A (including the element 5 on the surface 30A).

Next, as shown in FIG. 10B, a resist pattern 41 is formed over the entire surface 30 </ b> A of the substrate 30 so as to cover the entire insulating film 45. An opening 42 is formed in the resist pattern 41.
FIG. 11 is a schematic plan view of a part of a resist pattern used for forming a groove in the process of FIG. 10B.

  Referring to FIG. 11, the openings 42 of the resist pattern 41 are seen in a plan view when a large number of chip resistors 1 (in other words, the above-described chip component region Y) are arranged in a matrix (also in a lattice shape). It corresponds to (corresponds to) the region between the outlines of the adjacent chip resistors 1 (the hatched portion in FIG. 11, in other words, the boundary region Z). Therefore, the entire shape of the opening 42 is a lattice shape having a plurality of linear portions 42A and 42B orthogonal to each other. Further, on the side that divides the straight portions 42A and 42B, the unevenness 14 that coincides with the unevenness 12 of the chip resistor 1 is formed.

In the resist pattern 41, the straight portions 42A and 42B orthogonal to each other in the opening 42 are connected to each other while maintaining a state orthogonal to each other (without bending). Therefore, the intersecting portion 43 of the straight portions 42A and 42B is pointed so as to form approximately 90 ° in plan view.
Referring to FIG. 10B, each of insulating film 45, insulating layer 20, and substrate 30 is selectively removed by plasma etching using resist pattern 41 as a mask. As a result, the material of the substrate 30 is removed in the boundary region Z between the adjacent elements 5 (chip component region Y). As a result, a position (boundary region Z) coinciding with the opening 42 of the resist pattern 41 in plan view passes through the insulating film 45 and the insulating layer 20 and reaches the middle of the thickness of the substrate 30 from the surface 30A of the substrate 30. A groove 44 having a predetermined depth is formed. The groove 44 is defined by a pair of side walls 44A facing each other and a bottom wall 44B connecting the lower ends of the pair of side walls 44A (the end on the back surface 30B side of the substrate 30). The depth of the groove 44 with respect to the surface 30A of the substrate 30 is about 100 μm, and the width of the groove 44 (interval between the opposing side walls 44A) is about 20 μm, which is constant over the entire depth direction.

  The overall shape of the groove 44 in the substrate 30 is a lattice shape that coincides with the opening 42 (see FIG. 11) of the resist pattern 41 in plan view. On the surface 30A of the substrate 30, a rectangular frame portion (boundary region Z) in the groove 44 surrounds the chip component region Y where each element 5 is formed. A portion where the element 5 is formed on the substrate 30 is a semi-finished product 50 of the chip resistor 1. On the surface 30 </ b> A of the substrate 30, the semi-finished products 50 are located one by one in the chip component region Y surrounded by the grooves 44, and these semi-finished products 50 are arranged in a matrix. By forming the grooves 44 in this way, the substrate 30 is separated into the substrates 2 for each of the plurality of chip component regions Y.

In this step, since the grooves 44 that partition each chip resistor 1 are formed by plasma etching, unlike the case where a dicing saw is used, the irregularities 12 are easily formed on the surfaces to be the side surfaces 2C to 2F of the substrate 2. Can do.
After the groove 44 is formed as shown in FIG. 10B, the resist pattern 41 is removed, and the insulating film 45 is selectively removed by etching using the mask 65 as shown in FIG. 10C. In the mask 65, an opening 66 is formed in a portion of the insulating film 45 that coincides with each pad region 22A (see FIG. 9) in plan view. Thereby, a portion corresponding to the opening 66 in the insulating film 45 is removed by etching, and the opening 25 is formed in the portion. Thus, the insulating film 45 is formed so as to expose each pad region 22A in the opening 25. Two openings 25 are formed for one semi-finished product 50.

  In each semi-finished product 50, after two openings 25 are formed in the insulating film 45, a probe 70 of a resistance measuring device (not shown) is brought into contact with the pad region 22 </ b> A of each opening 25, so that the entire resistance value of the element 5 is obtained. Is detected. Then, by irradiating a laser beam (not shown) through the insulating film 45 to an arbitrary fuse F (see FIG. 2), the wiring film 22 in the trimming target region X is trimmed with the laser beam, and the fuse F is melted. In this way, by fusing (trimming) the fuse F so as to have a required resistance value, the resistance value of the entire semi-finished product 50 (in other words, the chip resistor 1) can be adjusted as described above. At this time, since the insulating film 45 is a cover film covering the element 5, it is possible to prevent debris and the like generated during fusing from adhering to the element 5 and causing a short circuit. Further, since the insulating film 45 covers the fuse F (resistor film 21), the energy of the laser beam can be stored in the fuse F, so that the fuse F can be surely blown.

  Thereafter, SiN is formed on the insulating film 45 by CVD, and the insulating film 45 is thickened. At this time, as shown in FIG. 10D, the insulating film 45 is also formed over the entire inner peripheral surface of the groove 44 (the above-described section screen 44C of the side wall 44A and the upper surface of the bottom wall 44B). The final insulating film 45 (the state shown in FIG. 10D) has a thickness of 1000 to 5000 mm (here, about 3000 mm). At this time, a part of the insulating film 45 enters each opening 25 and closes the opening 25.

  Thereafter, a liquid of photosensitive resin made of polyimide is spray-applied onto the substrate 30 from above the insulating film 45 to form a resin film 46 of photosensitive resin as shown in FIG. 10D. At this time, the liquid is applied to the substrate 30 through a mask (not shown) having a pattern that covers only the groove 44 in plan view so that the liquid does not enter the groove 44. As a result, the liquid photosensitive resin is formed only on the substrate 30 and becomes the resin film 46 on the substrate 30. The surface of the resin film 46 on the surface 30A is flat along the surface 30A.

Since the liquid does not enter the groove 44, the resin film 46 is not formed in the groove 44. In addition to spraying the photosensitive resin liquid, the resin film 46 may be formed by spin-coating the liquid or attaching a sheet made of the photosensitive resin to the surface 30A of the substrate 30. Good.
Next, the resin film 46 is subjected to heat treatment (curing treatment). Thereby, the thickness of the resin film 46 is thermally contracted, and the resin film 46 is cured and the film quality is stabilized.

  Next, as shown in FIG. 10E, the resin film 46 is patterned, and portions of the resin film 46 on the surface 30A that coincide with the pad regions 22A (openings 25) of the wiring film 22 in plan view are selectively removed. . Specifically, the resin film 46 is exposed and developed with the pattern 62 using a mask 62 in which openings 61 having a pattern that matches (matches) with each pad region 22A in a plan view. Thereby, the resin film 46 is separated above each pad region 22A. Next, the insulating film 45 on each pad region 22A is removed by RIE using a mask (not shown), whereby each opening 25 is opened and the pad region 22A is exposed.

Next, by forming an Ni / Pd / Au laminated film formed by laminating Ni, Pd and Au on the pad region 22A in each opening 25 by electroless plating, as shown in FIG. The first connection electrode 3 and the second connection electrode 4 are formed on the pad region 22A.
FIG. 12 is a diagram for explaining a manufacturing process of the first connection electrode and the second connection electrode.

  Specifically, referring to FIG. 12, first, the surface of pad region 22A is purified to remove (degrease) organic matter (including smut such as carbon stains and oily grease) on the surface. (Step S1). Next, the oxide film on the surface is removed (step S2). Next, a zincate process is performed on the surface, and Al (of the wiring film 22) on the surface is replaced with Zn (step S3). Next, Zn on the surface is stripped with nitric acid or the like, and new Al is exposed in the pad region 22A (step S4).

Next, Ni plating is performed on the surface of new Al in the pad region 22A by immersing the pad region 22A in a plating solution. Thereby, Ni in the plating solution is chemically reduced and deposited, and the Ni layer 33 is formed on the surface (step S5).
Next, Pd plating is performed on the surface of the Ni layer 33 by immersing the Ni layer 33 in another plating solution. Thereby, Pd in the plating solution is chemically reduced and deposited, and a Pd layer 34 is formed on the surface of the Ni layer 33 (step S6).

  Next, by immersing the Pd layer 34 in another plating solution, the surface of the Pd layer 34 is subjected to Au plating. Thereby, Au in the plating solution is chemically reduced and deposited, and an Au layer 35 is formed on the surface of the Pd layer 34 (step S7). As a result, the first connection electrode 3 and the second connection electrode 4 are formed, and when the first connection electrode 3 and the second connection electrode 4 are dried (step S8), the first connection electrode 3 and the second connection electrode are formed. The manufacturing process of the electrode 4 is completed. In addition, the process of wash | cleaning the semi-finished product 50 with water is suitably implemented between the steps which follow. In addition, the zincate process may be performed a plurality of times.

FIG. 10F shows a state after the first connection electrode 3 and the second connection electrode 4 are formed in each semi-finished product 50.
As described above, since the first connection electrode 3 and the second connection electrode 4 are formed by electroless plating, the first connection is compared with the case where the first connection electrode 3 and the second connection electrode 4 are formed by electrolytic plating. The productivity of the chip resistor 1 can be improved by reducing the number of steps of forming the electrode 3 and the second connection electrode 4 (for example, a lithography step required for electrolytic plating, a resist mask peeling step, etc.). Further, in the case of electroless plating, since a resist mask required for electrolytic plating is unnecessary, there is a shift in the formation positions of the first connection electrode 3 and the second connection electrode 4 due to a shift in the position of the resist mask. Since it does not occur, the formation position accuracy of the first connection electrode 3 and the second connection electrode 4 can be improved, and the yield can be improved.

After the first connection electrode 3 and the second connection electrode 4 are formed in this way, the current supply inspection is performed between the first connection electrode 3 and the second connection electrode 4, and then the substrate 30 is ground from the back surface 30B. The
Specifically, after forming the groove 44, as shown in FIG. 10G, a support tape 71 having a thin plate shape made of PET (polyethylene terephthalate) and having an adhesive surface 72 is formed on each of the semi-finished products 50 on the adhesive surface 72. Are attached to the first connection electrode 3 and the second connection electrode 4 side (that is, the surface 30A). Thereby, each semi-finished product 50 is supported by the support tape 71. Here, for example, a laminate tape can be used as the support tape 71.

  With each semi-finished product 50 supported by the support tape 71, the substrate 30 is ground from the back surface 30B side. When the substrate 30 is thinned by grinding until the upper surface of the bottom wall 44B (see FIG. 10F) of the groove 44 is reached, there is no connection between the adjacent semi-finished products 50, so the substrate 30 is divided at the groove 44 as a boundary. Then, the semi-finished products 50 are individually separated to be a finished product of the chip resistor 1. That is, the substrate 30 is cut (divided) in the groove 44 (in other words, the boundary region Z), whereby the individual chip resistors 1 are cut out. The chip resistor 1 may be cut out by etching the substrate 30 from the back surface 30B side to the bottom wall 44B of the groove 44.

  In each completed chip resistor 1, the portion that formed the section screen 44 </ b> C of the side wall 44 </ b> A of the groove 44 becomes one of the side surfaces 2 </ b> C to 2 </ b> F of the substrate 2, and the back surface 30 </ b> B becomes the back surface 2 </ b> B. That is, as described above, the step of forming the groove 44 by etching (see FIG. 10B) is included in the step of forming the side surfaces 2C to 2F. Further, the insulating film 45 becomes the passivation film 23, and the separated resin film 46 becomes the resin film 24.

  As described above, if the substrate 30 is ground from the back surface 30B side after the groove 44 is formed, a plurality of chip component regions Y formed on the substrate 30 are divided into individual chip resistors 1 (chip components) all at once. (A plurality of chip resistors 1 can be obtained at a time). Therefore, the productivity of the chip resistor 1 can be improved by shortening the manufacturing time of the plurality of chip resistors 1.

In addition, the back surface 2B of the substrate 2 in the completed chip resistor 1 may be mirror-finished by polishing or etching to clean the back surface 2B.
As mentioned above, although embodiment of this invention has been described, this invention can also be implemented with another form. For example, as an example of the chip component of the present invention, the chip resistor 1 is disclosed in the above-described embodiment, but the present invention can also be applied to a chip component such as a chip capacitor, a chip diode, or a chip inductor. Below, a chip capacitor is explained.

FIG. 13 is a plan view of a chip capacitor according to another embodiment of the present invention. FIG. 14 is a cross-sectional view taken along section line XIV-XIV in FIG. FIG. 15 is an exploded perspective view showing a part of the structure of the chip capacitor separately.
In the chip capacitor 101 to be described below, portions corresponding to the portions described in the above-described chip resistor 1 are denoted by the same reference numerals, and detailed description thereof is omitted. In the chip capacitor 101, a part denoted by the same reference numeral as that described for the chip resistor 1 has the same configuration as the part described for the chip resistor 1 unless otherwise specified. The same operation effect as the part demonstrated by 1 can be show | played.

  Referring to FIG. 13, similarly to the chip resistor 1, the chip capacitor 101 includes the substrate 2, the first connection electrode 3 disposed on the substrate 2 (on the element formation surface 2 </ b> A side), and the substrate 2 and the 2nd connection electrode 4 arrange | positioned. In this embodiment, the substrate 2 has a rectangular shape in plan view. The first connection electrode 3 and the second connection electrode 4 are respectively disposed at both ends in the longitudinal direction of the substrate 2. In this embodiment, the first connection electrode 3 and the second connection electrode 4 have a substantially rectangular planar shape extending in the short direction of the substrate 2. In the chip capacitor 101, similarly to the chip resistor 1, the first connection electrode 3 and the second connection electrode 4 are arranged on the element formation surface 2 </ b> A of the substrate 2 at a distance from the peripheral edge 85. Therefore, in the circuit assembly 100 (see FIG. 1B) in which the chip capacitor 101 is mounted on the mounting substrate 9, the chip capacitor 101 can be mounted on the mounting substrate 9 with a small mounting area as in the case of the chip resistor 1. it can. That is, the chip capacitor 101 can be mounted on the mounting substrate 9 with a small mounting area.

  A plurality of capacitor elements C <b> 1 to C <b> 9 are formed on the element formation surface 2 </ b> A of the substrate 2 in the capacitor arrangement region 105 between the first connection electrode 3 and the second connection electrode 4. The plurality of capacitor elements C <b> 1 to C <b> 9 are a plurality of element elements constituting the element 5 (capacitor element here) described above, and are connected between the first connection electrode 3 and the second connection electrode 4. Specifically, the plurality of capacitor elements C1 to C9 are electrically connected to each other through the plurality of fuse units 107 (corresponding to the above-described fuse F) so as to be separable from the second connection electrode 4. Yes.

  As shown in FIGS. 14 and 15, the insulating layer 20 is formed on the element formation surface 2 </ b> A of the substrate 2, and the lower electrode film 111 is formed on the surface of the insulating layer 20. The lower electrode film 111 extends over almost the entire capacitor arrangement region 105. Further, the lower electrode film 111 is formed to extend to a region immediately below the first connection electrode 3. More specifically, the lower electrode film 111 includes a capacitor electrode region 111 </ b> A that functions as a common lower electrode of the capacitor elements C <b> 1 to C <b> 9 in the capacitor arrangement region 105, and an external electrode lead disposed immediately below the first connection electrode 3. And a pad region 111B. The capacitor electrode region 111 </ b> A is located in the capacitor arrangement region 105, and the pad region 111 </ b> B is located immediately below the first connection electrode 3 and is in contact with the first connection electrode 3.

  A capacitor film (dielectric film) 112 is formed in the capacitor arrangement region 105 so as to cover and contact the lower electrode film 111 (capacitor electrode region 111A). The capacitive film 112 is formed over the entire capacitor electrode region 111A (capacitor placement region 105). In this embodiment, the capacitor film 112 further covers the insulating layer 20 outside the capacitor arrangement region 105.

  An upper electrode film 113 is formed on the capacitance film 112. In FIG. 13, for clarity, the upper electrode film 113 is shown in a colored manner. The upper electrode film 113 includes a capacitor electrode region 113A located in the capacitor arrangement region 105, a pad region 113B located immediately below the second connection electrode 4 and in contact with the second connection electrode 4, and the capacitor electrode region 113A and the pad region. 113B and a fuse region 113C disposed between them.

  In the capacitor electrode region 113A, the upper electrode film 113 is divided (separated) into a plurality of electrode film portions (upper electrode film portions) 131 to 139. In this embodiment, each of the electrode film portions 131 to 139 is formed in a rectangular shape, and extends in a strip shape from the fuse region 113 </ b> C toward the first connection electrode 3. The plurality of electrode film portions 131 to 139 are opposed to the lower electrode film 111 with a plurality of types of facing areas sandwiching the capacitor film 112 (in contact with the capacitor film 112). More specifically, the facing area of the electrode film portions 131 to 139 with respect to the lower electrode film 111 may be determined to be 1: 2: 4: 8: 16: 32: 64: 128: 128. That is, the plurality of electrode film portions 131 to 139 include a plurality of electrode film portions having different facing areas, and more specifically, a plurality of electrode film portions having a facing area set so as to form a geometric sequence with a common ratio of 2. The electrode film portions 131 to 138 (or 131 to 137, 139) are included. Accordingly, the plurality of capacitor elements C1 to C9 configured by the electrode film portions 131 to 139 and the lower electrode film 111 facing each other with the capacitor film 112 interposed therebetween include a plurality of capacitor elements having different capacitance values. . When the ratio of the facing areas of the electrode film portions 131 to 139 is as described above, the ratio of the capacitance values of the capacitor elements C1 to C9 is equal to the ratio of the facing areas, and is 1: 2: 4: 8: 16: 32. : 64: 128: 128. That is, the plurality of capacitor elements C1 to C9 include a plurality of capacitor elements C1 to C8 (or C1 to C7, C9) having capacitance values set so as to form a geometric sequence with a common ratio of 2.

  In this embodiment, the electrode film portions 131 to 135 are formed in a strip shape having the same width and a length ratio of 1: 2: 4: 8: 16. The electrode film portions 135, 136, 137, 138, and 139 are formed in a strip shape having the same length and the width ratio set to 1: 2: 4: 8: 8. The electrode film portions 135 to 139 are formed to extend over a range from the edge on the second connection electrode 4 side of the capacitor arrangement region 105 to the edge on the first connection electrode 3 side, and the electrode film portions 131 to 134 are formed. , Shorter than that.

The pad region 113B is formed substantially similar to the second connection electrode 4 and has a substantially rectangular planar shape. As shown in FIG. 14, the upper electrode film 113 in the pad region 113 </ b> B is in contact with the second connection electrode 4.
The fuse region 113 </ b> C is disposed on the substrate 2 along one long side of the pad region 113 </ b> B (long side on the inner side with respect to the periphery of the substrate 2). The fuse region 113C includes a plurality of fuse units 107 arranged along the one long side of the pad region 113B.

  The fuse unit 107 is integrally formed of the same material as that of the pad region 113B of the upper electrode film 113. The plurality of electrode film portions 131 to 139 are integrally formed with one or a plurality of fuse units 107, and are connected to the pad region 113B via the fuse units 107, and the pad regions 113B are connected to the electrode film portions 131 to 139. The second connection electrode 4 is electrically connected. As shown in FIG. 13, the electrode film portions 131 to 136 having a relatively small area are connected to the pad region 113B by one fuse unit 107, and the electrode film portions 137 to 139 having a relatively large area include a plurality of electrode film portions 137 to 139. It is connected to the pad region 113B through the fuse unit 107. Not all fuse units 107 need be used, and in this embodiment, some fuse units 107 are unused.

  The fuse unit 107 includes a first wide portion 107A for connection to the pad region 113B, a second wide portion 107B for connection to the electrode film portions 131 to 139, and the first and second wide portions 107A and 7B. And a narrow portion 107 </ b> C that connects the two. The narrow portion 107C is configured to be cut (fused) by laser light. Accordingly, unnecessary electrode film portions of the electrode film portions 131 to 139 can be electrically disconnected from the first and second connection electrodes 3 and 4 by cutting the fuse unit 107.

  Although not shown in FIGS. 13 and 15, as shown in FIG. 14, the surface of the chip capacitor 101 including the surface of the upper electrode film 113 is covered with the passivation film 23 described above. The passivation film 23 is made of, for example, a nitride film, and extends not only to the upper surface of the chip capacitor 101 but also to the side surfaces 2C to 2F of the substrate 2 so as to cover the entire side surfaces 2C to 2F. Further, the above-described resin film 24 is formed on the passivation film 23. The resin film 24 covers the element formation surface 2A.

  The passivation film 23 and the resin film 24 are protective films that protect the surface of the chip capacitor 101. In these, the openings 25 described above are formed in regions corresponding to the first connection electrode 3 and the second connection electrode 4, respectively. The openings 25 respectively penetrate the passivation film 23 and the resin film 24 so as to expose a part of the pad region 111B of the lower electrode film 111 and a part of the pad region 113B of the upper electrode film 113. Furthermore, in this embodiment, the opening 25 corresponding to the first connection electrode 3 also penetrates the capacitive film 112.

  In the opening 25, the first connection electrode 3 and the second connection electrode 4 are embedded. Accordingly, the first connection electrode 3 is bonded to the pad region 111B of the lower electrode film 111, and the second connection electrode 4 is bonded to the pad region 113B of the upper electrode film 113. The first and second connection electrodes 3 and 4 are formed so as to protrude from the surface of the resin film 24. Thereby, the chip capacitor 101 can be flip-chip bonded to the mounting substrate.

FIG. 16 is a circuit diagram showing an internal electrical configuration of the chip capacitor. A plurality of capacitor elements C1 to C9 are connected in parallel between the first connection electrode 3 and the second connection electrode 4. Between each of the capacitor elements C1 to C9 and the second connection electrode 4, fuses F1 to F9 each composed of one or a plurality of fuse units 107 are interposed in series.
When all the fuses F1 to F9 are connected, the capacitance value of the chip capacitor 101 is equal to the sum of the capacitance values of the capacitor elements C1 to C9. When one or more fuses selected from the plurality of fuses F1 to F9 are disconnected, the capacitor element corresponding to the disconnected fuse is disconnected, and the capacitance of the chip capacitor 101 is equal to the capacitance value of the disconnected capacitor element. The value decreases.

  Therefore, the capacitance value between the pad regions 111B and 113B (total capacitance value of the capacitor elements C1 to C9) is measured, and then one or more appropriately selected from the fuses F1 to F9 according to the desired capacitance value. If the fuse is blown with a laser beam, adjustment to a desired capacitance value (laser trimming) can be performed. In particular, if the capacitance values of the capacitor elements C1 to C8 are set to form a geometric sequence with a common ratio of 2, the capacitor element C1 having the minimum capacitance value (the value of the first term of the geometric sequence). Fine adjustment is possible to match the target capacitance value with accuracy corresponding to the capacitance value.

For example, the capacitance values of the capacitor elements C1 to C9 may be determined as follows.
C1 = 0.03125pF
C2 = 0.0625pF
C3 = 0.125pF
C4 = 0.25pF
C5 = 0.5pF
C6 = 1pF
C7 = 2pF
C8 = 4pF
C9 = 4pF
In this case, the capacitance of the chip capacitor 101 can be finely adjusted with a minimum fitting accuracy of 0.03125 pF. Further, by appropriately selecting a fuse to be cut from the fuses F1 to F9, it is possible to provide the chip capacitor 101 having an arbitrary capacitance value between 10 pF and 18 pF.

  As described above, according to this embodiment, a plurality of capacitor elements C1 to C9 that can be separated by the fuses F1 to F9 are provided between the first connection electrode 3 and the second connection electrode 4. Capacitor elements C1 to C9 include a plurality of capacitor elements having different capacitance values, more specifically, a plurality of capacitor elements having capacitance values set so as to form a geometric sequence. As a result, by selecting one or more fuses from the fuses F1 to F9 and fusing them with laser light, it is possible to cope with a plurality of types of capacitance values without changing the design and accurately match the desired capacitance values. The chip capacitor 101 that can be embedded can be realized with a common design.

Details of each part of the chip capacitor 101 will be described below.
Referring to FIG. 13, substrate 2 has a rectangular shape such as 0.3 mm × 0.15 mm or 0.4 mm × 0.2 mm in plan view (preferably a size of 0.4 mm × 0.2 mm or less). You may have. Capacitor arrangement region 105 is generally a square region having one side corresponding to the length of the short side of substrate 2. The thickness of the substrate 2 may be about 150 μm. Referring to FIG. 14, substrate 2 may be, for example, a substrate that has been thinned by grinding or polishing from the back side (the surface on which capacitor elements C1 to C9 are not formed). As a material of the substrate 2, a semiconductor substrate typified by a silicon substrate may be used, a glass substrate may be used, or a resin film may be used.

The insulating layer 20 may be an oxide film such as a silicon oxide film. The film thickness may be about 500 to 2000 mm.
The lower electrode film 111 is preferably a conductive film, particularly a metal film, and may be, for example, an aluminum film. The lower electrode film 111 made of an aluminum film can be formed by sputtering. Similarly, the upper electrode film 113 is preferably composed of a conductive film, particularly a metal film, and may be an aluminum film. The upper electrode film 113 made of an aluminum film can be formed by sputtering. Patterning for dividing the capacitor electrode region 113A of the upper electrode film 113 into electrode film portions 131 to 139 and shaping the fuse region 113C into a plurality of fuse units 107 can be performed by photolithography and etching processes.

The capacitor film 112 can be made of, for example, a silicon nitride film, and can have a thickness of 500 to 2000 mm (for example, 1000 mm). The capacitor film 112 may be a silicon nitride film formed by plasma CVD (chemical vapor deposition).
The passivation film 23 can be made of, for example, a silicon nitride film, and can be formed by, for example, a plasma CVD method. The film thickness may be about 8000 mm. As described above, the resin film 24 can be composed of a polyimide film or other resin film.

  The first and second connection electrodes 3 and 4 include, for example, a nickel layer in contact with the lower electrode film 111 or the upper electrode film 113, a palladium layer stacked on the nickel layer, and a gold layer stacked on the palladium layer. For example, it can be formed by a plating method (more specifically, an electroless plating method). The nickel layer contributes to improving the adhesion to the lower electrode film 111 or the upper electrode film 113, and the palladium layer is made of the material of the upper electrode film or the lower electrode film and the gold of the uppermost layer of the first and second connection electrodes 3 and 4. It functions as a diffusion preventing layer that suppresses mutual diffusion.

The manufacturing process of such a chip capacitor 101 is the same as the manufacturing process of the chip resistor 1 after the element 5 is formed.
When the element 5 (capacitor element) is formed in the chip capacitor 101, first, an oxide film (for example, a silicon oxide film) is formed on the surface of the substrate 30 (substrate 2) described above by a thermal oxidation method and / or a CVD method. An insulating layer 20 is formed. Next, the lower electrode film 111 made of an aluminum film is formed over the entire surface of the insulating layer 20 by, for example, sputtering. The thickness of the lower electrode film 111 may be about 8000 mm. Next, a resist pattern corresponding to the final shape of the lower electrode film 111 is formed on the surface of the lower electrode film by photolithography. By using this resist pattern as a mask, the lower electrode film is etched to obtain the lower electrode film 111 having the pattern shown in FIG. Etching of the lower electrode film 111 can be performed by, for example, reactive ion etching.

  Next, a capacitor film 112 made of a silicon nitride film or the like is formed on the lower electrode film 111 by, for example, plasma CVD. In the region where the lower electrode film 111 is not formed, the capacitor film 112 is formed on the surface of the insulating layer 20. Next, the upper electrode film 113 is formed on the capacitor film 112. The upper electrode film 113 is made of, for example, an aluminum film and can be formed by a sputtering method. The film thickness may be about 8000 mm. Next, a resist pattern corresponding to the final shape of the upper electrode film 113 is formed on the surface of the upper electrode film 113 by photolithography. By etching using the resist pattern as a mask, the upper electrode film 113 is patterned into a final shape (see FIG. 13 and the like). Accordingly, the upper electrode film 113 has a portion divided into a plurality of electrode film portions 131 to 139 in the capacitor electrode region 113A, and has a plurality of fuse units 107 in the fuse region 113C. A pattern having the connected pad region 113B is shaped. Etching for patterning the upper electrode film 113 may be performed by wet etching using an etchant such as phosphoric acid or by reactive ion etching.

  Thus, the element 5 (capacitor elements C1 to C9 and the fuse unit 107) in the chip capacitor 101 is formed. After the element 5 is formed, an insulating film 45 is formed by plasma CVD so as to cover the element 5 (the upper electrode film 113 and the capacitor film 112 in the region where the upper electrode film 113 is not formed) (FIG. 10A). Thereafter, after the groove 44 is formed (see FIG. 10B), the opening 25 is formed (see FIG. 10C). Then, the probe 70 is pressed against the pad region 113B of the upper electrode film 113 and the pad region 111B of the lower electrode film 111 exposed from the opening 25, and the total capacitance values of the plurality of capacitor elements C1 to C9 are measured ( (See FIG. 10C). Based on the measured total capacitance value, the capacitor element to be disconnected, that is, the fuse to be disconnected, is selected according to the target capacitance value of the chip capacitor 101.

  From this state, laser trimming for fusing the fuse unit 107 is performed. That is, a laser beam is applied to the fuse unit 107 constituting the fuse selected according to the measurement result of the total capacity value, and the narrow portion 107C (see FIG. 13) of the fuse unit 107 is melted. As a result, the corresponding capacitor element is separated from the pad region 113B. When the laser light is applied to the fuse unit 107, the energy of the laser light is accumulated in the vicinity of the fuse unit 107 by the action of the insulating film 45 which is a cover film, and thereby the fuse unit 107 is melted. Thereby, the capacitance value of the chip capacitor 101 can be reliably set to the target capacitance value.

  Next, a silicon nitride film is deposited on the cover film (insulating film 45) by plasma CVD, for example, and a passivation film 23 is formed. In the final form, the above-described cover film is integrated with the passivation film 23 and constitutes a part of the passivation film 23. The passivation film 23 formed after the fuse is cut enters into the opening of the cover film destroyed at the same time when the fuse is blown, and covers and protects the cut surface of the fuse unit 107. Therefore, the passivation film 23 prevents foreign matter from entering the cut portion of the fuse unit 107 and moisture from entering. Thereby, the highly reliable chip capacitor 101 can be manufactured. The passivation film 23 may be formed so as to have a film thickness of about 8000 mm as a whole.

Next, the resin film 46 described above is formed (see FIG. 10D). Thereafter, the opening 25 closed by the resin film 46 and the passivation film 23 is opened (see FIG. 10E), and the first connection electrode 3 and the second connection electrode 4 are formed in the opening 25 by, for example, electroless plating. Grown (see FIG. 10F).
Thereafter, as in the case of the chip resistor 1, when the substrate 30 is ground from the back surface 30B (see FIG. 10G), the individual pieces of the chip capacitor 101 can be cut out.

  In the patterning of the upper electrode film 113 using the photolithography process, the electrode film portions 131 to 139 having a small area can be formed with high accuracy, and the fuse unit 107 having a fine pattern can be formed. Then, after patterning the upper electrode film 113, the fuse to be cut is determined through measurement of the total capacitance value. By cutting the determined fuse, it is possible to obtain the chip capacitor 101 accurately adjusted to the desired capacitance value.

Although the chip components (chip resistor 1 and chip capacitor 101) of the present invention have been described above, the present invention can be implemented in other forms.
For example, in the above-described embodiment, in the case of the chip resistor 1, the plurality of resistor circuits have a plurality of resistor circuits having resistance values forming a series of geometric ratios with a common ratio r (0 <r, r ≠ 1) = 2. However, the common ratio of the geometric sequence may be a number other than two. Also, in the case of the chip capacitor 101, an example in which the capacitor element has a plurality of capacitor elements having capacitance values forming a geometric sequence of a common ratio r (0 <r, r ≠ 1) = 2 is shown. However, the common ratio of the geometric sequence may be a number other than two.

In the chip resistor 1 and the chip capacitor 101, the insulating layer 20 is formed on the surface of the substrate 2. However, if the substrate 2 is an insulating substrate, the insulating layer 20 can be omitted.
In the chip capacitor 101, only the upper electrode film 113 is divided into a plurality of electrode film portions. However, only the lower electrode film 111 is divided into a plurality of electrode film portions, or the upper electrode film 113 is divided. Both the lower electrode film 111 and the lower electrode film 111 may be divided into a plurality of electrode film portions. Furthermore, in the above-described embodiment, an example in which the upper electrode film or the lower electrode film and the fuse unit are integrated is shown. However, the fuse unit is formed of a conductor film different from the upper electrode film or the lower electrode film. May be. In the above-described chip capacitor 101, a single-layer capacitor structure having the upper electrode film 113 and the lower electrode film 111 is formed. Another electrode film is laminated on the upper electrode film 113 through a capacitive film. Thus, a plurality of capacitor structures may be stacked.

In the chip capacitor 101, a conductive substrate may be used as the substrate 2, the conductive substrate may be used as a lower electrode, and the capacitor film 112 may be formed in contact with the surface of the conductive substrate. In this case, one external electrode may be drawn from the back surface of the conductive substrate.
When the present invention is applied to a chip inductor, the element 5 formed on the substrate 2 in the chip inductor includes an inductor element including a plurality of inductor elements (element elements), and the first connection electrode 3 and the second connection electrode 4. The element 5 is provided in the multilayer wiring of the multilayer substrate described above, and is formed by the wiring film 22. In the chip inductor, the plurality of fuses F described above are provided on the substrate 2, and each inductor element can be separated from the first connection electrode 3 and the second connection electrode 4 via the fuse F. It is connected to the.

In this case, in the chip inductor, a combination pattern of a plurality of inductor elements can be changed to an arbitrary pattern by selecting and cutting one or a plurality of fuses F. Therefore, chip inductors having various electrical characteristics can be obtained. Can be realized with a common design.
When the present invention is applied to a chip diode, the element 5 formed on the substrate 2 in the chip diode includes a diode network (diode element) including a plurality of diode elements (element elements). . The diode element is formed on the substrate 2. In this chip diode, by selecting and cutting one or a plurality of fuses F, a combination pattern of a plurality of diode elements in the diode network can be changed to an arbitrary pattern. However, various chip diodes can be realized with a common design.

In any of the chip inductor and the chip diode, the same effects as those of the chip resistor 1 and the chip capacitor 101 can be obtained.
Further, in the first connection electrode 3 and the second connection electrode 4 described above, the Pd layer 34 interposed between the Ni layer 33 and the Au layer 35 can be omitted. Since the adhesion between the Ni layer 33 and the Au layer 35 is good, the Pd layer 34 may be omitted if the above-described pinhole cannot be formed in the Au layer 35.

  FIG. 17 is a perspective view showing an appearance of a smartphone which is an example of an electronic device in which the chip component of the present invention is used. The smartphone 201 is configured by housing electronic components in a flat rectangular parallelepiped casing 202. The housing 202 has a pair of rectangular main surfaces on the front side and the back side, and the pair of main surfaces are joined by four side surfaces. On one main surface of the housing 202, the display surface of the display panel 203 configured by a liquid crystal panel, an organic EL panel, or the like is exposed. The display surface of the display panel 203 forms a touch panel and provides an input interface for the user.

  The display panel 203 is formed in a rectangular shape that occupies most of one main surface of the housing 202. Operation buttons 204 are arranged along one short side of the display panel 203. In this embodiment, a plurality (three) of operation buttons 204 are arranged along the short side of the display panel 203. The user can operate the smartphone 201 by operating the operation buttons 204 and the touch panel, and call and execute necessary functions.

  A speaker 205 is arranged in the vicinity of another short side of the display panel 203. The speaker 205 provides an earpiece for a telephone function and is also used as an acoustic unit for reproducing music data and the like. On the other hand, a microphone 206 is disposed on one side surface of the housing 202 near the operation button 204. The microphone 206 can be used as a recording microphone in addition to providing a mouthpiece for a telephone function.

  FIG. 18 is a schematic plan view showing the configuration of the circuit assembly 100 housed in the housing 202. The circuit assembly 100 includes the above-described mounting board 9 (which may be the above-described multilayer board) and circuit components mounted on the mounting surface 9A of the mounting board 9. The plurality of circuit components include a plurality of integrated circuit elements (ICs) 212-220 and a plurality of chip components. The plurality of ICs include a transmission processing IC 212, a one-segment TV reception IC 213, a GPS reception IC 214, an FM tuner IC 215, a power supply IC 216, a flash memory 217, a microcomputer 218, a power supply IC 219, and a baseband IC 220. The plurality of chip components (corresponding to the chip components of the present invention) include chip inductors 221, 225, 235, chip resistors 222, 224, 233, chip capacitors 227, 230, 234, and chip diodes 228, 231.

The transmission processing IC 212 includes an electronic circuit that generates a display control signal for the display panel 203 and receives an input signal from a touch panel on the surface of the display panel 203. A flexible wiring 209 is connected to the transmission processing IC 212 for connection with the display panel 203.
The one-segment TV reception IC 213 incorporates an electronic circuit that constitutes a receiver for receiving radio waves of one-segment broadcasting (terrestrial digital television broadcasting whose reception target is a portable device). In the vicinity of the one-segment TV reception IC 213, a plurality of chip inductors 221 and a plurality of chip resistors 222 are arranged. The one-segment TV reception IC 213, the chip inductor 221 and the chip resistor 222 constitute a one-segment broadcast reception circuit 223. The chip inductor 221 and the chip resistor 222 respectively have an inductance and a resistance that are accurately matched, and give a highly accurate circuit constant to the one-segment broadcasting reception circuit 223.

The GPS reception IC 214 contains an electronic circuit that receives radio waves from GPS satellites and outputs position information of the smartphone 201.
The FM tuner IC 215 constitutes an FM broadcast receiving circuit 226 together with a plurality of chip resistors 224 and a plurality of chip inductors 225 mounted on the mounting substrate 9 in the vicinity thereof. The chip resistor 224 and the chip inductor 225 each have a resistance value and an inductance that are accurately adjusted, and give the FM broadcast receiving circuit 226 a highly accurate circuit constant.

In the vicinity of the power supply IC 216, a plurality of chip capacitors 227 and a plurality of chip diodes 228 are mounted on the mounting surface of the mounting substrate 9. The power supply IC 216 forms a power supply circuit 229 together with the chip capacitor 227 and the chip diode 228.
The flash memory 217 is a storage device for recording an operating system program, data generated inside the smartphone 201, data and programs acquired from the outside by a communication function, and the like.

The microcomputer 218 includes a CPU, a ROM, and a RAM, and is an arithmetic processing circuit that realizes a plurality of functions of the smartphone 201 by executing various arithmetic processes. More specifically, image processing and arithmetic processing for various application programs are realized by the action of the microcomputer 218.
Near the power supply IC 219, a plurality of chip capacitors 230 and a plurality of chip diodes 231 are mounted on the mounting surface of the mounting substrate 9. The power supply IC 219 constitutes a power supply circuit 232 together with the chip capacitor 230 and the chip diode 231.

  Near the baseband IC 220, a plurality of chip resistors 233, a plurality of chip capacitors 234, and a plurality of chip inductors 235 are mounted on the mounting surface 9 A of the mounting substrate 9. The baseband IC 220 constitutes a baseband communication circuit 236 together with the chip resistor 233, the chip capacitor 234, and the chip inductor 235. The baseband communication circuit 236 provides a communication function for telephone communication and data communication.

  With such a configuration, the power appropriately adjusted by the power supply circuits 229 and 232 is transmitted to the transmission processing IC 212, the GPS reception IC 214, the one-segment broadcast reception circuit 223, the FM broadcast reception circuit 226, the baseband communication circuit 236, the flash memory 217, and the like. It is supplied to the microcomputer 218. The microcomputer 218 performs arithmetic processing in response to an input signal input via the transmission processing IC 212 and outputs a display control signal from the transmission processing IC 212 to the display panel 203 to cause the display panel 203 to perform various displays. .

When reception of one-segment broadcasting is instructed by operating the touch panel or the operation button 204, the one-segment broadcasting is received by the operation of the one-segment broadcasting receiving circuit 223. Then, the microcomputer 218 executes arithmetic processing for outputting the received image to the display panel 203 and making the received sound audible from the speaker 205.
When the position information of the smartphone 201 is required, the microcomputer 218 acquires the position information output from the GPS reception IC 214 and executes a calculation process using the position information.

Further, when an FM broadcast reception command is input by operating the touch panel or the operation button 204, the microcomputer 218 activates the FM broadcast reception circuit 226 and executes arithmetic processing for outputting the received sound from the speaker 205. To do.
The flash memory 217 is used to store data acquired by communication, to store data created by calculation of the microcomputer 218 and input from the touch panel. The microcomputer 218 writes data to the flash memory 217 and reads data from the flash memory 217 as necessary.

The function of telephone communication or data communication is realized by the baseband communication circuit 236. The microcomputer 218 controls the baseband communication circuit 236 to perform processing for transmitting and receiving voice or data.
In addition, various design changes can be made within the scope of matters described in the claims.

DESCRIPTION OF SYMBOLS 1 Chip resistor 2 Board | substrate 2A Element formation surface 3 1st connection electrode 4 2nd connection electrode 5 Element 10 Concave part 11 Convex part 12 Concave part 21 Resistor film 22 Wiring film 33 Ni layer 34 Pd layer 35 Au layer 56 Resistance 101 Chip capacitor 111 Lower electrode film 112 Capacitance film 113 Upper electrode film 131 to 139 Electrode film portion 221 Chip inductor 222 Chip resistor 224 Chip resistor 225 Chip inductor 227 Chip capacitor 228 Chip diode 230 Chip capacitor 231 Chip diode 233 Chip resistor 234 Chip capacitor 235 Chip inductor C1-C9 Capacitor element F (F1-F9) Fuse R Resistor

Claims (16)

A substrate having a rectangular central region and a peripheral edge around the central region, and having one surface and the other surface opposite to the one surface;
An element circuit network including a plurality of element elements formed on the one surface of the central region of the substrate;
An electrode for externally connecting the element circuit network, provided on the one surface of the central region of the substrate;
On the side surface that intersects the one surface and the other surface of the substrate, concave and convex portions that are notched in the thickness direction of the substrate and convex portions adjacent to the concave portions are formed alternately. ,
The said recessed part and the said convex part are chip components provided in each edge | side from the said peripheral part of the one surface of the said board | substrate to the said peripheral part of the other side of the said board | substrate.   2. The chip component according to claim 1, wherein the convex portions are formed to have the same width and are arranged at a constant pitch in a circumferential direction of the side surface of the substrate.   The chip component according to claim 1, wherein the convex portion includes a convex portion wider than a width of the concave portion.   The chip component according to claim 1, wherein the unevenness is formed over the entire circumference of the side surface of the substrate.   5. The chip component according to claim 1, wherein the convex portion is formed in a quadrangular shape in a plan view as viewed from the normal direction of the one surface of the substrate.   5. The chip component according to claim 1, wherein the convex portion is formed in a triangular shape in a plan view as viewed from the normal direction of the one surface of the substrate.   5. The chip component according to claim 1, wherein the convex portion is formed in an arc shape in a plan view as viewed from the normal direction of the one surface of the substrate.   The chip component according to claim 1, comprising a plurality of fuses for connecting the plurality of element elements to the electrodes in a detachable manner. The element circuit network includes a resistor network including a plurality of resistors formed on the substrate;
The chip component according to claim 8, wherein the chip component is a chip resistor.   The chip component according to claim 9, wherein the resistor includes a resistor film formed on the substrate and a wiring film laminated on the resistor film. The element network includes a capacitor network including a plurality of capacitor elements formed on the substrate;
The chip component according to claim 8, wherein the chip component is a chip capacitor. The capacitor element includes a capacitor film formed on the substrate, and a lower electrode film and an upper electrode film facing each other with the capacitor film interposed therebetween,
The lower electrode film and the upper electrode film include a plurality of separated electrode film parts,
The chip component according to claim 11, wherein the plurality of electrode film portions are respectively connected to the plurality of fuses. The element network includes an inductor network including a plurality of inductor elements formed on the substrate;
The chip component according to claim 8, wherein the chip component is a chip inductor. The device circuitry comprises a diode circuitry comprising a plurality of diode elements formed on the substrate;
The chip component according to claim 8, wherein the chip component is a chip diode.   The chip part according to any one of claims 1 to 14, wherein the electrode includes a Ni layer and an Au layer, and the Au layer is exposed on an outermost surface.   The chip component according to claim 15, wherein the electrode further includes a Pd layer interposed between the Ni layer and the Au layer.

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