TW201304097A - Integrated circuit package - Google Patents

Abstract

The invention provides an integrated circuit package and method for fabricating thereof. The package comprises an integrated circuit chip having a photosensitive device thereon, a bonding pad formed on the integrated circuit chip and electrically connected to the photosensitive device, a first barrier formed between the photosensitive device and the bonding pad, and a conductive layer formed on a sidewall of the integrated circuit chip and electrically connected to the bonding pad. An adhesive agent in the package is resisted to overflow into an area of the photosensitive device by the first barrier, for improving a yield of fabricating integrated circuit package.

Description

Integrated circuit package

The present invention relates to an integrated circuit package and a method of fabricating the same, and more particularly to an integrated circuit package having high yield and a method of fabricating the same.

In the process of an integrated circuit device, the integrated circuit must be processed by a packaging process for use in various applications, such as a computer, a cell phone, or a digital camera. Therefore, the yield of the integrated circuit package also directly affects the yield of the final integrated circuit device.

The 1A-1D diagram shows a cross-sectional view of a conventional integrated circuit package. Figures 1A and 1B show the form in which the protective layer 8 is formed on the cover 4 before the joining step. On the other hand, the 1C and 1D drawings show the form in which the protective layer 8 is formed on the integrated circuit wafer 2 before the bonding step. In Fig. 1A, the integrated circuit wafer 2 on which the photosensitive element 12 is formed is shown, and the photosensitive element 12 is electrically connected to the bonding pad 6. Further, as shown in FIG. 1A, the cover 4 is attached to the upper surface of the integrated circuit wafer 2 by the adhesive 10, and a gap 14 is formed between the cover 4 and the integrated circuit wafer 2. In the above-described step of joining the cover 4 and the integrated circuit wafer 2, the adhesive 10 overflows to the area of the photosensitive member 12 as shown in Fig. 1A. Fig. 1B is a cross-sectional view showing the integrated circuit package in which the adhesive overflows to the photosensitive member in the bonding step in Fig. 1A. In Fig. 1B, the adhesive 10 will overflow to the area of the photosensitive member 12, and cover a portion of the photosensitive member 12, so that the photosensitive member 12 is opposed to The light reaction of the outside through the cover 4 and the gap 14 is inconsistent, resulting in a defective integrated circuit package.

As shown in FIG. 1C, the integrated circuit wafer 2 on which the photosensitive element 12 and the bonding pad 6 are formed is provided, and the protective layer 8 is covered above the bonding pad 6. Next, the cover 4 is bonded to the integrated circuit wafer 2, and a gap 14 is formed between the cover 4 and the integrated circuit wafer. At the above bonding step, the adhesive 10 overflows to the region of the photosensitive member 12 along the side wall of the protective layer 8, as shown in Fig. 1C. Fig. 1D is a cross-sectional view showing the integrated circuit package in which the adhesive overflows to the photosensitive member in the bonding step in Fig. 1C. As shown in Fig. 1D, the adhesive 10 overflows to the region of the photosensitive member 12 and covers a portion of the photosensitive member 12, thereby causing a decrease in the package yield of the integrated circuit package. Thus, it can be seen that the conventional joining method causes the above problems.

Therefore, there is a need for an integrated circuit package and a method of fabricating the same to solve the above problems and to improve the process yield of the integrated circuit package.

In view of the above, it is an object of the present invention to provide an integrated circuit package. The integrated circuit package includes an integrated circuit chip having a photosensitive element formed on an upper surface thereof; a bonding pad formed on an upper surface of the integrated circuit chip and electrically connected to the photosensitive element; a first retaining wall Formed between the photosensitive element and the bonding pad; and a conductive layer formed on the sidewall of the integrated circuit chip and electrically connected to the bonding pad.

Another object of the present invention is to provide an integrated circuit package method. The method for fabricating the integrated circuit package includes: providing an integrated circuit chip having a photosensitive element formed on the upper surface; forming a bonding pad on the integrated circuit package, and electrically connecting the photosensitive element; forming a first Retaining wall between the bonding pad and the photosensitive element; and forming a conductive layer on the sidewall of the integrated electric wafer, and electrically connecting the bonding pad. The integrated circuit package further includes bonding a first substrate over the integrated circuit wafer by an adhesive. In an integrated circuit package according to an embodiment of the present invention, a barrier wall is interposed between the bonding pad and the photosensitive member. Therefore, at the joining step, the retaining wall can block the area where the adhesive overflows to the photosensitive member. Moreover, since the retaining wall is provided between the bonding pad and the photosensitive element, the position and the amount of the adhesive formation can be more precisely controlled, thereby reducing the manufacturing cost.

The invention will be described in detail by way of example and with reference to the accompanying drawings In the drawings, the shape or thickness of the embodiments may be expanded to simplify or facilitate the marking. Portions of the elements in the drawings will be described by way of illustration. It will be appreciated that elements not shown or described may be in a variety of forms known to those skilled in the art. In addition, when a layer is referred to as being on a substrate or another layer, the layer may be directly on the substrate or on another layer, or may have an intervening layer therebetween.

In the second drawing, the cross-sectional view of the integrated circuit package according to the first embodiment of the present invention is shown. In Figure 2A, provided with the above table An integrated circuit wafer 102 of the face 103 and the lower surface 105 is formed with a photosensitive member 104 on the upper surface 103 of the integrated circuit wafer 102. Further, as shown in FIG. 2A, the bonding pad 106 is formed on the upper surface of the integrated circuit wafer 102, and the photosensitive element 104 is electrically connected.

In a preferred embodiment, the integrated circuit chip 102 may be a photoreceptor circuit chip, but is not limited thereto. The bond pads 106 are preferably copper, aluminum or other conductive materials. In a preferred embodiment, the bonding pad 106 is formed by, for example, sputtering or evaporation to form a conductive material layer, followed by lithography and etching. The bonding pad 106 described above is formed. Although a separate bond pad is shown in Figure 2A, it will be appreciated that the bond pad can also be an extended bond pad.

As shown in FIG. 2B, a barrier 108, which may also be referred to as a gate pattern, is formed on the upper surface of the integrated circuit wafer 102 and between the bonding pad 106 and the photosensitive element 104. between. In a preferred embodiment, the retaining wall 108 is preferably, for example, a polyimide resin (PI), an epoxy, a polyester, or other suitable insulating material. Preferably, the barrier layer 108 is formed by first forming an insulating material layer on the upper surface of the integrated circuit wafer 102 by coating, and then patterning the insulating material layer by lithography and etching. To form the retaining wall 108.

As shown in FIG. 2C, a first substrate 110 (also referred to as a cap plate) is provided, and a protective layer 112 is formed over the first substrate 110. The first substrate 110 may preferably be glass, quartz, opal, plastic or other A suitable transparent substrate. The protective layer 112 may preferably be a polyimide resin, an epoxy resin or other suitable insulating material. Further, as shown in Fig. 2C, an adhesive 114 is formed on the protective layer 112. The adhesive 114 may preferably be an adhesive material containing an epoxy resin.

In FIG. 2D, the first substrate 110 is bonded to the upper surface of the integrated circuit wafer 102 by the adhesive 114 to form a gap 116 between the first substrate 110 and the integrated circuit wafer 102. After the bonding step, the protective layer 112 covers the bonding pad 106 to protect the bonding pad 106, and the distance between the barrier 108 and the protective layer 112 is preferably greater than or equal to 0.5 μm.

It should be noted that in the present embodiment, since the retaining wall 108 is disposed between the bonding pad 106 and the photosensitive element 104, the adhesive 114 is formed between the retaining wall 108 and the bonding pad 106, as shown in FIG. 2D. Shown. Accordingly, in the bonding step, the retaining wall blocks the adhesion of the adhesive to the photosensitive member region to improve the performance of the integrated circuit package due to the overflow of the adhesive to the photosensitive member, for example, the adhesive covers the photosensitive member. The refractive index of the light incident on the photosensitive element is changed, and even the photosensitive element cannot sense the light, resulting in failure of the photosensitive element. Moreover, since the retaining wall is provided between the bonding pad and the photosensitive element, the position and the amount of the adhesive formation can be more precisely controlled, thereby reducing the manufacturing cost.

After the above bonding step is completed, a polishing step may be selectively performed to thin the thickness of the integrated circuit wafer 102. In a preferred embodiment, after the grinding step, the thickness of the integrated circuit wafer 102 may preferably be between 10 and 250 μm to facilitate subsequent cutting of the integrated circuit wafer 102. The steps are carried out.

As shown in FIG. 2E, a portion of the integrated circuit wafer 102 is removed along a predetermined dicing line that cuts individual dies using a lithography and etching step, and an opening 118 is formed to cut individual dies. The opening 118 exposes the bottom surface of the bond pad 106 and the protective layer 114.

In a preferred embodiment, the etching step may use SF _6, C ₄ F ₈ or other suitable dry etching of the dry etching gas, for example, the process is complete. In another embodiment, the etching step may also be a wet etching process including a ruthenium etching solution, such as 2.5% hydrofluoric acid (HF), 50% nitric acid (HNO3), 10% acetic acid (CH3COOH), and 37.5% water. The solution is mixed to remove a portion of the integrated circuit wafer 102 and expose the bond pads 106. In the wet etching process described above, an etching solution containing potassium hydroxide (KOH) may also be used.

Further, as shown in FIG. 2E, the glue 120 is formed on the lower surface 105 of the integrated circuit wafer 102 and filled in the opening 118. Next, a second substrate 122 is attached over the lower surface 105 of the integrated circuit wafer 102 by the adhesive material 120. The above-mentioned glue may preferably be an epoxy resin or other suitable material and formed on the lower surface 105 of the integrated circuit wafer 102 by, for example, coating. The second substrate 122 may be a substrate similar to the first substrate. It should be noted that the second substrate 112 may also be an opaque substrate of other suitable materials. Furthermore, the second substrate 122 can be used to carry the integrated circuit wafer 102, and thus can also be referred to as a carrier substrate.

As shown in Fig. 2F, the integrated circuit package in Fig. 2E is inverted by 180 degrees. In FIG. 2F, an insulating layer 124 is formed on the second substrate 122, and then, by means of a scoring device, a predetermined cut along the individual grains is performed. The dicing line is subjected to a scoring step (which may also be referred to as a dicing step) to form a recess 126 and expose the sidewalls of the bonding pad 106 and the surface of the first substrate 110.

In a preferred embodiment, the insulating layer 124 may be, for example, hafnium oxide, hafnium oxide, tantalum nitride, a photoresist material, or other suitable dielectric material, and the insulating layer 124 may be, for example, spin coated (spin) Coating), spray coating or, for example, low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD).

As shown in FIG. 2F, a conductive layer 128 is formed on the insulating layer 124 and extends into the recess 126 to electrically connect the bonding pads 106. The conductive layer 128 may preferably be aluminum, copper, nickel or other suitable electrically conductive material. In a preferred embodiment, the conductive layer 128 may be formed by conformally forming a conductive material layer over the insulating layer 124 by, for example, sputtering, evaporation, electroplating, or plasma enhanced vapor deposition. And a layer of conductive material may extend from the surface of the insulating layer 124 through the sidewall of the bonding pad 106 to the first substrate 110. Next, the conductive material layer is patterned by a lithography and etching step to form the conductive layer 128 and expose a portion of the surface of the insulating layer 124.

After the conductive layer 128 is completed, since the bottom of the recess 126 is generally narrow, the conductive material is not preferably formed at the bottom of the recess 126. Therefore, an electroless plating step can also be selectively performed to form a preferred conductive layer 128 at the bottom of the recess 126. It can be appreciated that the conductive layer 128 can also be formed directly by electroless plating.

As shown in FIG. 2G, a solder mask film 130 is formed over conductive layer 128 and a portion of conductive layer 128 is exposed to define the location of solder ball 132. Next, a solder ball 132 is formed over the exposed conductive layer 128 to electrically connect the conductive layer 128. The solder resist film 130 described above can serve as a protective layer.

After the above steps are completed, the individual dies are then divided by the dicing blade along the pre-cut lines of the individual dies to complete an integrated circuit package 140, as shown in FIG. In Fig. 2H, a cross-sectional view in which the integrated circuit package in Fig. 2G is inverted by 180 degrees after being processed by the dicing step is shown. As shown in FIG. 2H, the integrated circuit package 140 has a photosensitive element 104 and a bonding pad 106 formed thereon, and the bonding pad 106 is electrically connected to the photosensitive element 104. Further, as shown in FIG. 2H, the conductive layer 128 is formed on the sidewall of the integrated circuit wafer 102, and the bonding pad 106 and the solder ball are electrically connected.

A first substrate 110 is correspondingly disposed above the integrated circuit wafer 102, and forms a gap 116 with the surface of the integrated circuit wafer 102, as shown in FIG. 2H. It is to be noted that the integrated circuit package 140 according to the first embodiment of the present invention has a retaining wall 108 interposed between the bonding pad 106 and the photosensitive member 104 to prevent the adhesive from overflowing to the photosensitive portion during the bonding step. Above the component 104, thereby improving the defect in the packaging process.

As shown in Figs. 3A-3B, the integrated circuit package of the second embodiment of the present invention. In FIG. 3A, a photosensitive element 204 is formed above. The integrated circuit chip 202. Next, the bonding pad 206 is formed over the integrated circuit wafer 202 and electrically connected to the photosensitive element 204. Thereafter, a first retaining wall 208 and a second retaining wall 210 are formed above the integrated circuit wafer 202 and between the bonding pad 206 and the photosensitive element 204. In a preferred embodiment, the height of the second retaining wall 210 may be less than or equal to the height of the first retaining wall 208. The second retaining wall 210 is interposed between the first retaining wall 208 and the bonding pad 206, and the distance between the second retaining wall 210 and the protective layer 214 is preferably greater than or equal to 0.5 μm.

Further, as shown in FIG. 3A, a first substrate 212 having a protective layer 214 and an adhesive 216 formed thereon is provided. Next, the first substrate 212 is bonded over the integrated circuit wafer 202 by the adhesive 216 to form a gap 218. After the bonding step, the protective layer 214 will cover the bonding pads 206 and the adhesive 216 will wrap the second barrier 210.

After the above bonding step is completed, the step of cutting the integrated electric wafer 202 is performed, and then the second substrate 222 is attached to the lower surface of the integrated circuit wafer 202 using the adhesive 220. Thereafter, after forming an insulating layer 224 on the lower surface of the second substrate 222, a scratching step is then performed to expose the bonding pads 206. Then, a conductive layer 226 is formed on the sidewall of the second substrate 222 and extends to the bonding pad 206, and is electrically connected to the bonding pad 206, and then the solder resist film 228 is formed over the conductive layer 226. Finally, after the step of forming the solder ball 230 is performed, the dicing blade is used to divide the individual dies along the predetermined dicing line to complete the fabrication of the integrated body package 232, as shown in FIG. 3B. The material and formation manner of the above-mentioned components may be the same as those of the first embodiment, and therefore, details are not described herein again.

It is to be noted that the integrated circuit package according to the second embodiment of the present invention has a first retaining wall and a second retaining wall interposed between the bonding pad and the photosensitive member. Therefore, at the bonding step, the adhesive does not overflow to the region of the photosensitive member to improve the problem that the integrated circuit package is defective due to the overflow of the adhesive. Moreover, in the present embodiment, since the first and second retaining walls are formed, the overflow phenomenon of the adhesive can be more effectively blocked. It can be understood that in the first and second embodiments, the protective layer (Dam) may also be formed on the integrated circuit wafer, and the protective layer may also be formed simultaneously with the retaining wall to reduce the process steps.

4A-4D is a cross-sectional view showing the fabrication of the integrated circuit package of the third embodiment of the present invention. As shown in Fig. 4A, an integrated circuit wafer 302 having a photosensitive member 304 formed thereon is provided. A bonding pad 306 is formed over the integrated circuit wafer 302 and electrically connected to the photosensitive element. As further shown in FIG. 4A, a protective layer 308 is overlying the bond pads 306 to protect the bond pads 306. Next, an adhesive 310 is formed over the protective layer 308. The material and formation manner of the above components may be the same as those of the first embodiment, and thus will not be described again.

In Fig. 4B, a first substrate 312 having a retaining wall 314 formed thereon is shown. The material and formation of the first substrate 312 and the retaining wall 314 may be the same as in the first embodiment. Next, the first substrate 312 is bonded over the integrated circuit wafer 302 by the adhesive 310 to form a gap 316 between the first substrate 312 and the integrated circuit chip 302, as shown in FIG. 4C. .

In FIG. 4C, after the bonding step, the first substrate 302 is disposed. The upper retaining wall 314 is formed between the bonding pad 306 and the photosensitive member 304 to block the overflow of the adhesive 310 onto the photosensitive member 304. In an example, the material and formation of the retaining wall 314 may be the same as the retaining wall of the first embodiment. In a preferred embodiment, the distance between the retaining wall 314 and the protective layer 308 may be greater than or equal to 0.5 μm after the bonding step.

After the bonding step is completed, the integrated electric wafer 302 is cut by a lithography and etching process, and then the second substrate 320 is attached to the lower surface of the integrated circuit wafer 302 by using the adhesive 318. Thereafter, after forming an insulating layer 322 on the lower surface of the second substrate 320, a scratching step (which may also be referred to as a cutting step) is performed to expose the sidewalls of the bonding pad 306 and the surface of the first substrate 312. Then, a conductive layer 324 is formed on the sidewall of the integrated circuit wafer 302, electrically connected to the bonding pad 306, and then the partial conductive layer 324 is covered with the solder resist film 326. Finally, after the step of forming the solder ball 328 over the conductive layer 324, the dicing blade is used to divide the individual dies along the predetermined dicing line to complete the fabrication of the integrated body package 330, as shown in FIG. 4D. Show. The material and formation manner of the above-mentioned components may be the same as those of the first embodiment, and therefore, details are not described herein again.

It is to be noted that the integrated circuit package according to the third embodiment of the present invention has a retaining wall disposed on the first substrate. After the joining step, the retaining wall will be interposed between the bond pad and the photosensitive element. Therefore, at the bonding step, the adhesive does not overflow to the region of the photosensitive member to improve the problem that the integrated circuit package is defective due to the overflow of the adhesive.

5A-5B is a cross-sectional view showing the fabrication of an integrated circuit package in accordance with a fourth embodiment of the present invention. In Figure 5A, an upper formation is provided The integrated circuit wafer 402 of the photosensitive element 404. Next, the bonding pad 406 is formed over the integrated circuit wafer 402 and electrically connected to the photosensitive element 404. Thereafter, a protective layer 408 is overlying the bond pads 408 to protect the bond pads 408 and the adhesive 410 is formed over the protective layer 408.

As shown in FIG. 5A, a first substrate 412 having a first barrier 414 and a second barrier 416 formed thereon is bonded over the integrated circuit wafer 402 by an adhesive 410 to form a gap 418. . In a preferred embodiment, the height of the second retaining wall 416 may be less than or equal to the height of the first retaining wall 414. After the bonding step is completed, the first retaining wall 414 and the second retaining wall 416 are formed between the bonding pad 406 and the photosensitive element 418, and the distance between the second retaining wall 416 and the protective layer 408 may preferably be greater than Or equal to 0.5 μm. The first retaining wall 414 and the second retaining wall 416 may have a suitable distance to accommodate the adhesive 410 between the first retaining wall 414 and the second retaining wall 416.

After the bonding step is completed, the integrated electric wafer 402 is cut by a lithography and etching process, and the second substrate 422 is attached to the lower surface of the integrated circuit wafer 302 using the adhesive 420. Thereafter, after forming an insulating layer 424 on the lower surface of the second substrate 422, a scratching step (which may also be referred to as a dicing step) is performed to expose the sidewalls of the bonding pad 406 and the surface of the first substrate 412. Then, a conductive layer 426 is formed on the sidewall of the second substrate 422 and extends to the surface of the first substrate 412 to electrically connect the bonding pads 406, and then the partial conductive layer 426 is covered with the solder resist film 428. Finally, after the step of forming the solder ball 430 over the conductive layer 426, the dicing blade is used to divide into individual dies along a predetermined cutting line. The fabrication of the integrated electrical body package 432 is completed as shown in FIG. 5B. The material and formation manner of the above-mentioned components may be the same as those of the first embodiment, and therefore, details are not described herein again.

It is noted that the integrated circuit package according to the fourth embodiment of the present invention has a first retaining wall and a second retaining wall disposed on the first substrate. After the joining step, the retaining wall will be interposed between the bond pad and the photosensitive element. Therefore, at the bonding step, the adhesive does not overflow to the region of the photosensitive member to improve the problem that the integrated circuit package is defective due to the overflow of the adhesive. Furthermore, in the present embodiment, the integrated circuit package has the first and second retaining walls, so that the overflow phenomenon of the adhesive can be more effectively blocked.

It is worth mentioning that in the third and fourth embodiments, the protective layer may also be formed on the first substrate, and the protective layer may also be formed simultaneously with the retaining wall to reduce the process steps. Further, the above-mentioned retaining walls may be formed separately on the first substrate and the integrated circuit to block the overflow of the adhesive during the joining step. Furthermore, the above embodiments are all shown in cross-section. It can be understood that the above-mentioned retaining wall can be a ring shape and surround the photosensitive element on the integrated circuit wafer to limit the adhesion of the adhesive to the photosensitive element.

Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and it is to be understood that the present invention may be modified and retouched without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

2‧‧‧Integrated circuit chip

4‧‧‧ Cover

6‧‧‧Join pad

8‧‧‧Protective layer

10‧‧‧Adhesive

12‧‧‧Photosensitive elements

14‧‧‧ gap

102‧‧‧Integrated circuit chip

103‧‧‧ upper surface

104‧‧‧Photosensitive element

105‧‧‧lower surface

106‧‧‧ Bonding mat

108‧‧‧Retaining wall

110‧‧‧First substrate

112‧‧‧Protective layer

114‧‧‧Adhesive

116‧‧‧ gap

118‧‧‧ openings

120‧‧‧Stained materials

122‧‧‧second substrate

124‧‧‧Insulation

126‧‧‧ Groove

128‧‧‧ Conductive layer

130‧‧‧ solder mask

132‧‧‧ solder sphere

140‧‧‧Integrated circuit package

202‧‧‧Integrated circuit chip

204‧‧‧Photosensitive elements

206‧‧‧Material pads

208‧‧‧First retaining wall

210‧‧‧Second retaining wall

212‧‧‧First substrate

214‧‧‧protection layer

216‧‧‧Adhesive

218‧‧‧ gap

220‧‧‧Stained materials

222‧‧‧second substrate

224‧‧‧Insulation

226‧‧‧ Conductive layer

228‧‧‧ solder mask

230‧‧‧ solder sphere

232‧‧‧Integrated circuit package

302‧‧‧Integrated circuit chip

304‧‧‧Photosensitive element

306‧‧‧Join pad

308‧‧‧Protective layer

310‧‧‧Adhesive

312‧‧‧First substrate

314‧‧ ‧ retaining wall

316‧‧‧ gap

318‧‧‧Stained materials

320‧‧‧second substrate

322‧‧‧Insulation

324‧‧‧ Conductive layer

326‧‧‧ solder mask

328‧‧‧ solder sphere

330‧‧‧Integrated circuit package

402‧‧‧Integrated circuit chip

404‧‧‧Photosensitive element

406‧‧‧Contact pads

408‧‧‧protection layer

410‧‧‧Adhesive

412‧‧‧First substrate

414‧‧‧First retaining wall

416‧‧‧Second retaining wall

418‧‧‧ gap

420‧‧‧Stained materials

422‧‧‧second substrate

424‧‧‧Insulation

426‧‧‧ Conductive layer

428‧‧‧ solder mask

430‧‧‧ solder sphere

432‧‧‧Integrated electrode package

1A-1D is a cross-sectional view showing a conventional integrated circuit package; 2A-2H is a cross-sectional view showing the fabrication of the integrated circuit package according to the first embodiment of the present invention; and 3A-3B is a cross-sectional view showing the fabrication of the integrated circuit package according to the second embodiment of the present invention; 4A-4D are cross-sectional views showing the fabrication of an integrated circuit package in accordance with a third embodiment of the present invention; and FIGS. 5A-5B are cross-sectional views showing the fabrication of an integrated circuit package in accordance with a fourth embodiment of the present invention. .

102‧‧‧Integrated circuit chip

104‧‧‧Photosensitive element

106‧‧‧ Bonding mat

108‧‧‧Retaining wall

110‧‧‧First substrate

116‧‧‧ gap

128‧‧‧ Conductive layer

132‧‧‧ solder sphere

140‧‧‧Integrated circuit package

Claims (20)

An integrated circuit package comprising: an integrated circuit chip having a photosensitive element formed on an upper surface thereof; a cover plate disposed on the integrated circuit chip and having a protective layer spaced apart from the integrated circuit chip The protective layer and the cover plate enclose a space on the photosensitive element, wherein the protective layer is an insulating material; and a first retaining wall is formed between the photosensitive element and the protective layer, wherein the first The retaining wall is a patterned insulating layer. The integrated circuit package of claim 1, further comprising a second retaining wall between the protective layer and the first retaining wall. The integrated circuit package of claim 2, wherein the height of the second retaining wall is less than or equal to the height of the first retaining wall. The integrated circuit package of claim 2, wherein the second retaining wall is located on the integrated circuit chip. The integrated circuit package of claim 2, wherein the second retaining wall is located on the cover plate, and the cover plate is correspondingly disposed above the integrated circuit chip. The integrated circuit package of claim 1, wherein the first retaining wall is spaced apart from the protective layer by a distance. The integrated circuit package of claim 1, wherein a distance between the first retaining wall and the protective layer is greater than or equal to 0.5 μm. The integrated circuit package of claim 2, wherein the second retaining wall and the protective layer are separated by a distance. An integrated circuit package as described in claim 2, The distance between the second retaining wall and the protective layer is greater than or equal to 0.5 μm. The integrated circuit package of claim 1, wherein the height of the first retaining wall is equal to the height of the space. The integrated circuit package of claim 1, wherein the protective layer does not have any wire bonding structure. The integrated circuit package of claim 1, further comprising: an adhesive layer between the first retaining wall and the protective layer; and a bonding pad electrically connected to the photosensitive element, wherein the A protective layer covers the bond pad. The integrated circuit package of claim 12, wherein the first retaining wall isolates the adhesive layer from the light emitting element. The integrated circuit package of claim 12, wherein the protective layer completely covers the entire upper surface of the bonding pad. The integrated circuit package of claim 12, wherein the bonding pad directly contacts the protective layer. The integrated circuit package of claim 1, wherein the first retaining wall directly contacts the cover. The integrated circuit package of claim 1, wherein the first retaining wall directly contacts the integrated circuit chip. The integrated circuit package of claim 1, wherein the material of the first retaining wall comprises a polyimide, an epoxy resin, or a polyester resin. For example, the integrated circuit package described in claim 1 is The cover is a transparent substrate. The integrated circuit package of claim 1, wherein no adhesive is located between the first retaining wall and the cover, and no adhesive is located at the first retaining wall and the integrated circuit. Between wafers.