JP2017067992A - Exposure device, exposure device alignment method, and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an exposure device which performs alignment quickly and accurately on a substrate where a great number of patterns are disposed.SOLUTION: Provided is an exposure device which includes a camera and DMD used for alignment and is capable of forming a pattern according to Fan Out Wafer Level Package (FO-WLP), which captures a plurality of semiconductor chips SC in a visual field to pick up an image thereof simultaneously, extracts respective contours of the semiconductor chips SC from the image, and compares an image of a comparison target area TA in which connection pads CP to be marks are extracted with a template image to detect positional deviation amount of each of the chips.SELECTED DRAWING: Figure 6

Description

  The present invention relates to an exposure apparatus that forms a pattern on a substrate or the like, and more particularly to alignment with a substrate on which a large number of patterns are arranged.

  In recent years, an exposure method for drawing a large number of circuit patterns (such as semiconductor chip patterns) on a single substrate has been utilized. For example, fine-out wafer level packaging (FO-WLP) is known as a wafer level package (WLP) that performs an IC packaging process in a wafer state.

  There, a semiconductor substrate cut out from a wafer is arranged on a support substrate (called a pseudo wafer), a rewiring is formed in the gap between the semiconductor chips by pattern exposure, and then the pseudo wafer is cut to form a package. (This process is called mold-first (chip-first) FO-WLP).

  In FO-WLP, since a semiconductor chip is embedded in a resin-supporting substrate having a spreadability, each semiconductor chip has a random inherent positional shift, and it is necessary to correct the position of the rewiring pattern by alignment. There is.

  As an alignment method, the camera is scanned in accordance with the scanning band (bandwidth) of the projection area by the light modulation element array (DMD or the like), and an entire wide area image obtained by joining these images is acquired. And the position of the alignment mark, terminal pad, etc. which are formed in each chip | tip is detected, and the positional offset amount of each chip | tip is detected with a template matching system (refer patent document 1).

  On the other hand, even when a multilayer substrate is formed by patterning with multiple layers, the circuit pattern is overlaid and exposed on the lower layer pattern (first layer), so alignment is necessary. As a method for detecting the amount of positional deviation, for example, the positional deviation can be detected by using an alignment mark or a chip shape (die shape) (see Patent Document 2).

JP2013-58520A Special table 2013-520828 gazette

  A large resin substrate different from a wafer or the like has an extremely large number of patterns (for example, 10,000 or more), and it takes time to acquire an entire wide area image while imaging an area along a scanning band. There is. As a result, alignment calculation also takes time, and the productivity of the substrate decreases. On the other hand, when pattern alignment for each layer is performed, it is difficult to accurately detect the amount of misalignment unless the shape of the chip itself has a feature.

  Therefore, it is necessary to perform alignment quickly and accurately even on a substrate on which a large number of patterns are arranged.

  The exposure apparatus of the present invention is an exposure apparatus that can be patterned on a substrate on which a large number of patterns (hereinafter referred to as lower layer patterns) are arranged. For example, the exposure apparatus is formed on a support substrate formed based on FO-WLP. Thus, rewiring patterning can be performed. In particular, the exposure apparatus of the present invention can adjust the alignment with respect to a rectangular substrate in which a larger number (for example, 10,000 or more) of lower layer patterns are arranged in a matrix throughout. The lower layer pattern here includes a semiconductor package (chip), and also includes a circuit pattern that is regularly arranged on a glass substrate, a printed circuit board, or the like.

  The exposure apparatus according to the present invention includes an imaging unit, a measurement unit that measures each lower layer pattern position, and a correction unit that calculates a positional deviation amount of each lower layer pattern by template matching and corrects drawing data. For example, the imaging unit includes a camera that can move along the main scanning direction, and the imaging area can be scanned intermittently or continuously with respect to the substrate by driving and controlling the camera.

  In the present invention, the image pickup unit picks up an image so as to capture a plurality of lower layer patterns in the field of view among the many lower layer patterns by adjusting the image magnification and the like. For example, the imaging may be performed with a field frame larger than the scanning bandwidth of the light modulation element array. Further, it is possible to fit in the field frame by the number of the plurality of lower layer patterns arranged along the main scanning direction and the sub scanning direction.

  Then, the measurement unit performs template matching based on the comparison target image from which feature marks belonging to at least a partial area of each lower layer pattern are extracted, and detects a positional deviation. A plurality of lower layer patterns are simultaneously photographed, and at least a part of the lower layer pattern is used as a comparison target for template matching, and a connection target image formed as a comparison target image is extracted as a feature mark, thereby enabling rapid Alignment correction can be performed.

  In a lower layer pattern having a complicated wiring pattern, it is difficult to individually recognize a lower layer pattern from adjacent lower layer patterns that fit in the field frame. Therefore, the measurement unit may extract the comparison target image after detecting the contour of each lower layer pattern.

  When a large number of feature marks are present randomly in one lower layer pattern, the feature mark extraction process takes time. Therefore, the measurement unit may be configured to arbitrarily set the area of the comparison target image. For example, a part of the lower layer pattern area may be determined as the comparison target image.

  The measurement unit may refer to the amount of positional deviation between adjacent lower layer patterns in order to reduce the alignment adjustment time for lower layer patterns that cannot be detected. Also by this, since it is information of the adjacent lower layer pattern, effective alignment adjustment can be performed to some extent. Alternatively, for the lower layer pattern in which the position deviation cannot be detected, the position deviation amount of the lower layer pattern can be determined according to the extraction of the lower layer pattern contour based on the operation of the operator. For example, the contour detection assist function supports the contour detection on the screen for the operator, and the position shift amount can be detected based on the support.

  For a multi-package area composed of two or more lower layer patterns, the measurement unit may detect the amount of positional deviation of the lower layer patterns in the area after the imaging of all the lower layer patterns in the area is completed.

  The exposure apparatus alignment method of the present invention is an exposure apparatus alignment method for patterning on a substrate on which a large number of lower layer patterns are arranged, and images a plurality of lower layer patterns within a field of view. , An exposure method that measures the position of each lower layer pattern, calculates the amount of positional deviation of each lower layer pattern by template matching, and corrects drawing data, wherein feature marks belonging to at least a partial area of each lower layer pattern are extracted Template matching is performed based on the comparison target image to detect misalignment.

  The program according to the present invention includes an imaging device for patterning an exposure apparatus for patterning a substrate on which a plurality of lower layer patterns are arranged so as to capture a plurality of lower layer patterns within the field of view, and a position of each lower layer pattern. A comparison target image in which a feature mark belonging to at least a partial area of each of the lower layer patterns is extracted by calculating a positional deviation amount of each lower layer pattern by template measurement and calculating a positional deviation amount by template measurement and functioning as correction means for correcting drawing data Based on the above, template matching is performed to function as a measuring unit so as to detect misalignment.

  According to the present invention, alignment adjustment can be performed quickly and appropriately even on a substrate on which a large number of patterns are formed.

It is a block diagram of the exposure apparatus which is this embodiment. It is the figure which showed an example of the support substrate (temporary board | substrate) shape | molded in FO-WLP. It is the figure which showed the flowchart of alignment adjustment and a drawing process. It is the figure which showed the imaging range of the camera. It is the figure which showed the feature extraction of the semiconductor chip. It is the figure which defined a partial area of the semiconductor chip as a comparison object area. It is the figure which showed the data correction at the time of rewiring formation. It is the figure which showed the multichip.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram of an exposure apparatus according to this embodiment.

  The exposure apparatus 10 is a maskless exposure apparatus capable of forming a circuit pattern by irradiating light onto a substrate W, and includes an exposure head 18 provided with a DMD (Digital Micro-mirror Device) 22. The substrate W is mounted on the drawing table 12, and an XY coordinate system is defined on the drawing table 12 along the main scanning direction (X direction) and the sub-scanning direction (Y direction).

  The exposure head 18 includes an illumination optical system and an imaging optical system (not shown here) together with the DMD 22. Light emitted from a light source 20 (laser or discharge lamp) provided in the exposure apparatus 10 is guided to the DMD 22 by an illumination optical system.

  The DMD 22 is a light modulation element array in which minute rectangular micromirrors (here, several μm to several tens of μm) are two-dimensionally arranged in a matrix, and is composed of, for example, a 1024 × 768 micromirror. Each micromirror has one of a first posture (ON state) for reflecting the beam from the light source 20 in the direction of the exposure surface of the substrate W and a second posture (OFF state) for reflecting the beam in the direction outside the exposure surface. And the posture is switched according to the control signal (exposure data).

  In the DMD 22, each micromirror is selectively ON / OFF controlled, and the light reflected on the micromirror in the ON state passes through the imaging optical system and irradiates the substrate W. Therefore, the light irradiated to the substrate W is composed of a light beam selectively reflected by each micromirror, and becomes pattern light according to a circuit pattern to be formed on the exposure surface.

  When all the micromirrors are in the ON state, an exposure area serving as a rectangular projection area having a predetermined size is defined on the substrate W. For example, when the magnification of the imaging optical system 23 is 1, the size of the exposure area matches the size of the DMD 22. The substrate W is exposed by moving (scanning) the exposure area relatively on the substrate W while moving the drawing table 12 in the X direction by the table driving mechanism 15.

  The exposure head 18 is arranged such that the exposure area by the DMD 22 is inclined by a predetermined minute angle with respect to the scanning direction. As a result, the locus of the microprojection areas of the micromirrors arranged along the main scanning direction is shifted by a microdistance along the subscanning direction.

  Regarding the exposure operation, since multiple exposure is performed, the exposure pitch (exposure operation time interval) is determined so that the microprojection areas of the micromirrors overlap each other. As a result, the exposure area is shifted from the main scanning direction by a minute distance so that the center points (exposure points) of the minute projection area at the time of exposure shot are scattered in one minute projection area (cell). become. As a result, a pattern is formed with a resolution smaller than the cell size.

  As the exposure area moves relative to the substrate W continuously or intermittently along the main scanning direction (X direction), a pattern is formed on the substrate W along the main scanning direction. When the multiple exposure operation along one scanning band is completed from end to end of the substrate W, the multiple exposure operation along the next scanning band is performed. By completely exposing the substrate W, the drawing process is completed.

  A controller 30 connected to an external workstation (not shown) controls the drawing process and outputs a control signal to the DMD driving circuit 24, a read address control circuit (not shown), the light source driving unit 21, and the like. A program for controlling the exposure operation is stored in advance in a ROM (not shown) in the controller 30.

  The pattern data sent as CAD / CAM data from the workstation is vector data which is coordinate data, and the raster conversion circuit 26 converts the vector data into raster data. Raster data represented by binary data of 1 or 0 determines the position of each micromirror to be in an ON state or an OFF state. The generated raster data is sent to the DMD driving circuit 24 in accordance with the exposure operation. The raster data read / write timing is controlled by a read address control circuit.

  Since the substrate W is thermally deformed, alignment adjustment is performed before performing multiple exposure. The camera 29 is arranged so as to image the substrate W on the drawing table 12, and the image magnification of the imaging target can be changed by a built-in focusing lens. Exposure control such as image magnification, AF processing, and aperture adjustment in the camera 29 is executed by the exposure control unit 31.

  The controller 30 controls the table driving mechanism 15 to control the scanning speed and the like while the camera 29 images the substrate W. The measurement circuit 27 detects the position of a feature point such as an alignment mark based on the image data captured by the camera 29. Note that a plurality of cameras may be arranged at predetermined intervals and photographed while being moved in parallel during alignment adjustment.

  The controller 30 performs alignment adjustment based on a positional deviation amount that is a difference between the position of the detected feature point and an ideal (design) reference position. Specifically, the pattern drawing position (drawing timing) is corrected according to the calculated amount of positional deviation.

  FIG. 2 is a diagram illustrating an example of a support substrate (temporary substrate) formed in FO-WLP.

  On a support substrate (hereinafter referred to as B in FIG. 1), semiconductor packages (hereinafter referred to as semiconductor chips) SC are arranged in a matrix at a predetermined pitch. Here, 125 × 160 semiconductor chips SC are arranged. Although the array is shown as being embedded in the resin support substrate W, in practice, 20,000 or more semiconductor chips SC may be arrayed. On the support substrate W, for example, semiconductor chips SC of 5 mm or less are arranged with a pitch of 10 mm or less.

  In FO-WLP, it is necessary to form a rewiring pattern on the resin portion that corresponds to the gap between adjacent semiconductor chips SC. However, the semiconductor chip SC has a random displacement amount due to the resin spreadability. If the actual position of the connection pad of the semiconductor chip SC is shifted from the design position, the resin portion of the semiconductor chip SC is not formed when the pattern is formed. A state occurs in which the wiring is not connected to the semiconductor chip SC.

  Therefore, alignment data is adjusted before drawing to correct drawing data. In the present embodiment, when detecting the amount of misalignment of each of the enormous number of semiconductor chips SC, it is performed by imaging with a wide field of view and template matching. This will be described below.

  FIG. 3 is a flowchart of the alignment adjustment and drawing processing. FIG. 4 is a diagram illustrating the imaging range of the camera. FIG. 5 is a diagram illustrating feature extraction of a semiconductor chip.

  When the substrate W is mounted on the drawing table 12, the image magnification of the camera 29 is controlled and the drawing table 12 is moved intermittently to perform camera scanning (S101). At this time, the image magnification is determined so that the plurality of semiconductor chips SC are within the camera field of view VF.

  In FIG. 4, the image magnification is determined so that six semiconductor chips SC can be imaged as a whole chip. This camera field of view VF is a range different from the band area BA that is the scanning area of the exposure area of the DMD 22, and is larger than the width of the band area BA. When the imaging of the six semiconductor chips SC is completed, the next six semiconductor chips SC are imaged at once and this is repeated. Further, the scanning speed is adjusted according to the complexity of the pattern.

  While moving the drawing table 12 and performing camera scanning, the image data sent from the camera 29 is acquired, and the area to be compared by template matching is extracted. As shown in FIG. The connection pad CP having a circular shape is extracted as a mark. The extraction (image recognition) of the connection pad CP is executed by a known image recognition process (S102, S103). At this time, after extracting the outline of the semiconductor chip SC within the camera field of view VF, an area TA (hereinafter referred to as a comparison target area) TA is extracted.

  In FIG. 5, the outline PC of the semiconductor chip SC is drawn. However, since the outline PC is simply a boundary line with the resin portion of the support substrate W, wiring is formed as image data sent to the measurement circuit 27. It is not possible to determine whether the line is a chip edge. Therefore, the outline of the semiconductor chip SC is extracted by edge detection or the like based on the chip size information input in advance.

  Then, an image TI of the comparison target area TA in which the connection pads CP of this semiconductor chip size are extracted as marks is determined as a template matching comparison target. In order to increase the alignment processing speed, a part of the area can be extracted as a comparison target area.

  FIG. 6 is a diagram in which the partial area is determined as a comparison target area. Here, it can be said that the comparison target area TA1 is determined so that template matching is performed on the image at the right corner of the comparison target area TA. Since the size of the comparison target area TA1 is small, the number of connection pads CP is reduced, and the template matching processing time can be shortened. The controller 30 can arbitrarily set the size and position of the comparison target area TA1 according to the complexity of the pattern by an input operation of the operator.

  When the comparison target area TA (or TA1) where the mutual positional relationship of the connection pads CP appears is extracted, a known template matching process is executed based on the template pattern of the semiconductor chip SC prepared in advance, and the connection pads The positional deviation amount of the semiconductor chip SC is calculated from the positional deviation amount of the CP (S104, S105).

  Here, the displacement and the rotation amount in the X- and Y-axis directions are detected and stored in the memory 32 as the positional deviation amount. When the amount of displacement is detected, the pattern data is corrected according to the position of each semiconductor chip SC (S106). When a semiconductor chip is generated in which the amount of positional deviation cannot be detected, the amount of positional deviation is obtained with reference to the adjacent pattern.

  Further, as another processing method when a semiconductor chip in which the displacement amount cannot be detected is generated, the operator of the exposure apparatus may determine the displacement amount by manual operation. While watching the image data displayed on the external monitor screen, the operator teaches the measurement circuit 27 the outline of the semiconductor chip in which the amount of misalignment cannot be detected using the outline detection assist function provided by the controller 30. The measurement circuit 27 measures the positional deviation amount of the semiconductor chip from which the positional deviation amount cannot be detected from the input contour. This processing may be executed collectively for the semiconductor chips for which the amount of misalignment cannot be detected after the misregistration detection (S105) of all the semiconductor chips on the substrate is completed.

  FIG. 7 is a diagram showing data correction at the time of rewiring formation. Since the semiconductor chip SC is at a randomly rotated position, the position of the connection pad is also deviated from the designed position. For this reason, the gap between the chips is divided as shown in FIG. 7 to calculate the amount of positional deviation of the resin portion, and the pattern position is corrected accordingly to connect the wiring and the connection pad CP. When the alignment adjustment of the entire support substrate W is completed by parallel processing of camera scanning and pattern data correction, a drawing process is executed (S107). During camera scanning, it is preferable to increase the scanning speed for a section without a pattern.

  As described above, according to the present embodiment, a plurality of semiconductor chips SC are captured in the field of view simultaneously, the outline of each semiconductor chip SC is extracted from the image, and the connection pad CP to be a mark is extracted. And the template image are compared to detect the amount of misalignment of each chip. Since a plurality of chips are imaged at a time and template matching of each chip is performed, alignment processing can be quickly performed even on a substrate on which a large number of chips are mounted.

  In this embodiment, the single chip type alignment method in which one semiconductor chip is mounted in one package has been described. However, alignment is similarly performed for a multichip in which a plurality of semiconductor chips are mounted in one package. It can be carried out.

  FIG. 8 shows a multichip. In the case of a multi-chip, after detecting the amount of positional deviation of all the semiconductor chips forming one package pattern, the alignment correction amount of the entire package is calculated. Therefore, when the imaging of the semiconductor chips constituting the multichip cannot be performed at once, the positional deviation amount is calculated after the imaging of all the chips is completed. At the time of alignment correction, a data correction amount is calculated for the resin mold region RM between chips.

  In the present embodiment, alignment processing for a substrate used in FO-WLP is shown, but it is also effective when stacking patterns. In addition, the characteristic marks necessary for template matching may be elements other than connection pads, components, wirings, and the like.

10 Exposure equipment 22 DMD
27 Measurement circuit (measurement unit)
29 Camera (imaging part)
30 controller (measurement unit, imaging unit)
31 Exposure control unit (imaging unit)

Claims (11)

In an exposure apparatus for patterning a substrate on which a large number of lower layer patterns are arranged,
An imaging unit that captures images so as to capture a plurality of lower layer patterns within the field of view among the plurality of lower layer patterns,
A measurement unit for measuring each lower layer pattern position;
A correction unit that calculates a positional deviation amount of each lower layer pattern by template matching and corrects drawing data;
An exposure apparatus, wherein the measurement unit performs template matching based on a comparison target image from which a feature mark belonging to at least a partial area of each lower layer pattern is extracted, and detects a positional deviation.   The exposure apparatus according to claim 1, wherein the measuring unit extracts a comparison target image after detecting an outline of each lower layer pattern.   The exposure apparatus according to claim 1, wherein the measurement unit can arbitrarily set an area of the comparison target image.   4. The exposure apparatus according to claim 1, wherein the measurement unit refers to a position shift amount of an adjacent lower layer pattern for a lower layer pattern in which the position shift cannot be detected. 5.   4. The lower layer pattern misregistration amount is determined in accordance with extraction of a lower layer pattern contour based on an operator's operation for the lower layer pattern in which the measurement unit cannot detect misregistration. Exposure equipment.   The measurement unit, for a multi-package area composed of two or more lower layer patterns, detects the amount of positional deviation of the lower layer patterns in the area after the imaging of all the lower layer patterns in the area is completed. The exposure apparatus according to any one of 1 to 5.   The exposure apparatus according to claim 1, wherein the measurement unit extracts a connection pad as a feature mark.   8. The exposure apparatus according to claim 1, wherein the substrate has a rectangular shape, and a plurality of lower layer patterns are arranged on the entire substrate.   The exposure apparatus according to claim 1, wherein the substrate is a support substrate formed based on FO-WLP. An alignment method of an exposure apparatus for patterning on a substrate on which a number of lower layer patterns are arranged,
Imaging to capture a plurality of lower layer patterns in the field of view among the many lower layer patterns,
Measure each lower layer pattern position,
An exposure method for calculating a positional deviation amount of each lower layer pattern by template matching and correcting drawing data,
An alignment method for an exposure apparatus, comprising: performing template matching based on a comparison target image from which a feature mark belonging to at least a partial area of each lower layer pattern is extracted to detect a positional deviation. An exposure apparatus for patterning a substrate on which a number of lower layer patterns are arranged,
An imaging means for imaging so as to capture a plurality of lower layer patterns within the field of view among the plurality of lower layer patterns;
A measuring means for measuring each lower layer pattern position;
Calculate the amount of positional deviation of each lower layer pattern by template matching, function as a correction means to correct the drawing data,
A program that functions as the measurement unit so as to perform template matching based on a comparison target image from which feature marks belonging to at least a partial area of each lower layer pattern are extracted, and detect a positional deviation.

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