JP2017050568A - 配線基板の製造方法 - Google Patents
配線基板の製造方法 Download PDFInfo
- Publication number
- JP2017050568A JP2017050568A JP2016233772A JP2016233772A JP2017050568A JP 2017050568 A JP2017050568 A JP 2017050568A JP 2016233772 A JP2016233772 A JP 2016233772A JP 2016233772 A JP2016233772 A JP 2016233772A JP 2017050568 A JP2017050568 A JP 2017050568A
- Authority
- JP
- Japan
- Prior art keywords
- core
- build
- wiring conductor
- wiring
- insulating layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
2 コア絶縁層
3 コア配線導体
4 ビア導体
5 ビルドアップ絶縁層
6 ビルドアップ配線導体
D5 ダミーのビルドアップ絶縁層
D6 ダミーのビルドアップ配線導体
Claims (1)
- 表面に銅箔から成るコア配線導体が埋入された多数のコア絶縁層が積層されており、前記各コア絶縁層を挟んで上下に位置する前記コア配線導体同士が前記各コア絶縁層を貫通するビアホール内に充填された導電性ペーストの硬化物から成るビア導体で電気的に接続されているとともに上面中央部に凹みを有するコア基板の表面に、ビルドアップ絶縁層とビルドアップ配線導体とが積層されて成る配線基板の製造方法であって、前記コア基板の上面に、ダミーのビルドアップ絶縁層を、前記凹みを埋めるとともに、その上面が平坦となるように積層し、該ダミーのビルドアップ絶縁層上に、コア基板上面の最表層のコア配線導体と接続されたダミーのビルドアップ配線導体を、該ダミーのビルドアップ配線導体と前記最表層のコア配線導体とのうち、互いに接続されたもの同士のみが上下に重なるように形成し、該ダミーのビルドアップ絶縁層およびダミーの配線導体の上に、ビルドアップ絶縁層およびビルドアップ配線導体を積層することを特徴とする配線基板の製造方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2016233772A JP6259054B2 (ja) | 2016-12-01 | 2016-12-01 | 配線基板の製造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2016233772A JP6259054B2 (ja) | 2016-12-01 | 2016-12-01 | 配線基板の製造方法 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2014015471A Division JP6062872B2 (ja) | 2014-01-30 | 2014-01-30 | 配線基板 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2017050568A true JP2017050568A (ja) | 2017-03-09 |
JP6259054B2 JP6259054B2 (ja) | 2018-01-10 |
Family
ID=58280313
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2016233772A Expired - Fee Related JP6259054B2 (ja) | 2016-12-01 | 2016-12-01 | 配線基板の製造方法 |
Country Status (1)
Country | Link |
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JP (1) | JP6259054B2 (ja) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007266197A (ja) * | 2006-03-28 | 2007-10-11 | Ngk Spark Plug Co Ltd | 配線基板 |
JP2010157600A (ja) * | 2008-12-26 | 2010-07-15 | Kyocer Slc Technologies Corp | 配線基板の製造方法 |
JP2010171413A (ja) * | 2008-12-26 | 2010-08-05 | Ngk Spark Plug Co Ltd | 部品内蔵配線基板の製造方法 |
-
2016
- 2016-12-01 JP JP2016233772A patent/JP6259054B2/ja not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007266197A (ja) * | 2006-03-28 | 2007-10-11 | Ngk Spark Plug Co Ltd | 配線基板 |
JP2010157600A (ja) * | 2008-12-26 | 2010-07-15 | Kyocer Slc Technologies Corp | 配線基板の製造方法 |
JP2010171413A (ja) * | 2008-12-26 | 2010-08-05 | Ngk Spark Plug Co Ltd | 部品内蔵配線基板の製造方法 |
Also Published As
Publication number | Publication date |
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JP6259054B2 (ja) | 2018-01-10 |
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