JP2017045457A5 - - Google Patents

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Publication number
JP2017045457A5
JP2017045457A5 JP2016162674A JP2016162674A JP2017045457A5 JP 2017045457 A5 JP2017045457 A5 JP 2017045457A5 JP 2016162674 A JP2016162674 A JP 2016162674A JP 2016162674 A JP2016162674 A JP 2016162674A JP 2017045457 A5 JP2017045457 A5 JP 2017045457A5
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JP
Japan
Prior art keywords
cache
memory
dram
controller
transaction
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2016162674A
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English (en)
Japanese (ja)
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JP2017045457A (ja
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Publication date
Priority claimed from US14/947,145 external-priority patent/US20170060434A1/en
Application filed filed Critical
Publication of JP2017045457A publication Critical patent/JP2017045457A/ja
Publication of JP2017045457A5 publication Critical patent/JP2017045457A5/ja
Pending legal-status Critical Current

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JP2016162674A 2015-08-27 2016-08-23 トランザクション基盤のハイブリッドメモリモジュール、及びそれを動作させる方法 Pending JP2017045457A (ja)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201562210939P 2015-08-27 2015-08-27
US62/210939 2015-08-27
US14/947,145 US20170060434A1 (en) 2015-08-27 2015-11-20 Transaction-based hybrid memory module
US14/947145 2015-11-20

Publications (2)

Publication Number Publication Date
JP2017045457A JP2017045457A (ja) 2017-03-02
JP2017045457A5 true JP2017045457A5 (enExample) 2019-08-29

Family

ID=58104058

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2016162674A Pending JP2017045457A (ja) 2015-08-27 2016-08-23 トランザクション基盤のハイブリッドメモリモジュール、及びそれを動作させる方法

Country Status (5)

Country Link
US (1) US20170060434A1 (enExample)
JP (1) JP2017045457A (enExample)
KR (1) KR20170026114A (enExample)
CN (1) CN106484628A (enExample)
TW (1) TW201710910A (enExample)

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US10482013B2 (en) * 2014-09-30 2019-11-19 Hewlett Packard Enterprise Development Lp Eliding memory page writes upon eviction after page modification
US10387315B2 (en) * 2016-01-25 2019-08-20 Advanced Micro Devices, Inc. Region migration cache
US9830086B2 (en) * 2016-03-03 2017-11-28 Samsung Electronics Co., Ltd. Hybrid memory controller for arbitrating access to volatile and non-volatile memories in a hybrid memory group
US11080185B2 (en) 2017-06-15 2021-08-03 Rambus Inc. Hybrid memory module
KR102319189B1 (ko) 2017-06-21 2021-10-28 삼성전자주식회사 스토리지 장치, 이를 포함하는 스토리지 시스템 및 스토리지 장치의 동작 방법
CN107844436B (zh) * 2017-11-02 2021-07-16 郑州云海信息技术有限公司 一种缓存中脏数据的组织管理方法、系统及存储系统
KR102101622B1 (ko) * 2017-12-06 2020-04-17 주식회사 멤레이 메모리 제어 장치 및 이를 포함하는 컴퓨팅 디바이스
US10929291B2 (en) * 2017-12-06 2021-02-23 MemRay Corporation Memory controlling device and computing device including the same
CN108052296B (zh) * 2017-12-30 2021-02-19 惠龙易通国际物流股份有限公司 一种数据读取方法、设备及计算机存储介质
US10990463B2 (en) 2018-03-27 2021-04-27 Samsung Electronics Co., Ltd. Semiconductor memory module and memory system including the same
KR102538679B1 (ko) 2018-04-06 2023-06-02 삼성전자주식회사 메모리 시스템 및 메모리 시스템의 동작 방법
US10977198B2 (en) * 2018-09-12 2021-04-13 Micron Technology, Inc. Hybrid memory system interface
CN111399750B (zh) * 2019-01-03 2023-05-26 慧荣科技股份有限公司 闪存数据写入方法及计算机可读取存储介质
US11199991B2 (en) 2019-01-03 2021-12-14 Silicon Motion, Inc. Method and apparatus for controlling different types of storage units
CN109960471B (zh) * 2019-03-29 2022-06-03 深圳大学 数据存储方法、装置、设备以及存储介质
KR20220086785A (ko) * 2020-12-16 2022-06-24 삼성전자주식회사 트랜잭션 가속기의 동작 방법. 트랜잭션 가속기를 포함하는 컴퓨팅 장치의 동작 방법, 그리고 트랜잭션 가속기를 포함하는 컴퓨팅 장치
KR102560109B1 (ko) 2023-03-20 2023-07-27 메티스엑스 주식회사 바이트 어드레서블 장치 및 이를 포함하는 컴퓨팅 시스템
US12656954B2 (en) * 2023-03-21 2026-06-16 Micron Technology, Inc. Compute express link DRAM + NAND system solution

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KR101085406B1 (ko) * 2004-02-16 2011-11-21 삼성전자주식회사 불 휘발성 메모리를 제어하기 위한 컨트롤러
JP2006127110A (ja) * 2004-10-28 2006-05-18 Canon Inc Dramメモリアクセス制御手法、および手段
US8397013B1 (en) * 2006-10-05 2013-03-12 Google Inc. Hybrid memory module
US20070136523A1 (en) * 2005-12-08 2007-06-14 Bonella Randy M Advanced dynamic disk memory module special operations
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US7730268B2 (en) * 2006-08-18 2010-06-01 Cypress Semiconductor Corporation Multiprocessor system having an input/output (I/O) bridge circuit for transferring data between volatile and non-volatile memory
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