JP2017034115A - Printed circuit board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a printed circuit board capable of suppressing performance degradation of a bypass circuit including a capacitor.SOLUTION: A printed circuit board includes wiring lines W1a, W2a formed as a part of a wiring layer WL1, a bypass capacitor 13 having one electrode terminal connected electrically with one end of the wiring line W1a, a wiring line W9 formed as a part of a wiring layer WL2, an interlayer connection hole Ha for conducting one end of the wiring line W1a with one end of the wiring line W9, and an interlayer connection hole Hb for conducting one end of the wiring line W2a with the other end of the wiring line W9. The wiring lines W1a, W2a are connected in series via the wiring line W9, and extending in parallel with each other so as to couple magnetically.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a printed circuit board having a noise filter.

  A noise filter is mounted on the printed circuit board in order to remove high frequency band electromagnetic noise leaking from circuit elements such as an LSI (Large Scale Integrated Circuit) or an IC (Integrated Circuit). FIG. 7 is a diagram illustrating an example of a conventional noise filter mounted on the printed circuit board 100. A circuit element 101, a connector circuit 102, a bypass capacitor 104, a power supply wiring pattern 111 and a ground wiring pattern 112 are mounted on the printed circuit board 100.

  As shown in FIG. 7, one end of the power supply wiring pattern 111 is connected to the circuit element 101, and the other end of the power supply wiring pattern 111 is connected to the external power supply 103 via the connector circuit 102. One end of the bypass capacitor 104 is connected to the power supply wiring pattern 111 via the lead wiring 113, and the other end of the bypass capacitor 104 is connected to the ground wiring pattern 112 via the lead wiring 114. If the high-frequency electromagnetic noise generated in the circuit element 101 propagates to the external power supply 103, for example, the power supply voltage fluctuates to cause malfunction of the circuit element 101 or other circuit elements (not shown) that receive power supply from the external power supply 103. ) May cause a problem of malfunction. The bypass capacitor 104 functions as a noise filter for high frequency electromagnetic noise, and can bypass the high frequency electromagnetic noise propagating through the power supply wiring pattern 111 to the ground wiring pattern 112. As a result, power quality can be improved.

  However, the bypass capacitor 104 has a parasitic inductance. Since the bypass performance of the bypass capacitor 104 deteriorates due to this parasitic inductance, there is a problem that high-frequency electromagnetic noise leaking to the external power supply 103 cannot be sufficiently reduced. For this problem, for example, the prior art disclosed in Japanese Patent Application Laid-Open No. 2005-303193 is known. Since the chip capacitor array disclosed in Patent Document 1 includes a plurality of capacitors connected in parallel with the common external electrode, the parasitic inductance of the chip capacitor array itself can be reduced.

Japanese Patent Laying-Open No. 2005-303193 (for example, FIGS. 1 to 4 and paragraphs 0020 to 0030)

  However, the conventional technology of Patent Document 1 cannot suppress the deterioration of the bypass performance due to the parasitic inductance of the wiring used for mounting the bypass capacitor.

  In view of the above, an object of the present invention is to provide a printed circuit board that can suppress performance deterioration of a bypass circuit including a capacitor.

  A printed circuit board according to an aspect of the present invention is a printed circuit board having a structure in which a first wiring layer and a second wiring layer are stacked with an insulating layer interposed therebetween, and as a part of the first wiring layer The first and second wiring lines formed and the first wiring layer are disposed, have a pair of electrode terminals, and one of the pair of electrode terminals is the first electrode terminal. A bypass capacitor electrically connected to one end of the wiring line, a third wiring line formed as a part of the second wiring layer, and another part of the second wiring layer A first interlayer connection hole formed through the insulating layer and electrically connecting the one end of the first wiring line to one end of the third wiring line; and the insulation Forming one end of the second wiring line. A second interlayer connection hole that is electrically connected to the other end of the third wiring line and the insulating layer are formed so that the other electrode terminal of the pair of electrode terminals is electrically connected to the ground conductor surface. The first and second wiring lines are opposed to each other so as to be magnetically coupled and extend in parallel to each other, and the first wiring lines The one end of the line faces the other end of the second wiring line, and the one end of the second wiring line faces the other end of the first wiring line. And

  According to the present invention, the first wiring line and the second wiring line are connected in series via the third wiring line, and form a mutual inductance by magnetic coupling. The negative inductance appearing equivalent to the mutual inductance can cancel the parasitic inductance of the bypass circuit including the bypass capacitor. Therefore, the performance deterioration of the bypass circuit can be suppressed without adding new electronic components.

It is a figure which shows roughly an example of the cross-section of the double-sided printed circuit board of Embodiment 1 which concerns on this invention. (A), (B) is a top view of the wiring layer which comprises the double-sided printed circuit board of Embodiment 1. FIG. (A) is a figure which shows the mutual induction circuit containing a pair of parasitic inductor, (B) is a figure which shows the T type | mold equivalent circuit of this mutual induction circuit. FIG. 3 is a diagram schematically showing a main part of an equivalent circuit of the double-sided printed circuit board according to the first embodiment. 4 is a plan view showing an example of a magnetic body according to Embodiment 1. FIG. It is a figure which shows schematically the principal part of the cross-sectional structure in the VI-VI line of FIG. It is a figure which shows an example of the conventional noise filter mounted in the printed circuit board.

  Hereinafter, various embodiments according to the present invention will be described in detail with reference to the drawings. In addition, the component which attached | subjected the same code | symbol in drawing shall have the same function and the same structure.

Embodiment 1 FIG.
FIG. 1 is a diagram schematically showing an example of a cross-sectional structure of a double-sided printed circuit board 1 according to Embodiment 1 of the present invention. FIGS. 2A and 2B constitute the double-sided printed circuit board 1. It is a top view of a wiring layer. 2A and 2B show planar configurations of the upper wiring layer WL1 and the lower wiring layer WL2 when viewed from the same direction.

  As shown in FIG. 1, the double-sided printed circuit board 1 includes an upper wiring layer WL1 that is a first wiring layer, a lower wiring layer WL2 that is a second wiring layer, and these upper wiring layer WL1 and lower wiring layer WL2. Between the insulating layer IL and the magnetic body 23 provided on the upper wiring layer WL1. The double-sided printed circuit board 1 has a structure in which an upper wiring layer WL1, an insulating layer IL, and a lower wiring layer WL2 are stacked in the thickness direction (vertical direction in the drawing). Here, the insulating layer IL is made of an electrically insulating material such as a non-conductive resin.

  As shown in FIGS. 2A and 2B, vias Ha, Hb, Hc, Hd, and He which are interlayer connection holes penetrating the insulating layer IL are formed in the double-sided printed circuit board 1. The vias Ha, Hb, Hc, Hd, and He are filled with, for example, a conductive paste, or a metal layer such as copper is formed by electroless plating. Therefore, the vias Ha, Hb, Hc, Hd and He have conductivity. Therefore, the vias Ha, Hb, Hc, Hd, and He can electrically connect the upper wiring layer WL1 and the lower wiring layer WL2.

  The upper wiring layer WL1 is formed on the upper surface of both surfaces in the thickness direction of the insulating layer IL. As shown in FIG. 2A, the upper wiring layer WL1 is electrically connected to a circuit element 10 that is an electronic component such as an LSI or an IC and an external power source 12 such as a DC-DC converter or an in-vehicle battery. A connector circuit 11 and a bypass capacitor 13 for removing electromagnetic noise are provided.

  Further, as the wiring pattern constituting the upper wiring layer WL1, the power supply wiring pattern W1 connected to the power supply terminal of the circuit element 10 and the power supply electrically connected to the plus terminal of the external power supply 12 via the connector circuit 11 are used. A wiring pattern W2, a lead wiring W3 that electrically connects one electrode terminal of the bypass capacitor 13 to the power supply wiring pattern W1, a wiring W4 that electrically connects the other electrode terminal of the bypass capacitor 13 to the via Hc, A ground wiring W5 that electrically connects the ground terminal of the circuit element 10 to the via Hd and a ground wiring W6 that electrically connects the ground terminal of the connector circuit 11 to the via He are formed. The power supply wiring patterns W1 and W2, the lead-out wiring W3, the wiring W4, and the ground wirings W5 and W6 may be made of a conductor such as copper foil.

  On the other hand, the lower wiring layer WL2 is formed on the lower surface of the insulating layer IL as shown in FIG. As shown in FIG. 2B, the wiring pattern constituting the lower wiring layer WL2 includes a wiring line W9 that electrically connects the vias Ha and Hb, and a ground conductor surface 22 that is electrically grounded. Consists of. The ground conductor surface 22 is electrically insulated from the wiring line W9. The wiring line W9 and the ground conductor surface 22 may be made of a conductor such as copper foil. The negative terminal of the external power supply 12 is connected to the ground conductor surface 22 via the connector circuit 11, the ground wiring W6, and the via He in the upper wiring layer WL1.

  The wiring line W9 has a bent portion that is bent at a right angle as shown in FIG. 2B, but is not limited to this. Instead of such a wiring line W9, a linear wiring line or a circular or elliptical wiring line may be adopted.

  Next, referring to FIG. 2A, in the upper wiring layer WL1, one power wiring pattern W1 is opposed to the other power wiring pattern W2 and is formed at a position close to the first wiring line W1a. The other power wiring pattern W2 includes a second wiring line W2a formed at a position facing and close to one power wiring pattern W1. These first and second wiring lines W1a, W2a (hereinafter referred to as “proximity wiring lines W1a, W2a”) are formed so as to face each other and extend in parallel to each other. The wiring line W9 of the lower wiring layer WL2 is a third wiring line for connecting these adjacent wiring lines W1a and W2a in series.

  As shown in FIG. 2A, the left end portion of the adjacent wiring line W1a is electrically connected to the via Ha. Thereby, as shown in FIG. 2B, the adjacent wiring line W1a is electrically connected to the left end portion of the wiring line W9 of the lower wiring layer WL2 through the via Ha. One end portion on the right side of the other adjacent wiring line W2a is electrically connected to the via Hb as shown in FIG. Thereby, as shown in FIG. 2B, the adjacent wiring line W2a is electrically connected to the other right end portion of the wiring line W9 of the lower wiring layer WL2 through the via Hb. Accordingly, the ends of the adjacent wiring lines W1a and W2a are connected in series via the via Ha, the wiring line W9, and the via Hb. Therefore, the direction of the current flowing through the adjacent wiring lines W1a and W2a is the same direction. Further, the directions of magnetic fluxes generated in the adjacent wiring lines W1a and W2a due to the parasitic inductance are almost the same.

  Further, the left end portion of the adjacent wiring line W1a is electrically connected to one electrode terminal of the bypass capacitor 13 through the lead-out wiring W3 as shown in FIG. The other electrode terminal of the bypass capacitor 13 is electrically connected to the via Hc through the wiring W4. Thereby, the other electrode terminal is electrically connected to the ground conductor surface 22 of the lower wiring layer WL2 through the via Hc. On the other hand, the other end portion on the right side of the adjacent wiring line W1a is a portion facing the right end portion (portion connected to the via Hb) of the adjacent wiring line W2a, which is not clearly shown in FIG. It is electrically connected to the power supply terminal of the circuit element 10 through another wiring portion of the line W1. Further, the other end portion on the left side of the proximity wiring line W2a is also a portion facing the left end portion (portion connected to the via Ha) of the proximity wiring line W1a, although not clearly shown in FIG. It is electrically connected to the external power source 12 via the other wiring portion of the line W2 and the connector circuit 11.

The noise filter of the present embodiment is configured to include the adjacent wiring lines W1a and W2a and the bypass capacitor 13. The adjacent wiring lines W1a and W2a have a pair of parasitic inductors that are magnetically coupled to each other to cause mutual induction. FIG. 3A is a diagram schematically showing a mutual induction circuit including the parasitic inductor 41 of the adjacent wiring line W1a and the parasitic inductor 42 of the adjacent wiring line W2a, and FIG. It is a figure which shows a T type | mold equivalent circuit. When currents i ₁ and i ₂ flow into the parasitic inductors 41 and 42 from the nodes a1 and a2, respectively, a mutual inductance −M is formed between the parasitic inductors 41 and 42. If the nodes b1 and b2 have a common potential, the mutual induction circuit includes three inductors 51, 52, and 53 having three inductances L1 + M, L2 + M, and −M, as shown in FIG. It can be considered as an equivalent circuit. This type of equivalent circuit is called a T-type equivalent circuit.

Here, when the adjacent wiring lines W1a and W2a are opposed to each other by a distance d (unit: m) and the line lengths of the adjacent wiring lines W1a and W2a are both R (unit: m), the adjacent wiring line W1a. , W2a, the mutual inductance magnitude M (unit: H = Wb / A) is given by, for example, the following approximate expression (1).
M = (μ ₀ / (2π)) × R × (ln (2R / d) −1) (1)

Here, μ ₀ is the vacuum permeability (= 4π × 10 ⁻⁷ H / m). The mutual inductance can be designed based on this equation (1).

The mutual inductance magnitude M between the adjacent wiring lines W1a and W2a is also given by the following equation (2).
M = k × (L1 × L2) ^1/2 (2)

  Here, k is a coupling coefficient.

FIG. 4 is a diagram schematically showing a main part of an equivalent circuit of the double-sided printed circuit board 1 having a noise filter. The equivalent circuit shown in FIG. 4 includes a circuit element 10, the above-described T-type equivalent circuit, a bypass capacitor 13, a parasitic inductor 54 having a wiring inductance L4, and a connector circuit 11. The equivalent inductance of the inductor 51 is L1 + M, and the equivalent inductance of the inductor 52 is L2 + M. The bypass capacitor 13 includes a capacitor component 13C having a capacitance C and a parasitic inductor 13 _ESL having a residual inductance Lp that is an equivalent series inductance (ESL). Here, the parasitic inductor 54 is formed by the via Hc in FIGS. In FIG. 4, for convenience of explanation, the display of other circuit elements (for example, the resistance component and parasitic inductor component of the lead-out wiring W3) is omitted.

The bypass circuit of the present embodiment includes the lead-out wiring W3, the bypass capacitor 13, the wiring W4, and the via Hc shown in FIG. In this bypass circuit, when the adjacent wiring lines W1a and W2a are magnetically coupled, an inductor 53 having a negative inductance -M appears equivalently as shown in FIG. That is, the inductor 53 is equivalently connected to the series connection point Np between the inductors 51 and 52. Therefore, at this time, in the bypass circuit, the inductor 53 having the negative inductance −M, the capacitor component 13C, and the parasitic inductor 13 _ESL are connected in series.

  Here, for the wiring inductance L4 of the via Hc, the wiring inductance L4 can be approximately calculated based on the dimensions (for example, length and via diameter) of the via Hc. Further, the residual inductance Lp can be calculated by measuring the characteristics of the bypass capacitor 13.

  Therefore, the impedance of the bypass circuit is set to the capacitor component 13C by designing the inductance -M so that the impedance cancels out with respect to the negative inductance -M, the wiring inductance L4 of the via Hc, and the residual inductance Lp of the bypass capacitor 13. It can be equivalent to only impedance. For example, it is possible to design using the above equation (1) so that the negative inductance −M becomes an optimum value. Thereby, since the bypass path in the bypass circuit substantially does not include an inductance component, it is possible to prevent the bypass performance from deteriorating even if the frequency of electromagnetic noise propagating through the power supply wiring pattern W1 is high.

  Here, it is also possible to design the inductance -M in consideration of the parasitic inductance of the lead-out wiring W3 and the wiring W4 used for mounting the bypass capacitor 13.

  Next, the magnetic body 23 shown in FIG. 1 will be described. The magnetic body 23 is disposed in the vicinity of the adjacent wiring lines W1a and W2a, and is disposed at least in a region between the adjacent wiring lines W1a and W2a in plan view. Thereby, a part of the magnetic path of the magnetic flux generated between the adjacent wiring lines W1a and W2a can be confined inside the magnetic body 23.

  FIG. 5 is a plan view showing an example of the magnetic body 23 provided on the upper wiring layer WL1, and FIG. 6 is a diagram schematically showing the main part of the cross-sectional structure taken along the line VI-VI in FIG. As shown in FIGS. 5 and 6, the magnetic body 23 is disposed so as to abut against the adjacent wiring lines W1a and W2a and cover the adjacent wiring lines W1a and W2a. Thereby, a magnetic path through which the magnetic flux MF generated between the adjacent wiring lines W1a and W2a passes is formed inside the magnetic body 23. When all of the magnetic flux generated from one of the adjacent wiring lines W1a and W2a is linked to the other side without leaking into the air, it is between the parasitic inductors 41 and 42 of the adjacent wiring lines W1a and W2a. The coupling coefficient k is the highest value “1”. By disposing the magnetic body 23 in the vicinity of the adjacent wiring lines W1a and W2a, the magnetic flux MF is concentrated inside the magnetic body 23, so that the amount of magnetic flux leaking into the air can be reduced. As a result, the coupling coefficient k approaches the value “1”, and the magnitude M of the mutual inductance is increased by the above equation (2). Therefore, the self-inductances L1 and L2 can be set to small values in accordance with the increase in the coupling coefficient k. Thereby, the line length R of the adjacent wiring lines W1a and W2a can be shortened. Therefore, the dimensions of the adjacent wiring lines W1a and W2a necessary for obtaining the inductance -M can be reduced.

  As the magnetic body 23, a ferrite magnetic body having a high magnetic permeability with respect to a high frequency signal of several MHz or more is preferable. For example, a resin sheet in which soft magnetic metal powder is dispersed or a ferrite plating film having a thickness of about several μm can be used as the magnetic body 23.

  As described above, in the double-sided printed circuit board 1 of the first embodiment, the adjacent wiring lines W1a and W2a are connected in series via the wiring line W9 and face each other so as to form a mutual inductance by magnetic coupling. And it extends in the same direction. The parasitic inductance of the entire bypass circuit including the bypass capacitor 13 can be canceled by the negative inductance −M that appears equivalently corresponding to the magnetic coupling. Therefore, it is possible to suppress deterioration of the bypass performance of the bypass capacitor 13 without adding new electronic components. Therefore, electromagnetic noise propagating through the power supply wiring pattern W1 can be effectively removed.

  Here, in order to cancel the parasitic inductance of the bypass circuit, it is conceivable to additionally mount an electronic component such as an inductor. However, the addition of a new electronic component may increase the manufacturing cost of the printed circuit board, and the new electronic component may adversely affect other wiring or other electronic components on the printed circuit board. There is. The double-sided printed circuit board 1 according to the present embodiment can suppress the deterioration of the bypass performance without additionally mounting such electronic components.

  Further, as shown in FIG. 2B, since the wiring line W9 that connects the adjacent wiring lines W1a and W2a in series is formed in the lower wiring layer WL2 that is the same as the ground conductor surface 22, the number of wiring layers is reduced. Therefore, the double-sided printed circuit board 1 can be downsized.

  As mentioned above, although embodiment which concerns on this invention was described with reference to drawings, this embodiment is an illustration of this invention, Various forms other than this embodiment can also be employ | adopted. For example, although the above embodiment is a double-sided printed circuit board having a two-layer structure, the present invention is not limited to this. The present invention can be applied to a multilayer printed board having three or more wiring layers.

  In place of the external power supply 12, a power supply element that is an internal power supply may be mounted on the double-sided printed circuit board 1 of the above embodiment. Even in this case, it is possible to suppress the propagation of high-frequency electromagnetic noise to the mounted power supply element.

  Within the scope of the present invention, the constituent elements of the above embodiment can be freely combined, any constituent element of the above embodiment can be modified, or any constituent element of the above embodiment can be omitted.

  WL1 upper wiring layer, WL2 lower wiring layer, IL insulating layer, W1, W2 power supply wiring pattern, W1a, W2a proximity wiring line (first and second wiring lines), W9 wiring line, Ha, Hb, Hc, Hd, He via, MF magnetic flux, 1 double-sided printed circuit board, 10 circuit element, 11 connector circuit, 12 external power supply, 13 bypass capacitor, 22 ground conductor surface, 23 magnetic body, 41, 42 parasitic inductor, 51-53 inductor, 54 parasitic inductor .

Claims (6)

A printed circuit board having a structure in which a first wiring layer and a second wiring layer are laminated via an insulating layer,
First and second wiring lines formed as part of the first wiring layer;
It is arrange | positioned at the said 1st wiring layer, has a pair of electrode terminal, and one electrode terminal of the said pair of electrode terminals is electrically connected with the one end part of the said 1st wiring line. A bypass capacitor;
A third wiring line formed as part of the second wiring layer;
A ground conductor surface formed as another part of the second wiring layer;
A first interlayer connection hole formed through the insulating layer and electrically connecting the one end of the first wiring line to one end of the third wiring line;
A second interlayer connection hole formed through the insulating layer and electrically connecting one end of the second wiring line to the other end of the third wiring line;
A third interlayer connection hole formed through the insulating layer and electrically conducting the other electrode terminal of the pair of electrode terminals to the ground conductor surface;
The first and second wiring lines face each other so as to be magnetically coupled and extend in parallel with each other, and the one end portion of the first wiring line is connected to the second wiring line. Facing one end and the one end of the second wiring line is facing the other end of the first wiring line;
A printed circuit board characterized by that.   The printed circuit board according to claim 1, wherein the first wiring line and the second wiring line are magnetically coupled to form an equivalent negative inductance. The printed circuit board according to claim 1 or 2, further comprising a circuit element disposed in the first wiring layer,
The other end of the first wiring line is electrically connected to a power supply terminal of the circuit element,
The other end of the second wiring line is electrically connected to a power source.
A printed circuit board characterized by that. 4. The printed circuit board according to claim 1, further comprising a magnetic body that confines at least a part of a magnetic flux generated between the first wiring line and the second wiring line. 5. Prepared,
The magnetic body is disposed at least in a region between the first wiring line and the second wiring line in a plan view from the thickness direction of the first wiring layer.
A printed circuit board characterized by that.   5. The printed circuit board according to claim 4, wherein the magnetic body is disposed so as to cover the first wiring line and the second wiring line. 6.   6. The printed circuit board according to claim 4, wherein the magnetic body is a ferrite magnetic body.

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