JP2017017156A - Wiring board, thermal head, and method for producing wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a wiring board having high density and high reliability.SOLUTION: A wiring board includes an insulating substrate and a first conductive layer and a second conductive layer that are layered on the substrate. The second conductive layer has a lower ionization tendency than the first conductive layer. A stepped section or an alloy section in which the second conductive layer protrudes laterally beyond the first conductive layer is provided to the outer periphery of the boundary between the first conductive layer and the second conductive layer by performing etching processing one time on the first conductive layer and the second conductive layer.SELECTED DRAWING: Figure 4

Description

  The present invention relates to a wiring board, a thermal head, and a manufacturing method of the wiring board.

  In recent years, there has been a strong demand for miniaturization and weight reduction of wiring boards. In order to reduce the size and weight of the wiring board, it is important to realize high-density wiring, but there is a problem of migration in the wiring electrode. Migration (electrochemical migration) is a phenomenon in which metal ions are deposited on the cathode side when an electric field is applied between narrowly spaced electrodes, which extend to the anode side in a branch shape and short-circuit between conductor circuits. Say.

  Conventionally, a technique has been proposed that can suppress migration of wiring electrodes and prevent a substrate from being defective due to a short circuit of wiring electrode patterns (see Patent Document 1). In Patent Document 1, gold (Au) paste-like composition is printed on a substrate in a predetermined pattern, and silver (Ag) powder is conductorized on the thick film of the formed paste-like composition. A method for manufacturing a high-density wiring board is described in which a paste-like composition containing a material is printed with a size smaller than the predetermined pattern size.

JP-A-10-209611

  However, the high-density wiring board described in Patent Document 1 forms a predetermined pattern of Au paste-like composition by printing, and then has a size smaller than the predetermined pattern size of Ag paste-like composition. Since the pattern is formed by printing, it is not suitable for forming a fine pattern, and there is room for improvement.

The wiring board according to claim 1 includes an insulating substrate, and a first conductive layer and a second conductive layer laminated on the substrate, and the second conductive layer has a tendency to ionize more than the first conductive layer. The step portion or the alloy portion in which the second conductive layer protrudes to the side of the first conductive layer by one etching process on the first conductive layer and the second conductive layer is formed into the first conductive layer and the second conductive layer. Provided on the outer periphery of the boundary with the layer.
The wiring substrate according to claim 2 includes an insulating substrate, and a first conductive layer and a second conductive layer stacked on the substrate, and the second conductive layer is more ionized than the first conductive layer. And a stepped portion or an alloy portion in which the second conductive layer protrudes laterally from the first conductive layer is formed at the outer periphery of the boundary between the first conductive layer and the second conductive layer. The positional accuracy with respect to the two conductive layers or the width or interval of the laminated structure composed of the first conductive layer and the second conductive layer is set to 10 μm or less.
The wiring board according to claim 6 is provided on the same plane as the first conductive layer on the substrate, the insulating board, the first conductive layer provided on the board, and more than the first conductive layer. A second conductive layer having a low ionization tendency, and the second conductive layer has an overlapping portion that overlaps the edge of the first conductive layer and a non-overlapping portion that does not overlap the first conductive layer. The overlapping portion is configured as an electrode terminal.
The method for manufacturing a wiring board according to claim 8, wherein a first conductive layer and a second conductive layer having a smaller ionization tendency than the first conductive layer are stacked on an insulating substrate, and the first conductive layer is arranged. A stepped portion or an alloy portion in which the second conductive layer protrudes to the side of the first conductive layer is formed on the layer and the second conductive layer by a single etching process.

  ADVANTAGE OF THE INVENTION According to this invention, it is a reliable wiring board by which migration was suppressed, Comprising: A higher-density wiring board can be provided.

FIG. 3 is a schematic cross-sectional view showing a configuration of a thermal head. FIG. 6 is a schematic diagram showing a main part of a conventional thermal head. The schematic diagram which expands and shows the wire bonding part of FIG. FIG. 3 is a schematic diagram illustrating a main part of the thermal head according to the first embodiment. (A) is a plane schematic diagram of the wiring board before the etching process, (b) is a side cross-sectional schematic diagram of the wiring board before the etching process. (A) is a plane schematic diagram of the wiring board after an etching process, (b) is a side surface schematic diagram of the wiring board after an etching process. (A) is the elements on larger scale which show the VII part of Fig.6 (a), FIG.7 (b) is the viib-viib line schematic diagram of Fig.7 (a). The graph which shows the experimental result about the migration tolerance of a wiring board. The table | surface which shows the experimental result about the migration tolerance of a wiring board. The table | surface which shows the experimental result about the sulfidation tolerance of a wiring board. The schematic diagram which shows the principal part of the thermal head which concerns on 2nd Embodiment. (A) is a plane schematic diagram of the wiring board before the etching process, (b) is a side cross-sectional schematic diagram of the wiring board before the etching process. (A) is a plane schematic diagram of the wiring board after an etching process, (b) is a side surface schematic diagram of the wiring board after an etching process. (A) is the elements on larger scale which show the XIV part of Fig.13 (a), (b) is the xivb-xivb sectional schematic diagram of Fig.14 (a). The schematic diagram which shows the principal part of the thermal head which concerns on 3rd Embodiment.

-First embodiment-
FIG. 1 is a schematic cross-sectional view showing the configuration of the thermal head 100. FIG. 2 is a schematic diagram showing a main part of a conventional thermal head 100. FIG. 2A is a schematic plan view of a main part of the thermal head 100, and FIG. 2B is a schematic cross-sectional view of the main part of the thermal head 100. In addition, in the schematic plan view of FIG. 2A, for convenience of explanation, hatching that represents a cross section of each component in FIG. FIG. 3 is an enlarged schematic view showing the wire bonding portion of FIG. As shown in FIG. 1, the thermal head 100 includes a wiring board 50 and a printed wiring board 30 fixed on a support plate 32. On the printed wiring board 30, a driver IC 11 and a connector 31 for connecting the thermal head 100 to an external device that performs printing control and the like are provided.

  The wiring board 50 will be described in detail. The wiring board 50 has wirings and electrodes formed on the insulating substrate 12. The insulating substrate 12 is formed of an electrically insulating ceramic or the like. A glaze layer 13 made of glass or the like is formed on the entire top surface of the insulating substrate 12. The glaze layer 13 serves as a heat storage layer that shortens the time required to raise the temperature of the heating resistor 6 described later and enhances the thermal response characteristics of the thermal head 100.

  A common electrode 5 and a plurality of individual electrodes 8 are formed on the upper surface of the glaze layer 13. As shown in FIG. 2A, the common electrode 5 includes a rectangular electrode surface 5a in a plan view and a conveyance direction of thermal paper (not shown) from the electrode surface 5a (the x direction shown in FIG. 2A). It is made into the comb-tooth shape provided with the some strip | belt-shaped electrode 5b extended along. Each of the plurality of individual electrodes 8 has a strip shape extending along the transport direction x. The plurality of strip electrodes 5 b and the plurality of individual electrodes 8 are alternately arranged in the y direction orthogonal to the transport direction x.

A linear heating resistor 6 is formed on the common electrode 5 and the plurality of individual electrodes 8 by thick film printing or the like. The heating resistor 6 extends along the y direction so as to straddle the plurality of strip electrodes 5b and the plurality of individual electrodes 8. The heating resistor 6 is made of, for example, ruthenium oxide (RuO ₂ ).

  As shown in FIG. 1, one end of each individual electrode 8 is connected to a driver IC 11 via a gold wire 10. The gold wire 10 and the driver IC 11 are molded with a sealing resin 16 made of an epoxy resin material. A driver circuit (not shown) of the driver IC 22 causes a current to flow from the common electrode 5 to each individual electrode 8 via the heating resistor 6. As shown in FIG. 2A, when a current flows through the heating resistor 6 between the strip electrode 5b and the individual electrode 8 in the common electrode 5, the portion generates heat. When this heat is transmitted to thermal paper (not shown), the thermal paper develops color and a predetermined print image is formed on the thermal paper.

As shown in FIG. 2, in the thermal head 100, an insulating protective film 7 is formed on the entire surface of the insulating substrate 12 so as to cover the individual electrodes 8, the common electrode 5, and the heating resistor 6. The insulating protective film 7 is made of, for example, a PbO—SiO ₂ —ZrO ₂ glass material having electrical insulation. Since the heating resistor 6 is covered with the insulating protective film 7, the heat of the heating resistor 6 is transmitted to the thermal paper (not shown) through the insulating protective film 7.

  As shown in FIGS. 2 and 3, conventionally, a low purity gold-containing paste 14 is formed on an insulating substrate 12 using a low-purity gold-containing paste, and a high-purity gold-containing paste is used as an upper layer of the low-purity gold layer 14. The wire bonding part 9 which is an electrode terminal of the individual electrode 8 was formed by laminating the formed high purity gold layer 15.

  Gold (Au) is a metal that is less prone to migration than silver (Ag), but is very expensive and increases manufacturing costs. Therefore, it is conceivable to use a material that is less expensive than gold, such as silver, instead of gold, but there is a problem that migration is likely to occur compared to gold.

  FIG. 4 is a view similar to FIG. 3, and is a schematic view showing a main part of the thermal head 100A according to the first embodiment. 4A is a schematic plan view of the main part of the thermal head 100A, and FIG. 4B is a schematic cross-sectional view of the main part of the thermal head 100A.

  In this embodiment, in order to suppress the amount of expensive gold used, gold is used for a part of the wire bonding portion 18 of the individual electrode 8 and silver is used for the other part. Further, in each of the plurality of wire bonding portions 18 adjacent to each other in the y direction, the size of the second conductive layer made of gold is made larger than the size of the first conductive layer made of silver. Migration was suppressed by making the outermost peripheral portion a second conductive layer made of gold. Further, by utilizing the characteristic that the etching rates of the two types of conductive layers are different, the second conductive layer is protruded to the side of the first conductive layer by one etching process for the two types of conductive layers. The step portion 23 or the alloy layer (alloy portion) 24 is formed on the outer peripheral portion of the wire bonding portion 18. Since a fine pattern can be formed by etching, high-density wiring can be realized. Details will be described below.

  In the thermal head 100A according to the present embodiment, the configuration of the individual electrode 17 is different from that of the individual electrode 17 of the conventional thermal head 100, but the other configuration is the same, and thus the description thereof is omitted. The individual electrode 17 of the thermal head 100A according to the first embodiment includes a silver layer (first conductive layer) 20 in which a wiring portion extending in the x direction is made of silver. A wire bonding portion 18 to be wire-bonded is provided as an electrode terminal at an end portion of the individual electrode 17 in the x direction.

  In the present specification, an electrode terminal that is an exposed portion of the individual electrode 17 that is not covered with the insulating protective film 7 is referred to as a wire bonding portion 18. The wire bonding portion 18 has a laminated structure including a gold layer (second conductive layer) 19 made of gold provided on the insulating substrate 12 via the glaze layer 13 and a silver layer 20 provided on the gold layer 19. Has been. The gold layer 19 has a size that is slightly larger in area on the xy plane than the silver layer 20, and a stepped portion 23 or an alloy layer 24 is formed on the outer periphery of the boundary between the gold layer 19 and the silver layer 20.

  Since the wire bonding part 18 is not covered with the insulating protective film 7, it is necessary to suppress the occurrence of migration between adjacent wire bonding parts 18. In the present embodiment, in order to prevent the occurrence of migration, the outer peripheral size of the gold layer 19 is made slightly larger than the outer peripheral size of the silver layer 20 in the wire bonding portion 18 as described above. A method of forming such a wire bonding portion 18 will be described with reference to FIGS. In FIGS. 5 to 7, a simple shape is used for easy understanding. 5 to 7, the glaze layer is omitted.

(Gold layer and silver layer forming process)
FIG. 5A is a schematic plan view of the wiring board before the etching process, FIG. 5B is a schematic side sectional view of the wiring board before the etching process, and is cut along the line vb-vb in FIG. A cross section is shown. As shown in FIG. 5, a gold paste composition (for example, the gold content is 15 to 100% by weight) is extended in parallel to the short direction of the insulating substrate 1 on the rectangular flat insulating substrate 1. Printing is performed with an existing rectangular pattern. Thereafter, a silver paste-like composition (for example, the silver content is 15 to 100% by weight) is a rectangular pattern having a size slightly smaller than that of the insulating substrate 1 so as to cover the pattern of the gold paste-like composition. Print with. Then, the gold layer 2 and the silver layer 3 are formed by baking the insulating substrate 1 (for example, about 800 ° C.). By firing, a gold-silver alloy layer 4 is formed at the boundary between the gold layer 2 and the silver layer 3 (not shown in FIG. 5, see FIG. 7). That is, the gold layer 2 and the silver layer 3 are laminated and disposed on the insulating substrate 1 by printing and baking. In the present embodiment, since the above-described step portion 23 is not formed by printing, high accuracy is not required in this step.

(Photolithographic etching process)
In FIG. 5, a substantially H-shaped pattern as shown by a one-dot chain line is formed by photolithography. Thereafter, wet etching treatment is performed once, that is, by immersing the wiring board in the etching solution, the portions other than the portion surrounded by the alternate long and short dash line (substantially H-shaped pattern) shown in FIG. 5A are dissolved and removed. To do.

  Here, the gold constituting the gold layer 2 is a material having a smaller ionization tendency than the silver constituting the silver layer 3. For this reason, the dissolution rate (etching rate) of the gold layer 2 is slower than the dissolution rate (etching rate) of the silver layer 3. In this embodiment, a potassium iodide solution in which the mixing ratio of iodine, potassium iodide, and water is 1: 2: 10 (wt ratio) is used as an etching solution. In this case, the gold layer 2 and the silver layer 3 have a difference of about three times in the speed (side etching speed) at which the dissolution proceeds toward the side.

  6A is a schematic plan view of the wiring board after the etching process, FIG. 6B is a schematic side sectional view of the wiring board after the etching process, and is cut along the vib-vib line in FIG. A cross section is shown. FIG. 7A is a partially enlarged view showing a VII portion in FIG. 6A, and FIG. 7B is a schematic cross-sectional view taken along line viib-viib in FIG. 7A. As shown in FIGS. 6 and 7, in the etching process, since the etching proceeds from the outer surface, the upper part of the silver layer 3 is dissolved most and the amount of dissolution is decreased downward. For this reason, as shown in FIG. 7, the dimension between the side surfaces which oppose in the groove | channel 26 between a pair of substantially H-shaped pattern is short toward the lower part from the upper part. In the gold layer 2 as well, the upper part is dissolved most, and the amount of dissolution decreases downward. For this reason, the dimension between the side surfaces which oppose in the groove | channel 27 between a pair of substantially H-shaped patterns is short toward the lower part from the upper part.

  As described above, in the gold layer 2 and the silver layer 3, the dissolution rate of the silver layer 3 is faster than the dissolution rate of the gold layer 2. For this reason, the interval between the grooves 26 is larger than the interval between the grooves 27.

  The side surface of the groove 26 is an inclined surface that spreads sideward (outward) from the top of the silver layer 3 downward. Similarly, the side surface of the groove 27 is an inclined surface that spreads sideward (outward) from the top of the gold layer 2 toward the lower side. Since the dissolution rate of the gold layer 2 is slower than that of the silver layer 3, a stepped portion 23 is formed at the outer periphery of the boundary between the silver layer 3 and the gold layer 2. The gold layer 2 is formed so as to protrude about 1 μm to the side as compared with the silver layer 3. Further, the alloy layer 4 formed by firing is exposed by the etching process. That is, the gold and silver alloy layer 4 is formed on the outer periphery of the boundary between the gold layer 2 and the silver layer 3 by the etching process. By arranging the gold layer 2 on the outer peripheral side of the laminated structure and forming the alloy layer 4 of gold and silver, the effect of suppressing migration is improved and the effect of suppressing sulfidation is also improved. To do.

  With reference to FIGS. 8-10, the suppression effect of a migration and the suppression effect of a sulfidation are demonstrated. 8 and 9 are a graph and a table showing experimental results on the migration resistance of the wiring board. On the wiring board used in the experiment, a pattern having an electrode length of 30 mm and a distance of 100 μm was formed. After the silver layer 3 was laminated on the gold layer 2, the gold layer 2 and the silver layer 3 were subjected to photolithographic etching treatment once (simultaneously). The environmental conditions were 85 ° C. and 85% RH. Under this environment, a voltage of DC 32V was applied and energized continuously to measure the time until the insulation resistance value became 10 MΩ or less, which is a determination reference value.

  As a comparative example with the present embodiment, a wiring board in which an electrode is constituted only by a gold layer 2 having a film thickness of 0.66 μm is a comparative example 1, and a wiring in which an electrode is constituted only by a silver layer 3 having a film thickness of 3.3 μm The substrate is referred to as Comparative Example 2. Two types of wiring boards of the present embodiment were prepared, and experiments were conducted respectively. In the first wiring board of the present embodiment, the gold layer 2 has a thickness of 0.25 μm and the silver layer 3 has a thickness of 0.80 μm. That is, in the first wiring board, the thickness of the gold layer 2 is set to about 1/3 of the thickness of the silver layer 3. In the second wiring board of the present embodiment, the gold layer 2 has a thickness of 1.00 μm and the silver layer 3 has a thickness of 1.57 μm. That is, in the second wiring board, the film thickness of the gold layer 2 is about 2/3 of the film thickness of the silver layer 3.

  As shown in FIGS. 8 and 9, in Comparative Example 1, the insulation resistance value hardly decreased even when the continuous energization time exceeded 2000 hours, and a high migration resistance result was obtained. In Comparative Example 2, the insulation resistance value became 10 MΩ (judgment reference value) or less before the continuous energization time was less than 50 hours. Thus, there is a large difference in migration resistance between the gold layer 2 and the silver layer 3. However, in Comparative Example 1, since the electrode is composed only of the gold layer 2, the cost increases.

  As shown in FIGS. 8 and 9, in the first wiring board of the present embodiment, it was possible to maintain a high insulation resistance value until the continuous energization time was 200 hours. It was confirmed that the migration resistance of the first wiring board was greatly improved as compared with Comparative Example 2. In the second wiring board of the present embodiment, it was found that even when the continuous energization time exceeded 2000 hours, the insulation resistance value hardly decreased and high migration resistance could be obtained. From this experimental result, it was found that the migration resistance can be improved by increasing the ratio of the thickness of the gold layer 2. That is, by changing the ratio of the film thickness of the gold layer 19 and the silver layer 20, the degree of suppression of migration can be adjusted as necessary.

  FIG. 10 is a table showing experimental results on the resistance to sulfurization of the wiring board. As a comparative example of the present embodiment, a wiring board in which an electrode is constituted only by a gold layer 2 having a film thickness of 0.65 μm is a comparative example 3, and a wiring board in which an electrode is constituted only by a silver layer 3 having a film thickness of 3.3 μm Is referred to as Comparative Example 4. Two types of wiring boards of the present embodiment were prepared, and experiments were conducted respectively. In the third wiring board of the present embodiment, the gold layer 2 has a thickness of 0.3 μm and the silver layer 3 has a thickness of 3.3 μm. That is, in the third wiring board, the thickness of the gold layer 2 is about 1/10 of the thickness of the silver layer 3. In the fourth wiring board of the present embodiment, the gold layer 2 has a thickness of 3.3 μm and the silver layer 3 has a thickness of 0.3 μm. That is, in the fourth wiring board, the film thickness of the gold layer 2 is about 10 times the film thickness of the silver layer 3. In the fourth wiring board, the gold layer 2 is arranged in the upper layer and the silver layer 3 is arranged in the lower layer, which corresponds to a second embodiment to be described later.

  In the experiment, each wiring board is left unattended for a predetermined period. A resistance value fluctuation of less than + 1% is marked as very good. A resistance value fluctuation of + 1% or more and less than + 20% is marked as good. Of + 20% or more and less than + 100% was judged as bad Δ, and resistance value fluctuation of + 100% or more was judged as poor x.

  As shown in FIG. 10, in Comparative Example 3, even if it was left for 36 months, there was almost no change in resistance value, and it was determined that it was very good. In Comparative Example 4, it was determined to be defective in about one month, and was determined to be inferior in about three months.

  In the third wiring board of the present embodiment, even when left for 12 months, there was almost no change in resistance value, and it was determined to be very good. The third wiring board was judged to be good even after being left for 36 months, and a high sulfidation resistance result was obtained. In the fourth wiring board, even when left for 36 months, there was almost no change in resistance value, and it was determined to be very good. According to this experimental result, regardless of whether the gold layer 2 or the silver layer 3 is arranged on the lower layer side, a high sulfidation resistance can be obtained by forming the gold layer 2 and the silver layer 3 in a laminated structure. I understood. Further, it was found from this experimental result that the resistance to sulfurization can be improved by increasing the ratio of the thickness of the gold layer 2. That is, by changing the ratio of the film thickness of the gold layer 19 and the silver layer 20, the degree of suppression of sulfidation can be adjusted as necessary.

According to the embodiment described above, the following operational effects can be obtained.
(1) The wiring board according to the present embodiment includes an insulating substrate 1 and a silver layer 3 and a gold layer 2 laminated on the insulating substrate 1. The gold layer 2 has a smaller ionization tendency than the silver layer 3. By a single etching process on the silver layer 3 and the gold layer 2, a step portion 23 in which the gold layer 2 protrudes to the side of the silver layer 3 was provided at the boundary outer peripheral portion between the silver layer 3 and the gold layer 2. By providing the step 23 or the alloy layer 24 in which the gold layer 2 protrudes to the side of the silver layer 3, the migration resistance can be improved. Furthermore, the resistance to sulfurization can be improved.

(2) Since the step portion 23 in which the gold layer 2 protrudes laterally from the silver layer 3 can be formed by a single etching process, it is possible to prevent the displacement of the gold layer 2 and the silver layer 3 from occurring. . According to the present embodiment, the positional accuracy between the gold layer 2 and the silver layer 3 (that is, the maximum value of the relative displacement between the gold layer 2 and the silver layer 3) can be 10 μm or less. Moreover, a fine pattern having a width dimension of 5 μm or less can be formed by the laminated structure including the gold layer 2 and the silver layer 3. Furthermore, the interval between the laminated structures composed of the gold layer 2 and the silver layer 3 can be set to 10 μm or less. For this reason, compared with the invention described in Patent Document 1, a higher-density wiring board can be provided.

(3) Since there is no need to perform the etching process in multiple steps, the number of manufacturing steps can be reduced.

-Second Embodiment-
A thermal head 100B according to a second embodiment will be described with reference to FIGS. In the figure, the same or corresponding parts as those in the first embodiment are denoted by the same reference numerals, and differences will be mainly described. FIG. 11 is a diagram similar to FIG. 4, and is a schematic diagram illustrating a main part of a thermal head 100 </ b> B according to the second embodiment.

  In the first embodiment, the example in which the silver layer 20 is provided on the gold layer 19 in the wire bonding portion 18 has been described (see FIG. 4). In contrast, in the second embodiment, in the wire bonding portion 18B, the gold layer 19B is provided on the silver layer 20B, and wire bonding is performed on the upper surface of the gold layer 19.

  In the wire bonding portion 18B, the gold layer 19B protrudes laterally from the silver layer 20B, and a step portion 23B or an alloy layer 24B is formed on the outer periphery of the boundary between the silver layer 20B and the gold layer 19B. A method of forming such a wire bonding portion 18B will be described with reference to FIGS. In FIG. 12 to FIG. 14, a simple shape is used for easy understanding. 12 to 14, the glaze layer is omitted.

(Gold layer and silver layer forming process)
FIG. 12A is a schematic plan view of the wiring board before the etching process, FIG. 12B is a schematic side sectional view of the wiring board before the etching process, and is cut along the line xiib-xiib in FIG. A cross section is shown. As shown in FIG. 12, a silver paste composition is printed on a rectangular flat plate-like insulating substrate 1 in a rectangular pattern having a size slightly smaller than that of the insulating substrate 1. Thereafter, the gold paste composition is printed in a rectangular pattern extending in parallel with the short direction of the insulating substrate 1 on the upper surface of the central portion of the silver paste composition pattern. Then, the gold layer 2 and the silver layer 3 are formed by baking the insulating substrate 1 (for example, about 800 ° C.). By firing, a gold-silver alloy layer 4 is formed at the boundary between the gold layer 2 and the silver layer 3 (not shown in FIG. 12, see FIG. 14).

(Photolithographic etching process)
In FIG. 12, a substantially H-shaped pattern as shown by a one-dot chain line is formed by photolithography. After that, by performing wet etching once, that is, by immersing the wiring board in the etching solution, parts other than the part surrounded by the alternate long and short dash line (substantially H-shaped pattern) shown in FIG. To do.

  FIG. 13A is a schematic plan view of the wiring board after the etching process, FIG. 13B is a schematic side sectional view of the wiring board after the etching process, and is cut along the line xiiib-xiiib in FIG. A cross section is shown. 14A is a partially enlarged view showing the XIV part of FIG. 13A, and FIG. 14B is a schematic cross-sectional view taken along the line xivb-xivb of FIG. 14A. As shown in FIG. 13 and FIG. 14, in the etching process, etching proceeds from the outer surface, so that the upper part of the gold layer 2 is dissolved most and the amount of dissolution decreases downward. For this reason, as shown in FIG. 14, the dimension between the side surfaces which oppose in the groove | channel 27 between a pair of substantially H-shaped pattern is short toward the lower part from the upper part. Also in the silver layer 3, the upper part is dissolved most, and the amount of dissolution becomes smaller downward. For this reason, the dimension between the side surfaces which oppose in the groove | channel 26 between a pair of substantially H-shaped patterns is short toward the lower part from the upper part.

  As described above, in the gold layer 2 and the silver layer 3, the dissolution rate of the silver layer 3 is faster than the dissolution rate of the gold layer 2. For this reason, the interval between the grooves 26 is larger than the interval between the grooves 27.

  The side surface of the groove 26 is an inclined surface that spreads sideward (outward) from the top of the silver layer 3 downward. Similarly, the side surface of the groove 27 is an inclined surface that spreads sideward (outward) from the top of the gold layer 2 toward the lower side. Since the dissolution rate of the gold layer 2 is slower than that of the silver layer 3, a step portion 23 is formed at the outer periphery of the boundary between the silver layer 3 and the gold layer 2. The gold layer 2 is formed so as to protrude sideways compared to the silver layer 3. Further, the alloy layer 4 formed by firing is exposed by the etching process. That is, the gold and silver alloy layer 4 is formed on the outer periphery of the boundary between the gold layer 2 and the silver layer 3 by the etching process. By arranging the gold layer 2 on the outer peripheral side of the laminated structure and forming the alloy layer 4 of gold and silver, the effect of suppressing migration is improved and the effect of suppressing sulfidation is also improved. To do.

  According to such 2nd Embodiment, there exists an effect similar to 1st Embodiment.

-Third embodiment-
With reference to FIG. 15, a thermal head 100C according to a third embodiment will be described. In the figure, the same or corresponding parts as those in the first embodiment are denoted by the same reference numerals, and differences will be mainly described. FIG. 15 is a diagram similar to FIG. 4, and is a schematic diagram showing a main part of a thermal head 100 </ b> C according to the third embodiment.

  The wiring board according to the third embodiment is provided with the insulating substrate 12, the silver layer 20C provided on the insulating substrate 12, and the insulating substrate 12 provided on the same plane as the silver layer 20C. And a gold layer 19C having a smaller ionization tendency. The gold layer 19C has an overlapping portion 19a that overlaps the edge of the silver layer 20C and a non-overlapping portion 19b that does not overlap the silver layer 20C, and the non-overlapping portion 19b is configured as a wire bonding portion (electrode terminal) 18C. Has been. In the present embodiment, the non-overlapping portions 19b of the silver layer 20C and the gold layer 19 are disposed on the insulating substrate 12 via the glaze layer 13, respectively.

  In the third embodiment, the overlapping portion 19a of the gold layer 19C and the silver layer 20C have a laminated structure, whereby the gold-silver alloy layer 24C can be formed by firing. Moreover, since the wire bonding part 18C consists only of the gold layer 19C, it has high migration resistance and sulfidation resistance.

  According to the third embodiment, a wiring board having high migration resistance and high sulfidation resistance can be provided as in the first embodiment.

The following modifications are also within the scope of the present invention, and one or a plurality of modifications can be combined with the above-described embodiment.
(Modification 1)
In the above-described embodiment, an example in which the first conductive layer having a large ionization tendency is the silver layers 20, 20B, and 20C and the second conductive layer having a small ionization tendency is the gold layers 19, 19B, and 19C has been described. Is not limited to this. The first conductive layer may be a copper layer made of copper or an aluminum layer made of aluminum, and the second conductive layer may be a platinum layer made of platinum or a palladium layer made of palladium. At least the second conductive layer has a lower ionization tendency than the first conductive layer, and the stepped portion 23 or the alloy layers 24, 24B, 24C are formed by projecting the second conductive layer to the side of the first conductive layer. The present invention can be applied to this wiring board.

(Modification 2)
In the first and second embodiments, examples have been described in which the gold layers 19 and 19B and the silver layers 20 and 20B are formed by printing and firing, respectively, but the present invention is not limited to this. Each of the gold layers 19 and 19B and the silver layers 20 and 20B is formed by vapor deposition or sputtering, and then the stepped portion 23 is formed by a single etching process on the stacked structure portion of the gold layers 19 and 19B and the silver layers 20 and 20B. May be formed. Note that when the gold layers 19 and 19B and the silver layers 20 and 20B are formed by vapor deposition or sputtering, the above-described alloy layers 24 and 24B are not formed. That is, the case where only the step portion 23 is formed and the alloy layers 24 and 24B are not formed is within the scope of the present invention. Further, the case where only the alloy layers 24 and 24B are formed and the step portion 23 is not formed is also within the scope of the present invention. Even when only the alloy layers 24 and 24B are formed, the migration resistance and the sulfidation resistance can be improved. Since not only the step portion 23 but also the alloy layer 24 is formed, the migration resistance and the sulfidation resistance can be greatly improved. Therefore, it is preferable to form both the step portion 23 and the alloy layer 24.

(Modification 3)
In the above-described embodiment, the example in which the step portion 23 is formed in the wire bonding portion 18 of the individual electrode 17 has been described, but the present invention is not limited to this. The step portion 23 or the alloy layer 24 may be formed in the wiring portion not covered with the insulating protective film 7 to suppress the occurrence of migration.

(Modification 4)
In the embodiment described above, the thermal head 100 including the glaze layer 13 has been described as an example. However, the present invention may be applied to a thermal head that does not include the glaze layer 13.

(Modification 5)
In the above-described embodiment, the example in which the present invention is applied to the wiring board of the thermal head has been described, but the present invention is not limited to this. The present invention can be applied to substrates of various electronic devices. For example, the present invention can be applied to a catalyst substrate in a steam reformer that produces hydrogen from a source gas and steam by catalytic reforming.

  Although various embodiments and modifications have been described above, the present invention is not limited to these contents. Other embodiments conceivable within the scope of the technical idea of the present invention are also included in the scope of the present invention.

1 Insulating substrate, 2 Gold layer, 3 Silver layer, 4 Alloy layer, 5 Common electrode, 5a Electrode surface, 5b Strip electrode, 6 Heating resistor, 7 Insulating protective film, 8 Individual electrode, 9 Wire bonding part, 10 Gold Wire, 11 Driver IC, 12 Insulating substrate, 13 Glaze layer, 14 Low purity gold layer, 15 High purity gold layer, 16 Sealing resin, 17 Individual electrode, 18 Wire bonding part, 19 Gold layer, 20 Silver layer, 23 Step Part, 24, alloy layer, 26 groove, 27 groove, 30 printed wiring board, 31 connector, 32 support plate, 50 wiring board, 100 thermal head

Claims (8)

An insulating substrate;
A first conductive layer and a second conductive layer laminated on the substrate,
The second conductive layer has a smaller ionization tendency than the first conductive layer,
A step portion or an alloy portion in which the second conductive layer protrudes laterally from the first conductive layer by one etching process on the first conductive layer and the second conductive layer is formed between the first conductive layer and the first conductive layer. A wiring board provided on the outer periphery of the boundary with the second conductive layer. An insulating substrate;
A first conductive layer and a second conductive layer laminated on the substrate,
The second conductive layer has a smaller ionization tendency than the first conductive layer,
A stepped portion or an alloy portion in which the second conductive layer protrudes laterally from the first conductive layer is formed at the outer periphery of the boundary between the first conductive layer and the second conductive layer.
The wiring board, wherein the positional accuracy between the first conductive layer and the second conductive layer or the width or interval of the laminated structure composed of the first conductive layer and the second conductive layer is 10 μm or less. In the wiring board according to claim 1 or 2,
The wiring board, wherein the first conductive layer is provided on the second conductive layer. In the wiring board according to claim 1 or 2,
The wiring board, wherein the second conductive layer is provided on the first conductive layer. In the wiring board as described in any one of Claim 1 thru | or 3,
The wiring board, wherein the stepped portion or the alloy portion is exposed. An insulating substrate;
A first conductive layer provided on the substrate;
A second conductive layer provided on the same plane as the first conductive layer and having a smaller ionization tendency than the first conductive layer on the substrate;
The second conductive layer has an overlapping portion that overlaps with an edge of the first conductive layer and a non-overlapping portion that does not overlap with the first conductive layer, and the non-overlapping portion is configured as an electrode terminal. Wiring board. A thermal head comprising the wiring board according to claim 1,
A glaze layer provided on the substrate;
A heating resistor provided on the glaze layer;
A common electrode and a plurality of individual electrodes provided on the glaze layer;
An insulating protective film covering a part of the individual electrode;
A driver IC for supplying current to the individual electrodes;
An electrode terminal of the individual electrode not covered with the protective film, and a wire connecting the driver IC,
The stepped portion or the alloy portion is a thermal head formed at each electrode terminal of the plurality of individual electrodes. On the insulating substrate, the first conductive layer and the second conductive layer having a smaller ionization tendency than the first conductive layer are stacked and arranged,
The first conductive layer and the second conductive layer are subjected to a single etching process so that the stepped portion or alloy portion in which the second conductive layer protrudes to the side of the first conductive layer is formed as the first conductive layer. A method of manufacturing a wiring board, which is formed on the outer periphery of the boundary between a layer and the second conductive layer.

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