JP2008078294A - Chip component and manufacturing method thereof - Google Patents

Chip component and manufacturing method thereof Download PDF

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JP2008078294A
JP2008078294A JP2006254322A JP2006254322A JP2008078294A JP 2008078294 A JP2008078294 A JP 2008078294A JP 2006254322 A JP2006254322 A JP 2006254322A JP 2006254322 A JP2006254322 A JP 2006254322A JP 2008078294 A JP2008078294 A JP 2008078294A
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conductor
electrode
electrically connected
surface electrode
protective film
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Taiji Kinoshita
泰治 木下
Seiji Hoshitoku
聖治 星徳
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a chip component capable of obtaining a low, stable resistance value without being affected by an increase in the resistance value due to the alloying reaction between an upper surface electrode and a conductor. <P>SOLUTION: The chip component comprises: the pair of upper surface electrodes 12 that is formed at both the ends of the upper surface of an insulating substrate 11 and uses gold as a main constituent; a conductor 13 that is formed so that it is electrically connected to the pair of upper surface electrodes 12 and uses silver as a main constituent; a protective film 14 for covering the conductor 13; an end face electrode 15 formed on the back and end face of the insulating substrate 11 so that it is electrically connected to the upper surface electrode 12; and plated layers 17, 18 electrically connected to the pair of upper surface electrodes 12, the conductor 13, and the end face electrode 15. The conductor 13 is electrically connected to the pair of upper surface electrodes 12 so that one portion of the conductor 13 is positioned outside both the ends in the width direction of the pair of upper surface electrodes 12, and the protective film 14 covers only one portion of the conductor 13, thus exposing a part without overlapping with the pair of upper surface electrodes 12 in the conductor 13. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明はチップ部品、特に微小のジャンパーチップ部品およびその製造方法に関するものである。   The present invention relates to a chip component, in particular, a minute jumper chip component and a manufacturing method thereof.

以下、従来のチップ部品の製造方法について、図面を参照しながら説明する。   A conventional chip component manufacturing method will be described below with reference to the drawings.

図7(a)〜(c)および図8(a)〜(e)は従来のチップ部品の一例であるジャンパーチップ部品の製造工程図を示したもので、この図7(a)〜(c)および図8(a)〜(e)に基づいて、その製造方法を以下に説明する。   7 (a) to (c) and FIGS. 8 (a) to (e) show manufacturing process diagrams of jumper chip parts which are examples of conventional chip parts. FIGS. 7 (a) to (c) ) And FIGS. 8A to 8E, the manufacturing method will be described below.

まず、図7(a)に示すように、1次分割ライン1と2次分割ライン2を有し、かつ純度96%のアルミナからなるシート状の絶縁基板3の上面に、複数の上面電極4をスクリーン印刷工法で、1次分割ライン1を跨ぐように形成する。   First, as shown in FIG. 7A, a plurality of upper surface electrodes 4 are formed on the upper surface of a sheet-like insulating substrate 3 having a primary dividing line 1 and a secondary dividing line 2 and made of alumina having a purity of 96%. Is formed so as to straddle the primary dividing line 1 by a screen printing method.

次に、図7(b)に示すように、1次分割ライン1と2次分割ライン2で囲まれた個片領域内に、複数の上面電極4に電気的に接続されるように複数の導体5を複数の上面電極4に重ねて形成する。   Next, as shown in FIG. 7 (b), a plurality of upper surface electrodes 4 are electrically connected to each other in the individual region surrounded by the primary division line 1 and the secondary division line 2. The conductor 5 is formed so as to overlap the plurality of upper surface electrodes 4.

次に、図7(c)に示すように、複数の導体5の全面を覆うようにスクリーン印刷工法により樹脂保護層6を形成する。   Next, as shown in FIG. 7C, a resin protective layer 6 is formed by a screen printing method so as to cover the entire surface of the plurality of conductors 5.

次に、図8(a)に示すように、複数の上面電極4を切断するようにシート状の絶縁基板3を1次分割ライン1に沿ってダイシングで切断することにより、図8(b)に示すような短冊状の基板7を得る。   Next, as shown in FIG. 8A, the sheet-like insulating substrate 3 is cut by dicing along the primary dividing line 1 so as to cut the plurality of upper surface electrodes 4, thereby FIG. A strip-shaped substrate 7 as shown in FIG.

次に、図8(c)に示すように、短冊状の基板7の端面に上面電極4と電気的に接続されるようにスパッタ等を用いて端面電極8を形成する。   Next, as shown in FIG. 8C, the end surface electrode 8 is formed by sputtering or the like so as to be electrically connected to the upper surface electrode 4 on the end surface of the strip-shaped substrate 7.

最後に、図8(d)に示すように、2次分割ライン2に沿って短冊状の基板7を分割することにより個片状の基板9を形成し、その後、図8(e)に示すようにバレルめっき法を用いて端面電極8の表面にニッケルめっき層(図示せず)と錫めっき層10を形成することによって、従来のチップ部品を製造していた。   Finally, as shown in FIG. 8 (d), the strip-shaped substrate 7 is divided along the secondary dividing line 2 to form a piece-like substrate 9, and then shown in FIG. 8 (e). Thus, the conventional chip component was manufactured by forming the nickel plating layer (not shown) and the tin plating layer 10 on the surface of the end surface electrode 8 using the barrel plating method.

なお、この出願の発明に関する先行技術文献情報としては、例えば、特許文献1が知られている。
特開2005−78874号公報
As prior art document information relating to the invention of this application, for example, Patent Document 1 is known.
JP 2005-78874 A

上記した従来のチップ部品の製造方法においては、上面電極4を構成する材料と導体5を構成する材料が異なる場合、両者の重なり部分において合金化反応を起こして導体5の抵抗値が上昇するもので、特に低い抵抗値が要求されるジャンパーチップ部品においては特性が不安定になるものであった。特に、上面電極4はダイシング時のバリ発生を抑制する目的で金系の材料を用いて薄く印刷形成しており、また導体5は抵抗値の低い銀系の材料で構成することが多く、この場合、金系の上面電極4と銀系の導体5の重なり部分においては合金化反応が促進され、そしてこの合金化した部分で抵抗値が上昇するものである。この場合、従来のチップ部品は、導体5の全面が樹脂保護層6で覆われているため、めっき層を上面電極4に形成する場合、めっき層は抵抗値が上昇している合金化された部分に形成されることになり、その結果、安定した低い抵抗値を有するチップ部品が得られないという課題を有していた。   In the above-described conventional method for manufacturing a chip component, when the material constituting the upper surface electrode 4 and the material constituting the conductor 5 are different, an alloying reaction occurs in the overlapping portion between the two and the resistance value of the conductor 5 increases. In particular, the characteristics of the jumper chip component requiring a low resistance value become unstable. In particular, the top electrode 4 is thinly printed using a gold-based material for the purpose of suppressing the occurrence of burrs during dicing, and the conductor 5 is often composed of a silver-based material having a low resistance value. In this case, the alloying reaction is promoted at the overlapping portion of the gold-based top electrode 4 and the silver-based conductor 5, and the resistance value increases at the alloyed portion. In this case, since the entire surface of the conductor 5 is covered with the resin protective layer 6 in the conventional chip component, when the plating layer is formed on the upper surface electrode 4, the plating layer is alloyed with an increased resistance value. As a result, a chip component having a stable low resistance value cannot be obtained.

本発明は上記従来の課題を解決するもので、上面電極と導体の合金化反応による抵抗値の上昇の影響を受けることなく、微小サイズで安定した低い抵抗値が得られるチップ部品およびその製造方法を提供することを目的とするものである。   SUMMARY OF THE INVENTION The present invention solves the above-described conventional problems, and provides a chip component capable of obtaining a stable and low resistance value in a small size without being affected by an increase in resistance value due to an alloying reaction between the upper surface electrode and a conductor, and a method for manufacturing the chip component Is intended to provide.

上記目的を達成するために、本発明は以下の構成を有するものである。   In order to achieve the above object, the present invention has the following configuration.

本発明の請求項1に記載の発明は、絶縁基板の上面の両端部に形成された金を主成分とする一対の上面電極と、この一対の上面電極に電気的に接続されるように形成された銀を主成分とする導体と、この導体を覆う保護膜と、前記一対の上面電極と電気的に接続されるように前記絶縁基板の裏面および端面に形成された端面電極と、前記上面電極と導体および端面電極に電気的に接続されるように形成されためっき層とを備え、前記導体の一部が前記一対の上面電極の幅方向両端部よりも外側に位置するように前記導体を一対の上面電極に電気的に接続し、かつ前記保護膜が前記導体の一部のみを覆う構成とすることにより、前記導体における上面電極と重ならない部分を露出させるように構成したもので、この構成によれば、導体の一部が一対の上面電極の幅方向両端部よりも外側に位置するように前記導体を一対の上面電極に電気的に接続し、かつ前記保護膜が前記導体の一部のみを覆う構成とすることにより、前記導体における上面電極と重ならない部分を露出させるように構成しているため、上面電極と電気的に接続される導体は上面電極と重ならない部分が保護膜から大きくはみ出すことになり、そしてこの保護膜からはみ出した導体部分は上面電極と合金化されていないため、上面電極と導体の重なる部分が合金化して抵抗値が上昇した場合でも、上面電極と重ならずに合金化されていない導体にめっき層を直接電気的に接続されるように形成することができ、これにより、安定した低い抵抗値を有するチップ部品が得られるという作用効果を有するものである。   The invention according to claim 1 of the present invention is formed so as to be electrically connected to a pair of upper surface electrodes mainly composed of gold and formed on both ends of the upper surface of the insulating substrate. A conductor composed mainly of silver, a protective film covering the conductor, end face electrodes formed on the back and end faces of the insulating substrate so as to be electrically connected to the pair of top face electrodes, and the top face An electrode and a plating layer formed so as to be electrically connected to the conductor and the end surface electrode, and the conductor is positioned so that a part of the conductor is located outside both ends in the width direction of the pair of upper surface electrodes. Is electrically connected to a pair of upper surface electrodes, and the protective film covers only a part of the conductor, thereby exposing a portion of the conductor that does not overlap with the upper surface electrode. According to this configuration, a part of the conductor is By electrically connecting the conductor to the pair of upper surface electrodes so as to be located outside both ends of the pair of upper surface electrodes in the width direction, and the protective film covers only a part of the conductor, Since the portion of the conductor that does not overlap with the upper surface electrode is exposed, the portion of the conductor that is electrically connected to the upper surface electrode does not overlap the upper surface electrode, and this protection Since the conductor portion that protrudes from the film is not alloyed with the top electrode, even if the overlapping portion between the top electrode and the conductor is alloyed and the resistance value is increased, the conductor is not alloyed without overlapping with the top electrode. The plating layer can be formed so as to be directly electrically connected, and this has the effect of obtaining a chip component having a stable low resistance value.

本発明の請求項2に記載の発明は、特に、上面電極と導体および端面電極に電気的に接続されるように補助上面電極をスパッタで形成し、かつ保護膜をガラスで形成したもので、この構成によれば、上面電極と導体および端面電極に電気的に接続されるように補助上面電極をスパッタで形成し、かつ保護膜をガラスで形成しているため、保護膜を樹脂で形成した場合に生じる樹脂のブリーディング(滲み出し)がなくなり、これにより、導体と補助上面電極および/またはめっき層との間にブリーディング膜が介在することがなくなるため、安定した低い抵抗値を有するチップ部品が得られるという作用効果を有するものである。   The invention according to claim 2 of the present invention is such that, in particular, the auxiliary upper surface electrode is formed by sputtering so as to be electrically connected to the upper surface electrode, the conductor and the end surface electrode, and the protective film is formed of glass. According to this configuration, the auxiliary upper surface electrode is formed by sputtering so as to be electrically connected to the upper surface electrode, the conductor, and the end surface electrode, and the protective film is formed of glass, so the protective film is formed of resin. As a result, there is no bleeding of the resin that occurs in some cases, and thus no bleeding film is interposed between the conductor and the auxiliary upper surface electrode and / or the plating layer, so that a chip component having a stable low resistance value can be obtained. It has the effect of being obtained.

本発明の請求項3に記載の発明は、1次分割ラインと2次分割ラインを有するシート状の絶縁基板の上面に複数の上面電極を前記1次分割ラインのみを跨ぐように形成する工程と、前記複数の上面電極と電気的に接続されるように前記1次分割ラインと2次分割ラインで囲まれた複数の個片領域内に導体を形成する工程と、前記導体を覆うように保護膜を形成する工程と、前記シート状の絶縁基板を前記1次分割ラインに沿って1次ダイシングする工程と、前記シート状の絶縁基板の裏面と前記1次ダイシングによって得られた端面に前記複数の上面電極と導体に電気的に接続されるように端面電極を形成する工程と、前記上面電極と導体および端面電極に電気的に接続されるように補助上面電極をスパッタで形成する工程と、前記2次分割ラインに沿って絶縁基板を分割し個片状の基板を得る工程と、前記個片状の基板の両端面に前記端面電極と補助上面電極の全面を覆うようにめっき層を形成する工程とを備え、前記複数の導体を複数の上面電極に電気的に接続されるように形成する工程において、前記複数の導体の一部が個片領域内において前記複数の上面電極の1次分割ライン方向の両端部よりも外側に位置するように前記複数の導体を複数の上面電極に電気的に接続し、かつ前記導体を覆うように保護膜を形成する工程において、前記保護膜は前記導体の一部のみを覆う構成とすることにより、前記導体における上面電極と重ならない部分を露出させるように構成したもので、この製造方法によれば、複数の導体を複数の上面電極に電気的に接続されるように形成する工程において、前記複数の導体の一部が個片領域内において前記複数の上面電極の1次分割ライン方向の両端部よりも外側に位置するように前記複数の導体を複数の上面電極に電気的に接続し、かつ前記導体を覆うように保護膜を形成する工程において、前記保護膜が導体の一部のみを覆う構成とすることにより、前記導体における上面電極と重ならない部分を露出させるように構成しているため、上面電極と電気的に接続される導体は上面電極と重ならない部分が保護膜から大きくはみ出すことになり、そしてこの保護膜からはみ出した導体部分は上面電極と合金化されていないため、上面電極と導体の重なる部分が合金化して抵抗値が上昇した場合でも、上面電極と重ならずに合金化されていない導体にめっき層を補助上面電極を介して直接電気的に接続されるように形成することができ、これにより、安定した低い抵抗値を有するチップ部品が得られるという作用効果を有するものである。   The invention according to claim 3 of the present invention includes a step of forming a plurality of upper surface electrodes on the upper surface of a sheet-like insulating substrate having a primary division line and a secondary division line so as to straddle only the primary division line. Forming a conductor in a plurality of individual regions surrounded by the primary dividing line and the secondary dividing line so as to be electrically connected to the plurality of upper surface electrodes, and protecting the conductor so as to cover the conductor A step of forming a film; a step of primary dicing the sheet-like insulating substrate along the primary dividing line; and a plurality of the plurality of a plurality of the plurality of portions on the back surface of the sheet-like insulating substrate and the end face obtained by the primary dicing. Forming an end surface electrode so as to be electrically connected to the upper surface electrode and the conductor, and forming an auxiliary upper surface electrode by sputtering so as to be electrically connected to the upper surface electrode, the conductor and the end surface electrode; Secondary division Dividing the insulating substrate along the in-line to obtain an individual substrate, and forming a plating layer on both end surfaces of the individual substrate so as to cover the entire surface of the end surface electrode and the auxiliary upper surface electrode. And the step of forming the plurality of conductors so as to be electrically connected to the plurality of upper surface electrodes, wherein a part of the plurality of conductors is arranged in the direction of a primary dividing line of the plurality of upper surface electrodes in a piece region. In the step of electrically connecting the plurality of conductors to the plurality of upper surface electrodes so as to be located outside both ends, and forming the protective film so as to cover the conductor, the protective film is a part of the conductor In this configuration, a plurality of conductors are electrically connected to a plurality of upper surface electrodes. In this manufacturing method, a plurality of conductors are electrically connected to a plurality of upper surface electrodes. So as to form The plurality of conductors are electrically connected to the plurality of upper surface electrodes so that a part of the plurality of conductors is located outside both ends of the plurality of upper surface electrodes in the primary dividing line direction within the individual region. In the step of forming a protective film so as to connect and cover the conductor, the protective film covers only a part of the conductor so that a portion of the conductor that does not overlap with the upper surface electrode is exposed. Therefore, the part of the conductor that is electrically connected to the upper surface electrode does not overlap with the upper surface electrode, and the portion of the conductor that protrudes from the protective film is not alloyed with the upper surface electrode. Therefore, even when the overlapping portion of the upper surface electrode and the conductor is alloyed to increase the resistance value, the plating layer is directly applied to the non-alloyed conductor without overlapping the upper surface electrode via the auxiliary upper surface electrode. It can be formed so as to be electrically connected, and this has the effect of obtaining a chip component having a stable low resistance value.

以上のように本発明のチップ部品は、導体の一部が一対の上面電極の幅方向両端部よりも外側に位置するように前記導体を一対の上面電極に電気的に接続し、かつ導体を覆う保護膜が導体の一部のみを覆う構成とすることにより、前記導体における上面電極と重ならない部分を露出させるように構成しているため、上面電極と電気的に接続される導体は上面電極と重ならない部分が保護膜から大きくはみ出すことになり、そしてこの保護膜からはみ出した導体部分は上面電極と合金化されていないため、上面電極と導体の重なる部分が合金化して抵抗値が上昇した場合でも、上面電極と重ならずに合金化されていない導体にめっき層を直接電気的に接続されるように形成することができ、これにより、安定した低い抵抗値を有するチップ部品が得られるという優れた効果を奏するものである。   As described above, the chip component of the present invention electrically connects the conductor to the pair of upper surface electrodes so that a part of the conductor is positioned outside both ends in the width direction of the pair of upper surface electrodes, Since the protective film is configured to cover only a part of the conductor so that a portion of the conductor that does not overlap with the upper surface electrode is exposed, the conductor electrically connected to the upper surface electrode is the upper surface electrode. The part that does not overlap with the protective film greatly protrudes from the protective film, and the conductor part that protrudes from the protective film is not alloyed with the upper surface electrode, so the overlapping part of the upper surface electrode and the conductor is alloyed to increase the resistance value. Even in this case, the plated layer can be formed so as to be directly electrically connected to a non-alloyed conductor that does not overlap with the upper surface electrode, and thereby a chip component having a stable low resistance value. In which exhibits an excellent effect that is obtained.

以下、本発明の一実施の形態におけるチップ部品の製造方法について、図面を参照しながら説明する。   Hereinafter, a chip part manufacturing method according to an embodiment of the present invention will be described with reference to the drawings.

図1は本発明の一実施の形態におけるチップ部品の一例であるジャンパーチップ部品の断面図、図2(a)〜(c)、図3(a)〜(c)および図4(a)〜(c)は同ジャンパーチップ部品の製造方法を示す製造工程図である。   FIG. 1 is a cross-sectional view of a jumper chip part which is an example of a chip part in an embodiment of the present invention, FIGS. 2 (a) to (c), FIGS. 3 (a) to (c), and FIG. 4 (a) to FIG. (C) is a manufacturing process figure which shows the manufacturing method of the jumper chip component.

図1において、11は純度96%のアルミナからなる矩形状の絶縁基板、12は絶縁基板11の上面の両端部の中央に設けられた金を主成分とする上面電極、13は上面電極12と電気的に接続されるように設けられた銀を主成分とする導体、14は導体13の一部を覆うように設けられた保護膜である。15は絶縁基板11の裏面から端面にかけて設けられ、かつ前記上面電極12と電気的に接続される端面電極、16は前記上面電極12と導体13および端面電極15に電気的に接続されるように形成された補助上面電極である。17は前記端面電極15と補助上面電極16の上に形成されたニッケルめっき層、18はニッケルめっき層17の上に形成された錫めっき層である。   In FIG. 1, reference numeral 11 denotes a rectangular insulating substrate made of alumina having a purity of 96%, 12 denotes a top electrode mainly composed of gold provided at the center of both ends of the top surface of the insulating substrate 11, and 13 denotes an upper electrode 12. A conductor mainly composed of silver provided so as to be electrically connected, and 14 is a protective film provided so as to cover a part of the conductor 13. 15 is an end surface electrode provided from the back surface to the end surface of the insulating substrate 11 and is electrically connected to the upper surface electrode 12, and 16 is electrically connected to the upper surface electrode 12, the conductor 13 and the end surface electrode 15. It is the formed auxiliary upper surface electrode. Reference numeral 17 denotes a nickel plating layer formed on the end face electrode 15 and the auxiliary upper surface electrode 16, and reference numeral 18 denotes a tin plating layer formed on the nickel plating layer 17.

次に、図2(a)〜(c)、図3(a)〜(c)および図4(a)〜(c)を用いて、本発明の一実施の形態におけるジャンパーチップ部品の製造方法を説明する。   Next, referring to FIGS. 2A to 2C, FIGS. 3A to 3C, and FIGS. 4A to 4C, a method of manufacturing a jumper chip component according to an embodiment of the present invention. Will be explained.

まず、図2(a)に示すように、1次分割ライン11aと2次分割ライン11bを有する純度96%のアルミナ等からなるシート状の絶縁基板11cを用意し、そしてこのシート状の絶縁基板11cの上面に、金レジネート等の金を主成分とする材料からなる複数の上面電極12を、1次分割ライン11aのみを跨ぐように升目状にスクリーン印刷し、ピーク温度850℃の焼成プロファイルで焼成する。なお、上面電極12を金レジネートを用いて形成すると薄く印刷することができるため、後述する1次ダイシングで上面電極12を切断する際にもバリが発生し難いものである。また、1次分割ライン11aと2次分割ライン11bはスリット状の分割溝としてあらかじめシート状の絶縁基板11cの上面および/または裏面に形成しておいてもよいものであるが、製造する部品が小型化して1次分割ライン11aと2次分割ライン11bで囲まれる領域(以下、個片領域とする)が狭くなると、スリット状の分割溝をあらかじめ設けておくことはシート状の絶縁基板11cの強度低下を招いてものづくりが困難になるため、通常は1次分割ライン11aと2次分割ライン11bにあらかじめスリット状の分割溝は設けないものである。   First, as shown in FIG. 2A, a sheet-like insulating substrate 11c made of alumina having a purity of 96% having a primary dividing line 11a and a secondary dividing line 11b is prepared, and this sheet-like insulating substrate is prepared. A plurality of upper surface electrodes 12 made of a material mainly composed of gold, such as gold resinate, are screen-printed on the upper surface of 11c in a grid pattern so as to straddle only the primary dividing line 11a, and have a firing profile with a peak temperature of 850 ° C. Bake. In addition, since it can print thinly when the upper surface electrode 12 is formed using gold resinate, it is hard to generate | occur | produce a burr | flash also when cut | disconnecting the upper surface electrode 12 by the primary dicing mentioned later. Further, the primary dividing line 11a and the secondary dividing line 11b may be formed in advance on the upper surface and / or the back surface of the sheet-like insulating substrate 11c as slit-shaped dividing grooves. When the area surrounded by the primary dividing line 11a and the secondary dividing line 11b (hereinafter referred to as an individual area) is reduced in size, the slit-shaped dividing grooves are provided in advance on the sheet-like insulating substrate 11c. Since manufacturing is difficult due to a decrease in strength, the primary dividing line 11a and the secondary dividing line 11b are usually not provided with slit-shaped dividing grooves in advance.

次に、図2(b)に示すように、シート状の絶縁基板11cの上面に、1次分割ライン11aと2次分割ライン11bで囲まれた複数の個片領域内に上面電極12と電気的に接続されるように、銀パラジウム合金等の銀を主成分とする導電性ペーストからなる導体13を、個片領域内において上面電極12の1次分割ライン11a方向の両端部よりも外側に位置するように形成し、ピーク温度850℃の焼成プロファイルで焼成する。この場合、前記導体13は1次分割ライン11aと2次分割ライン11bで囲まれた複数の個片領域内にそれぞれ2個ずつ形成しているため、導体13の印刷位置が1次分割ライン11aの方向にずれた場合でも、いずれか一方の導体13が一対の上面電極12と確実に接続されることになり、導通不良は生じないものである。なお、導体13は必ずしも個片領域内に2個独立に形成しなくてもよく、一対の上面電極12の1次分割ライン11a方向の両端部よりも外側に十分はみ出す程度に導体13を幅広く形成する場合は、導体13は個片領域内に1個だけ形成してもよいものである。   Next, as shown in FIG. 2 (b), the upper surface electrode 12 and the electricity are formed on the upper surface of the sheet-like insulating substrate 11c in a plurality of individual regions surrounded by the primary division line 11a and the secondary division line 11b. So that the conductor 13 made of a conductive paste mainly composed of silver, such as a silver-palladium alloy, is placed outside the both ends of the upper electrode 12 in the direction of the primary dividing line 11a in the individual piece region. And are fired with a firing profile having a peak temperature of 850 ° C. In this case, since two conductors 13 are formed in each of the plurality of individual regions surrounded by the primary division line 11a and the secondary division line 11b, the printing position of the conductor 13 is the primary division line 11a. Even if it deviates in this direction, either one of the conductors 13 will be reliably connected to the pair of upper surface electrodes 12, and no conduction failure will occur. Note that two conductors 13 do not necessarily have to be formed independently in the individual region, and the conductors 13 are formed in a wide enough range so as to protrude beyond both ends of the pair of upper surface electrodes 12 in the primary division line 11a direction. In this case, only one conductor 13 may be formed in the piece region.

次に、図2(c)に示すように、複数の導体13の一部のみを覆うように1次分割ライン11aと平行に複数の保護膜14を形成する。ここで保護膜14を樹脂で形成すると、樹脂のブリーディング膜が形成されて導体13と後述するめっき層との接合が不安定になるため、保護膜14はガラスで形成するのが好ましい。また保護膜14は、導体13における露出部分をできるだけ広く確保するために、上面電極12と導体13の重なり部分を覆わないように図2(c)に示すように幅を狭くして形成しているものである。   Next, as shown in FIG. 2C, a plurality of protective films 14 are formed in parallel with the primary dividing line 11a so as to cover only a part of the plurality of conductors 13. Here, if the protective film 14 is formed of resin, a resin bleeding film is formed and bonding between the conductor 13 and a plating layer described later becomes unstable. Therefore, the protective film 14 is preferably formed of glass. The protective film 14 is formed to have a narrow width as shown in FIG. 2C so as not to cover the overlapping portion of the upper surface electrode 12 and the conductor 13 in order to secure the exposed portion of the conductor 13 as wide as possible. It is what.

次に、図3(a)に示すように、1次分割ライン11aに沿ってシート状の絶縁基板11cをダイシングすることにより、図3(b)に示すような短冊状の基板11dを得る。このダイシング時においては、1次分割ライン11aの上には金を主成分とする上面電極12のみが薄く形成されているだけであるため、ダイシング時のバリは発生し難いものである。   Next, as shown in FIG. 3A, the sheet-like insulating substrate 11c is diced along the primary dividing line 11a to obtain a strip-like substrate 11d as shown in FIG. At the time of dicing, since only the upper surface electrode 12 mainly composed of gold is thinly formed on the primary dividing line 11a, burrs are hardly generated at the time of dicing.

次に、図3(c)に示すように、短冊状の基板11dの裏面側からニッケルクロム合金等よりなるスパッタを施すことにより、短冊状の基板11dの裏面(図示せず)と端面に上面電極12と電気的に接続される端面電極15を形成する。なお、この端面電極15はニッケルクロム合金のスパッタ膜に限定されるものではなく他の材料で形成してもよいもので、例えばクロムからなる第1層と銅ニッケル合金からなる第2層の2層構造で形成してもよく、あるいは短冊状の基板11dの裏面と端面に導電性ペーストを塗布して形成してもよいものである。また、この端面電極15は、短冊状の基板11dの裏面中央部を覆うようにメタルマスクを設置し、そしてこの設置状態で形成することにより所望の形状を得ることができるが、シート状の絶縁基板11cを1次分割ライン11aに沿って1次ダイシングで分割する際に、1次ダイシングのスリットをシート状の絶縁基板11cの端部まで貫通させないようにし、そしてこの1次ダイシングのスリットが形成された状態のシート状の絶縁基板11cの裏面にメタルマスクを配置して裏面からスパッタを施すようにすれば、複数の短冊状の基板11dについて端面電極15の形成を同時に行うことができるものである。   Next, as shown in FIG. 3C, the back surface (not shown) and the end surface of the strip-shaped substrate 11d are top surfaces by performing sputtering made of nickel chromium alloy or the like from the back surface side of the strip-shaped substrate 11d. An end face electrode 15 electrically connected to the electrode 12 is formed. The end face electrode 15 is not limited to a nickel-chrome alloy sputtered film, and may be formed of other materials. For example, the first layer 15 made of chromium and the second layer 2 made of copper-nickel alloy are used. It may be formed in a layer structure, or may be formed by applying a conductive paste to the back and end surfaces of the strip-shaped substrate 11d. Further, the end face electrode 15 can be obtained in a desired shape by installing a metal mask so as to cover the center of the back surface of the strip-shaped substrate 11d and forming it in this installed state. When the substrate 11c is divided by primary dicing along the primary dividing line 11a, the slit of the primary dicing is prevented from penetrating to the end of the sheet-like insulating substrate 11c, and the slit of the primary dicing is formed. If a metal mask is disposed on the back surface of the sheet-like insulating substrate 11c in a state of being formed and sputtering is performed from the back surface, the end face electrodes 15 can be simultaneously formed on the plurality of strip-shaped substrates 11d. is there.

次に、図4(a)に示すように、短冊状の基板11dの上面からニッケルクロム合金等からなるスパッタを施すことにより、短冊状の基板11dの上面と端面に上面電極12と導体13および端面電極15に電気的に接続される補助上面電極16を形成する。なお、この補助上面電極16は、短冊状の基板11dの上面中央部(保護膜14の形成部分)を覆うようにメタルマスクを設置することによって所望の形状を得ることができるが、シート状の絶縁基板11cを1次分割ライン11aに沿って1次ダイシングで分割する際に、1次ダイシングのスリットをシート状の絶縁基板11cの端部まで貫通させないようにし、そしてこの1次ダイシングのスリットが形成された状態のシート状の絶縁基板11cの上面にメタルマスクを配置して上面からスパッタを施すようにすれば、複数の短冊状の基板11dについて補助上面電極16の形成を同時に行うことができるものである。また、図4(a)においては、補助上面電極16が上面電極12と導体13を完全に覆うとともに、保護膜14の一部を覆うように形成されているが、保護膜14を覆わずに導体13の一部を露出させるようにしてもよいものである。   Next, as shown in FIG. 4A, the upper surface electrode 12 and the conductors 13 are formed on the upper surface and the end surface of the strip-shaped substrate 11d by sputtering from the upper surface of the strip-shaped substrate 11d. An auxiliary upper surface electrode 16 electrically connected to the end surface electrode 15 is formed. The auxiliary upper surface electrode 16 can have a desired shape by installing a metal mask so as to cover the upper surface central portion (the portion where the protective film 14 is formed) of the strip-shaped substrate 11d. When the insulating substrate 11c is divided by primary dicing along the primary dividing line 11a, the slit of the primary dicing is prevented from penetrating to the end of the sheet-like insulating substrate 11c. If a metal mask is arranged on the upper surface of the formed sheet-like insulating substrate 11c and sputtering is performed from the upper surface, the auxiliary upper surface electrode 16 can be simultaneously formed on the plurality of strip-shaped substrates 11d. Is. In FIG. 4A, the auxiliary upper surface electrode 16 is formed so as to completely cover the upper surface electrode 12 and the conductor 13 and to cover a part of the protective film 14, but without covering the protective film 14. A part of the conductor 13 may be exposed.

次に、短冊状の基板11dを図4(a)に示す2次分割ライン11bに沿って分割することにより、図4(b)に示すような個片状の基板11eを得る。   Next, the strip-shaped substrate 11d is divided along a secondary dividing line 11b shown in FIG. 4A, thereby obtaining an individual substrate 11e as shown in FIG. 4B.

最後に、図4(c)に示すように、個片状の基板11eにおける端面電極15および補助上面電極16の露出部分に、ニッケルめっき層17(図示せず)と錫めっき層18からなるめっき層を形成して、本発明の一実施の形態におけるジャンパーチップ部品を製造するものである。   Finally, as shown in FIG. 4C, the exposed portion of the end surface electrode 15 and the auxiliary upper surface electrode 16 in the individual substrate 11e is plated with a nickel plating layer 17 (not shown) and a tin plating layer 18. A layer is formed to manufacture a jumper chip component according to an embodiment of the present invention.

上記した本発明の一実施の形態におけるチップ部品の製造方法によって製造されたジャンパーチップ部品は、導体13の一部が一対の上面電極12の幅方向両端部よりも外側に位置するように導体13を一対の上面電極12に電気的に接続し、かつ保護膜14が導体13の一部のみを覆う構成とすることにより、導体13における上面電極12と重ならない部分を露出させるように構成しているため、上面電極12と電気的に接続される導体13は上面電極12と重ならない部分が保護膜14から大きくはみ出すことになり、そしてこの保護膜14からはみ出した導体13の部分は上面電極12と合金化されていないため、上面電極12と導体13の重なる部分が合金化して抵抗値が上昇した場合でも、上面電極12と重ならずに合金化されていない導体13にめっき層14を補助上面電極16を介して直接電気的に接続されるように形成することができ、これにより、安定した低い抵抗値を有するチップ部品を提供することができるという効果が得られるものである。また、保護膜14をガラスで形成しているため、保護膜14を樹脂で形成した場合に生じる樹脂のブリーディング(滲み出し)がなくなり、これにより、導体13と補助上面電極16および/またはニッケルめっき層17との間にブリーディング膜が介在することがなくなるため、特にジャンパーチップ部品に要求される低い抵抗値が安定して得られるものである。   In the jumper chip component manufactured by the chip component manufacturing method according to the embodiment of the present invention described above, the conductor 13 is such that a part of the conductor 13 is located outside the both ends in the width direction of the pair of upper surface electrodes 12. Are electrically connected to the pair of upper surface electrodes 12, and the protective film 14 covers only a part of the conductor 13, so that a portion of the conductor 13 that does not overlap the upper surface electrode 12 is exposed. Therefore, the portion of the conductor 13 electrically connected to the upper surface electrode 12 that does not overlap the upper surface electrode 12 protrudes greatly from the protective film 14, and the portion of the conductor 13 that protrudes from the protective film 14 is the upper surface electrode 12. Therefore, even when the overlapping portion of the upper surface electrode 12 and the conductor 13 is alloyed to increase the resistance value, it is alloyed without overlapping with the upper surface electrode 12. The plating layer 14 can be formed so as to be directly electrically connected to the non-conductor 13 via the auxiliary upper surface electrode 16, thereby providing a chip component having a stable low resistance value. Is obtained. In addition, since the protective film 14 is formed of glass, there is no bleeding of the resin that occurs when the protective film 14 is formed of resin, thereby preventing the conductor 13 and the auxiliary upper surface electrode 16 and / or nickel plating. Since the bleeding film does not intervene with the layer 17, a low resistance value required particularly for the jumper chip component can be stably obtained.

図5は、従来のチップ部品の一例であるジャンパーチップ部品と本発明の一実施の形態におけるチップ部品の一例であるジャンパーチップ部品の特性を比較した図を示したもので、この図5において、横軸は初期抵抗値、縦軸は100サイクルの熱衝撃試験を実施した後の抵抗値変化率を示す。導体13の一部を、個片領域内において上面電極12の1次分割ライン11a方向の両端部よりも外側に配置するとともに、保護膜14にガラスを用いてなる〇印で示された本発明の一実施の形態におけるチップ部品は、初期抵抗値が30mΩ付近で安定して低く、かつ熱衝撃試験後の抵抗値変化率も10%以下と低いもので、ジャンパーチップ部品に要求される低い抵抗値が安定して得られる特性を十分に満足しているものである。一方、導体を個片領域内において上面電極の1次分割ライン方向の両端部よりも内側のみに配置するとともに、保護膜に樹脂を用いてなる□印で示された従来例1と、導体を個片領域内において上面電極の1次分割ライン方向の両端部よりも内側のみに配置するとともに、保護膜にガラスを用いてなる△印で示された従来例2においては、初期抵抗値が40〜100mΩと高く、特に従来例1では保護膜に樹脂を用いているため、図6に示すような樹脂のブリーディング膜19が形成されて導体13と補助上面電極16との間の導通が不安定になり、これにより、抵抗値変化率が大きくなるものである。特に、ブリーディング膜19が緻密に形成されてしまうと、導体13と錫めっき層18との間の導電経路が必ず上面電極12を通ることになり、この場合、上面電極12は抵抗値の高い金レジネートで形成されているため、その影響により抵抗値が高くなってしまうものである。   FIG. 5 shows a comparison of the characteristics of a jumper chip part, which is an example of a conventional chip part, and a jumper chip part, which is an example of a chip part in an embodiment of the present invention. The horizontal axis represents the initial resistance value, and the vertical axis represents the resistance value change rate after the thermal shock test of 100 cycles. A part of the conductor 13 is disposed outside the both end portions of the upper surface electrode 12 in the direction of the primary dividing line 11a in the individual region, and the present invention indicated by a symbol ○ which is made of glass for the protective film 14. The chip component in one embodiment of the present invention has an initial resistance value that is stably low at around 30 mΩ and a resistance value change rate after a thermal shock test as low as 10% or less, and a low resistance required for a jumper chip component. The characteristic that the value is stably obtained is sufficiently satisfied. On the other hand, the conductor is arranged only inside the both end portions in the primary dividing line direction of the upper surface electrode within the individual piece region, and the conventional example 1 indicated by □ made of resin for the protective film and the conductor In the conventional example 2 which is disposed only inside both ends of the upper surface electrode in the direction of the primary dividing line in the individual piece region, and indicated by the Δ mark made of glass as the protective film, the initial resistance value is 40. Since the resin is used for the protective film in the first conventional example, a resin bleeding film 19 as shown in FIG. 6 is formed, and the conduction between the conductor 13 and the auxiliary upper surface electrode 16 is unstable. Thus, the rate of change in resistance value is increased. In particular, if the bleeding film 19 is formed densely, the conductive path between the conductor 13 and the tin plating layer 18 always passes through the upper surface electrode 12, and in this case, the upper surface electrode 12 is made of gold having a high resistance value. Since it is formed of resinate, the resistance value is increased due to the influence.

なお、上記本発明の一実施の形態においては、チップ部品の一例としてジャンパーチップ部品を例に説明したが、特に、このジャンパーチップ部品に限定されるものではなく、導体13をレーザートリミング等で切削して抵抗値を調整することにより、低い抵抗値を有する高精度のチップ抵抗器に適用することもできるものである。   In the above-described embodiment of the present invention, the jumper chip component is described as an example of the chip component. However, the jumper chip component is not particularly limited, and the conductor 13 is cut by laser trimming or the like. Thus, by adjusting the resistance value, it can be applied to a highly accurate chip resistor having a low resistance value.

本発明に係るチップ部品およびその製造方法は、上面電極と導体の重なる部分が合金化して抵抗値が上昇した場合でも、上面電極と重ならずに合金化されていない導体にめっき層を直接電気的に接続されるように形成することができるため、安定した低い抵抗値が得られるという効果を有するものであり、特に微小サイズのジャンパーチップ部品の製造方法に適用することにより有用となるものである。   In the chip component and the manufacturing method thereof according to the present invention, even when the overlapping portion of the upper surface electrode and the conductor is alloyed and the resistance value is increased, the plating layer is directly applied to the non-alloyed conductor without overlapping the upper surface electrode. Since it can be formed so as to be connected to each other, it has an effect that a stable low resistance value can be obtained, and is particularly useful when applied to a manufacturing method of a micro jumper chip component. is there.

本発明の一実施の形態におけるチップ部品の一例であるジャンパーチップ部品の断面図Sectional drawing of the jumper chip component which is an example of the chip component in one embodiment of this invention (a)〜(c)同ジャンパーチップ部品の製造方法を示す製造工程図(A)-(c) Manufacturing process figure which shows the manufacturing method of the jumper chip component (a)〜(c)同ジャンパーチップ部品の製造方法を示す製造工程図(A)-(c) Manufacturing process figure which shows the manufacturing method of the jumper chip component (a)〜(c)同ジャンパーチップ部品の製造方法を示す製造工程図(A)-(c) Manufacturing process figure which shows the manufacturing method of the jumper chip component 従来のチップ部品の一例であるジャンパーチップ部品と本発明の一実施の形態におけるチップ部品の一例であるジャンパーチップ部品の特性を比較した図The figure which compared the characteristic of the jumper chip component which is an example of the chip component in one embodiment of this invention and the jumper chip component which is an example of the conventional chip component 本発明の一実施の形態におけるチップ部品の一例であるジャンパーチップ部品の保護膜がブリーディングを起こした場合の断面図Sectional drawing when the protective film of the jumper chip part which is an example of the chip part in one embodiment of this invention raise | generates bleeding (a)〜(c)従来のチップ部品の一例であるジャンパーチップ部品の製造方法を示す製造工程図(A)-(c) Manufacturing process figure which shows the manufacturing method of the jumper chip component which is an example of the conventional chip component (a)〜(e)同ジャンパーチップ部品の製造方法を示す製造工程図(A)-(e) Manufacturing process figure which shows the manufacturing method of the jumper chip component

符号の説明Explanation of symbols

11 絶縁基板
11a 1次分割ライン
11b 2次分割ライン
11c シート状の絶縁基板
11d 短冊状の基板
11e 個片状の基板
12 上面電極
13 導体
14 保護膜
15 端面電極
16 補助上面電極
17 ニッケルめっき層
18 錫めっき層
DESCRIPTION OF SYMBOLS 11 Insulation board | substrate 11a Primary division line 11b Secondary division line 11c Sheet-like insulation board | substrate 11d Strip-shaped board | substrate 11e Single piece board | substrate 12 Upper surface electrode 13 Conductor 14 Protective film 15 End surface electrode 16 Auxiliary upper surface electrode 17 Nickel plating layer 18 Tin plating layer

Claims (3)

絶縁基板の上面の両端部に形成された金を主成分とする一対の上面電極と、この一対の上面電極に電気的に接続されるように形成された銀を主成分とする導体と、この導体を覆う保護膜と、前記一対の上面電極と電気的に接続されるように前記絶縁基板の裏面および端面に形成された端面電極と、前記上面電極と導体および端面電極に電気的に接続されるように形成されためっき層とを備え、前記導体の一部が前記一対の上面電極の幅方向両端部よりも外側に位置するように前記導体を一対の上面電極に電気的に接続し、かつ前記保護膜は前記導体の一部のみを覆う構成とすることにより、前記導体における上面電極と重ならない部分を露出させるように構成したチップ部品。 A pair of upper surface electrodes mainly composed of gold formed on both ends of the upper surface of the insulating substrate, a conductor mainly composed of silver formed so as to be electrically connected to the pair of upper surface electrodes, A protective film covering the conductor, an end surface electrode formed on the back surface and the end surface of the insulating substrate so as to be electrically connected to the pair of upper surface electrodes, and an electrical connection to the upper surface electrode, the conductor and the end surface electrode And the conductive layer is electrically connected to the pair of upper surface electrodes such that a part of the conductor is positioned outside both ends in the width direction of the pair of upper surface electrodes, And the chip part comprised so that the part which does not overlap with the upper surface electrode in the said conductor might be exposed by making the said protective film cover only a part of said conductor. 上面電極と導体および端面電極に電気的に接続されるように補助上面電極をスパッタで形成し、かつ保護膜をガラスで形成した請求項1記載のチップ部品。 2. The chip component according to claim 1, wherein the auxiliary upper surface electrode is formed by sputtering so as to be electrically connected to the upper surface electrode, the conductor, and the end surface electrode, and the protective film is formed of glass. 1次分割ラインと2次分割ラインを有するシート状の絶縁基板の上面に複数の上面電極を前記1次分割ラインのみを跨ぐように形成する工程と、前記複数の上面電極と電気的に接続されるように前記1次分割ラインと2次分割ラインで囲まれた複数の個片領域内に導体を形成する工程と、前記導体を覆うように保護膜を形成する工程と、前記シート状の絶縁基板を前記1次分割ラインに沿って1次ダイシングする工程と、前記シート状の絶縁基板の裏面と前記1次ダイシングによって得られた端面に前記複数の上面電極と導体に電気的に接続されるように端面電極を形成する工程と、前記上面電極と導体および端面電極に電気的に接続されるように補助上面電極をスパッタで形成する工程と、前記2次分割ラインに沿って絶縁基板を分割し個片状の基板を得る工程と、前記個片状の基板の両端面に前記端面電極と補助上面電極の全面を覆うようにめっき層を形成する工程とを備え、前記複数の導体を複数の上面電極に電気的に接続されるように形成する工程において、前記複数の導体の一部が個片領域内において前記複数の上面電極の1次分割ライン方向の両端部よりも外側に位置するように前記複数の導体を複数の上面電極に電気的に接続し、かつ前記導体を覆うように保護膜を形成する工程において、前記保護膜は前記導体の一部のみを覆う構成とすることにより、前記導体における上面電極と重ならない部分を露出させるように構成したチップ部品の製造方法。 Forming a plurality of upper surface electrodes on an upper surface of a sheet-like insulating substrate having a primary division line and a secondary division line so as to straddle only the primary division line; and being electrically connected to the plurality of upper surface electrodes. A step of forming a conductor in a plurality of individual regions surrounded by the primary dividing line and the secondary dividing line, a step of forming a protective film so as to cover the conductor, and the sheet-like insulation A step of primary dicing the substrate along the primary dividing line, and a back surface of the sheet-like insulating substrate and an end surface obtained by the primary dicing are electrically connected to the plurality of upper surface electrodes and conductors. Forming the end face electrode, forming the auxiliary upper face electrode by sputtering so as to be electrically connected to the upper face electrode, the conductor and the end face electrode, and dividing the insulating substrate along the secondary dividing line. Piece And a step of forming a plating layer so as to cover the entire surface of the end surface electrode and the auxiliary upper surface electrode on both end surfaces of the individual substrate, and the plurality of conductors are connected to the plurality of upper surface electrodes. In the step of forming the plurality of conductors so as to be electrically connected to each other, the part of the plurality of conductors is positioned outside the both ends of the plurality of upper surface electrodes in the primary division line direction in the piece region. In the step of electrically connecting a plurality of conductors to a plurality of upper surface electrodes and forming a protective film so as to cover the conductor, the protective film covers only a part of the conductor, whereby the conductor A method of manufacturing a chip component configured to expose a portion that does not overlap with the upper surface electrode.
JP2006254322A 2006-09-20 2006-09-20 Chip component and manufacturing method thereof Pending JP2008078294A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022091644A1 (en) * 2020-11-02 2022-05-05 ローム株式会社 Chip resistor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022091644A1 (en) * 2020-11-02 2022-05-05 ローム株式会社 Chip resistor

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