JP2024010234A - chip resistor - Google Patents

Abstract

To provide a chip resistor capable of preventing disconnection of an electrode due to sulfidation even if a crack of a protection film is developed due to thermal impact generated in the electrode.SOLUTION: A chip resistor A4 includes a substrate 1, a pair of upper surface electrodes 31, a resistor 2, a protection film 5 covering a part of each of the pair of upper surface electrodes 31 and the resistor 2, a side surface electrode 33, an intermediate electrode 34, and an external electrode 35. The protection film 5 includes a lower protection film 51, and an upper protection film 52 that is stacked on the lower protection film 51. The lower protection film 51 has a property highly resistant against thermal impact compared to the upper protection film 52. A part of each of the pair of upper surface electrodes 31 is covered with the lower protection film 51. In a plan view, the side surface electrode 33 includes a first edge that forms a boundary with any of the pair of upper surface electrodes 31. In the plan view, the lower protection film 51 includes a part extending from the first edge toward a side surface 13 of the substrate 1.SELECTED DRAWING: Figure 33

Description

The present invention relates to chip resistors.

The internal electrodes (top electrode, back electrode, and side electrode) that constitute part of the electrodes of the chip resistor mainly contain Ag. If sulfide gas (H ₂ S, SO _2, etc.) exists in the surrounding environment of electronic equipment in which chip resistors are used, the internal electrodes will combine with the sulfide gas and produce black silver sulfide (Ag ₂ S). generate. Since silver sulfide has electrical insulating properties, if the sulfidation of the internal electrodes progresses, there is a risk that the internal electrodes will be disconnected, that is, the electrodes of the chip resistor may be disconnected.

Under these circumstances, as disclosed in Patent Document 1, for example, a chip resistor has been known in which the upper electrode of the internal electrode is made of an Ag--Pd alloy. Although Ag--Pd alloy is a material with excellent sulfidation resistance, it has the disadvantage of being expensive and being less economical.

Therefore, Patent Document 1 also discloses a chip resistor further comprising a top electrode located on the top electrode and made of an epoxy resin containing metal particles such as Ag and carbon particles. The upper surface electrode is less likely to sulfurize than the upper surface electrode, and is also less expensive than an electrode made of an Ag--Pd alloy. Therefore, a chip resistor including a top electrode has the advantage of being economical while having sulfurization resistance.

Here, the chip resistor including the top electrode includes a Ni plating layer (intermediate electrode) covering the top electrode. The top electrode contains carbon particles. The higher the content of carbon particles, the better the sulfidation resistance of the top electrode. However, when the content of carbon particles exceeds a specified amount, the adhesion between the Ni plating layer and the upper electrode decreases, so that the Ni plating layer may peel off. If the Ni plating layer peels off, there is a concern that sulfide gas will enter the internal electrodes (top electrode and side electrodes), and the electrodes of the chip resistor will become disconnected due to the progress of sulfidation of the internal electrodes.

Further, generally, as in the chip resistor disclosed in Patent Document 2, the surface of the resistor is covered with a protective film made of a paste containing an epoxy resin.

Depending on how the chip resistor is used, the temperature of the Ni plating layer (intermediate electrode) covering the internal electrodes increases significantly. At this time, thermal shock may occur at the tip of the Ni plating layer (the boundary between the Ni plating layer and the protective film in plan view). When the thermal shock acts on the protective film, cracks occur in the protective film. When the crack develops toward the internal electrode, the internal electrode is exposed. At this time, if sulfide gas is present in the surrounding environment of the electronic device in which the chip resistor is used, the internal electrodes may combine with the sulfide gas, as described above, and the electrodes of the chip resistor may be disconnected.

JP2013-258292A Japanese Patent Application Publication No. 2012-151195

In view of the above-mentioned circumstances, it is an object of the present invention to provide a chip resistor and a method for manufacturing the same, which improve sulfurization resistance while reducing costs. Furthermore, in view of the above-mentioned circumstances, the present invention provides a chip resistor and a method for manufacturing the same that can prevent disconnection of the electrode due to sulfidation even if cracks develop in the protective film due to thermal shock generated in the electrode. The task is to do so.

A chip resistor provided by a first aspect of the present invention includes a substrate having a mounting surface and a mounting surface facing opposite sides, a pair of upper surface electrodes disposed at both ends of the mounting surface of the substrate, and a portion disposed on a side surface of the substrate located between the mounting surface and the mounting surface of the substrate, and a portion overlapping the mounting surface and the mounting surface when viewed in the thickness direction of the substrate, and a side electrode that is electrically connected to the top electrode; a resistor mounted between the pair of top electrodes on the mounting surface of the substrate; an intermediate electrode that covers the side electrode; and an external electrode that covers the intermediate electrode. A chip resistor comprising an electrode, which is located between the top electrode and the intermediate electrode and in contact with the top electrode and the side electrode, and is less susceptible to sulfurization than the top electrode. a first protective layer having a conductive property, located between the first protective layer and the intermediate electrode, and disposed in contact with the first protective layer, the side electrode, and the intermediate electrode; A second protective layer comprising:

Preferably, in the practice of the present invention, the first protective layer includes carbon particles.

Preferably in the practice of the invention, the first protective layer is an electrical insulator.

Preferably, in the practice of the present invention, the second protective layer contains Ag.

Preferably, in the practice of the present invention, the side electrode is made of a Ni--Cr alloy.

Preferably, in the implementation of the present invention, the device further includes a pair of back electrodes arranged at both ends of the mounting surface of the substrate, and the side electrodes are electrically connected to the back electrode.

In implementing the present invention, preferably the back electrode is covered with the intermediate electrode.

Preferably in the practice of the invention, the substrate is an electrical insulator.

Preferably in the practice of the invention, the substrate is made of alumina.

In implementing the present invention, preferably, the resistor has a serpentine shape in plan view.

Preferably, in the practice of the present invention, the resistor includes RuO ₂ or an Ag--Pd alloy.

In the practice of the present invention, preferably, a trimming groove passing through the resistor is formed in the resistor.

In carrying out the present invention, preferably the intermediate electrode and the external electrode are made of a plating layer.

In the practice of the present invention, preferably the intermediate electrode is made of a Ni plating layer.

In the practice of the present invention, preferably, the external electrode is made of a Sn plating layer.

Preferably, in the implementation of the present invention, a protective film covering the resistor and a portion of the upper surface electrode is further provided.

In implementing the present invention, preferably, a portion of the first protective layer is covered with the protective film.

Preferably, in the practice of the present invention, the protective film has a lower protective film and an upper protective film.

In the practice of the present invention, preferably, the lower protective film includes glass.

In the practice of the present invention, preferably, the upper protective film includes an epoxy resin.

A method for manufacturing a chip resistor provided by a second aspect of the present invention includes preparing a sheet-like substrate having a mounting surface and a mounting surface facing oppositely to each other, and placing the mounting surface of the sheet-like substrate on the mounting surface at a distance from each other. forming a top electrode having a pair of regions, and mounting a resistor conductive to the top electrode in a region sandwiched between the pair of regions on the mounting surface of the sheet-like substrate; a step of forming a first protective layer on the upper surface of the upper electrode that has a property of being less susceptible to sulfurization than the upper electrode; and a step of forming a second protective layer having conductivity on the upper surface of the first protective layer. , the step of dividing the sheet-like substrate into a plurality of strip-shaped substrates, and the step of dividing the sheet-like substrate into a plurality of strip-shaped substrates, and the side surfaces, the mounting surface, and the mounting surface located along both ends of the strip-shaped substrate in the longitudinal direction are electrically connected to the upper surface electrode, and the first electrode is electrically connected to the upper surface electrode. a step of forming a side electrode in contact with the first protective layer and the second protective layer, a step of forming an intermediate electrode covering the side electrode and the second protective layer, and an external electrode covering the intermediate electrode, respectively; It is characterized by having the following.

In the practice of the present invention, preferably, in the step of forming the first protective layer, the first protective layer is formed by a method using printing.

In the practice of the present invention, preferably, in the step of forming the second protective layer, the second protective layer is formed by a method using printing.

In implementing the present invention, preferably, in the step of forming the side electrode, the side electrode is formed by physical vapor deposition.

Preferably, in the practice of the present invention, the physical vapor deposition is a sputtering method.

In implementing the present invention, preferably, in the step of mounting the resistor, the resistor is mounted by a method using printing or a method using physical vapor deposition and photolithography.

In the implementation of the present invention, preferably, the method further includes a step of dividing the strip-shaped substrate into a plurality of pieces before the step of forming the intermediate electrode and the external electrode, respectively.

In implementing the present invention, preferably, in the step of forming the intermediate electrode and the external electrode, the intermediate electrode and the external electrode are each formed by plating.

Preferably, the present invention further includes a step of forming a back electrode having a pair of regions spaced apart from each other on the mounting surface of the sheet-like substrate.

Preferably, in the implementation of the present invention, the resistor further includes a step of forming a trimming groove passing through the resistor.

Preferably, the present invention further includes the step of forming a protective film covering the resistor and a portion of each of the upper surface electrode and the first protective layer.

In the practice of the present invention, preferably, the step of forming the protective film includes the steps of forming a lower protective film and forming an upper protective film.

A chip resistor provided by a third aspect of the present invention includes a substrate having a mounting surface and a mounting surface facing opposite to each other, a pair of upper surface electrodes arranged at both ends of the mounting surface of the substrate, and On the mounting surface of the substrate, a resistor mounted between the pair of upper electrodes, a protective film covering the resistor and a part of the upper electrode, and a protective film covering the mounting surface and the mounting surface of the substrate. a side electrode having a portion disposed on a side surface of the substrate located between and a portion overlapping the mounting surface and the mounting surface in a plan view of the substrate, and being electrically connected to the upper surface electrode; A chip resistor comprising an intermediate electrode covering the side electrode and an external electrode covering the intermediate electrode, wherein the protective film has a lower protective film and an upper protective film stacked on each other, and the lower protective film The film is made of a material that is more resistant to thermal shock than the upper protective film, and a portion of the upper electrode is covered with the lower protective film.

In implementing the present invention, preferably, each of the upper surface electrode and the upper protective film is partially covered with the side electrode.

The present invention preferably further includes a protective layer that covers at least a portion of the upper surface of the top electrode and has a property of being less susceptible to sulfurization than the top electrode, and at least a portion of the protective layer covers the side electrode. It is being said.

In implementing the present invention, preferably, a portion of the protective layer is covered with the upper protective film.

Preferably, in the practice of the present invention, the protective layer includes carbon particles.

Preferably in the practice of the invention said protective layer is an electrical insulator.

In the practice of the present invention, preferably, the lower protective film includes glass.

In the practice of the present invention, preferably, the upper protective film includes an epoxy resin.

Preferably, in the practice of the present invention, the side electrode is made of a Ni--Cr alloy.

Preferably, in the implementation of the present invention, the device further includes a pair of back electrodes arranged at both ends of the mounting surface of the substrate, and the side electrodes are electrically connected to the back electrode.

In implementing the present invention, preferably the back electrode is covered with the intermediate electrode.

Preferably in the practice of the invention, the substrate is an electrical insulator.

Preferably in the practice of the invention, the substrate is made of alumina.

In the practice of the present invention, preferably, a trimming groove passing through the resistor is formed in the resistor.

In carrying out the present invention, preferably the intermediate electrode and the external electrode are made of a plating layer.

In the practice of the present invention, preferably the intermediate electrode is made of a Ni plating layer.

In the practice of the present invention, preferably, the external electrode is made of a Sn plating layer.

A method for manufacturing a chip resistor provided by a fourth aspect of the present invention includes preparing a sheet-like substrate having a mounting surface and a mounting surface facing oppositely to each other, and disposing the mounting surface of the sheet-like substrate at a distance from each other. forming a top electrode having a pair of regions, and mounting a resistor conductive to the top electrode in a region sandwiched between the pair of regions on the mounting surface of the sheet-like substrate; forming a lower protective film covering the resistor and part of the upper surface electrode; forming an upper protective film covering the lower protective film; and dividing the sheet-like substrate into a plurality of strip-like substrates. a step of forming a side electrode electrically connected to the upper surface electrode on the side surface, the mounting surface, and the mounting surface located along both longitudinal ends of the strip-shaped substrate; an intermediate electrode covering the side electrode; The method is characterized by comprising a step of forming external electrodes that cover the intermediate electrodes, respectively.

In implementing the present invention, preferably, in the step of forming the side electrode, the side electrode is formed by partially covering each of the upper surface electrode and the upper protective film with the side electrode.

Preferably, the present invention further includes the step of forming a protective layer that covers at least a portion of the upper surface of the upper electrode and has a property of being less susceptible to sulfurization than the upper electrode.

In the practice of the present invention, preferably, in the step of forming the protective layer, the protective layer is formed by a method using printing.

In implementing the present invention, preferably, in the step of forming the side electrode, the side electrode is formed by covering at least a portion of the protective layer with the side electrode.

In implementing the present invention, preferably, in the step of forming the upper protective film, the upper protective film is formed by covering a part of the protective layer with the upper protective film.

In implementing the present invention, preferably, in the step of forming the lower protective film, the lower protective film is formed by a method using printing.

In implementing the present invention, preferably, in the step of forming the upper protective film, the upper protective film is formed by a method using printing.

In implementing the present invention, preferably, in the step of forming the side electrode, the side electrode is formed by physical vapor deposition.

Preferably, in the practice of the present invention, the physical vapor deposition is a sputtering method.

In implementing the present invention, preferably, in the step of forming the intermediate electrode and the external electrode, the intermediate electrode and the external electrode are respectively formed by plating.

In the implementation of the present invention, preferably, the method further includes a step of dividing the strip-shaped substrate into a plurality of pieces before the step of forming the intermediate electrode and the outer electrode, respectively.

Preferably, the present invention further includes a step of forming a back electrode having a pair of regions spaced apart from each other on the mounting surface of the sheet-like substrate.

Preferably, in the implementation of the present invention, the resistor further includes a step of forming a trimming groove passing through the resistor.

The chip resistor according to the present invention includes a first protective layer located between a top electrode and an intermediate electrode and in contact with the top electrode and side electrode. Therefore, the upper surface electrode is covered with the first protective layer. The first protective layer has a property that it is less likely to be sulfurized than the upper electrode. Therefore, the first protective layer prevents the upper electrode from being sulfurized and prevents the upper electrode from being disconnected. Further, in the chip resistor according to the present invention, the chip resistor is located between the first protective layer and the intermediate electrode together with the first protective layer, and the first protective layer, the side electrode, and the intermediate electrode. a second protective layer disposed in contact with the second protective layer; The first protective layer is covered with the second protective layer having conductivity and the side electrode. Therefore, the intermediate electrode is configured not to be in contact with the first protective layer. Therefore, peeling of the plating layer constituting the intermediate electrode can be avoided. As described above, by providing the first protective layer and the second protective layer, it is possible to improve the sulfidation resistance while suppressing the cost of the chip resistor.

Moreover, the chip resistor according to the present invention has a lower protective film and an upper protective film that are stacked on each other, and a part of the upper surface electrode is covered with the lower protective film. The lower protective film is made of a material that is more resistant to thermal shock than the upper protective film. Therefore, even if a crack occurs in the upper protective film due to a thermal shock occurring at the tip of the plating layer that is the intermediate electrode and the outer electrode (the boundary between the plating layer and the upper protective film in plan view), The growth of the crack is suppressed by the lower protective film. Therefore, since the upper surface electrode is not exposed due to the crack, sulfide gas generated around the chip resistor does not enter through the crack to the upper surface electrode. Therefore, even if a crack occurs in the upper protective film due to a thermal shock generated in the electrode, it is possible to prevent the electrode from being disconnected due to sulfidation.

Other features and advantages of the invention will become more apparent from the detailed description given below with reference to the accompanying drawings.

FIG. 1 is a plan view showing a chip resistor according to a first embodiment of the present invention. 2 is a sectional view taken along line II-II in FIG. 1. FIG. FIG. 3 is a partially enlarged cross-sectional view of a part of FIG. 2; FIG. 2 is a plan view showing steps related to the method for manufacturing the chip resistor of FIG. 1; FIG. 2 is a plan view showing steps related to the method for manufacturing the chip resistor of FIG. 1; FIG. 2 is a plan view showing steps related to the method for manufacturing the chip resistor of FIG. 1; FIG. 2 is a plan view showing steps related to the method for manufacturing the chip resistor of FIG. 1; FIG. 2 is a plan view showing steps related to the method for manufacturing the chip resistor of FIG. 1; FIG. 2 is a plan view showing steps related to the method for manufacturing the chip resistor of FIG. 1; FIG. 2 is a plan view showing steps related to the method for manufacturing the chip resistor of FIG. 1; FIG. 2 is a plan view showing steps related to the method for manufacturing the chip resistor of FIG. 1; FIG. 2 is a perspective view showing steps related to the method for manufacturing the chip resistor of FIG. 1; FIG. 2 is a perspective view showing steps related to the method for manufacturing the chip resistor of FIG. 1; FIG. 2 is a perspective view showing steps related to the method for manufacturing the chip resistor of FIG. 1; FIG. 2 is a perspective view showing steps related to the method for manufacturing the chip resistor of FIG. 1; It is a top view which shows the chip resistor based on 2nd Embodiment of this invention. 17 is a sectional view taken along line XVII-XVII in FIG. 16. FIG. It is a top view which shows the chip resistor based on 3rd Embodiment of this invention. 19 is a sectional view taken along line XIX-XIX in FIG. 18. FIG. FIG. 20 is a partially enlarged cross-sectional view of a portion of FIG. 19; FIG. 19 is a plan view showing steps related to the method for manufacturing the chip resistor of FIG. 18; FIG. 19 is a plan view showing steps related to the method for manufacturing the chip resistor of FIG. 18; FIG. 19 is a plan view showing steps related to the method for manufacturing the chip resistor of FIG. 18; FIG. 19 is a plan view showing steps related to the method for manufacturing the chip resistor of FIG. 18; FIG. 19 is a plan view showing steps related to the method for manufacturing the chip resistor of FIG. 18; FIG. 19 is a plan view showing steps related to the method for manufacturing the chip resistor of FIG. 18; FIG. 19 is a perspective view showing steps related to the method for manufacturing the chip resistor of FIG. 18; FIG. 19 is a perspective view showing steps related to the method for manufacturing the chip resistor of FIG. 18; FIG. 19 is a perspective view showing steps related to the method for manufacturing the chip resistor of FIG. 18; FIG. 19 is a perspective view showing steps related to the method for manufacturing the chip resistor of FIG. 18; It is a top view which shows the chip resistor based on 4th Embodiment of this invention. 32 is a sectional view taken along the line XXXII-XXXII in FIG. 31. FIG. FIG. 33 is a partially enlarged cross-sectional view of a portion of FIG. 32; FIG. 32 is a plan view showing steps related to the method for manufacturing the chip resistor of FIG. 31;

DESCRIPTION OF THE PREFERRED EMBODIMENTS A mode for carrying out the present invention will be described based on the accompanying drawings.

[First embodiment]
A chip resistor A1 according to a first embodiment of the present invention will be explained based on FIGS. 1 to 3. Here, in FIG. 1, for convenience of understanding, an intermediate electrode 34, an external electrode 35, and a protective film 5, which will be described later, are omitted.

The chip resistor A1 shown in these figures is of a type that is surface mounted on circuit boards of various electronic devices. The chip resistor A1 according to this embodiment includes a substrate 1, a resistor 2, an electrode 3, a protective layer 4, and a protective film 5. In this embodiment, the chip resistor A1 has a rectangular shape in plan view. The chip resistor A1 according to this embodiment is a so-called thick film (metal glaze film) chip resistor.

As shown in FIGS. 1 and 2, the substrate 1 is a member on which a resistor 2 is mounted and a chip resistor A1 is mounted on a circuit board of various electronic devices. Substrate 1 is an electrical insulator. In this embodiment, the substrate 1 is made of, for example, alumina (Al ₂ O ₃ ). In order to easily dissipate heat generated by the resistor 2 to the outside when the chip resistor A1 is used, the substrate 1 is preferably made of a material with high thermal conductivity. The substrate 1 has a mounting surface 11, a mounting surface 12, and a side surface 13. In this embodiment, the substrate 1 has a rectangular shape in plan view.

The mounting surface 11 is the upper surface of the substrate 1 shown in FIG. 2, and is the surface on which the resistor 2 is mounted. The mounting surface 12 is the lower surface of the substrate 1 shown in FIG. 2, and is a surface used when mounting the chip resistor A1 on a circuit board of various electronic devices. The mounting surface 11 and the mounting surface 12 face opposite sides of each other. As shown in FIGS. 1 and 2, the side surfaces 13 are a pair of surfaces that are perpendicular to the mounting surface 11 and the mounting surface 12 and face in the longitudinal direction of the substrate 1 (direction X shown in FIG. 1). The side surface 13 is located between the mounting surface 11 and the mounting surface 12.

The resistor 2 is an element that functions to limit current or detect current. In this embodiment, the shape of the resistor 2 in plan view is a band shape extending in the direction X shown in FIG. The resistor 2 is made of a paste containing a metal such as RuO ₂ or an Ag--Pd alloy. In this embodiment, the shape of the resistor 2 in plan view is a band shape, but the shape can be any shape, such as a serpentine shape. The resistor 2 has a trimming groove 21.

The trimming groove 21 is a groove that penetrates the resistor 2 in the thickness direction, as shown in FIGS. 1 and 2. The trimming groove 21 forms an opening in the side surface of the resistor 2 along the longitudinal direction (direction X shown in FIG. 1). In this embodiment, an L-shaped trimming groove 21 is formed in the resistor 2 when viewed from above. The trimming groove 21 is formed to adjust the resistance value of the resistor 2 to a specified value.

As shown in FIGS. 1 to 3, the electrodes 3 are a pair of members spaced apart from each other for conducting to the resistor 2 and interconnecting the chip resistor A1 and the wiring patterns of the circuit boards of various electronic devices. It is. The electrodes 3 are arranged on both sides of the resistor 2 in the direction X shown in FIG. In this embodiment, the electrode 3 includes a top electrode 31, a back electrode 32, a side electrode 33, an intermediate electrode 34, and an external electrode 35.

As shown in FIGS. 1 to 3, the upper surface electrode 31 has a pair of regions spaced apart from each other and arranged at both ends of the mounting surface 11 of the substrate 1. The upper surface electrode 31 has a rectangular shape in plan view. Further, a part of the upper electrode 31 is sandwiched between the mounting surface 11 and the resistor 2. Therefore, the resistor 2 is electrically connected to the upper electrode 31. The upper surface electrode 31 is made of a paste containing Ag, for example.

As shown in FIGS. 1 to 3, the back electrode 32 has a pair of regions spaced apart from each other and arranged at both ends of the mounting surface 12 of the substrate 1. The planar shape of the back electrode 32 is substantially the same as the top electrode 31 (not shown). The back electrode 32, like the top electrode 31, is made of a paste containing Ag, for example. Note that the back electrode 32 can be omitted.

As shown in FIGS. 1 to 3, the side electrode 33 has a pair of regions arranged on the side surface 13 of the substrate 1 and spaced apart from each other. In addition to the side surface 13, the side surface electrode 33 covers a portion of each of the top surface electrode 31, the back surface electrode 32, and the protective layer 4. That is, the side electrode 33 has a portion disposed on the side surface 13 and a portion overlapping with the mounting surface 11 and the mounting surface 12 of the substrate 1 when viewed in the thickness direction of the substrate 1. The top electrode 31 and the back electrode 32 are electrically connected to each other by the side electrode 33 . Therefore, the resistor 2 is electrically connected to the back electrode 32 through the top electrode 31 and the side electrode 33 . In this embodiment, the side electrode 33 is made of, for example, a Ni--Cr alloy. Note that the material of the side electrode 33 may be any metal as long as it has conductivity and is resistant to sulfurization.

As shown in FIGS. 2 and 3, the intermediate electrode 34 is a pair of portions that cover the back electrode 32, the side electrode 33, and the protective layer 4 and are spaced apart from each other. In this embodiment, the intermediate electrode 34 is made of, for example, a Ni plating layer. The intermediate electrode 34 functions to protect the electrode 3 from heat and shock.

As shown in FIGS. 2 and 3, the external electrodes 35 are a pair of parts that cover the intermediate electrode 34 and are spaced apart from each other. In this embodiment, the external electrode 35 is made of, for example, a Sn plating layer. By attaching solder to the external electrode 35 and integrating the external electrode 35 with the solder, the chip resistor A1 and the wiring pattern of the circuit board of various electronic devices are interconnected. In this embodiment, since the intermediate electrode 34 is made of a Ni plating layer, it is difficult to directly attach solder to the intermediate electrode 34. Therefore, the external electrode 35 made of a Sn plating layer is required.

The protective layer 4 is a pair of members spaced apart from each other and covers at least a portion of the upper surface electrode 31, as shown in FIGS. 1 to 3. In this embodiment, the protective layer 4 includes a first protective layer 41 and a second protective layer 42 . The protective layer 4 functions to prevent the upper electrode 31 from being sulfurized.

The first protective layer 41 has a pair of regions spaced apart from each other, which are formed on the upper surface of the upper surface electrode 31 shown in FIGS. 2 and 3. The first protective layer 41 has a property that it is less likely to be sulfided than the upper electrode 31. Further, the first protective layer 41 is located between the upper surface electrode 31 and the intermediate electrode 34 and is disposed in contact with the upper surface electrode 31 and the side electrode 33. In this embodiment, the first protective layer 41 is made of a paste containing glass and metal oxide, such as Ru, carbon particles (carbon black), and epoxy resin. In this case, the first protective layer 41 has conductivity. Here, the first protective layer 41 may be an electrical insulator. The first protective layer 41, which is an electrical insulator, is made of, for example, a paste containing glass.

The second protective layer 42 has a pair of regions spaced apart from each other, which are formed on the upper surface of the first protective layer 41 shown in FIGS. 2 and 3. The second protective layer 42 has conductivity. Further, the second protective layer 42 is located between the first protective layer 41 and the intermediate electrode 34 and is disposed in contact with the first protective layer 41, the side electrode 33, and the intermediate electrode 34. In this embodiment, the second protective layer 42 is made of a paste containing, for example, Ag and epoxy resin.

As shown in FIGS. 1 to 3, the protective film 5 is a member that covers the resistor 2 and serves to protect the resistor 2 from the outside. The protective film 5 has a lower protective film 51 and an upper protective film 52. The lower protective film 51 covers the surface of the resistor 2 (the upper surface of the resistor 2 shown in FIG. 2). The lower protective film 51 is made of, for example, a paste containing glass. The upper protective film 52 covers a portion of the substrate 1 , the resistor 2 , and a portion of the upper electrode 31 . In this embodiment, a portion of the first protective layer 41 is covered with an upper protective film 52. Here, a part of the upper protective film 52 may be covered with the first protective layer 41. The upper protective film 52 is made of, for example, a paste containing epoxy resin.

Next, a method for manufacturing the chip resistor A1 will be explained based on FIGS. 4 to 15. 4 to 11 are plan views showing steps related to the method for manufacturing the chip resistor A1. 12 to 15 are perspective views showing steps related to the method for manufacturing the chip resistor A1. Note that in FIGS. 10 to 15, the lower protective film 51 of the protective film 5 is omitted for convenience of understanding. 12 and 13, for convenience of understanding, the respective thicknesses of the resistor 2, top electrode 31, side electrode 33, first protective layer 41, second protective layer 42, and upper protective film 52 are ignored. ing.

First, as shown in FIG. 4, a sheet-like substrate 81 made of alumina is prepared. The sheet-like substrate 81 has a mounting surface 11 and a mounting surface 12. The mounting surface 11 and the mounting surface 12 face opposite sides of each other. FIG. 4 shows the mounting surface 11 of the sheet-like substrate 81. On the mounting surface 11, a plurality of primary dividing grooves 811 are formed in the vertical direction as shown in FIG. 4, and a plurality of secondary dividing grooves 812 are formed in the horizontal direction as shown in FIG. 4 in a checkerboard pattern. The same number of primary dividing grooves 811 and secondary dividing grooves 812 are formed on the mounting surface 12 opposite to the mounting surface 11 (not shown). The positions of the primary dividing groove 811 and the secondary dividing groove 812 in plan view are the same on both the mounting surface 11 and the mounting surface 12. The section formed by the primary dividing groove 811 and the secondary dividing groove 812 is a region corresponding to the substrate 1 of the chip resistor A1.

Next, as shown in FIG. 5, the upper surface electrode 31 is formed on the mounting surface 11 of the sheet-like substrate 81 so as to straddle the primary dividing groove 811 of the sheet-like substrate 81. At the same time, a back electrode 32 is formed on the mounting surface 12 of the sheet-like substrate 81 so as to straddle the primary dividing groove 811 (not shown). The positions and sizes of the top electrode 31 and the back electrode 32 in plan view are substantially the same. In this embodiment, the top electrode 31 and the back electrode 32 are formed by printing a paste of Ag containing glass frit on the mounting surface 11 and the mounting surface 12 using a silk screen, respectively, and firing the paste in a firing furnace. It is formed. Through this step, the top electrode 31 and the back electrode 32 having a pair of regions spaced apart from each other are formed on the mounting surface 11 and the mounting surface 12.

Next, as shown in FIG. 6, on the mounting surface 11 of the sheet-like substrate 81, a resistor 2 that is electrically connected to the upper surface electrode 31 is mounted in a region sandwiched between the pair of regions that the upper surface electrode 31 has. In this embodiment, the resistor 2 is mounted by printing a paste made of metal such as RuO ₂ or Ag--Pd alloy containing glass frit using a silk screen and firing it in a firing furnace.

Next, as shown in FIG. 7, a first protective layer 41 having a property of being less susceptible to sulfurization than the upper electrode 31 is formed on the upper surface of the upper electrode 31 and in a region sandwiched between the resistors 2. In this embodiment, the first protective layer 41 is formed by printing a paste containing glass made of Ru or the like, a metal oxide, carbon particles, and an epoxy resin using a silk screen and curing the paste. Ru. The first protective layer 41 in this case has conductivity. When the first protective layer 41 is an electrical insulator, it is formed by printing a paste containing glass using a silk screen and firing it in a firing furnace. Here, in forming the first protective layer 41 having conductivity, a gap is provided between the first protective layer 41 and the resistor 2 in plan view so that the first protective layer 41 does not come into contact with the resistor 2. . This is because when the first protective layer 41 comes into contact with the resistor 2, the resistance value of the chip resistor A1 changes. Through this step, a part of the upper surface electrode 31 is covered with the first protective layer 41.

Next, as shown in FIG. 8, a conductive second protective layer 42 is formed on the upper surface of the first protective layer 41. In this embodiment, the second protective layer 42 is formed by printing a paste containing Ag and epoxy resin using a silk screen and curing the paste. When forming the second protective layer 42, the first protective layer 41 is exposed at the end of the second protective layer 42 adjacent to the resistor 2. Through this step, a portion of the first protective layer 41 is covered with the second protective layer 42.

Next, as shown in FIG. 9, a lower protective film 51 covering the surface of the resistor 2 is formed. In this embodiment, the lower protective film 51 is formed by printing a paste containing glass using a silk screen and firing it in a firing furnace. In the step of forming the trimming groove 21 in the resistor 2, which is the subsequent step of the post-process, since the groove is formed by laser, a thermal shock is applied to the resistor 2 and fine particles of the resistor 2 are generated. . Therefore, the lower protective film 51 has the function of mitigating the thermal shock and preventing the fine particles from re-adhering to the resistor 2 and causing the resistance value of the resistor 2 to fluctuate.

Next, as shown in FIG. 10, a trimming groove 21 passing through the resistor 2 is formed in the resistor 2. The trimming groove 21 is formed by a laser trimming device (not shown). The procedure for forming the trimming groove 21 is as follows. First, trimming grooves 21 are formed from one side of a pair of side surfaces along the longitudinal direction of the resistor 2 toward the other side so as to be perpendicular to the direction of current flowing through the resistor 2 . Next, after the resistance value of the resistor 2 has increased to a value close to the required value of the chip resistor A1, the resistor 2 is kept parallel to the direction of the current flowing through the resistor 2 (the longitudinal direction of the resistor 2). The direction is changed by 90° to form the trimming groove 21. When the resistance value of the resistor 2 reaches the required value of the chip resistor A1, the formation of the trimming groove 21 is completed. Through this process, an L-shaped trimming groove 21 is formed in the resistor 2 in plan view. Note that the trimming groove 21 is formed while a resistance value measuring probe (not shown) is brought into contact with both ends of the resistor 2 in the longitudinal direction.

Next, as shown in FIG. 11, an upper protective film 52 is formed on the mounting surface 11 of the sheet-like substrate 81. At this time, in addition to the resistor 2, a portion of each of the upper surface electrode 31 and the first protective layer 41 is covered with the upper protective film 52. Note that the second protective layer 42 is not covered by the upper protective film 52. In this embodiment, the upper protective film 52 is formed in a plurality of strips extending along the primary dividing groove 811 of the sheet-like substrate 81 so as to straddle the secondary dividing groove 812 of the sheet-like substrate 81 . Further, in this embodiment, the upper protective film 52 is formed by printing a paste containing an epoxy resin using a silk screen and curing the paste. Note that the upper protective film 52 may be formed so as to be separated for each resistor 2, similarly to the lower protective film 51 of the protective film 5 shown in FIG.

Next, as shown in FIG. 12, the sheet-like substrate 81 is cut along the primary dividing grooves 811 of the sheet-like substrate 81 to divide it into a plurality of strip-like substrates 86. At this time, side surfaces 13 are formed on both sides of the strip substrate 86 along the longitudinal direction of the strip substrate 86.

Next, as shown in FIG. 13, side electrodes 33 are formed on side surfaces 13 located along both ends of the strip substrate 86 in the longitudinal direction, and on portions of each of the mounting surface 11 and the mounting surface 12. In this embodiment, the side electrodes 33 are formed by forming a film of a Ni--Cr alloy by physical vapor deposition (PVD) using a sputtering method or the like. In forming the side electrode 33, the side electrode 33 is formed so that the side surface 13, and a portion of each surface of the second protective layer 42 and the back electrode 32, which are arranged orthogonally to the side surface 13, are integrally covered with the side electrode 33. (The back electrode 32 is not shown). At this time, the side electrode 33 contacts the respective ends of the second protective layer 42 , the first protective layer 41 , the top electrode 31 , and the back electrode 32 along the side surface 13 . Through this process, the top electrode 31 and the back electrode 32 are electrically connected to each other through the side electrode 33.

Next, as shown in FIG. 14, the strip substrate 86 is cut along the secondary dividing groove 812 of the strip substrate 86 to divide it into a plurality of individual pieces 87. At this time, the shape of the side electrode 33 becomes a U-shape with the substrate 1 sandwiched therebetween. Further, the side electrodes 33 are arranged on the mounting surface 11 and the mounting surface 12 of the substrate 1, which are located at both ends of the side electrode 33 formed on a part of the surface of the second protective layer 42 and the back electrode 32, respectively. (The back electrode 32 is not shown).

Next, as shown in FIG. 15, in each piece 87, an intermediate electrode 34 that covers the back electrode 32, the side electrode 33, and the second protective layer 42, and an external electrode 35 that covers the intermediate electrode 34 are formed. 32 (not shown). In this embodiment, the intermediate electrode 34 is formed by Ni plating, and the external electrode 35 is formed by Sn plating. Through this process, a pair of electrodes 3 that are electrically connected to the resistor 2 are formed. Through the above steps, chip resistor A1 is manufactured.

Next, the effects of the chip resistor A1 will be explained.

According to this embodiment, the chip resistor A1 has the first protective layer 41 located between the top electrode 31 and the intermediate electrode 34 and in contact with the top electrode 31 and the side electrode 33. Therefore, at least a portion of the upper electrode 31 is covered with the first protective layer 41. Since the first protective layer 41 contains carbon particles, it has a property that it is less likely to be sulfurized than the upper electrode 31. Therefore, the first protective layer 41 prevents the upper surface electrode 31 from being sulfurized, thereby avoiding disconnection of the upper surface electrode 31.

In addition, the chip resistor A1 is located between the first protective layer 41 and the intermediate electrode 34 together with the first protective layer 41, and is in contact with the first protective layer 41, the side electrode 33, and the intermediate electrode 34. A second protective layer 42 is provided. The second protective layer 42 contains Ag and is therefore electrically conductive. The first protective layer 41 is covered with a second protective layer 42 and a side electrode 33 that also has conductivity. Therefore, the intermediate electrode 34 is configured not to be in contact with the first protective layer 41 containing carbon particles. Therefore, peeling of the Ni plating layer that is the intermediate electrode 34 can be avoided.

From the above, the cost of the chip resistor A1 can be reduced by providing the first protective layer 41, which has a property of being less susceptible to sulfurization than the upper surface electrode 31 containing carbon particles, and the second protective layer 42, which contains Ag and has conductivity. It becomes possible to improve the sulfurization resistance while suppressing the sulfidation resistance.

Most of the sulfide gas that causes sulfidation of the upper surface electrode 31 and the like is generated along the interface between the plating layer forming the intermediate electrode 34 and the outer electrode 35 and the upper protective film 52 of the protective film 5 in the chip resistor A1. It enters inside the chip resistor A1. Therefore, by configuring the first protective layer 41 to be partially covered with the upper protective film 52, the effect of shielding the sulfide gas that has entered along the interface becomes greater. Note that even if the first protective layer 41 partially covers the upper protective film 52, the sulfurization resistance of the chip resistor A1 is ensured.

If sulfide gas enters along the interface, the second protective layer 42 containing Ag will be preferentially sulfurized. That is, the second protective layer 42 functions similar to a sacrificial electrode. Further, since the second protective layer 42 is configured so as not to contact the top electrode 31 due to the first protective layer 41 and the side electrode 33, the top electrode 31 will not be sulfurized even if the second protective layer 42 is sulfurized. Therefore, by having the second protective layer 42 containing Ag, it is possible to further improve the sulfidation resistance of the chip resistor A1.

By making the material of the side electrode 33 a Ni--Cr alloy that has conductivity and has characteristics that prevent it from sulfiding, the side electrode 33 will not sulfurize. Therefore, disconnection of the side electrode 33 is avoided, and sulfidation of the upper surface electrode 31 via the side electrode 33 is prevented. Furthermore, since the side electrodes 33 are formed by physical vapor deposition such as sputtering, the first protective layer 41 in contact with the side electrodes 33 can be an electrical insulator. In this case, since the first protective layer 41 is made of, for example, a paste containing glass, it is possible to further reduce the cost of the chip resistor A1.

[Second embodiment]
A chip resistor A2 according to a second embodiment of the present invention will be described based on FIGS. 16 and 17. In these figures, the same or similar elements as those of the chip resistor A1 described above are given the same reference numerals, and redundant explanation will be omitted.

Here, in FIG. 16, for convenience of understanding, the intermediate electrode 34, the external electrode 35, and the protective film 5 are omitted. In this embodiment, the chip resistor A2 has a rectangular shape in plan view.

The chip resistor A2 according to this embodiment is different from the chip resistor A1 in the plan view shape of the resistor 2 and the configuration of the protective film 5. In this embodiment, the resistor 2 has a serpentine shape in plan view. The resistor 2 having this shape can be formed by a method using photolithography after the resistor 2 is mounted on the mounting surface 11 of the substrate 1 by physical vapor deposition using a sputtering method or the like. In this case, the resistor 2 is made of, for example, a Ni--Cr alloy. That is, the chip resistor A2 according to this embodiment is a so-called thin film chip resistor. Furthermore, in this embodiment, the lower protective film 51 of the protective film 5 is omitted.

Next, the effects of the chip resistor A2 will be explained.

Also in this embodiment, similarly to the chip resistor A1, a first protective layer 41 having a property of being less susceptible to sulfurization than the upper surface electrode 31 containing carbon particles, and a second protective layer 42 containing Ag and having conductivity are used. By providing this, it is possible to improve the sulfurization resistance while suppressing the cost of the chip resistor A2. Further, by making the resistor 2 have a serpentine shape in plan view, the resistance value of the chip resistor A2 can be made relatively higher than that of the chip resistor A1, and the accuracy of the resistance value can be improved.

[Third embodiment]
A chip resistor A3 according to a third embodiment of the present invention will be described based on FIGS. 18 to 20. In these figures, the same or similar elements as those of the chip resistor A1 described above are given the same reference numerals, and redundant explanation will be omitted.

Here, in FIG. 18, for convenience of understanding, the intermediate electrode 34 and the external electrode 35 are omitted. The chip resistor A3 according to this embodiment is a so-called thick film chip resistor like the chip resistor A1. Furthermore, in this embodiment, the chip resistor A3 has a rectangular shape in plan view.

The chip resistor A3 of this embodiment differs from the chip resistor A1 in that the protective layer 4 is omitted and the configurations of the electrode 3 and the protective film 5 are different.

The electrode 3 according to this embodiment has a top electrode 31, a back electrode 32, a side electrode 33, an intermediate electrode 34, and an external electrode 35, like the chip resistor A1. Among these, the configurations of the side electrode 33, intermediate electrode 34, and external electrode 35 are different from that of the chip resistor A1.

The side electrode 33 is a portion disposed on the side surface 13 of the substrate 1, as shown in FIGS. 18 to 20. In addition to the side surface 13, the side surface electrode 33 covers a portion of each of the top surface electrode 31, the back surface electrode 32, and the top protective film 52. That is, the side electrode 33 has a portion disposed on the side surface 13 and a portion overlapping with the mounting surface 11 and the mounting surface 12 of the substrate 1 when the substrate 1 is viewed from above. The top electrode 31 and the back electrode 32 are electrically connected to each other by the side electrode 33 . Therefore, the resistor 2 is electrically connected to the back electrode 32 through the top electrode 31 and the side electrode 33 . In this embodiment, the side electrode 33 is made of, for example, a Ni--Cr alloy. Note that the material of the side electrode 33 may be any metal as long as it has conductivity and is resistant to sulfurization.

The intermediate electrode 34 is a portion that covers the back electrode 32 and the side electrode 33, as shown in FIGS. 19 and 20. In this embodiment, the intermediate electrode 34 is made of, for example, a Ni plating layer.

The external electrode 35 is a portion that covers the intermediate electrode 34, as shown in FIGS. 19 and 20. In this embodiment, the external electrode 35 is made of, for example, a Sn plating layer.

The protective film 5 is a member that covers the resistor 2 and protects the resistor 2 from the outside, as shown in FIGS. 18 to 20. The protective film 5 has a lower protective film 51 and an upper protective film 52. The lower protective film 51 and the upper protective film 52 are stacked on each other. Both the lower protective film 51 and the upper protective film 52 are electrical insulators. The lower protective film 51 according to this embodiment is made of a material that is more resistant to thermal shock than the upper protective film 52.

The lower protective film 51 is a portion that covers the resistor 2 . The lower protective film 51 is located below the upper protective film 52 shown in FIGS. 19 and 20. The lower protective film 51 covers not only the resistor 2 but also a part of the surface of the upper electrode 31 (the upper surface of the upper electrode 31 shown in FIGS. 19 and 20). As shown in FIG. 18, the lower protective film 51 has a shape that extends outward toward the side surface 13 of the substrate 1 from the boundary between the side electrode 33 and the upper protective film 52 in a plan view of the chip resistor A3. It becomes. The lower protective film 51 is made of, for example, a paste containing glass.

The upper protective film 52 is a portion that covers parts of the substrate 1 and the upper electrode 31, and the lower protective film 51 that covers the resistor 2. The upper protective film 52 is located above the lower protective film 51 shown in FIGS. 19 and 20. In this embodiment, a portion of the upper protective film 52 is covered with the side electrode 33. The upper protective film 52 is made of, for example, a paste containing epoxy resin.

Next, a method for manufacturing the chip resistor A3 will be described based on FIGS. 21 to 30. FIGS. 21 to 6 are plan views showing steps related to the method for manufacturing the chip resistor A3. 27 to 30 are perspective views showing steps related to the method of manufacturing chip resistor A3. 27 and 28 ignore the respective thicknesses of the resistor 2, the upper surface electrode 31, the side electrode 33, the lower protective film 51, and the upper protective film 52 for convenience of understanding.

First, as shown in FIG. 21, a sheet-like substrate 81 made of alumina is prepared. The sheet-like substrate 81 has a mounting surface 11 and a mounting surface 12. The mounting surface 11 and the mounting surface 12 face opposite sides of each other. FIG. 21 shows the mounting surface 11 of the sheet-like substrate 81. On the mounting surface 11, a plurality of primary dividing grooves 811 are formed in the vertical direction as shown in FIG. 21, and a plurality of secondary dividing grooves 812 are formed in the horizontal direction as shown in FIG. 21 in a checkerboard pattern. The same number of primary dividing grooves 811 and secondary dividing grooves 812 are formed on the mounting surface 12 as on the mounting surface 11 (not shown). The positions of the primary dividing groove 811 and the secondary dividing groove 812 in plan view are the same on both the mounting surface 11 and the mounting surface 12. The section formed by the primary dividing groove 811 and the secondary dividing groove 812 is a region that becomes the substrate 1 of the chip resistor A3.

Next, as shown in FIG. 22, the upper surface electrode 31 is formed on the mounting surface 11 of the sheet-like substrate 81 so as to straddle the primary dividing groove 811 of the sheet-like substrate 81. At the same time, a back electrode 32 is formed on the mounting surface 12 of the sheet-like substrate 81 so as to straddle the primary dividing groove 811 (not shown). The positions of the top electrode 31 and the back electrode 32 in plan view are substantially the same. In this embodiment, the top electrode 31 and the back electrode 32 are formed by printing a paste of Ag containing glass frit on the mounting surface 11 and the mounting surface 12 using a silk screen, respectively, and firing the paste in a firing furnace. It is formed. Through this step, the top electrode 31 and the back electrode 32 having a pair of regions spaced apart from each other are formed on the mounting surface 11 and the mounting surface 12.

Next, as shown in FIG. 23, on the mounting surface 11 of the sheet-like substrate 81, a resistor 2 that is electrically connected to the upper surface electrode 31 is mounted in a region sandwiched between the pair of regions that the upper surface electrode 31 has. In this embodiment, the resistor 2 is mounted by printing a paste made of metal such as RuO2 or Ag--Pd alloy containing glass frit using a silk screen and firing it in a firing furnace.

Next, as shown in FIG. 24, a lower protective film 51 covering the surface of the resistor 2 is formed. In this embodiment, the lower protective film 51 is formed by printing a paste containing glass using a silk screen and firing it in a firing furnace. Through this step, the surface of the resistor 2 and a portion of the upper electrode 31 are covered with the lower protective film 51.

Next, as shown in FIG. 25, a trimming groove 21 passing through the resistor 2 is formed in each of the resistors 2. The trimming groove 21 is formed by a laser trimming device (not shown). The procedure for forming the trimming groove 21 is the same as the procedure for forming the trimming groove 21 in the chip resistor A1 shown in FIG. 10 described above. Through this process, an L-shaped trimming groove 21 is formed in the resistor 2 in plan view. Note that the trimming groove 21 is formed while a resistance value measuring probe (not shown) is brought into contact with the exposed portion of the pair of upper surface electrodes 31 that sandwich the resistor 2 .

Next, as shown in FIG. 26, an upper protective film 52 is formed on the mounting surface 11 of the sheet-like substrate 81. At this time, the lower protective film 51 that covers the surface of the resistor 2 and a part of the upper electrode 31 and a part of the upper electrode 31 are covered with the upper protective film 52 . In this embodiment, the upper protective film 52 is formed in a plurality of strips extending along the primary dividing groove 811 of the sheet-like substrate 81 so as to straddle the secondary dividing groove 812 of the sheet-like substrate 81 . Further, in this embodiment, the upper protective film 52 is formed by printing a paste containing an epoxy resin using a silk screen and curing the paste. Note that the upper protective film 52 may be formed so as to be separated for each resistor 2, similarly to the lower protective film 51 shown in FIG.

Next, as shown in FIG. 27, the sheet-like substrate 81 is cut along the primary dividing grooves 811 of the sheet-like substrate 81 to divide it into a plurality of strip-like substrates 86. At this time, side surfaces 13 are formed on both sides of the strip substrate 86 along the longitudinal direction of the strip substrate 86.

Next, as shown in FIG. 28, side electrodes 33 are formed on side surfaces 13 located along both ends of the strip substrate 86 in the longitudinal direction, and on portions of each of the mounting surface 11 and the mounting surface 12. In this embodiment, the side electrodes 33 are formed by depositing a Ni--Cr alloy by physical vapor deposition using sputtering or the like. In forming the side electrode 33, the side surface 13 and a portion of each surface of the top surface electrode 31, the back surface electrode 32, and the top protective film 52, which are arranged orthogonally to the side surface 13, are integrated into the side surface electrode 33. (The back electrode 32 is not shown). At this time, the side electrode 33 contacts the respective ends of the top electrode 31 and the back electrode 32 along the side surface 13. Through this process, the top electrode 31 and the back electrode 32 are electrically connected to each other through the side electrode 33.

Next, as shown in FIG. 29, the strip substrate 86 is cut along the secondary dividing grooves 812 of the strip substrate 86 to divide it into a plurality of individual pieces 87. At this time, the shape of the side electrode 33 becomes a U-shape with the substrate 1 sandwiched therebetween. Further, the side electrode 33 is located on one side of the mounting surface 11 and the mounting surface 12 of the substrate 1, which are located on both sides of the side electrode 33 formed on a part of the surface of the top electrode 31 and the back electrode 32, respectively. They are also formed in each section.

Next, as shown in FIG. 30, in each piece 87, an intermediate electrode 34 that covers the back electrode 32 and the side electrode 33, and an external electrode 35 that covers the intermediate electrode 34 are formed (the back electrode 32 is not shown). In this embodiment, the intermediate electrode 34 is formed by Ni plating, and the external electrode 35 is formed by Sn plating. Through this process, a pair of electrodes 3 that are electrically connected to the resistor 2 are formed. Through the above steps, chip resistor A3 is manufactured.

Next, the effects of the chip resistor A3 will be explained.

According to this embodiment, the chip resistor A3 has a lower protective film 51 and an upper protective film 52 that are stacked on each other, and a part of the upper surface electrode 31 is covered with the lower protective film 51. . The lower protective film 51 is made of a material that is more resistant to thermal shock than the upper protective film 52. Therefore, cracks are generated in the upper protective film 52 due to thermal shock generated at the tips of the plating layers that are the intermediate electrode 34 and the outer electrode 35 (the boundary between the plating layer and the upper protective film 52 in plan view). Also, the growth of the crack is suppressed by the lower protective film 51. Therefore, since the upper surface electrode 31 is not exposed due to the crack, the sulfide gas generated around the chip resistor A3 does not enter the upper surface electrode 31 through the crack. Therefore, even if a crack occurs in the upper protective film 52 due to the thermal shock generated in the electrode 3, it is possible to prevent the electrode 3 from being disconnected due to sulfidation.

Sulfurization of the side electrode 33 is suppressed by using a Ni--Cr alloy that is conductive and resistant to sulfidation as the material of the side electrode 33. Therefore, disconnection of the side electrode 33 is avoided, and sulfidation of the upper surface electrode 31 via the side electrode 33 is also avoided. Furthermore, since the side electrodes 33 are formed by physical vapor deposition such as sputtering, the adhesion performance with the upper protective film 52, which is an electrical insulator, is further improved. Therefore, peeling of the Ni plating layer that is the intermediate electrode 34 together with the side electrode 33 is avoided, so that the fear that a part of the upper electrode 31 is exposed due to the peeling and that the exposed portion is sulfurized is eliminated.

[Fourth embodiment]
A chip resistor A4 according to a fourth embodiment of the present invention will be described based on FIGS. 31 to 33. In these figures, the same or similar elements as those of the chip resistor A1 described above are given the same reference numerals, and redundant explanation will be omitted.

Here, in FIG. 31, for convenience of understanding, the intermediate electrode 34 and the external electrode 35 are omitted. The chip resistor A4 according to this embodiment is a so-called thick film chip resistor like the chip resistor A1. Furthermore, in this embodiment, the chip resistor A4 has a rectangular shape in plan view.

The chip resistor A4 of this embodiment differs from the chip resistor A1 in the configurations of the protective layer 4 and the protective film 5.

The protective layer 4 is a member formed on the upper surface of the upper electrode 31 and has a pair of regions spaced apart from each other, as shown in FIGS. 31 to 33. The protective layer 4 has a property that it is less likely to be sulfurized than the upper electrode 31. In this embodiment, the protective layer 4 covers a portion of each of the upper surface electrode 31 and the lower protective film 51. Note that the protective layer 4 does not need to cover a part of the lower protective film 51. Further, in this embodiment, a portion of the protective layer 4 is covered by the side electrode 33 and the upper protective film 52, respectively, and is in contact with the side electrode 33 on a surface that is aligned with the side surface 13 of the substrate 1. Like the first protective layer 41 of the chip resistor A1, the protective layer 4 according to the present embodiment is made of a paste containing glass and metal oxide such as Ru, carbon particles (carbon black), and epoxy resin. Become. In this case, the protective layer 4 has conductivity. Note that the protective layer 4 may be an electrical insulator made of a paste containing glass, for example.

The protective film 5 is a member that covers the resistor 2 and protects the resistor 2 from the outside, as shown in FIGS. 31 to 33. The protective film 5 has a lower protective film 51 and an upper protective film 52. The lower protective film 51 and the upper protective film 52 are stacked on each other. Both the lower protective film 51 and the upper protective film 52 are electrical insulators. The material of the lower protective film 51 according to this embodiment is the same as that of the lower protective film 51 of the chip resistor A3, and the material of the upper protective film 52 is the same as that of the chip resistor A3.

The lower protective film 51 is a portion that covers the resistor 2 . The lower protective film 51 is located below the upper protective film 52 shown in FIGS. 32 and 33. Similarly to the chip resistor A3, the lower protective film 51 covers not only the resistor 2 but also a part of the surface of the upper electrode 31 (the upper surface of the upper electrode 31 shown in FIGS. 32 and 33). As shown in FIG. 31, the lower protective film 51 has a shape extending outward toward the side surface 13 of the substrate 1 from the boundary between the side electrode 33 and the upper protective film 52 in a plan view of the chip resistor A4. It becomes.

The upper protective film 52 is a portion that covers parts of the substrate 1 and the protective layer 4 , and the lower protective film 51 that covers the resistor 2 . The upper protective film 52 is located above the lower protective film 51 shown in FIGS. 32 and 33. In this embodiment, a portion of the upper protective film 52 is in contact with the side electrode 33, the intermediate electrode 34, and the external electrode 35.

Next, a method for manufacturing the chip resistor A4 will be described based on FIG. 34. In manufacturing the chip resistor A3 mentioned above, there are a step of preparing the sheet-like substrate 81 shown in FIGS. 21 and 22 and forming the upper surface electrode 31, a step of mounting the resistor 2 shown in FIG. 23, and a step shown in FIG. The process of forming the lower protective film 51 shown in FIG. 25 and the process of forming the trimming groove 21 shown in FIG. 25 are the same in manufacturing the chip resistor A4.

As shown in FIG. 34, after forming the trimming groove 21 in the resistor 2, a protective layer 4 having a property of being less susceptible to sulfurization than the upper electrode 31 is formed on the exposed portion of the upper electrode 31. In this embodiment, the protective layer 4 is formed by printing a paste containing a glass made of Ru or the like, a metal oxide, carbon particles, and an epoxy resin using a silk screen and curing the paste. . The protective layer 4 in this case has conductivity. When the protective layer 4 is an electrical insulator, it is formed by printing a paste containing glass using a silk screen and firing it in a firing furnace. Through this step, the exposed portion of the upper surface electrode 31 and a portion of the lower protective film 51 are covered with the protective layer 4.

Next, the upper protective film 52 is formed on the mounting surface 11 of the sheet-like substrate 81. At this time, the lower protective film 51 that covers the surface of the resistor 2 and a part of the upper electrode 31 and a part of the protective layer 4 are covered with the upper protective film 52. The method for forming the upper protective film 52 is similar to the method for forming the upper protective film 52 in the process related to the manufacturing method of the chip resistor A3 shown in FIG. The steps from forming the upper protective film 52 to manufacturing the chip resistor A4 are the same as those for the chip resistor A3.

Next, the effects of the chip resistor A4 will be explained.

In this embodiment as well, similar to the chip resistor A3, a part of the upper surface electrode 31 is covered with the lower protective film 51, so that the upper protective film 52 is prevented from cracking due to thermal shock generated in the electrode 3. Even if this occurs, it is possible to prevent disconnection of the electrode 3 due to sulfidation. Further, by providing the protective layer 4, the upper surface of the upper electrode 31 is covered not only with the lower protective film 51 but also with the protective layer 4. The protective layer 4 has a property that it is less likely to be sulfurized than the upper electrode 31. Therefore, it is possible to further improve the sulfurization resistance of the chip resistor A4 than that of the chip resistor A3.

The chip resistor according to the present invention is not limited to the embodiments described above. The specific configuration of each part of the chip resistor according to the present invention can be changed in design in various ways.

A1, A2, A3, A4: Chip resistor 1: Substrate 11: Mounting surface 12: Mounting surface 13: Side surface 2: Resistor 21: Trimming groove 3: Electrode 31: Top electrode 32: Back electrode 33: Side electrode 34: Intermediate electrode 35: External electrode 4: Protective layer 41, 42: First protective layer, second protective layer 5: Protective film 51: Lower protective film 52: Upper protective film 81: Sheet-like substrate 811, 812: Primary dividing groove, Secondary dividing groove 86: Band-shaped substrate 87: Individual piece X: Direction

Claims (11)

a substrate having a mounting surface and a mounting surface facing oppositely to each other;
a pair of upper surface electrodes arranged at both ends of the mounting surface;
a resistor mounted between the pair of upper surface electrodes on the mounting surface;
a protective film that covers the resistor and a portion of each of the pair of upper surface electrodes;
a portion disposed on a side surface of the substrate located between the mounting surface and the mounting surface; and a portion overlapping the mounting surface and the mounting surface in plan view; a side electrode that is electrically conductive to the
an intermediate electrode covering the side electrode;
an external electrode covering the intermediate electrode,
The protective film includes a lower protective film and an upper protective film laminated on the lower protective film,
The lower protective film is made of a material that is more resistant to thermal shock than the upper protective film,
A portion of each of the pair of upper surface electrodes is covered with the lower protective film,
In the plan view, the side electrode has a first edge that forms a boundary with either of the pair of upper electrodes,
In the plan view, the lower protective film includes a portion extending from the first edge toward the side surface. In the plan view, the upper protective film has a second edge in contact with the first edge,
In the plan view, the lower protective film has a third edge located between the first edge and the side surface,
The directions in which each of the second end edge and the third end edge extend are equal to each other,
The chip resistor according to claim 1, wherein the second edge is located closer to the resistor than the third edge in the plan view. The chip resistor according to claim 2, wherein the lower protective film includes glass. The chip resistor according to claim 2 or 3, wherein the upper protective film contains epoxy resin. The chip resistor according to any one of claims 1 to 4, wherein the side electrode is made of a Ni-Cr alloy. further comprising a pair of back electrodes arranged at both ends of the mounting surface,
6. The chip resistor according to claim 1, wherein the side electrode is electrically connected to either of the pair of back electrodes. The chip resistor according to claim 6, wherein one of the pair of back electrodes is covered by the intermediate electrode. 8. The chip resistor according to claim 1, wherein the resistor has a trimming groove formed therein. The chip resistor according to any one of claims 1 to 8, wherein the intermediate electrode and the external electrode are made of a plating layer. The chip resistor according to claim 9, wherein the intermediate electrode is made of a Ni plating layer. The chip resistor according to claim 9 or 10, wherein the external electrode is made of a Sn plating layer.

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