JP2016171306A - Chip resistor and method for manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a chip resistor with improved sulfur-resistance performance while suppressing cost, and a method for manufacturing the same.SOLUTION: A chip resistor A1 includes: a substrate 1 having a mounting surface 11 and a packaging surface 12; a pair of upper electrodes 31 arranged on both ends of the mounting surface 11; a resistor element 2 installed between the pair of upper electrodes 31; a side electrode 33 which has a portion arranged on a side surface 13 of the substrate 1 and a portion overlapping with the mounting surface 11 and the packaging surface 12, and which is electrically connected to the upper electrodes 31; and an intermediate electrode 34 covering the side electrode 33, and an external electrode 35. The chip electrode also includes: a first protective layer 41 which is disposed between the upper electrodes 31 and the intermediate electrode 34 and arranged in contact with the upper electrodes 31 and the side electrode 33, the first protective layer having a characteristic that is more resistant to sulfurization than the upper electrodes 31; and a second protective layer 42 which is disposed between the first protective layer 41 and the intermediate electrode 34 and arranged in contact with the first protective layer 41, the side electrode 33 and the intermediate electrode 34, the second protective layer having conductivity.SELECTED DRAWING: Figure 3

Description

  The present invention relates to a chip resistor used in various electronic devices and a manufacturing method thereof.

The internal electrodes (upper surface electrode, rear surface electrode, and side surface electrode) that constitute part of the electrode of the chip resistor mainly contain Ag. When sulfur gas (H ₂ S, SO _2, etc.) is present in the surrounding environment of the electronic equipment in which the chip resistor is used, the internal electrode combines with the sulfur gas to convert black silver sulfide (Ag ₂ S). Generate. Since silver sulfide has electrical insulation, the internal electrode may break when the sulfidation of the internal electrode progresses, that is, the chip resistor electrode may break.

  Under such circumstances, for example, as disclosed in Patent Document 1, there is a conventional chip resistor in which the material of the upper electrode among the internal electrodes is an Ag—Pd alloy. Although the Ag—Pd alloy is a material excellent in resistance to sulfidation, it is expensive and has a demerit that it is inferior in economic efficiency.

  Accordingly, Patent Document 1 discloses a chip resistor further including a re-upper surface electrode made of an epoxy resin containing metal particles such as Ag and carbon particles on the upper surface of the upper electrode of the internal electrode. The re-upper surface electrode is an electrode that is less likely to be sulfided than the upper surface electrode and is less expensive than an electrode made of an Ag—Pd alloy. Therefore, the chip resistor having the resurfaced electrode has a merit that it is advantageous in terms of economy while having antisulfurization performance.

  Here, the chip resistor provided with the upper surface electrode includes an Ni plating layer (intermediate electrode) that covers the upper surface electrode. The resurface electrode includes carbon particles, and the greater the carbon particle content, the better the sulfidation resistance of the resurface electrode. However, when the content of the carbon particles exceeds an arbitrary amount, the adhesion between the Ni plating layer and the resurface electrode may be reduced, and the Ni plating layer may be peeled off. When the Ni plating layer is peeled off, there is a concern that the sulfide gas enters the internal electrodes (upper surface electrode and side electrode), and the electrode of the chip resistor is disconnected due to the progress of sulfidation of the internal electrode.

  Moreover, generally, like the chip resistor disclosed in Patent Document 2, the surface of the resistor is covered with a protective film made of a paste containing an epoxy resin.

  Depending on the usage state of the chip resistor, the temperature of the Ni plating layer (intermediate electrode) covering the internal electrode is remarkably increased. At this time, a thermal shock may occur at the tip of the Ni plating layer (the boundary between the Ni plating layer and the protective film in plan view). When the thermal shock acts on the protective film, a crack occurs in the protective film. When the crack propagates toward the internal electrode, the internal electrode is exposed. At this time, when sulfur gas is present in the surrounding environment of the electronic device in which the chip resistor is used, as described above, the internal electrode may be combined with the sulfur gas, and the electrode of the chip resistor may be disconnected.

JP 2013-258292 A JP 2012-151195 A

  In view of the circumstances described above, it is an object of the present invention to provide a chip resistor and a method for manufacturing the chip resistor that improve the resistance to sulfuration while suppressing cost. In addition, in view of the above-described circumstances, the present invention provides a chip resistor that can prevent disconnection of the electrode due to sulfurization even if a crack develops in the protective film due to a thermal shock generated in the electrode, and a manufacturing method thereof That is the issue.

  The chip resistor provided by the first aspect of the present invention includes a substrate having a mounting surface and a mounting surface facing away from each other, a pair of upper surface electrodes disposed at both ends of the mounting surface of the substrate, A portion disposed on a side surface of the substrate located between the mounting surface and the mounting surface of the substrate; and a portion overlapping the mounting surface and the mounting surface in a thickness direction view of the substrate; And a side electrode electrically connected to the upper surface electrode, a resistor mounted between the pair of upper surface electrodes on the mounting surface of the substrate, an intermediate electrode that covers the side electrode, and an intermediate electrode that covers the intermediate electrode A chip resistor comprising an external electrode, which is located between the upper surface electrode and the intermediate electrode and is in contact with the upper surface electrode and the side electrode, and is more sulfided than the upper surface electrode. No. with difficult characteristics A conductive second protection layer positioned between the first protective layer and the intermediate electrode and in contact with the first protective layer, the side electrode and the intermediate electrode; And a layer.

  In a preferred embodiment of the present invention, the first protective layer includes carbon particles.

  In a preferred embodiment of the present invention, the first protective layer is an electrical insulator.

  In a preferred embodiment of the present invention, the second protective layer contains Ag.

  In a preferred embodiment of the present invention, the side electrode is made of a Ni—Cr alloy.

  In a preferred embodiment of the present invention, the apparatus further includes a pair of back electrodes disposed at both ends of the mounting surface of the substrate, and the side electrodes are electrically connected to the back electrode.

  In a preferred embodiment of the present invention, the back electrode is covered with the intermediate electrode.

  In a preferred embodiment of the present invention, the substrate is an electrical insulator.

  In a preferred embodiment of the present invention, the substrate is made of alumina.

  In a preferred embodiment of the present invention, the planar shape of the resistor is a serpentine shape.

In a preferred embodiment of the present invention, the resistor includes RuO ₂ or an Ag—Pd alloy.

  In a preferred embodiment of the present invention, a trimming groove penetrating the resistor is formed in the resistor.

  In a preferred embodiment of the present invention, the intermediate electrode and the external electrode are made of a plating layer.

  In a preferred embodiment of the present invention, the intermediate electrode is made of a Ni plating layer.

  In a preferred embodiment of the present invention, the external electrode is made of a Sn plating layer.

  In preferable embodiment of this invention, the protective film which covers the said resistor and a part of said upper surface electrode is further provided.

  In a preferred embodiment of the present invention, a part of the first protective layer is covered with the protective film.

  In a preferred embodiment of the present invention, the protective film has a lower protective film and an upper protective film.

  In a preferred embodiment of the present invention, the lower protective film includes glass.

  In a preferred embodiment of the present invention, the upper protective film includes an epoxy resin.

  A method for manufacturing a chip resistor provided by the second aspect of the present invention provides a sheet-like substrate having a mounting surface and a mounting surface facing opposite to each other, and the mounting surface of the sheet-like substrate is mutually attached to the mounting surface. Forming a top surface electrode having a pair of spaced apart regions, and mounting a resistor conductive to the top surface electrode in a region sandwiched between the pair of regions of the mounting surface of the sheet-like substrate; A step of forming a first protective layer on the upper surface of the upper surface electrode, the first protective layer having characteristics that are less likely to be sulfided than the upper surface electrode; and a second protective layer having conductivity on the upper surface of the first protective layer. A step of dividing the sheet-like substrate into a plurality of belt-like substrates, a side surface located along both longitudinal ends of the belt-like substrate, the mounting surface, and the mounting surface, and being electrically connected to the upper surface electrode, And the first protective layer and the front Forming a side electrode in contact with the second protective layer, forming an intermediate electrode covering the side electrode and the second protective layer, and forming an external electrode covering the intermediate electrode, respectively. It is said.

  In a preferred embodiment of the present invention, in the step of forming the first protective layer, the first protective layer is formed by a technique using printing.

  In a preferred embodiment of the present invention, in the step of forming the second protective layer, the second protective layer is formed by a technique using printing.

  In a preferred embodiment of the present invention, in the step of forming the side electrode, the side electrode is formed by physical vapor deposition.

  In a preferred embodiment of the present invention, the physical vapor deposition is a sputtering method.

  In a preferred embodiment of the present invention, in the step of mounting the resistor, the resistor is mounted by a technique using printing or a technique using physical vapor deposition and photolithography.

  In a preferred embodiment of the present invention, the method further includes a step of dividing the strip substrate into a plurality of pieces before the step of forming the intermediate electrode and the external electrode.

  In a preferred embodiment of the present invention, in the step of forming the intermediate electrode and the external electrode, the intermediate electrode and the external electrode are formed by plating, respectively.

  In a preferred embodiment of the present invention, the method further includes forming a back electrode having a pair of regions spaced from each other on the mounting surface of the sheet-like substrate.

  In a preferred embodiment of the present invention, the resistor further includes a step of forming a trimming groove penetrating the resistor.

  In a preferred embodiment of the present invention, the method further includes a step of forming a protective film that covers the resistor and each of the upper surface electrode and the first protective layer.

  In a preferred embodiment of the present invention, the step of forming the protective film includes a step of forming a lower protective film and a step of forming an upper protective film.

  The chip resistor provided by the third aspect of the present invention includes a substrate having a mounting surface and a mounting surface facing opposite to each other, a pair of upper surface electrodes disposed at both ends of the mounting surface of the substrate, In the mounting surface of the substrate, a resistor mounted between the pair of upper surface electrodes, a protective film that covers the resistor and a part of the upper surface electrode, and the mounting surface and the mounting surface of the substrate A side electrode disposed between the side electrode and the side electrode of the substrate, and a portion overlapping the mounting surface and the mounting surface in a plan view of the substrate, A chip resistor comprising an intermediate electrode that covers the side electrode and an external electrode that covers the intermediate electrode, wherein the protective film includes a lower protective film and an upper protective film stacked on each other; The protective film is the upper protective film. Also made strong material to thermal shock, a portion of the upper surface electrode is characterized by being covered on the lower protective layer.

  In a preferred embodiment of the present invention, a part of each of the upper surface electrode and the upper protective film is covered with the side electrode.

  In a preferred embodiment of the present invention, the semiconductor device further includes a protective layer that covers at least a part of the upper surface of the upper electrode, and has a characteristic that it is less likely to be sulfided than the upper electrode, and at least a part of the protective layer is the side surface. Covered with electrodes.

  In a preferred embodiment of the present invention, a part of the protective layer is covered with the upper protective film.

  In a preferred embodiment of the present invention, the protective layer includes carbon particles.

  In a preferred embodiment of the present invention, the protective layer is an electrical insulator.

  In a preferred embodiment of the present invention, the lower protective film includes glass.

  In a preferred embodiment of the present invention, the upper protective film includes an epoxy resin.

  In a preferred embodiment of the present invention, the side electrode is made of a Ni—Cr alloy.

  In a preferred embodiment of the present invention, the apparatus further includes a pair of back electrodes disposed at both ends of the mounting surface of the substrate, and the side electrodes are electrically connected to the back electrode.

  In a preferred embodiment of the present invention, the back electrode is covered with the intermediate electrode.

  In a preferred embodiment of the present invention, the substrate is an electrical insulator.

  In a preferred embodiment of the present invention, the substrate is made of alumina.

  In a preferred embodiment of the present invention, a trimming groove penetrating the resistor is formed in the resistor.

  In a preferred embodiment of the present invention, the intermediate electrode and the external electrode are made of a plating layer.

  In a preferred embodiment of the present invention, the intermediate electrode is made of a Ni plating layer.

  In a preferred embodiment of the present invention, the external electrode is made of a Sn plating layer.

  According to a fourth aspect of the present invention, there is provided a chip resistor manufacturing method, comprising: preparing a sheet-like substrate having a mounting surface and a mounting surface facing opposite to each other; Forming a top surface electrode having a pair of spaced apart regions, and mounting a resistor conductive to the top surface electrode in a region sandwiched between the pair of regions of the mounting surface of the sheet-like substrate; A step of forming a lower protective film covering the resistor and a part of the upper surface electrode; a step of forming an upper protective film covering the lower protective film; and dividing the sheet-like substrate into a plurality of strip-like substrates A step of forming side electrodes that are electrically connected to the upper surface electrode on the side surface located along the longitudinal ends of the belt-shaped substrate, the mounting surface, and the mounting surface; and an intermediate electrode that covers the side electrode; The intermediate power It is characterized in that it comprises a step of forming respectively an external electrode covering the.

  In a preferred embodiment of the present invention, in the step of forming the side electrode, the side electrode is formed by covering a part of each of the upper surface electrode and the upper protective film with the side electrode. The

  In a preferred embodiment of the present invention, the method further includes the step of forming a protective layer that covers at least a part of the upper surface of the upper surface electrode and has a characteristic that it is less likely to be sulfided than the upper surface electrode.

  In a preferred embodiment of the present invention, in the step of forming the protective layer, the protective layer is formed by a technique using printing.

  In a preferred embodiment of the present invention, in the step of forming the side electrode, the side electrode is formed by covering at least a part of the protective layer with the side electrode.

  In a preferred embodiment of the present invention, in the step of forming the upper protective film, the upper protective film is formed by covering a part of the protective layer with the upper protective film.

  In a preferred embodiment of the present invention, in the step of forming the lower protective film, the lower protective film is formed by a technique using printing.

  In a preferred embodiment of the present invention, in the step of forming the upper protective film, the upper protective film is formed by a technique using printing.

  In a preferred embodiment of the present invention, in the step of forming the side electrode, the side electrode is formed by physical vapor deposition.

  In a preferred embodiment of the present invention, the physical vapor deposition is a sputtering method.

  In a preferred embodiment of the present invention, in the step of forming the intermediate electrode and the external electrode, the intermediate electrode and the external electrode are formed by plating, respectively.

  In a preferred embodiment of the present invention, the method further includes a step of dividing the strip substrate into a plurality of pieces before the step of forming the intermediate electrode and the external electrode.

  In a preferred embodiment of the present invention, the method further includes forming a back electrode having a pair of regions spaced from each other on the mounting surface of the sheet-like substrate.

  In a preferred embodiment of the present invention, the resistor further includes a step of forming a trimming groove penetrating the resistor.

  The chip resistor according to the present invention includes a first protective layer that is located between the upper surface electrode and the intermediate electrode and is disposed in contact with the upper surface electrode and the side electrode. Therefore, the upper surface electrode is covered with the first protective layer. The first protective layer has a characteristic that it is less likely to be sulfided than the upper surface electrode. Therefore, the first protective layer prevents sulphidation of the upper surface electrode and avoids disconnection of the upper surface electrode. Further, the chip resistor according to the present invention is located between the first protective layer and the intermediate electrode together with the first protective layer, and the first protective layer, the side electrode, and the intermediate electrode A second protective layer disposed in contact with the second protective layer. The first protective layer is configured to be covered with the conductive second conductive layer and the side electrode. Therefore, the intermediate electrode is configured not to contact the first protective layer. Accordingly, it is possible to avoid peeling of the plating layer constituting the intermediate electrode. As described above, by providing the first protective layer and the second protective layer, it is possible to improve the resistance to sulfuration while suppressing the cost of the chip resistor.

  The chip resistor according to the present invention has a lower protective film and an upper protective film laminated on each other, and a part of the upper surface electrode is covered with the lower protective film. The lower protective film is made of a material that is more resistant to thermal shock than the upper protective film. For this reason, even if a crack occurs in the upper protective film due to the thermal shock generated at the tip part of the plating layer that is the intermediate electrode and the external electrode (the boundary part between the plating layer and the upper protective film in a plan view) The progress of the crack is suppressed by the lower protective film. Therefore, since the upper surface electrode is not exposed by the crack, the sulfide gas generated around the chip resistor does not enter the upper surface electrode through the crack. Therefore, even if a crack occurs in the upper protective film due to the thermal shock generated in the electrode, it is possible to prevent disconnection of the electrode due to sulfurization.

  Other features and advantages of the present invention will become more apparent from the detailed description given below with reference to the accompanying drawings.

It is a top view which shows the chip resistor concerning 1st Embodiment of this invention. It is sectional drawing which follows the II-II line | wire of FIG. It is the elements on larger scale which expanded a part of FIG. It is a top view which shows the process concerning the manufacturing method of the chip resistor of FIG. It is a top view which shows the process concerning the manufacturing method of the chip resistor of FIG. It is a top view which shows the process concerning the manufacturing method of the chip resistor of FIG. It is a top view which shows the process concerning the manufacturing method of the chip resistor of FIG. It is a top view which shows the process concerning the manufacturing method of the chip resistor of FIG. It is a top view which shows the process concerning the manufacturing method of the chip resistor of FIG. It is a top view which shows the process concerning the manufacturing method of the chip resistor of FIG. It is a top view which shows the process concerning the manufacturing method of the chip resistor of FIG. It is a perspective view which shows the process concerning the manufacturing method of the chip resistor of FIG. It is a perspective view which shows the process concerning the manufacturing method of the chip resistor of FIG. It is a perspective view which shows the process concerning the manufacturing method of the chip resistor of FIG. It is a perspective view which shows the process concerning the manufacturing method of the chip resistor of FIG. It is a top view which shows the chip resistor concerning 2nd Embodiment of this invention. It is sectional drawing which follows the XVII-XVII line of FIG. It is a top view which shows the chip resistor concerning 3rd Embodiment of this invention. It is sectional drawing which follows the XIX-XIX line | wire of FIG. It is the elements on larger scale which expanded a part of FIG. It is a top view which shows the process concerning the manufacturing method of the chip resistor of FIG. It is a top view which shows the process concerning the manufacturing method of the chip resistor of FIG. It is a top view which shows the process concerning the manufacturing method of the chip resistor of FIG. It is a top view which shows the process concerning the manufacturing method of the chip resistor of FIG. It is a top view which shows the process concerning the manufacturing method of the chip resistor of FIG. It is a top view which shows the process concerning the manufacturing method of the chip resistor of FIG. It is a perspective view which shows the process concerning the manufacturing method of the chip resistor of FIG. It is a perspective view which shows the process concerning the manufacturing method of the chip resistor of FIG. It is a perspective view which shows the process concerning the manufacturing method of the chip resistor of FIG. It is a perspective view which shows the process concerning the manufacturing method of the chip resistor of FIG. It is a top view which shows the chip resistor concerning 4th Embodiment of this invention. FIG. 32 is a cross-sectional view taken along line XXXII-XXXII in FIG. 31. It is a partial expanded sectional view which expanded a part of FIG. FIG. 32 is a plan view showing a process according to the method for manufacturing the chip resistor of FIG. 31.

  A mode for carrying out the present invention (hereinafter referred to as “embodiment”) will be described with reference to the accompanying drawings.

[First Embodiment]
The chip resistor A1 according to the first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a plan view showing the chip resistor A1. 2 is a cross-sectional view taken along line II-II in FIG. FIG. 3 is a partially enlarged sectional view in which a part of FIG. 2 is enlarged. In FIG. 1, for convenience of understanding, an intermediate electrode 34, an external electrode 35, and a protective film 5, which will be described later, are omitted.

  The chip resistor A1 shown in these drawings is of a type that is surface-mounted on circuit boards of various electronic devices. A chip resistor A1 according to this embodiment includes a substrate 1, a resistor 2, an electrode 3, a protective layer 4, and a protective film 5. In the present embodiment, the chip resistor A1 has a rectangular shape in plan view. The chip resistor A1 according to this embodiment is a so-called thick film (metal glaze film) chip resistor.

As shown in FIGS. 1 and 2, the substrate 1 is a member on which the resistor 2 is mounted and the chip resistor A1 is mounted on circuit boards of various electronic devices. The substrate 1 is an electrical insulator. In the present embodiment, the substrate 1 is made of alumina (Al ₂ O ₃ ), for example. When the chip resistor A1 is used, the substrate 1 is preferably made of a material having high thermal conductivity so that heat generated from the resistor 2 can be easily dissipated to the outside. The substrate 1 has a mounting surface 11, a mounting surface 12 and a side surface 13. In the present embodiment, the substrate 1 has a rectangular shape in plan view.

  The mounting surface 11 is an upper surface of the substrate 1 shown in FIG. 2 and is a surface on which the resistor 2 is mounted. The mounting surface 12 is the lower surface of the substrate 1 shown in FIG. 2, and is a surface used when the chip resistor A1 is mounted on the circuit boards of various electronic devices. The mounting surface 11 and the mounting surface 12 face opposite sides. As shown in FIGS. 1 and 2, the side surface 13 is a pair of surfaces that are orthogonal to the mounting surface 11 and the mounting surface 12 and that face the longitudinal direction of the substrate 1 (direction X shown in FIG. 1). The side surface 13 is located between the mounting surface 11 and the mounting surface 12.

The resistor 2 is an element that performs a function of limiting current or detecting current. In this embodiment, the planar view shape of the resistor 2 is a strip shape extending in the direction X shown in FIG. The resistor 2 is made of a paste containing a metal such as RuO ₂ or an Ag—Pd alloy. In the present embodiment, the shape of the resistor 2 in plan view is a band shape, but can be any shape such as a serpentine shape. The resistor 2 has a trimming groove 21.

  As shown in FIGS. 1 and 2, the trimming groove 21 is a groove penetrating in the thickness direction of the resistor 2. The trimming groove 21 forms an opening on a side surface along the longitudinal direction of the resistor 2 (direction X shown in FIG. 1). In the present embodiment, a trimming groove 21 having an L shape in plan view is formed in the resistor 2. The trimming groove 21 is formed to adjust the resistance value of the resistor 2 to a required value.

  As shown in FIGS. 1 to 3, the electrode 3 is electrically connected to the resistor 2 and is a pair of spaced apart members for interconnecting the chip resistor A <b> 1 and the wiring patterns of the circuit boards of various electronic devices. It is. The electrodes 3 are arranged on both sides of the resistor 2 in the direction X shown in FIG. In the present embodiment, the electrode 3 includes a top electrode 31, a back electrode 32, a side electrode 33, an intermediate electrode 34, and an external electrode 35.

  As shown in FIGS. 1 to 3, the upper surface electrode 31 has a pair of regions arranged at both ends on the mounting surface 11 of the substrate 1 and spaced from each other. The upper surface electrode 31 has a rectangular shape in plan view. A part of the upper surface electrode 31 is sandwiched between the mounting surface 11 and the resistor 2. Therefore, the resistor 2 is electrically connected to the upper surface electrode 31. The upper surface electrode 31 is made of, for example, a paste containing Ag.

  As shown in FIGS. 1 to 3, the back electrode 32 has a pair of regions arranged at both ends on the mounting surface 12 of the substrate 1 and spaced apart from each other. The shape of the back electrode 32 in plan view is substantially the same as that of the top electrode 31 (not shown). The back electrode 32 is made of, for example, a paste containing Ag, like the top electrode 31. The back electrode 32 can be omitted.

  As shown in FIGS. 1 to 3, the side electrode 33 has a pair of regions disposed on the side surface 13 of the substrate 1 and spaced apart from each other. In addition to the side surface 13, the side surface electrode 33 covers a part of the upper surface electrode 31, the back surface electrode 32, and the protective layer 4. That is, the side electrode 33 has a portion disposed on the side surface 13 and a portion overlapping the mounting surface 11 and the mounting surface 12 of the substrate 1 when viewed in the thickness direction of the substrate 1. The upper surface electrode 31 and the rear surface electrode 32 are electrically connected to each other by the side electrode 33. Therefore, the resistor 2 is electrically connected to the back electrode 32 by the top electrode 31 and the side electrode 33. In the present embodiment, the side electrode 33 is made of, for example, a Ni—Cr alloy. The material of the side electrode 33 may be any metal as long as it is conductive and has a characteristic that it is difficult to be sulfided.

  As shown in FIGS. 2 and 3, the intermediate electrode 34 is a pair of spaced apart portions that cover the back electrode 32, the side electrode 33, and the protective layer 4. In the present embodiment, the intermediate electrode 34 is made of, for example, a Ni plating layer. The intermediate electrode 34 functions to protect the electrode 3 from heat and impact.

  As shown in FIGS. 2 and 3, the external electrode 35 is a pair of spaced apart portions that cover the intermediate electrode 34. In the present embodiment, the external electrode 35 is made of, for example, a Sn plating layer. Solder adheres to the external electrode 35 and the external electrode 35 is integrated with the solder, whereby the chip resistor A1 and the wiring patterns of the circuit boards of various electronic devices are interconnected. In the present embodiment, since the intermediate electrode 34 is made of a Ni plating layer, it is difficult to directly attach solder to the intermediate electrode 34. Therefore, the external electrode 35 made of a Sn plating layer is necessary.

  As shown in FIGS. 1 to 3, the protective layer 4 is a pair of members that cover at least a part of the upper surface electrode 31 and are separated from each other. In the present embodiment, the protective layer 4 includes a first protective layer 41 and a second protective layer 42. The protective layer 4 functions to prevent sulfurization of the upper surface electrode 31.

  The first protective layer 41 has a pair of regions formed on the upper surface of the upper surface electrode 31 shown in FIGS. 2 and 3 and spaced from each other. The first protective layer 41 has a characteristic that it is less likely to be sulfided than the upper surface electrode 31. The first protective layer 41 is located between the upper surface electrode 31 and the intermediate electrode 34 and is in contact with the upper surface electrode 31 and the side electrode 33. In the present embodiment, the first protective layer 41 is made of a paste containing glass and metal oxide made of, for example, Ru, carbon particles (carbon black), and an epoxy resin. In this case, the first protective layer 41 has conductivity. Here, the first protective layer 41 may be an electrical insulator. The first protective layer 41 that is an electrical insulator is made of, for example, a paste containing glass.

  The second protective layer 42 has a pair of regions formed on the upper surface of the first protective layer 41 shown in FIGS. The second protective layer 42 has conductivity. The second protective layer 42 is located between the first protective layer 41 and the intermediate electrode 34 and is in contact with the first protective layer 41, the side electrode 33, and the intermediate electrode 34. In the present embodiment, the second protective layer 42 is made of a paste containing, for example, Ag and an epoxy resin.

  As shown in FIGS. 1 to 3, the protective film 5 is a member that covers the resistor 2 and functions to protect the resistor 2 from the outside. The protective film 5 includes a lower protective film 51 and an upper protective film 52. The lower protective film 51 covers the surface of the resistor 2 (the upper surface of the resistor 2 shown in FIG. 2). The lower protective film 51 is made of, for example, a paste containing glass. The upper protective film 52 covers a part of the substrate 1, the resistor 2, and a part of the upper surface electrode 31. In the present embodiment, a part of the first protective layer 41 is covered with the upper protective film 52. Here, a part of the upper protective film 52 may be covered with the first protective layer 41. The upper protective film 52 is made of, for example, a paste containing an epoxy resin.

  Next, a manufacturing method of the chip resistor A1 will be described with reference to FIGS. 4-11 is a top view which shows the process concerning the manufacturing method of chip resistor A1. 12-15 is a perspective view which shows the process concerning the manufacturing method of chip resistor A1. 10 to 15, the lower protective film 51 of the protective film 5 is omitted for convenience of understanding. 12 and 13 ignore the thicknesses of the resistor 2, the upper surface electrode 31, the side electrode 33, the first protective layer 41, the second protective layer 42, and the upper protective film 52 for the sake of convenience. ing.

  First, as shown in FIG. 4, a sheet-like substrate 81 made of alumina is prepared. The sheet-like substrate 81 has a mounting surface 11 and a mounting surface 12. The mounting surface 11 and the mounting surface 12 face opposite sides. FIG. 4 shows the mounting surface 11 of the sheet-like substrate 81. On the mounting surface 11, a plurality of primary division grooves 811 are formed in a grid pattern in the vertical direction shown in FIG. The same number of primary divided grooves 811 and secondary divided grooves 812 are formed on the mounting surface 12 opposite to the mounting surface 11 (not shown). The positions of the primary dividing groove 811 and the secondary dividing groove 812 in plan view are the same for both the mounting surface 11 and the mounting surface 12. A section formed by the primary dividing groove 811 and the secondary dividing groove 812 is an area corresponding to the substrate 1 of the chip resistor A1.

  Next, as shown in FIG. 5, the upper surface electrode 31 is formed on the mounting surface 11 of the sheet-like substrate 81 so as to straddle the primary division grooves 811 of the sheet-like substrate 81. In addition, the back surface electrode 32 is formed on the mounting surface 12 of the sheet-like substrate 81 so as to straddle the primary division grooves 811 (not shown). The positions and sizes of the top electrode 31 and the back electrode 32 in plan view are substantially the same. In the present embodiment, the top electrode 31 and the back electrode 32 are obtained by printing a paste containing glass frit in Ag using a silk screen on the mounting surface 11 and the mounting surface 12, respectively, and firing them in a firing furnace. It is formed. By this step, the top electrode 31 and the back electrode 32 having a pair of regions separated from each other are formed on the mounting surface 11 and the mounting surface 12.

Next, as shown in FIG. 6, the resistor 2 that is electrically connected to the upper surface electrode 31 is mounted in a region between the pair of regions of the upper surface electrode 31 in the mounting surface 11 of the sheet-like substrate 81. In the present embodiment, the resistor 2 is mounted by printing a paste containing a glass frit in a metal such as RuO ₂ or an Ag—Pd alloy using a silk screen and firing it in a firing furnace.

  Next, as shown in FIG. 7, a first protective layer 41 having characteristics that are less likely to be sulfided than the upper surface electrode 31 is formed on the upper surface of the upper surface electrode 31 and in a region sandwiched between the resistors 2. In the present embodiment, the first protective layer 41 is formed by printing and curing a paste containing glass and metal oxide made of Ru or the like, carbon particles, and an epoxy resin using a silk screen. The In this case, the first protective layer 41 has conductivity. When the first protective layer 41 is an electrical insulator, it is formed by printing a paste containing glass using a silk screen and firing it in a firing furnace. Here, when forming the first protective layer 41 having conductivity, a gap is provided between the first protective layer 41 and the resistor 2 in plan view so that the first protective layer 41 does not contact the resistor 2. . This is because when the first protective layer 41 is in contact with the resistor 2, the resistance value of the chip resistor A1 varies. Through this step, a part of the upper surface electrode 31 is covered with the first protective layer 41.

  Next, as shown in FIG. 8, a second protective layer 42 having conductivity is formed on the upper surface of the first protective layer 41. In the present embodiment, the second protective layer 42 is formed by printing and curing a paste containing Ag and an epoxy resin using a silk screen. In forming the second protective layer 42, the first protective layer 41 is exposed at the end of the second protective layer 42 adjacent to the resistor 2. Through this step, a part of the first protective layer 41 is covered with the second protective layer 42.

  Next, as shown in FIG. 9, a lower protective film 51 that covers the surface of the resistor 2 is formed. In the present embodiment, the lower protective film 51 is formed by printing a paste containing glass using a silk screen and baking it in a baking furnace. In the step of forming the trimming groove 21 in the resistor 2, which is a subsequent step of the subsequent step, since the groove is formed by a laser, thermal shock acts on the resistor 2 and fine particles of the resistor 2 are generated. . Therefore, the lower protective film 51 functions to prevent the fine particles from reattaching to the resistor 2 and reducing the resistance value of the resistor 2 while relaxing the thermal shock.

  Next, as shown in FIG. 10, a trimming groove 21 that penetrates the resistor 2 is formed in the resistor 2. The trimming groove 21 is formed by a laser trimming apparatus (not shown). The procedure for forming the trimming groove 21 is as follows. First, of the pair of side surfaces along the longitudinal direction of the resistor 2, the trimming groove 21 is formed so as to be orthogonal to the direction of current flowing through the resistor 2 from one side surface to the other side surface. Next, after the resistance value of the resistor 2 rises to a value close to the required value of the chip resistor A1, the current value flowing through the resistor 2 (longitudinal direction of the resistor 2) is parallel to the current value. The trimming groove 21 is formed by changing the direction by 90 °. When the resistance value of the resistor 2 reaches the required value of the chip resistor A1, the formation of the trimming groove 21 is finished. Through this step, a trimming groove 21 having an L shape in plan view is formed in the resistor 2. The trimming grooves 21 are formed in a state in which resistance measurement probes (not shown) are in contact with both ends of the resistor 2 in the longitudinal direction.

  Next, as shown in FIG. 11, the upper protective film 52 is formed on the mounting surface 11 of the sheet-like substrate 81. At this time, in addition to the resistor 2, a part of each of the upper surface electrode 31 and the first protective layer 41 is covered with the upper protective film 52. The second protective layer 42 is not covered with the upper protective film 52. In the present embodiment, the upper protective film 52 is formed in a plurality of strips extending along the primary division grooves 811 of the sheet substrate 81 so as to straddle the secondary division grooves 812 of the sheet substrate 81. In the present embodiment, the upper protective film 52 is formed by printing and curing a paste containing an epoxy resin using a silk screen. The upper protective film 52 may be formed so as to be separated for each resistor 2 in the same manner as the lower protective film 51 of the protective film 5 shown in FIG.

  Next, as shown in FIG. 12, the sheet-like substrate 81 is cut by the primary division grooves 811 of the sheet-like substrate 81 and divided into a plurality of strip-like substrates 86. At this time, the side surfaces 13 are formed on both sides of the strip substrate 86 along the longitudinal direction of the strip substrate 86.

  Next, as shown in FIG. 13, the side surface electrodes 33 are formed on the side surface 13 positioned along the longitudinal ends of the belt-like substrate 86 and a part of each of the mounting surface 11 and the mounting surface 12. In the present embodiment, the side electrode 33 is formed by depositing a Ni—Cr alloy by physical vapor deposition (PVD: Physical Vapor Deposition) such as sputtering. In forming the side electrode 33, the side surface 13 and a part of the surface of each of the second protective layer 42 and the back electrode 32 arranged orthogonal to the side surface 13 are covered with the side electrode 33 as a unit. (The back electrode 32 is not shown). At this time, the side electrode 33 is in contact with the respective end portions along the side surface 13 of the second protective layer 42, the first protective layer 41, the upper surface electrode 31, and the back electrode 32. By this step, the upper surface electrode 31 and the rear surface electrode 32 are electrically connected to each other by the side surface electrode 33.

  Next, as shown in FIG. 14, the belt-like substrate 86 is cut by the secondary dividing grooves 812 of the belt-like substrate 86 and divided into a plurality of pieces 87. At this time, the shape of the side electrode 33 is a U-shape sandwiching the substrate 1. In addition, the side electrodes 33 are mounted on both the mounting surface 11 and the mounting surface 12 of the substrate 1 that are located on both sides of the portion of the side electrode 33 formed on a part of the surface of each of the second protective layer 42 and the back electrode 32. The back electrode 32 is not shown.

  Next, as shown in FIG. 15, in the individual piece 87, an intermediate electrode 34 covering the back electrode 32, the side electrode 33 and the second protective layer 42 and an external electrode 35 covering the intermediate electrode 34 are formed (back electrode). 32 is omitted). In the present embodiment, the intermediate electrode 34 is formed by Ni plating, and the external electrode 35 is formed by Sn plating. By this step, a pair of electrodes 3 that are electrically connected to the resistor 2 are formed. Through the above steps, the chip resistor A1 is manufactured.

  Next, the function and effect of the chip resistor A1 will be described.

  According to the present embodiment, the chip resistor A1 includes the first protective layer 41 that is located between the upper surface electrode 31 and the intermediate electrode 34 and that is disposed in contact with the upper surface electrode 31 and the side surface electrode 33. Therefore, at least a part of the upper surface electrode 31 is covered with the first protective layer 41. Since the first protective layer 41 includes carbon particles, the first protective layer 41 has a characteristic that it is less likely to be sulfided than the upper surface electrode 31. Therefore, the first protective layer 41 prevents the upper surface electrode 31 from being sulfided and avoids disconnection of the upper surface electrode 31.

  The chip resistor A1 is located between the first protective layer 41 and the intermediate electrode 34 together with the first protective layer 41, and is in contact with the first protective layer 41, the side electrode 33, and the intermediate electrode 34. It has the 2nd protective layer 42 arrange | positioned. Since the 2nd protective layer 42 contains Ag, it has electroconductivity. The first protective layer 41 is configured to be covered with the second protective layer 42 and the side electrode 33 having the same conductivity. Therefore, the intermediate electrode 34 is configured not to contact the first protective layer 41 containing carbon particles. Therefore, peeling of the Ni plating layer that is the intermediate electrode 34 can be avoided.

  As described above, the chip resistor A1 is provided with the first protective layer 41 having the characteristic that it is less likely to be sulfided than the upper surface electrode 31 including carbon particles, and the second protective layer 42 having conductivity including Ag. It is possible to improve the resistance to sulfuration while suppressing the cost.

  Most of the sulfurized gas that causes sulfidation such as the upper surface electrode 31 is along the interface between the plating layer constituting the intermediate electrode 34 and the external electrode 35 and the upper protective film 52 of the protective film 5 in the chip resistor A1. Enter the chip resistor A1. Therefore, by adopting a configuration in which a part of the first protective layer 41 is covered with the upper protective film 52, the effect of shielding the sulfide gas that has entered along the interface is further increased. Even if the first protective layer 41 is configured to cover a part of the upper protective film 52, the anti-sulfurization performance of the chip resistor A1 is ensured.

  If the sulfide gas enters along the interface, the second protective layer 42 containing Ag is preferentially sulfided. That is, the second protective layer 42 performs a function similar to that of the sacrificial electrode. In addition, since the second protective layer 42 is configured not to be in contact with the upper surface electrode 31 by the first protective layer 41 and the side electrode 33, the upper surface electrode 31 is not sulfided even if the second protective layer 42 is sulfurized. Therefore, by having the second protective layer 42 containing Ag, it is possible to further improve the sulfur resistance of the chip resistor A1.

  By making the material of the side electrode 33 Ni-Cr alloy having conductivity and not easily sulfided, the side electrode 33 is not sulfided. Therefore, disconnection of the side electrode 33 is avoided, and sulfidation of the upper surface electrode 31 through the side electrode 33 is prevented. Further, since the side electrode 33 is formed by physical vapor deposition using a sputtering method or the like, the first protective layer 41 in contact with the side electrode 33 can be used as an electrical insulator. In this case, since the first protective layer 41 is made of, for example, a paste containing glass, the cost of the chip resistor A1 can be further reduced.

[Second Embodiment]
A chip resistor A2 according to the second embodiment of the present invention will be described with reference to FIGS. In these drawings, the same or similar elements as those of the chip resistor A1 described above are denoted by the same reference numerals, and redundant description will be omitted.

  FIG. 16 is a plan view showing the chip resistor A2. 17 is a cross-sectional view taken along line XVII-XVII in FIG. In FIG. 16, the intermediate electrode 34, the external electrode 35, and the protective film 5 are omitted for convenience of understanding. In the present embodiment, the chip resistor A2 has a rectangular shape in plan view.

  The chip resistor A2 according to this embodiment is different from the chip resistor A1 in the plan view shape of the resistor 2 and the configuration of the protective film 5. In this embodiment, the planar view shape of the resistor 2 is a serpentine shape. The resistor 2 having the shape can be formed by a technique using photolithography after the resistor 2 is mounted on the mounting surface 11 of the substrate 1 by physical vapor deposition such as sputtering. In this case, the resistor 2 is made of, for example, a Ni—Cr alloy. That is, the chip resistor A2 according to the present embodiment is a so-called thin film chip resistor. In the present embodiment, the lower protective film 51 of the protective film 5 is omitted.

  Next, the function and effect of the chip resistor A2 will be described.

  Also according to the present embodiment, like the chip resistor A1, the first protective layer 41 having a characteristic that it is less likely to be sulfided than the upper surface electrode 31 including carbon particles, and the second protective layer 42 having conductivity including Ag. It is possible to improve the resistance to sulfuration while suppressing the cost of the chip resistor A2. In addition, by making the resistor 2 in a plan view shape, the resistance value of the chip resistor A2 can be made relatively higher than that of the chip resistor A1, and the accuracy of the resistance value can be improved.

[Third Embodiment]
Based on FIGS. 18-20, the chip resistor A3 concerning 3rd Embodiment of this invention is demonstrated. In these drawings, the same or similar elements as those of the chip resistor A1 described above are denoted by the same reference numerals, and redundant description will be omitted.

  FIG. 18 is a plan view showing the chip resistor A3. 19 is a cross-sectional view taken along line XIX-XIX in FIG. 20 is a partially enlarged cross-sectional view in which a part of FIG. 19 is enlarged. In FIG. 18, the intermediate electrode 34 and the external electrode 35 are omitted for convenience of understanding. The chip resistor A3 according to this embodiment is a so-called thick film chip resistor, like the chip resistor A1. In the present embodiment, the chip resistor A3 has a rectangular shape in plan view.

  The chip resistor A3 of the present embodiment is different from the chip resistor A1 in that the protective layer 4 is omitted and the configuration of the electrode 3 and the protective film 5 is different.

  The electrode 3 according to the present embodiment includes an upper surface electrode 31, a back surface electrode 32, a side surface electrode 33, an intermediate electrode 34, and an external electrode 35 similarly to the chip resistor A1. Among these, the configurations of the side electrode 33, the intermediate electrode 34, and the external electrode 35 are different from the chip resistor A1.

  The side electrode 33 is a part disposed on the side surface 13 of the substrate 1 as shown in FIGS. In addition to the side surface 13, the side surface electrode 33 covers a part of the upper surface electrode 31, the back surface electrode 32, and the upper protective film 52. That is, the side electrode 33 has a portion disposed on the side surface 13 and a portion overlapping the mounting surface 11 and the mounting surface 12 of the substrate 1 in plan view of the substrate 1. The upper surface electrode 31 and the rear surface electrode 32 are electrically connected to each other by the side electrode 33. Therefore, the resistor 2 is electrically connected to the back electrode 32 by the top electrode 31 and the side electrode 33. In the present embodiment, the side electrode 33 is made of, for example, a Ni—Cr alloy. The material of the side electrode 33 may be any metal as long as it is conductive and has a characteristic that it is difficult to be sulfided.

  As shown in FIGS. 19 and 20, the intermediate electrode 34 is a portion that covers the back electrode 32 and the side electrode 33. In the present embodiment, the intermediate electrode 34 is made of, for example, a Ni plating layer.

  As shown in FIGS. 19 and 20, the external electrode 35 is a part that covers the intermediate electrode 34. In the present embodiment, the external electrode 35 is made of, for example, a Sn plating layer.

  As shown in FIGS. 18 to 20, the protective film 5 is a member that covers the resistor 2 and functions to protect the resistor 2 from the outside. The protective film 5 includes a lower protective film 51 and an upper protective film 52. The lower protective film 51 and the upper protective film 52 are stacked on each other. The lower protective film 51 and the upper protective film 52 are both electrical insulators. The lower protective film 51 according to the present embodiment is made of a material that is more resistant to thermal shock than the upper protective film 52.

  The lower protective film 51 is a part that covers the resistor 2. The lower protective film 51 is located below the upper protective film 52 shown in FIGS. In addition to the resistor 2, the lower protective film 51 covers a part of the surface of the upper surface electrode 31 (the upper surface of the upper surface electrode 31 shown in FIGS. 19 and 20). As shown in FIG. 18, the lower protective film 51 has a shape extending outward from the boundary between the side electrode 33 and the upper protective film 52 in plan view of the chip resistor A3 toward the side surface 13 of the substrate 1. It has become. The lower protective film 51 is made of, for example, a paste containing glass.

  The upper protective film 52 is a part that covers a part of the substrate 1 and the upper surface electrode 31 and the lower protective film 51 that covers the resistor 2. The upper protective film 52 is located above the lower protective film 51 shown in FIGS. In the present embodiment, a part of the upper protective film 52 is covered with the side electrode 33. The upper protective film 52 is made of, for example, a paste containing an epoxy resin.

  Next, a manufacturing method of the chip resistor A3 will be described with reference to FIGS. FIG. 21 to FIG. 6 are plan views showing steps according to the manufacturing method of the chip resistor A3. FIG. 27 to FIG. 30 are perspective views showing steps according to the manufacturing method of the chip resistor A3. 27 and 28 ignore the thicknesses of the resistor 2, the upper surface electrode 31, the side surface electrode 33, the lower protective film 51, and the upper protective film 52 for convenience of understanding.

  First, as shown in FIG. 21, a sheet-like substrate 81 made of alumina is prepared. The sheet-like substrate 81 has a mounting surface 11 and a mounting surface 12. The mounting surface 11 and the mounting surface 12 face opposite sides. FIG. 21 shows the mounting surface 11 of the sheet-like substrate 81. In the mounting surface 11, a plurality of primary division grooves 811 are formed in a grid pattern in the vertical direction shown in FIG. 21, and a plurality of secondary division grooves 812 are formed in the horizontal direction shown in FIG. The primary dividing grooves 811 and the secondary dividing grooves 812 have the same number as the number formed on the mounting surface 11 on the mounting surface 12 (not shown). The positions of the primary dividing groove 811 and the secondary dividing groove 812 in plan view are the same for both the mounting surface 11 and the mounting surface 12. A section formed by the primary dividing groove 811 and the secondary dividing groove 812 is an area to be the substrate 1 of the chip resistor A3.

  Next, as shown in FIG. 22, the upper surface electrode 31 is formed on the mounting surface 11 of the sheet-like substrate 81 so as to straddle the primary division grooves 811 of the sheet-like substrate 81. In addition, the back surface electrode 32 is formed on the mounting surface 12 of the sheet-like substrate 81 so as to straddle the primary division grooves 811 (not shown). The positions of the top electrode 31 and the back electrode 32 in plan view are substantially the same. In the present embodiment, the top electrode 31 and the back electrode 32 are obtained by printing a paste containing glass frit in Ag using a silk screen on the mounting surface 11 and the mounting surface 12, respectively, and firing them in a firing furnace. It is formed. By this step, the top electrode 31 and the back electrode 32 having a pair of regions separated from each other are formed on the mounting surface 11 and the mounting surface 12.

Next, as shown in FIG. 23, the resistor 2 that is electrically connected to the upper surface electrode 31 is mounted on a region sandwiched between the pair of regions of the upper surface electrode 31 in the mounting surface 11 of the sheet-like substrate 81. In the present embodiment, the resistor 2 is mounted by printing a paste containing a glass frit in a metal such as RuO ₂ or an Ag—Pd alloy using a silk screen and firing it in a firing furnace.

  Next, as shown in FIG. 24, a lower protective film 51 that covers the surface of the resistor 2 is formed. In the present embodiment, the lower protective film 51 is formed by printing a paste containing glass using a silk screen and baking it in a baking furnace. By this step, the surface of the resistor 2 and a part of the upper surface electrode 31 are covered with the lower protective film 51.

  Next, as shown in FIG. 25, a trimming groove 21 that penetrates the resistor 2 is formed in each resistor 2. The trimming groove 21 is formed by a laser trimming apparatus (not shown). The procedure for forming the trimming groove 21 is the same as the procedure for forming the trimming groove 21 in the chip resistor A1 shown in FIG. Through this step, a trimming groove 21 having an L shape in plan view is formed in the resistor 2. The trimming groove 21 is formed in a state in which a resistance measurement probe (not shown) is in contact with an exposed portion of the pair of upper surface electrodes 31 sandwiching the resistor 2.

  Next, as shown in FIG. 26, the upper protective film 52 is formed on the mounting surface 11 of the sheet-like substrate 81. At this time, the lower protective film 51 covering the surface of the resistor 2 and a part of the upper surface electrode 31 and a part of the upper surface electrode 31 are covered with the upper protective film 52. In the present embodiment, the upper protective film 52 is formed in a plurality of strips extending along the primary division grooves 811 of the sheet substrate 81 so as to straddle the secondary division grooves 812 of the sheet substrate 81. In the present embodiment, the upper protective film 52 is formed by printing and curing a paste containing an epoxy resin using a silk screen. Note that the upper protective film 52 may be formed so as to be separated for each resistor 2, similarly to the lower protective film 51 shown in FIG. 24.

  Next, as shown in FIG. 27, the sheet-like substrate 81 is cut by the primary division grooves 811 of the sheet-like substrate 81 and divided into a plurality of strip-like substrates 86. At this time, the side surfaces 13 are formed on both sides of the strip substrate 86 along the longitudinal direction of the strip substrate 86.

  Next, as shown in FIG. 28, the side surface electrodes 33 are formed on the side surface 13 located along both ends in the longitudinal direction of the belt-like substrate 86 and a part of each of the mounting surface 11 and the mounting surface 12. In the present embodiment, the side electrode 33 is formed by depositing a Ni—Cr alloy by physical vapor deposition using a sputtering method or the like. In forming the side electrode 33, the side surface 13 and a part of the surface of each of the upper surface electrode 31, the back surface electrode 32, and the upper protective film 52 arranged orthogonal to the side surface 13 are integrated with the side surface electrode 33. The back electrode 32 is not shown. At this time, the side electrode 33 is in contact with the respective end portions along the side surface 13 of the top electrode 31 and the back electrode 32. By this step, the upper surface electrode 31 and the rear surface electrode 32 are electrically connected to each other by the side surface electrode 33.

  Next, as shown in FIG. 29, the belt-like substrate 86 is cut by the secondary dividing grooves 812 of the belt-like substrate 86 and divided into a plurality of pieces 87. At this time, the shape of the side electrode 33 is a U-shape sandwiching the substrate 1. The side electrode 33 is one of the mounting surface 11 and the mounting surface 12 of the substrate 1 located on both sides of the side electrode 33 formed on a part of the surface of each of the top electrode 31 and the back electrode 32. It is also formed in each part.

  Next, as shown in FIG. 30, in the individual piece 87, an intermediate electrode 34 that covers the back electrode 32 and the side electrode 33 and an external electrode 35 that covers the intermediate electrode 34 are formed (the back electrode 32 is not shown). In the present embodiment, the intermediate electrode 34 is formed by Ni plating, and the external electrode 35 is formed by Sn plating. By this step, a pair of electrodes 3 that are electrically connected to the resistor 2 are formed. Through the above steps, the chip resistor A3 is manufactured.

  Next, the function and effect of the chip resistor A3 will be described.

  According to the present embodiment, the chip resistor A3 has a lower protective film 51 and an upper protective film 52 that are stacked on each other, and a part of the upper surface electrode 31 is covered with the lower protective film 51. . The lower protective film 51 is made of a material that is more resistant to thermal shock than the upper protective film 52. For this reason, cracks are generated in the upper protective film 52 due to the thermal shock generated at the tip portions of the plating layers that are the intermediate electrode 34 and the external electrode 35 (the boundary portion between the plating layer and the upper protective film 52 in plan view). In addition, the progress of the crack is suppressed by the lower protective film 51. Therefore, since the upper surface electrode 31 is not exposed by the crack, the sulfide gas generated around the chip resistor A3 does not enter the upper surface electrode 31 through the crack. Therefore, even if a crack occurs in the upper protective film 52 due to the thermal shock generated in the electrode 3, disconnection of the electrode 3 due to sulfuration can be prevented.

  By making the material of the side electrode 33 Ni-Cr alloy having conductivity and not easily sulfided, sulfidation of the side electrode 33 is suppressed. Therefore, disconnection of the side electrode 33 is avoided and sulfidation of the upper surface electrode 31 via the side electrode 33 is avoided. Further, since the side electrode 33 is formed by physical vapor deposition using a sputtering method or the like, the adhesion performance with the upper protective film 52 that is an electrical insulator is further improved. Therefore, peeling of the Ni plating layer that is the intermediate electrode 34 together with the side electrode 33 is avoided, so that the concern that a part of the upper surface electrode 31 is exposed and the exposed portion is sulfided due to the peeling.

[Fourth Embodiment]
A chip resistor A4 according to the fourth embodiment of the present invention will be described with reference to FIGS. In these drawings, the same or similar elements as those of the chip resistor A1 described above are denoted by the same reference numerals, and redundant description will be omitted.

  FIG. 31 is a plan view showing the chip resistor A4. 32 is a cross-sectional view taken along line XXXII-XXXII in FIG. FIG. 33 is a partially enlarged cross-sectional view in which a part of FIG. 32 is enlarged. In FIG. 31, the intermediate electrode 34 and the external electrode 35 are omitted for convenience of understanding. The chip resistor A4 according to the present embodiment is a so-called thick film chip resistor, like the chip resistor A1. In the present embodiment, the chip resistor A4 has a rectangular shape in plan view.

  The chip resistor A4 of the present embodiment is different from the chip resistor A1 in the configuration of the protective layer 4 and the protective film 5.

  As shown in FIGS. 31 to 33, the protective layer 4 is a member formed on the upper surface of the upper surface electrode 31 and having a pair of regions separated from each other. The protective layer 4 has a characteristic that it is less likely to be sulfided than the upper surface electrode 31. In the present embodiment, the protective layer 4 covers a part of each of the upper surface electrode 31 and the lower protective film 51. The protective layer 4 may not cover a part of the lower protective film 51. In the present embodiment, each part of the protective layer 4 is covered with the side electrode 33 and the upper protective film 52 and is in contact with the side electrode 33 on the surface that is aligned with the side surface 13 of the substrate 1. The protective layer 4 according to the present embodiment is made of a paste including glass and metal oxide made of, for example, Ru, carbon particles (carbon black), and an epoxy resin, like the first protective layer 41 of the chip resistor A1. Become. In this case, the protective layer 4 has conductivity. The protective layer 4 may be an electrical insulator made of, for example, a paste containing glass.

  As shown in FIGS. 31 to 33, the protective film 5 is a member that covers the resistor 2 and functions to protect the resistor 2 from the outside. The protective film 5 includes a lower protective film 51 and an upper protective film 52. The lower protective film 51 and the upper protective film 52 are stacked on each other. The lower protective film 51 and the upper protective film 52 are both electrical insulators. The material of the lower protective film 51 according to the present embodiment is the same as the lower protective film 51 of the chip resistor A3, and the material of the upper protective film 52 is the same as the material of the chip resistor A3.

  The lower protective film 51 is a part that covers the resistor 2. The lower protective film 51 is located below the upper protective film 52 shown in FIGS. Similar to the chip resistor A3, the lower protective film 51 covers a part of the surface of the upper surface electrode 31 (the upper surface of the upper surface electrode 31 shown in FIGS. 32 and 33) in addition to the resistor 2. As shown in FIG. 31, the lower protective film 51 has a shape extending outward from the boundary between the side electrode 33 and the upper protective film 52 in the plan view of the chip resistor A4 toward the side surface 13 of the substrate 1. It has become.

  The upper protective film 52 is a part that covers a part of the substrate 1 and the protective layer 4 and the lower protective film 51 that covers the resistor 2. The upper protective film 52 is located above the lower protective film 51 shown in FIGS. In the present embodiment, a part of the upper protective film 52 is in contact with the side electrode 33, the intermediate electrode 34, and the external electrode 35.

  Next, a manufacturing method of the chip resistor A4 will be described based on FIG. In the manufacture of the chip resistor A3 described above, the step of preparing the sheet-like substrate 81 shown in FIGS. 21 and 22 and forming the upper surface electrode 31, the step of mounting the resistor 2 shown in FIG. 23, and FIG. The process of forming the lower protective film 51 shown and the process of forming the trimming groove 21 shown in FIG. 25 are the same in the manufacture of the chip resistor A4.

  As shown in FIG. 34, after the trimming groove 21 is formed in the resistor 2, the protective layer 4 having a characteristic that is harder to sulfidize than the upper surface electrode 31 is formed in a portion where the upper surface electrode 31 is exposed. In the present embodiment, the protective layer 4 is formed by printing and curing a paste containing glass and metal oxide made of Ru, for example, carbon particles, and an epoxy resin using a silk screen. . In this case, the protective layer 4 has conductivity. When the protective layer 4 is an electrical insulator, it is formed by printing a paste containing glass using a silk screen and firing it in a firing furnace. Through this step, the portion where the upper surface electrode 31 is exposed and a portion of the lower protective film 51 are covered with the protective layer 4.

  Next, the upper protective film 52 is formed on the mounting surface 11 of the sheet-like substrate 81. At this time, the lower protective film 51 covering the surface of the resistor 2 and a part of the upper surface electrode 31 and a part of the protective layer 4 are covered with the upper protective film 52. The method for forming the upper protective film 52 is the same as the method for forming the chip resistor A3 shown in FIG. The process until the chip resistor A4 is manufactured after the formation of the upper protective film 52 is the same as that of the chip resistor A3.

  Next, the function and effect of the chip resistor A4 will be described.

  Also in the present embodiment, like the chip resistor A3, the upper protective film 52 is cracked by the thermal shock generated in the electrode 3 by adopting a configuration in which a part of the upper surface electrode 31 is covered with the lower protective film 51. Even if it occurs, disconnection of the electrode 3 due to sulfurization can be prevented. Further, by providing the protective layer 4, the upper surface of the upper surface electrode 31 is covered with the protective layer 4 in addition to the lower protective film 51. The protective layer 4 has a characteristic that it is less likely to be sulfided than the upper surface electrode 31. Therefore, the sulfur resistance performance of the chip resistor A4 can be further improved as compared with the chip resistor A3.

  The chip resistor according to the present invention is not limited to the above-described embodiment. The specific configuration of each part of the chip resistor according to the present invention can be varied in design in various ways.

  The technical configuration of the chip resistor and the manufacturing method thereof provided by the present invention will be described below.

[Appendix 1]
A substrate having a mounting surface and a mounting surface facing away from each other;
A pair of upper surface electrodes disposed at both ends of the mounting surface of the substrate;
A resistor mounted between the pair of upper surface electrodes on the mounting surface of the substrate;
A protective film covering the resistor and a part of the upper surface electrode;
A portion disposed on a side surface of the substrate located between the mounting surface and the mounting surface of the substrate; a portion overlapping the mounting surface and the mounting surface in a plan view of the substrate; and A side electrode in conduction with the top electrode;
An intermediate electrode covering the side electrode;
A chip resistor comprising an external electrode covering the intermediate electrode,
The protective film has a lower protective film and an upper protective film stacked on each other,
The lower protective film is made of a material that is more resistant to thermal shock than the upper protective film,
A chip resistor, wherein a part of the upper surface electrode is covered with the lower protective film.
[Appendix 2]
The chip resistor according to appendix 1, wherein a part of each of the upper surface electrode and the upper protective film is covered with the side electrode.
[Appendix 3]
Supplementary note 1, further comprising a protective layer that covers at least a part of the upper surface of the upper electrode, and has a characteristic that it is less likely to be sulfided than the upper electrode, wherein at least a part of the protective layer is covered with the side electrode Chip resistor described.
[Appendix 4]
4. The chip resistor according to appendix 3, wherein a part of the protective layer is covered with the upper protective film.
[Appendix 5]
The chip resistor according to appendix 3 or 4, wherein the protective layer includes carbon particles.
[Appendix 6]
The chip resistor according to appendix 3 or 4, wherein the protective layer is an electrical insulator.
[Appendix 7]
The chip resistor according to any one of appendices 1 to 6, wherein the lower protective film includes glass.
[Appendix 8]
The chip resistor according to any one of appendices 1 to 7, wherein the upper protective film includes an epoxy resin.
[Appendix 9]
The chip resistor according to any one of appendices 1 to 8, wherein the side electrode is made of a Ni—Cr alloy.
[Appendix 10]
The chip resistor according to any one of appendices 1 to 9, further comprising a pair of back surface electrodes disposed at both ends of the mounting surface of the substrate, wherein the side surface electrode is electrically connected to the back surface electrode.
[Appendix 11]
The chip resistor according to appendix 10, wherein the back electrode is covered with the intermediate electrode.
[Appendix 12]
The chip resistor according to any one of appendices 1 to 11, wherein the substrate is an electrical insulator.
[Appendix 13]
The chip resistor according to appendix 12, wherein the substrate is made of alumina.
[Appendix 14]
The chip resistor according to any one of appendices 1 to 13, wherein a trimming groove penetrating the resistor is formed in the resistor.
[Appendix 15]
The chip resistor according to any one of appendices 1 to 14, wherein the intermediate electrode and the external electrode are made of a plating layer.
[Appendix 16]
The chip resistor according to appendix 15, wherein the intermediate electrode is made of a Ni plating layer.
[Appendix 17]
The chip resistor according to appendix 15, wherein the external electrode is made of a Sn plating layer.
[Appendix 18]
Preparing a sheet-like substrate having a mounting surface and a mounting surface facing away from each other, and forming a top surface electrode having a pair of regions spaced from each other on the mounting surface of the sheet-like substrate;
A step of mounting a resistor that is electrically connected to the upper surface electrode in a region sandwiched between the pair of regions of the mounting surface of the sheet-like substrate;
Forming a lower protective film covering the resistor and a part of the upper surface electrode;
Forming an upper protective film covering the lower protective film;
Dividing the sheet-like substrate into a plurality of strip-like substrates;
Forming side electrodes that are electrically connected to the upper surface electrodes on side surfaces located along both longitudinal ends of the belt-like substrate, the mounting surface, and the mounting surface;
A method of manufacturing a chip resistor, comprising: forming an intermediate electrode that covers the side electrode and an external electrode that covers the intermediate electrode.
[Appendix 19]
19. The chip resistor according to appendix 18, wherein, in the step of forming the side electrode, the side electrode is formed by covering a part of each of the upper surface electrode and the upper protective film with the side electrode. Manufacturing method.
[Appendix 20]
19. The method for manufacturing a chip resistor according to appendix 18, further comprising a step of forming a protective layer that covers at least a part of the upper surface of the upper surface electrode and has a characteristic that is less sulfidized than the upper surface electrode.
[Appendix 21]
The manufacturing method of the chip resistor according to appendix 20, wherein the protective layer is formed by a technique using printing in the step of forming the protective layer.
[Appendix 22]
The method for manufacturing a chip resistor according to appendix 20 or 21, wherein, in the step of forming the side electrode, the side electrode is formed by covering at least a part of the protective layer with the side electrode.
[Appendix 23]
23. The method of manufacturing a chip resistor according to appendix 22, wherein in the step of forming the upper protective film, the upper protective film is formed by covering a part of the protective layer with the upper protective film.
[Appendix 24]
24. The method for manufacturing a chip resistor according to any one of appendices 18 to 23, wherein, in the step of forming the lower protective film, the lower protective film is formed by a technique using printing.
[Appendix 25]
25. The method of manufacturing a chip resistor according to any one of appendices 18 to 24, wherein in the step of forming the upper protective film, the upper protective film is formed by a technique using printing.
[Appendix 26]
The method for manufacturing a chip resistor according to any one of appendices 18 to 25, wherein, in the step of forming the side electrode, the side electrode is formed by physical vapor deposition.
[Appendix 27]
27. The method for manufacturing a chip resistor according to appendix 26, wherein the physical vapor deposition is a sputtering method.
[Appendix 28]
28. The method for manufacturing a chip resistor according to any one of appendices 18 to 27, wherein, in the step of forming the intermediate electrode and the external electrode, respectively, the intermediate electrode and the external electrode are formed by plating.
[Appendix 29]
29. The method for manufacturing a chip resistor according to appendix 28, further comprising a step of dividing the strip substrate into a plurality of pieces before the step of forming the intermediate electrode and the external electrode, respectively.
[Appendix 30]
30. The method for manufacturing a chip resistor according to any one of appendices 18 to 29, further comprising forming a back electrode having a pair of regions spaced from each other on the mounting surface of the sheet-like substrate.
[Appendix 31]
31. The method for manufacturing a chip resistor according to any one of appendices 18 to 30, further comprising a step of forming a trimming groove penetrating the resistor in the resistor.

A1, A2, A3, A4: Chip resistor 1: Substrate 11: Mounting surface 12: Mounting surface 13: Side surface 2: Resistor 21: Trimming groove 3: Electrode 31: Upper surface electrode 32: Back surface electrode 33: Side surface electrode 34: Intermediate electrode 35: External electrode 4: Protective layer 41: First protective layer 42: Second protective layer 5: Protective film 51: Lower protective film 52: Upper protective film 81: Sheet-like substrate 811: Primary divided groove 812: Secondary Dividing groove 86: strip substrate 87: piece X: direction

Claims (32)

A substrate having a mounting surface and a mounting surface facing away from each other;
A pair of upper surface electrodes disposed at both ends of the mounting surface of the substrate;
A resistor mounted between the pair of upper surface electrodes on the mounting surface of the substrate;
A portion disposed on a side surface of the substrate located between the mounting surface and the mounting surface of the substrate; and a portion overlapping the mounting surface and the mounting surface in a thickness direction view of the substrate; And a side electrode in conduction with the upper surface electrode;
An intermediate electrode covering the side electrode;
A chip resistor comprising an external electrode covering the intermediate electrode,
A first protective layer that is located between the upper surface electrode and the intermediate electrode and that is disposed in contact with the upper surface electrode and the side electrode, and has a property that is less susceptible to sulfidation than the upper surface electrode;
A conductive second protective layer positioned between the first protective layer and the intermediate electrode and disposed in contact with the first protective layer, the side electrode, and the intermediate electrode; A chip resistor, comprising:   The chip resistor according to claim 1, wherein the first protective layer includes carbon particles.   The chip resistor according to claim 1, wherein the first protective layer is an electrical insulator.   The chip resistor according to claim 1, wherein the second protective layer contains Ag.   The chip resistor according to claim 1, wherein the side electrode is made of a Ni—Cr alloy.   6. The chip resistor according to claim 1, further comprising a pair of back surface electrodes disposed at both ends of the mounting surface of the substrate, wherein the side surface electrodes are electrically connected to the back surface electrode.   The chip resistor according to claim 6, wherein the back electrode is covered with the intermediate electrode.   The chip resistor according to claim 1, wherein the substrate is an electrical insulator.   The chip resistor according to claim 8, wherein the substrate is made of alumina.   The chip resistor according to claim 1, wherein a shape of the resistor in plan view is a serpentine shape. The chip resistor according to claim 1, wherein the resistor includes RuO ₂ or an Ag—Pd alloy.   The chip resistor according to claim 1, wherein a trimming groove penetrating the resistor is formed in the resistor.   The chip resistor according to claim 1, wherein the intermediate electrode and the external electrode are made of a plating layer.   The chip resistor according to claim 13, wherein the intermediate electrode is made of a Ni plating layer.   The chip resistor according to claim 13, wherein the external electrode is made of a Sn plating layer.   The chip resistor according to claim 1, further comprising a protective film that covers the resistor and a part of the upper surface electrode.   The chip resistor according to claim 16, wherein a part of the first protective layer is covered with the protective film.   The chip resistor according to claim 16, wherein the protective film includes a lower protective film and an upper protective film.   The chip resistor according to claim 18, wherein the lower protective film includes glass.   The chip resistor according to claim 18, wherein the upper protective film includes an epoxy resin. Preparing a sheet-like substrate having a mounting surface and a mounting surface facing away from each other, and forming a top surface electrode having a pair of regions spaced from each other on the mounting surface of the sheet-like substrate;
A step of mounting a resistor that is electrically connected to the upper surface electrode in a region sandwiched between the pair of regions of the mounting surface of the sheet-like substrate;
Forming a first protective layer on the upper surface of the upper electrode, which has a characteristic that it is less likely to be sulfided than the upper electrode;
Forming a conductive second protective layer on the upper surface of the first protective layer;
Dividing the sheet-like substrate into a plurality of strip-like substrates;
Side electrodes that are electrically connected to the upper surface electrode and are in contact with the first protective layer and the second protective layer are formed on the side surface, the mounting surface, and the mounting surface that are positioned along the longitudinal ends of the belt-shaped substrate. Process,
A method of manufacturing a chip resistor, comprising: forming an intermediate electrode that covers the side electrode and the second protective layer, and an external electrode that covers the intermediate electrode.   The method for manufacturing a chip resistor according to claim 21, wherein in the step of forming the first protective layer, the first protective layer is formed by a technique using printing.   The manufacturing method of the chip resistor according to claim 21 or 22, wherein, in the step of forming the second protective layer, the second protective layer is formed by a technique using printing.   The method for manufacturing a chip resistor according to claim 21, wherein in the step of forming the side electrode, the side electrode is formed by physical vapor deposition.   The method of manufacturing a chip resistor according to claim 24, wherein the physical vapor deposition is a sputtering method.   26. The chip resistor according to claim 21, wherein, in the step of mounting the resistor, the resistor is mounted by a technique using printing or a technique using physical vapor deposition and photolithography. Manufacturing method.   The chip resistor according to any one of claims 21 to 26, further comprising a step of dividing the strip substrate into a plurality of pieces before the step of forming the intermediate electrode and the external electrode, respectively. Production method.   28. The method of manufacturing a chip resistor according to claim 27, wherein, in the step of forming the intermediate electrode and the external electrode, respectively, the intermediate electrode and the external electrode are formed by plating.   29. The method for manufacturing a chip resistor according to claim 21, further comprising a step of forming a back electrode having a pair of regions spaced apart from each other on the mounting surface of the sheet-like substrate.   30. The method of manufacturing a chip resistor according to claim 21, further comprising a step of forming a trimming groove penetrating the resistor in the resistor.   31. The method of manufacturing a chip resistor according to claim 21, further comprising a step of forming a protective film that covers the resistor and a part of each of the upper surface electrode and the first protective layer. .   32. The method of manufacturing a chip resistor according to claim 31, wherein the step of forming the protective film includes a step of forming a lower protective film and a step of forming an upper protective film.

Images