JP5706186B2 - Chip resistor and manufacturing method thereof - Google Patents

Chip resistor and manufacturing method thereof Download PDF

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JP5706186B2
JP5706186B2 JP2011038627A JP2011038627A JP5706186B2 JP 5706186 B2 JP5706186 B2 JP 5706186B2 JP 2011038627 A JP2011038627 A JP 2011038627A JP 2011038627 A JP2011038627 A JP 2011038627A JP 5706186 B2 JP5706186 B2 JP 5706186B2
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chip resistor
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泰 赤羽
泰 赤羽
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Koa Corp
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本発明は、導電性接着剤を用いて回路基板上にフェースダウン実装されるチップ抵抗器と、その製造方法とに関する。   The present invention relates to a chip resistor that is mounted face-down on a circuit board using a conductive adhesive, and a manufacturing method thereof.

回路基板上にフェースダウン実装されるチップ抵抗器には、回路基板と対向する側の面に、保護膜に覆われた抵抗体や、抵抗体の両端部に重なり合う一対の電極が設けられている。   A chip resistor face-down mounted on a circuit board is provided with a resistor covered with a protective film and a pair of electrodes that overlap both ends of the resistor on the surface facing the circuit board. .

この種のチップ抵抗器の従来例として、直方体形状の絶縁性基板の片面(回路基板と対向する側の面)に、抵抗体と、この抵抗体の長手方向両端部を覆う一対の主電極と、これら主電極間に露出する抵抗体を被覆する保護膜とを設けると共に、絶縁性基板の長手方向両端面に端面電極を設け、この端面電極を主電極に密着接合させた構造のものが知られている(例えば、特許文献1参照)。かかる従来例において、主電極や端面電極の表面には、半田濡れ性を高める等の理由でメッキ処理が施されており、このチップ抵抗器をフェースダウン実装する際には、回路基板に設けられた配線パターン上に主電極を搭載して半田接合し、端面電極によって半田フィレットが形成されるようにしている。   As a conventional example of this type of chip resistor, a resistor and a pair of main electrodes that cover both ends of the resistor in the longitudinal direction are provided on one side (surface facing the circuit board) of a rectangular parallelepiped insulating substrate. And a protective film covering the resistor exposed between the main electrodes, and having end face electrodes on both end faces in the longitudinal direction of the insulating substrate, and the end face electrodes are closely bonded to the main electrodes. (For example, refer to Patent Document 1). In such a conventional example, the surface of the main electrode and the end face electrode is plated for reasons such as improving solder wettability. When this chip resistor is mounted face-down, it is provided on the circuit board. A main electrode is mounted on the wiring pattern and soldered, and a solder fillet is formed by the end face electrode.

しかしながら、かかる従来例では、主電極や端面電極の表面に2層以上のメッキ層(Niメッキ層や半田メッキ層等)を形成しなければならないため、メッキ処理工程が煩雑で安価に製造できないという難点があった。また、昨今、半田接合に際して、環境への配慮から鉛を含まない鉛フリー半田を用いることが推奨されているが、鉛フリー半田を溶融させるためには約260℃まで加熱する必要がある。したがって、鉛フリー半田を用いた半田接合に対応させようとすると、チップ抵抗器の耐熱性を大幅に高めておかねばならず、必然的にチップ抵抗器の製造コストは上昇してしまう。   However, in this conventional example, since two or more plating layers (Ni plating layer, solder plating layer, etc.) must be formed on the surface of the main electrode and the end face electrode, the plating process is complicated and cannot be manufactured at low cost. There were difficulties. In recent years, it has been recommended to use lead-free solder that does not contain lead in consideration of the environment when soldering, but it is necessary to heat the lead-free solder to about 260 ° C. in order to melt it. Therefore, when trying to cope with solder bonding using lead-free solder, the heat resistance of the chip resistor must be greatly increased, and the manufacturing cost of the chip resistor inevitably increases.

一方、半田の代わりに導電性接着剤を用いてチップ抵抗器を回路基板上に実装するという技術が従来より知られている(例えば、特許文献2参照)。この導電性接着剤は、金属粉末等の導電材料をエポキシ系等の樹脂材料に分散させたものであり、200℃以下の温度で硬化して、チップ抵抗器のメッキ処理されていない電極を回路基板上の配線パターンに接合させることができる。それゆえ、フェースダウン実装に際して導電性接着剤を用いることにすれば、チップ抵抗器の電極の表面にメッキ層を形成する必要がなくなり、かつチップ抵抗器の耐熱性を特に高める必要もなくなるため、チップ抵抗器を安価に製造することができるようになる。   On the other hand, a technique of mounting a chip resistor on a circuit board using a conductive adhesive instead of solder has been conventionally known (see, for example, Patent Document 2). This conductive adhesive is obtained by dispersing a conductive material such as metal powder in an epoxy-based resin material, and curing it at a temperature of 200 ° C. or lower to connect an unplated electrode of a chip resistor to a circuit. It can be bonded to the wiring pattern on the substrate. Therefore, if a conductive adhesive is used for face-down mounting, it is not necessary to form a plating layer on the surface of the chip resistor electrode, and it is not necessary to particularly increase the heat resistance of the chip resistor. Chip resistors can be manufactured at low cost.

ただし、一般的にチップ抵抗器の電極の表面は比較的平滑に形成されているため、導電性接着剤をチップ抵抗器の電極に直接付着させても所望の接着強度が得にくいものとなっている。このような理由から、特許文献2に開示されたチップ抵抗器では、電極を覆って絶縁性基板の端部を包み込むような比較的広い領域に、樹脂材料に導電材料を分散させたた導電性接続材料からなる外部電極を設け、この外部電極の樹脂材料として実装時に用いる導電性接着剤の樹脂材料との密着性が良好なものを選択しておくことにより、チップ抵抗器の外部電極に対する導電性接着剤の接着強度を高めている。   However, since the surface of the electrode of the chip resistor is generally formed to be relatively smooth, it is difficult to obtain a desired adhesive strength even if the conductive adhesive is directly attached to the electrode of the chip resistor. Yes. For this reason, in the chip resistor disclosed in Patent Document 2, a conductive material in which a conductive material is dispersed in a resin material in a relatively wide region that covers the electrode and wraps the end portion of the insulating substrate. By providing an external electrode made of a connecting material and selecting a resin material with good adhesion to the resin material of the conductive adhesive used during mounting as the resin material for this external electrode, The adhesive strength of the adhesive is increased.

特開2007−88162号公報JP 2007-88162 A 特開2010−225660号公報JP 2010-225660 A

特許文献2に開示されたチップ抵抗器のように、電極を予め導電性接続材料からなる外部電極で覆っておけば、煩雑なメッキ処理が不要となって製造コストを抑えやすくなると共に、導電性接着剤を用いて回路基板上にフェースダウン実装することが可能となる。しかし、かかる従来のチップ抵抗器においては、導電性接続材料からなる外部電極を形成するために、未硬化の導電性接続材料に絶縁性基板の分割端面を浸漬するディップ工程と、その未硬化材料を加熱硬化する加熱硬化工程とを追加しなければならないため、チップ抵抗器の製造コストを大幅に低下させることは困難であった。また、実装時に用いられる導電性接着剤の樹脂材料は必ずしも外部電極の樹脂材料と密着度が良好であると限らず、導電性接着剤の種類によっては所望の接着強度を得ることができず、チップ抵抗器の外部電極と導電性接着剤との導通の信頼性を損なう虞があった。   If the electrode is previously covered with an external electrode made of a conductive connecting material as in the chip resistor disclosed in Patent Document 2, a complicated plating process is not required, and the manufacturing cost can be easily reduced and the conductive property can be reduced. It becomes possible to mount face down on a circuit board using an adhesive. However, in such a conventional chip resistor, in order to form an external electrode made of a conductive connection material, a dipping step of immersing the divided end face of the insulating substrate in an uncured conductive connection material, and the uncured material Therefore, it has been difficult to significantly reduce the manufacturing cost of the chip resistor. In addition, the resin material of the conductive adhesive used at the time of mounting is not necessarily good adhesion with the resin material of the external electrode, depending on the type of conductive adhesive, it is not possible to obtain the desired adhesive strength, There is a possibility that the reliability of conduction between the external electrode of the chip resistor and the conductive adhesive is impaired.

本発明は、このような従来技術の実情に鑑みてなされたもので、その第1の目的は、導電性接着剤を用いたフェースダウン実装に好適で導通の信頼性が高いチップ抵抗器を提供することにある。また、本発明の第2の目的は、そのようなチップ抵抗器を安価に製造できる製造方法を提供することにある。   The present invention has been made in view of the actual situation of the prior art, and a first object thereof is to provide a chip resistor suitable for face-down mounting using a conductive adhesive and having high conduction reliability. There is to do. A second object of the present invention is to provide a manufacturing method capable of manufacturing such a chip resistor at a low cost.

上記の第1の目的を達成するために、本発明では、絶縁性基板の片面に、抵抗体と、この抵抗体の両端部に重なり合う一対の電極と、前記抵抗体を覆う保護膜とが設けられ、前記絶縁性基板の前記片面側を回路基板に対向させてフェースダウン実装されるチップ抵抗器において、前記電極が前記絶縁性基板の前記片面の外縁から離れた領域に設けられており、前記電極の表面を露出させると共に、この露出面が少なくとも前記絶縁性基板の表面よりも粗くなるように粗面化処理されているという構成にした。 In order to achieve the first object described above, in the present invention, a resistor, a pair of electrodes overlapping both ends of the resistor, and a protective film covering the resistor are provided on one surface of the insulating substrate. In the chip resistor mounted face down with the one side of the insulating substrate facing the circuit board, the electrode is provided in a region away from the outer edge of the one side of the insulating substrate, Rutotomoni to expose the surface of the electrode, the exposed surface is a configuration that has been surface-roughened to be rougher than at least the surface of the insulating substrate.

このように構成されたチップ抵抗器は、粗面化処理によって電極の露出面に微細な凹部が多数形成されており、該電極の露出面の表面積も凹部の存在で広くなっているため、電極の露出面に対する導電性接着剤の接着強度を大幅に高めることができる。それゆえ、このチップ抵抗器は半田を使用せずに導電性接着剤を用いて回路基板上にフェースダウン実装することができ、チップ抵抗器の電極と導電性接着剤との導通信頼性も良好となる。また、このチップ抵抗器には電極を覆うメッキ層や外部電極等が不要であり、チップ抵抗器の耐熱性を特に高める必要もないため、製造コストを大幅に低減することができる。さらに、電極が絶縁性基板の片面の外縁から離れた領域に設けられており、電極の露出した部分の周壁を絶縁性基板の片面の非印刷領域で包囲することができるため、チップ抵抗器をフェースダウン実装する際に該周壁すべてに導電性接着剤を容易に付着させることができ、電極の露出面を導電性接着剤で確実に覆えるようになる。それゆえ、電極の酸化や硫化を防止できて安定した性能が維持しやすくなる。しかも、このように電極を絶縁性基板の稜線(外形線)から離隔させておけば、チップ抵抗器の製造過程で絶縁性基板を多数個取りするための大判基板の分割溝に電極がオーバーラップしなくなるため、分割作業時の作業性が向上して製造歩留まりも高めやすくなる。 The chip resistor configured in this way has a large number of fine concave portions formed on the exposed surface of the electrode by the roughening treatment, and the surface area of the exposed surface of the electrode is wide due to the presence of the concave portion. The adhesive strength of the conductive adhesive to the exposed surface can be greatly increased. Therefore, this chip resistor can be mounted face-down on the circuit board using a conductive adhesive without using solder, and the conduction reliability between the electrode of the chip resistor and the conductive adhesive is also good. It becomes. Further, this chip resistor does not require a plating layer covering the electrode, an external electrode, or the like, and it is not necessary to particularly increase the heat resistance of the chip resistor, so that the manufacturing cost can be greatly reduced. Furthermore, the electrode is provided in a region away from the outer edge of one side of the insulating substrate, and the peripheral wall of the exposed portion of the electrode can be surrounded by the non-printing region on one side of the insulating substrate. When face-down mounting, the conductive adhesive can be easily attached to all the peripheral walls, and the exposed surface of the electrode can be reliably covered with the conductive adhesive. Therefore, oxidation and sulfurization of the electrode can be prevented and stable performance can be easily maintained. In addition, if the electrodes are separated from the ridgeline (outline) of the insulating substrate in this way, the electrodes overlap the dividing grooves of the large substrate for taking a large number of insulating substrates in the manufacturing process of the chip resistor. Therefore, workability at the time of division work is improved and the manufacturing yield is easily increased.

上記の構成のチップ抵抗器において、絶縁性基板の片面から保護膜の表面までの高さ寸法に比べて、絶縁性基板の片面から電極の露出面までの高さ寸法が同等以上の大きさに設定されていると、フェースダウン実装したチップ抵抗器が保護膜を支点として傾く虞がなくなるため、実装後のチップ抵抗器に上方から外力が作用してもクラック等を生じにくくなる。この場合において、絶縁性基板の片面の両端部に絶縁層を設け、この絶縁層を覆うように電極を設ければ、絶縁層の膜厚によって電極の高さ位置を容易に嵩上げできる。   In the chip resistor having the above configuration, the height dimension from one side of the insulating substrate to the exposed surface of the electrode is equal to or greater than the height dimension from one side of the insulating substrate to the surface of the protective film. If it is set, there is no possibility that the chip resistor mounted face-down will be inclined with the protective film as a fulcrum, so that even if an external force acts on the mounted chip resistor from above, cracks and the like are less likely to occur. In this case, if an insulating layer is provided on both ends of one side of the insulating substrate and an electrode is provided so as to cover the insulating layer, the height position of the electrode can be easily raised by the film thickness of the insulating layer.

また、上記の構成のチップ抵抗器において、絶縁性基板の片面と逆側の面に磁性体からなる磁性層が設けられていると、このチップ抵抗器をテーピング包装したり自動マウントする際に、磁石によってチップ抵抗器の姿勢を安定させることができる。   Further, in the chip resistor having the above configuration, when a magnetic layer made of a magnetic material is provided on the surface opposite to the one surface of the insulating substrate, when the chip resistor is taped and automatically mounted, The posture of the chip resistor can be stabilized by the magnet.

上記の第2の目的を達成するために、本発明では、絶縁性基板の片面に、抵抗体と、この抵抗体の両端部に重なり合う一対の電極と、前記抵抗体を覆う保護膜とが設けられ、前記絶縁性基板の前記片面側を回路基板に対向させてフェースダウン実装されるチップ抵抗器の製造方法において、前記絶縁性基板の前記片面に電極ペーストを厚膜印刷して前記電極を形成すると共に、軟化点の異なる複数種類のガラス材を前記電極ペーストに含有させることにより、前記電極の表面を少なくとも前記絶縁性基板の表面よりも粗くなるように粗面化処理したうえで露出させるようにした。 In order to achieve the second object described above, in the present invention, a resistor, a pair of electrodes overlapping both ends of the resistor, and a protective film covering the resistor are provided on one surface of the insulating substrate. In the method of manufacturing a chip resistor face-down mounted with the one side of the insulating substrate facing the circuit board, the electrode is formed by thick-film printing an electrode paste on the one side of the insulating substrate. In addition, by including a plurality of types of glass materials having different softening points in the electrode paste, the surface of the electrode is exposed after being roughened so as to be rougher than at least the surface of the insulating substrate. I made it.

このようにチップ抵抗器の電極の表面を粗面化処理したうえで露出させると、微細な凹部が多数形成されて表面積も広い電極の露出面を、導電性接着剤との接着強度が確保しやすい接着面として機能させることができる。それゆえ、こうして製造したチップ抵抗器は半田を使用せずに導電性接着剤を用いて回路基板上にフェースダウン実装することができ、チップ抵抗器の電極と導電性接着剤との導通信頼性も良好となる。また、こうして製造されるチップ抵抗器には電極を覆うメッキ層や外部電極等が不要であり、チップ抵抗器の耐熱性を特に高める必要もないため、製造コストを大幅に低減することができる。しかも、軟化点の異なる複数種類のガラス材を電極ペーストに含有させることにより、チップ抵抗器の電極を粗面化処理するようにしたため、電極の形成工程で粗面化処理を行うことができる。 Thus, when the surface of the chip resistor electrode is roughened and exposed, the exposed surface of the electrode having a large number of fine recesses and a large surface area ensures the adhesive strength with the conductive adhesive. It can function as an easy adhesive surface. Therefore, the chip resistor manufactured in this way can be mounted face-down on the circuit board using a conductive adhesive without using solder, and the conduction reliability between the electrode of the chip resistor and the conductive adhesive Will also be good. In addition, the chip resistor manufactured in this way does not require a plating layer covering the electrode, an external electrode, or the like, and it is not necessary to particularly improve the heat resistance of the chip resistor, so that the manufacturing cost can be greatly reduced. In addition, since the electrodes of the chip resistor are roughened by including a plurality of types of glass materials having different softening points in the electrode paste, the roughening treatment can be performed in the electrode forming step.

本発明のチップ抵抗器によれば、粗面化処理された電極の表面を露出させてあり、該電極の露出面に対する導電性接着剤の接着強度を大幅に高めることができる。そのため、このチップ抵抗器は半田を使用せずに導電性接着剤を用いて回路基板上にフェースダウン実装することができ、チップ抵抗器の電極と導電性接着剤との導通信頼性も良好となる。また、このチップ抵抗器には電極を覆うメッキ層や外部電極等が不要であり、チップ抵抗器の耐熱性を特に高める必要もないため、製造コストを大幅に低減することができる。   According to the chip resistor of the present invention, the surface of the roughened electrode is exposed, and the adhesive strength of the conductive adhesive to the exposed surface of the electrode can be greatly increased. Therefore, this chip resistor can be mounted face-down on a circuit board using a conductive adhesive without using solder, and the conduction reliability between the electrode of the chip resistor and the conductive adhesive is also good. Become. Further, this chip resistor does not require a plating layer covering the electrode, an external electrode, or the like, and it is not necessary to particularly increase the heat resistance of the chip resistor, so that the manufacturing cost can be greatly reduced.

本発明のチップ抵抗器の製造方法によれば、チップ抵抗器の電極の表面を粗面化処理したうえで露出させておくので、該電極の露出面を導電性接着剤との接着強度を確保しやすい接着面として機能させることができる。そのため、こうして製造したチップ抵抗器は半田を使用せずに導電性接着剤を用いて回路基板上にフェースダウン実装することができ、チップ抵抗器の電極と導電性接着剤との導通信頼性も良好となる。また、こうして製造されるチップ抵抗器には電極を覆うメッキ層や外部電極等が不要であり、チップ抵抗器の耐熱性を特に高める必要もないため、製造コストを大幅に低減することができる。   According to the manufacturing method of the chip resistor of the present invention, the surface of the electrode of the chip resistor is exposed after being roughened, so that the exposed surface of the electrode is secured with a conductive adhesive. It can function as an easy-to-use adhesive surface. Therefore, the chip resistor manufactured in this way can be mounted face-down on the circuit board using a conductive adhesive without using solder, and the conduction reliability between the electrode of the chip resistor and the conductive adhesive is also improved. It becomes good. In addition, the chip resistor manufactured in this way does not require a plating layer covering the electrode, an external electrode, or the like, and it is not necessary to particularly improve the heat resistance of the chip resistor, so that the manufacturing cost can be greatly reduced.

本発明の第1の実施形態に係るチップ抵抗器の平面図である。It is a top view of the chip resistor concerning a 1st embodiment of the present invention. 図1に示すチップ抵抗器をフェースダウン実装した状態を示す断面図である。It is sectional drawing which shows the state which mounted the chip resistor shown in FIG. 1 face down. 図1に示すチップ抵抗器の製造過程で大判基板に電極を形成した状態を示す工程図である。It is process drawing which shows the state which formed the electrode in the large format board | substrate in the manufacture process of the chip resistor shown in FIG. 図1に示すチップ抵抗器の製造過程で大判基板に抵抗体を形成した状態を示す工程図である。It is process drawing which shows the state which formed the resistor in the large format board | substrate in the manufacture process of the chip resistor shown in FIG. 図1に示すチップ抵抗器の製造過程で抵抗体を覆う保護膜を形成した状態を示す工程図である。It is process drawing which shows the state which formed the protective film which covers a resistor in the manufacture process of the chip resistor shown in FIG. 本発明の第2の実施形態に係るチップ抵抗器の断面図である。It is sectional drawing of the chip resistor which concerns on the 2nd Embodiment of this invention. 本発明の第3の実施形態に係るチップ抵抗器の断面図である。It is sectional drawing of the chip resistor which concerns on the 3rd Embodiment of this invention.

以下、本発明の実施形態について図面を参照しながら説明する。まず、図1と図2に基づいて本発明の第1の実施形態に係るチップ抵抗器について説明する。また、図3〜図5を参照しながら、このチップ抵抗器の製造方法について説明する。   Hereinafter, embodiments of the present invention will be described with reference to the drawings. First, a chip resistor according to a first embodiment of the present invention will be described with reference to FIGS. Further, a manufacturing method of this chip resistor will be described with reference to FIGS.

図1と図2に示すチップ抵抗器1は、直方体形状の絶縁性基板2と、絶縁性基板2の片面2aの中央部に帯状に設けられた抵抗体3と、絶縁性基板2の片面2aの長手方向両端寄りの領域に設けられて抵抗体3の長手方向両端部に重なり合う一対の電極5と、これら両電極5どうしの間に露出する抵抗体3を被覆する保護膜4とによって主に構成されており、各電極5の表面が露出している。図2に示すように、このチップ抵抗器1は、絶縁性基板2の片面2a側を回路基板10に対向させてフェースダウン実装され、回路基板10上に設けられた配線パターン11とチップ抵抗器1の各電極5とが導電性接着剤12によって電気的かつ機械的に接続されるようになっている。つまり、各電極5の露出面を導電性接着剤12に対する接着面となすことにより、チップ抵抗器1をフェースダウン実装できるように設計されている。そのため、この電極5の表面(露出面を含む)は、少なくとも絶縁性基板2の表面よりも粗くなるように粗面化処理されている。   A chip resistor 1 shown in FIGS. 1 and 2 includes a rectangular parallelepiped insulating substrate 2, a resistor 3 provided in a strip shape at the center of one surface 2a of the insulating substrate 2, and one surface 2a of the insulating substrate 2. And a protective film 4 that covers the resistor 3 exposed between the electrodes 5 and a pair of electrodes 5 that are provided in a region near both ends in the longitudinal direction of the resistor 3 and that overlaps both ends in the longitudinal direction of the resistor 3. The surface of each electrode 5 is exposed. As shown in FIG. 2, the chip resistor 1 is mounted face-down with one side 2 a of the insulating substrate 2 facing the circuit board 10, and a wiring pattern 11 provided on the circuit board 10 and the chip resistor. Each electrode 5 is electrically and mechanically connected by a conductive adhesive 12. That is, the chip resistor 1 is designed to be face-down mounted by making the exposed surface of each electrode 5 an adhesive surface with respect to the conductive adhesive 12. Therefore, the surface of the electrode 5 (including the exposed surface) is roughened so that it is at least rougher than the surface of the insulating substrate 2.

チップ抵抗器1の構成について詳しく説明すると、絶縁性基板2は例えばアルミナ基板である。抵抗体3は酸化ルテニウム等からなり、保護膜4はエポキシ系等の樹脂材料からなる。また、図示していないが、抵抗体3と保護膜4との間に薄いガラスコート層が設けられており、抵抗体3とこれを覆うガラスコート層に抵抗値調整用の図示せぬトリミング溝が形成されている。電極5はAg系の導電材料(AgやAg/Pd等)からなる。この電極5は抵抗体3側の一辺端部が抵抗体3や保護膜4によって覆われているが、電極5の大部分は露出しており、この露出した部分の周壁は絶縁性基板2の片面2aの非印刷領域に包囲されている。つまり、電極5は絶縁性基板2の片面2aの外縁から離れた領域に設けられている。また、この電極5は製造段階で表面にブラスト加工が施されているため、図2に示すように、電極5の全表面は粗面化されて微細な凹部5aが多数形成されている。ただし、図2では電極5の粗面化された状態を誇張して図示している。   The structure of the chip resistor 1 will be described in detail. The insulating substrate 2 is, for example, an alumina substrate. The resistor 3 is made of ruthenium oxide or the like, and the protective film 4 is made of an epoxy resin or the like. Although not shown, a thin glass coat layer is provided between the resistor 3 and the protective film 4, and a trimming groove (not shown) for adjusting the resistance value is formed in the resistor 3 and the glass coat layer covering the resistor 3. Is formed. The electrode 5 is made of an Ag-based conductive material (Ag, Ag / Pd, or the like). The electrode 5 is covered with the resistor 3 and the protective film 4 at one end portion on the resistor 3 side, but most of the electrode 5 is exposed, and the peripheral wall of the exposed portion is the insulating substrate 2. It is surrounded by a non-printing area on one side 2a. That is, the electrode 5 is provided in a region away from the outer edge of the one surface 2 a of the insulating substrate 2. Further, since the surface of the electrode 5 is blasted at the manufacturing stage, the entire surface of the electrode 5 is roughened to form a large number of fine recesses 5a as shown in FIG. However, in FIG. 2, the roughened state of the electrode 5 is exaggerated.

次に、このように構成されたチップ抵抗器1の製造方法について説明する。まず、図3に示すように、絶縁性基板2の集合体である大判基板20の所定位置に電極ペーストを厚膜印刷して焼成することにより、多数の電極5を形成する。この電極ペーストはAg系の導電材料やガラス材等を含有する公知のものである。また、大判基板20には予め格子状に延びる分割溝21が形成されており、各電極5は分割溝21の近傍領域に分割溝21に沿って形成する。   Next, a manufacturing method of the chip resistor 1 configured as described above will be described. First, as shown in FIG. 3, a large number of electrodes 5 are formed by printing and baking an electrode paste on a predetermined position of a large-sized substrate 20 that is an aggregate of insulating substrates 2. This electrode paste is a known one containing an Ag-based conductive material, a glass material, or the like. In addition, the large substrate 20 is formed with division grooves 21 extending in a lattice shape in advance, and each electrode 5 is formed along the division grooves 21 in a region near the division grooves 21.

次なる工程として、各電極5に対してサンドブラスト等のブラスト加工を行うことにより、各電極5の表面を粗面化処理する。この後、図4に示すように、所定間隔を存して並設されている電極5どうしを橋絡する帯状領域に、酸化ルテニウム等を含有した抵抗体ペーストを厚膜印刷して焼成することにより、多数の抵抗体3を形成する。これにより、各電極5は、一辺端部が抵抗体3と重なり合って該抵抗体3と導通される。   As the next step, the surface of each electrode 5 is roughened by performing blasting such as sand blasting on each electrode 5. Thereafter, as shown in FIG. 4, a resistor paste containing ruthenium oxide or the like is printed in a thick film and fired in a band-like region that bridges the electrodes 5 arranged in parallel at a predetermined interval. Thus, a large number of resistors 3 are formed. As a result, each electrode 5 is electrically connected to the resistor 3 with one end thereof overlapping the resistor 3.

次なる工程として、各抵抗体3を覆う領域にそれぞれガラスペーストを印刷して焼成することにより、多数の前記ガラスコート層を形成する。そして、各ガラスコート層にレーザを照射して各抵抗体3の一部に前記トリミング溝を形成することにより、抵抗値の調整を行う。   As the next step, a large number of glass coat layers are formed by printing and baking a glass paste on the regions covering the respective resistors 3. Then, the resistance value is adjusted by irradiating each glass coat layer with a laser to form the trimming groove in a part of each resistor 3.

しかる後、図5に示すように、列状に並ぶ複数の前記ガラスコート層を前記トリミング溝を含めて覆う帯状領域に、エポキシ系等の樹脂ペーストを厚膜印刷して焼成することにより、保護膜4の連続体を形成する。チップ抵抗器1の保護膜4は、この連続体を分割したものである。すなわち、次なる工程として、大判基板20を縦横の分割溝21に沿って分割することにより、大判基板20が多数の絶縁性基板2に分割されるため、個片化された多数のチップ抵抗器1が一括して得られる。   After that, as shown in FIG. 5, protection is provided by printing a thick film of epoxy-based resin paste on the strip-shaped region covering the plurality of glass coat layers arranged in a row including the trimming grooves, and baking it. A continuum of film 4 is formed. The protective film 4 of the chip resistor 1 is obtained by dividing this continuous body. That is, as the next step, the large substrate 20 is divided into a large number of insulating substrates 2 by dividing the large substrate 20 along the vertical and horizontal dividing grooves 21, so that a large number of chip resistors separated into individual pieces. 1 is obtained collectively.

このようにして製造されたチップ抵抗器1は、ブラスト加工によって粗面化された電極5の表面に微細な凹部5aが多数形成されており、これら凹部5aが電極5の表面積を増やしている。そして、この粗面化された電極5の表面の大部分を露出させてあるので、該電極5の露出面を導電性接着剤12との接着強度を確保しやすい接着面として機能させることができる。それゆえ、図2に示すように、このチップ抵抗器1は、導電性接着剤12を用いて回路基板10上にフェースダウン実装することができる。   The chip resistor 1 manufactured in this way has a large number of fine recesses 5 a formed on the surface of the electrode 5 roughened by blasting, and these recesses 5 a increase the surface area of the electrode 5. Since most of the roughened surface of the electrode 5 is exposed, the exposed surface of the electrode 5 can function as an adhesive surface that can easily secure the adhesive strength with the conductive adhesive 12. . Therefore, as shown in FIG. 2, the chip resistor 1 can be mounted face-down on the circuit board 10 using the conductive adhesive 12.

具体的には、回路基板10の所定の配線パターン11上に導電性接着剤12を塗布した後、チップ抵抗器1の片面2a側を回路基板10に対向させて各電極5を対応する配線パターン11上に搭載する。これにより、導電性接着剤12が電極5の露出面の凹部5a内に入り込むため、該電極5の露出面に対する導電性接着剤12の接触面積は十分に確保できて密着度も良好となる。また、電極5の露出した部分の周壁が絶縁性基板2の片面2aの非印刷領域で包囲されているため、該周壁すべてに導電性接着剤12が付着しやすくなって、電極5の露出面を導電性接着剤12で確実に覆うことができる。したがって、この導電性接着剤12を100〜200℃程度で加熱して硬化させることにより、チップ抵抗器1を回路基板10上に確実にフェースダウン実装することができる。   Specifically, after applying a conductive adhesive 12 on a predetermined wiring pattern 11 on the circuit board 10, the wiring pattern corresponding to each electrode 5 is arranged with the one side 2 a side of the chip resistor 1 facing the circuit board 10. 11 is mounted. Thereby, since the conductive adhesive 12 enters the recess 5a of the exposed surface of the electrode 5, a sufficient contact area of the conductive adhesive 12 with respect to the exposed surface of the electrode 5 can be ensured, and the adhesion degree is also good. Moreover, since the peripheral wall of the exposed part of the electrode 5 is surrounded by the non-printing region of the one surface 2a of the insulating substrate 2, the conductive adhesive 12 is easily attached to all the peripheral wall, and the exposed surface of the electrode 5 Can be reliably covered with the conductive adhesive 12. Therefore, the chip resistor 1 can be reliably face-down mounted on the circuit board 10 by heating and curing the conductive adhesive 12 at about 100 to 200 ° C.

以上説明したように、本実施形態に係るチップ抵抗器1は、粗面化処理(ブラスト加工)によって電極5の露出面に微細な凹部5aが多数形成されており、該電極5の露出面の表面積も凹部5aの存在で広くなっているため、電極5の露出面に対する導電性接着剤12の接着強度を大幅に高めることができる。それゆえ、このチップ抵抗器1は半田を使用せずに導電性接着剤12を用いて回路基板10上にフェースダウン実装することができ、チップ抵抗器1の電極5と導電性接着剤12との導通信頼性も良好となる。また、このチップ抵抗器1には電極5を覆うメッキ層や外部電極等が不要であり、チップ抵抗器1の耐熱性を特に高める必要もないため、製造コストを大幅に低減することができる。   As described above, the chip resistor 1 according to this embodiment has a number of fine recesses 5a formed on the exposed surface of the electrode 5 by the roughening process (blasting). Since the surface area is also wide due to the presence of the recess 5a, the adhesive strength of the conductive adhesive 12 to the exposed surface of the electrode 5 can be significantly increased. Therefore, the chip resistor 1 can be mounted face-down on the circuit board 10 using the conductive adhesive 12 without using solder, and the electrode 5 of the chip resistor 1 and the conductive adhesive 12 The conduction reliability is also improved. Further, the chip resistor 1 does not require a plating layer covering the electrode 5, an external electrode, or the like, and it is not necessary to particularly improve the heat resistance of the chip resistor 1, so that the manufacturing cost can be greatly reduced.

また、本実施形態に係るチップ抵抗器1は、絶縁性基板2の片面2aの外縁から離れた領域に電極5が設けられており、フェースダウン実装に際して電極5の露出面を導電性接着剤12で確実に覆うことができるため、電極5の酸化や硫化を防止できて安定した性能が維持しやすくなっている。しかも、このように電極5が絶縁性基板2の稜線(外形線)から離隔させてあるチップ抵抗器1は、その製造過程で大判基板20の分割溝21に電極5がオーバーラップしないため、分割作業時の作業性が向上して製造歩留まりも高めやすい。   In the chip resistor 1 according to this embodiment, the electrode 5 is provided in a region away from the outer edge of the one surface 2a of the insulating substrate 2, and the exposed surface of the electrode 5 is electrically conductive adhesive 12 when face-down mounting. Therefore, it is possible to prevent the electrode 5 from being oxidized or sulfided and to maintain stable performance. In addition, the chip resistor 1 in which the electrode 5 is separated from the ridge line (outline) of the insulating substrate 2 in this way is divided because the electrode 5 does not overlap the dividing groove 21 of the large substrate 20 in the manufacturing process. The workability during work is improved and the manufacturing yield is easily increased.

また、本実施形態においては、チップ抵抗器1を製造する際に、大判基板20の状態で多数の電極5の表面にブラスト加工を施して粗面化するので、短時間に効率よく粗面化処理を行うことができる。   In the present embodiment, when the chip resistor 1 is manufactured, the surface of the large number of electrodes 5 is blasted and roughened in the state of the large-sized substrate 20, so that the roughening can be efficiently performed in a short time. Processing can be performed.

ただし、チップ抵抗器1の電極5を粗面化処理するために他の手法を採用してもよい。例えば、軟化点の異なる複数種類のガラス材(ビスマス系ガラス等)を電極ペーストに含有させることによっても電極5を粗面化処理することが可能であり、この手法を採用すると、電極5の形成工程でその露出面を粗面化することができるため、電極5の形成後に粗面化処理を別途行う工程を省略できる。その一例としては、軟化点が400℃、600℃、700℃の3種類のガラス材を混合して電極ペーストに含有させればよい。また、別の手法として、粒径の異なる複数種類の金属粉末(Ag/Pd等)を電極ペーストに含有させることによっても電極5を粗面化することが可能であり、その一例としては、粒径1μm以下の金属粉末と粒径10μm程度の金属粉末を同量ずつ混合して電極ペーストに含有させればよい。   However, another method may be employed to roughen the electrode 5 of the chip resistor 1. For example, it is possible to roughen the electrode 5 by incorporating a plurality of types of glass materials (bismuth glass or the like) having different softening points into the electrode paste. Since the exposed surface can be roughened in the step, a step of separately performing the roughening treatment after the formation of the electrode 5 can be omitted. For example, three kinds of glass materials having softening points of 400 ° C., 600 ° C., and 700 ° C. may be mixed and contained in the electrode paste. Further, as another method, the electrode 5 can be roughened by including a plurality of types of metal powders (Ag / Pd, etc.) having different particle sizes in the electrode paste. A metal powder having a diameter of 1 μm or less and a metal powder having a particle diameter of about 10 μm may be mixed in the same amount and contained in the electrode paste.

また、本実施形態においては、チップ抵抗器1の製造過程で電極5の全表面を粗面化した後に抵抗体3や保護膜4を印刷形成するので、抵抗体3用の抵抗ペーストや保護膜4用の樹脂ペーストの液ダレが電極5の微細な凹部5aによって抑制される。それゆえ、抵抗体3や保護膜4を高い位置精度で印刷できるという付加的な効果もある。   In the present embodiment, since the resistor 3 and the protective film 4 are printed after the entire surface of the electrode 5 is roughened in the manufacturing process of the chip resistor 1, the resistor paste or protective film for the resistor 3 is formed. The dripping of the resin paste for 4 is suppressed by the fine recesses 5 a of the electrode 5. Therefore, there is an additional effect that the resistor 3 and the protective film 4 can be printed with high positional accuracy.

なお、上記の実施形態では、チップ抵抗器1の電極5を絶縁性基板2上に1層だけ形成しているが、電極5を2層以上の積層構造にして厚膜を増やすことも可能であり、その場合は電極5の最上層の表面を粗面化処理すればよい。   In the above embodiment, only one layer of the electrode 5 of the chip resistor 1 is formed on the insulating substrate 2. However, it is possible to increase the thickness of the electrode 5 by forming a laminated structure of two or more layers. In this case, the surface of the uppermost layer of the electrode 5 may be roughened.

図6は本発明の第2の実施形態に係るチップ抵抗器を示しており、図1と図2と対応する部分には同一符号を付してある。図6に示すチップ抵抗器1には、絶縁性基板2の片面2aと逆側の裏面2bに磁性体からなる磁性層6が設けられており、それ以外の構成は前述した第1の実施形態と同様である。この磁性層6は、スパッタリングや無電解メッキ、印刷等の適宜手法で形成することができる。   FIG. 6 shows a chip resistor according to the second embodiment of the present invention, and portions corresponding to those in FIG. 1 and FIG. In the chip resistor 1 shown in FIG. 6, the magnetic layer 6 made of a magnetic material is provided on the back surface 2b opposite to the one surface 2a of the insulating substrate 2, and the other configuration is the first embodiment described above. It is the same. The magnetic layer 6 can be formed by an appropriate method such as sputtering, electroless plating, or printing.

この第2の実施形態のように、絶縁性基板2の裏面2bに磁性層6が設けられていると、チップ抵抗器1をテーピング包装する際や、チップ抵抗器1を回路基板10に自動マウントする際に、図示せぬ磁石で磁性層6を吸着することによってチップ抵抗器1の姿勢を安定させることができる。   When the magnetic layer 6 is provided on the back surface 2b of the insulating substrate 2 as in the second embodiment, the chip resistor 1 is automatically mounted on the circuit board 10 when the chip resistor 1 is taped and packaged. When doing so, the posture of the chip resistor 1 can be stabilized by attracting the magnetic layer 6 with a magnet (not shown).

図7は本発明の第3の実施形態に係るチップ抵抗器を示しており、図1と図2と対応する部分には同一符号を付してある。図7に示すチップ抵抗器1には、電極5の高さ位置を嵩上げするための絶縁層7が付設されていると共に、これら電極5と絶縁層7が絶縁性基板2の片面2aの外縁まで延びている。すなわち、絶縁性基板2の片面2aの長手方向両端部に絶縁層7が設けてあり、電極5は絶縁層7を覆うように設けられているため、電極5の露出面の高さ位置と保護膜4の表面の高さ位置とが略同等になっている。なお、絶縁層7は、電極5を形成する前に、エポキシ系等の樹脂ペーストを厚膜印刷して焼成することにより形成できる。   FIG. 7 shows a chip resistor according to the third embodiment of the present invention, and portions corresponding to those in FIGS. 1 and 2 are denoted by the same reference numerals. The chip resistor 1 shown in FIG. 7 is provided with an insulating layer 7 for raising the height position of the electrode 5, and the electrode 5 and the insulating layer 7 extend to the outer edge of the one surface 2 a of the insulating substrate 2. It extends. That is, since the insulating layer 7 is provided at both longitudinal ends of the one surface 2a of the insulating substrate 2 and the electrode 5 is provided so as to cover the insulating layer 7, the height position of the exposed surface of the electrode 5 and the protection are provided. The height position of the surface of the film 4 is substantially the same. The insulating layer 7 can be formed by thickly printing an epoxy-based resin paste and baking it before forming the electrode 5.

この第3の実施形態のように、絶縁層7を付設することによって、絶縁性基板2の抵抗体形成面である片面2aから電極5の露出面までの高さ寸法が、該片面2aから保護膜4の表面までの高さ寸法と同程度になるようにしてあると、フェースダウン実装したチップ抵抗器1が保護膜4を支点として傾く虞がなくなるため、実装後のチップ抵抗器1に上方から外力が作用してもクラック等を生じにくくなる。また、電極5や絶縁層7が絶縁性基板2の片面2aの外縁まで延びているチップ抵抗器1は、製造時に2個分の電極5や2個分の絶縁層7を大判基板の分割線上で連続させておくことができるため、これら電極5や絶縁層7の印刷を比較的容易に行うことができる。なお、電極5の高さ位置は絶縁層7の膜厚によって容易に嵩上げできるため、絶縁層7をさらに厚く形成して電極5が保護膜4の表面よりも若干高い位置に露出するようにしてもよい。   By providing the insulating layer 7 as in the third embodiment, the height dimension from the one surface 2a which is the resistor forming surface of the insulating substrate 2 to the exposed surface of the electrode 5 is protected from the one surface 2a. If the height of the film resistor 4 is approximately the same as the height of the film 4, the chip resistor 1 mounted face-down will not be inclined with the protective film 4 as a fulcrum. Even if an external force is applied, cracks and the like are less likely to occur. In addition, the chip resistor 1 in which the electrodes 5 and the insulating layer 7 extend to the outer edge of the one surface 2a of the insulating substrate 2 has two electrodes 5 and two insulating layers 7 on the dividing line of the large substrate at the time of manufacture. Therefore, printing of the electrodes 5 and the insulating layer 7 can be performed relatively easily. Since the height of the electrode 5 can be easily raised by the film thickness of the insulating layer 7, the insulating layer 7 is formed thicker so that the electrode 5 is exposed at a position slightly higher than the surface of the protective film 4. Also good.

1 チップ抵抗器
2 絶縁性基板
2a 片面
3 抵抗体
4 保護膜
5 電極
5a 凹部
6 磁性層
7 絶縁層
10 回路基板
11 配線パターン
12 導電性接着剤
20 大判基板
21 分割溝
DESCRIPTION OF SYMBOLS 1 Chip resistor 2 Insulating board | substrate 2a Single side | surface 3 Resistor 4 Protective film 5 Electrode 5a Recess 6 Magnetic layer 7 Insulating layer 10 Circuit board 11 Wiring pattern 12 Conductive adhesive 20 Large format board 21 Divided groove

Claims (5)

絶縁性基板の片面に、抵抗体と、この抵抗体の両端部に重なり合う一対の電極と、前記抵抗体を覆う保護膜とが設けられ、前記絶縁性基板の前記片面側を回路基板に対向させてフェースダウン実装されるチップ抵抗器において、
前記電極が前記絶縁性基板の前記片面の外縁から離れた領域に設けられており、前記電極の表面を露出させると共に、この露出面が少なくとも前記絶縁性基板の表面よりも粗くなるように粗面化処理されていることを特徴とするチップ抵抗器。
A resistor, a pair of electrodes overlapping both ends of the resistor, and a protective film covering the resistor are provided on one side of the insulating substrate, and the one side of the insulating substrate is opposed to the circuit board. In chip resistors mounted face down,
The electrode is provided in a region remote from the one side of the outer edge of the insulating substrate, Rutotomoni to expose the surface of the electrode, crude as the exposed surface is rougher than at least the surface of the insulating substrate A chip resistor that is surface-treated.
請求項1の記載において、前記絶縁性基板の前記片面から前記保護膜の表面までの高さ寸法に比べて、前記絶縁性基板の前記片面から前記電極の露出面までの高さ寸法が同等以上の大きさに設定されていることを特徴とするチップ抵抗器。   The height dimension from the one surface of the insulating substrate to the exposed surface of the electrode is equal to or greater than the height dimension from the one surface of the insulating substrate to the surface of the protective film. Chip resistor characterized by being set to the size of 請求項2の記載において、前記絶縁性基板の前記片面の両端部に絶縁層を設け、この絶縁層を覆うように前記電極が設けられていることを特徴とするチップ抵抗器。   3. The chip resistor according to claim 2, wherein an insulating layer is provided at both ends of the one surface of the insulating substrate, and the electrode is provided so as to cover the insulating layer. 請求項1〜のいずれか1項の記載において、前記絶縁性基板の前記片面と逆側の面に磁性体からなる磁性層が設けられていることを特徴とするチップ抵抗器。 In the description of any one of claims 1 to 3 chip resistor, wherein a magnetic layer made of a magnetic material to the surface of the one side and opposite side of the insulating substrate is provided. 絶縁性基板の片面に、抵抗体と、この抵抗体の両端部に重なり合う一対の電極と、前記抵抗体を覆う保護膜とが設けられ、前記絶縁性基板の前記片面側を回路基板に対向させてフェースダウン実装されるチップ抵抗器の製造方法において、A resistor, a pair of electrodes overlapping both ends of the resistor, and a protective film covering the resistor are provided on one side of the insulating substrate, and the one side of the insulating substrate is opposed to the circuit board. In the manufacturing method of the chip resistor to be face-down mounted,
前記絶縁性基板の前記片面に電極ペーストを厚膜印刷して前記電極を形成すると共に、軟化点の異なる複数種類のガラス材を前記電極ペーストに含有させることにより、前記電極の表面を少なくとも前記絶縁性基板の表面よりも粗くなるように粗面化処理したうえで露出させるようにしたことを特徴とするチップ抵抗器の製造方法。  The electrode paste is formed by thick film printing on one side of the insulating substrate to form the electrode, and a plurality of types of glass materials having different softening points are included in the electrode paste, whereby at least the surface of the electrode is insulated. A method of manufacturing a chip resistor, characterized by being exposed after being roughened so as to be rougher than the surface of the conductive substrate.
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