JP2016524819A - Transistor and transistor manufacturing method - Google Patents

Abstract

The present invention includes a support substrate, a first semiconductor layer deposited on the support substrate and made of a first semiconductor material, a second semiconductor layer deposited on the first semiconductor layer and made of a second semiconductor material, A drain terminal and a source terminal embedded in the second semiconductor layer; a channel region between the drain terminal and the source terminal; a gate terminal at least partially covering the channel region; and the opposite side of the drain terminal and the source terminal The present invention relates to a transistor having a recess disposed on a surface of a support substrate and at least partially overlapping a channel region. The band gap of the first semiconductor material is different from the band gap of the second semiconductor material. The drain terminal and the source terminal can be used for electrical contact connection to the boundary layer between the first semiconductor layer and the second semiconductor layer. Side edges and / or bottoms of the recesses are covered with an insulating layer.

Description

The present invention relates to a transistor and a method for manufacturing the transistor.

  A HEMT transistor (High-Electro-Mobility Transistor) is a special structural form of a field effect transistor characterized by a conductive channel with high charge carrier mobility. This channel is conventionally made by heteroepitaxially growing a suitable semiconductor on a substrate, such as silicon, where the heterostructure is as cost effective as possible.

  However, in this embodiment they generally have the disadvantage that a higher substrate leakage current is expected than in the case of an insulating substrate, for example a semi-insulating SiC substrate. Therefore, the presence of a leakage current path extending into the substrate through the GaN buffer layer is one of a number of factors that limit the performance of GaN power transistors on Si. This necessitates a “trade-off” of substrate doping.

  One solution to this problem is, for example, after manufacturing the transistor, in this structure, the substrate is removed locally under the active transistor region, thereby removing the substrate leakage current and thus the breakdown characteristics of the device. It has been proposed that it can be remarkably improved. However, this is done at the expense of various thermal properties in the proposed structure, and these thermal properties are greatly impaired in the proposed structure.

  US 2006/0099978 describes a method for producing gallium nitride films with low defect density by vapor phase epitaxy.

DISCLOSURE OF THE INVENTION Against this background, the present invention provides a transistor and a method of manufacturing the transistor as set forth in the independent claims. Advantageous embodiments are obtained from the dependent claims and the following description, respectively.

According to the invention, a transistor having the following characteristic configuration:
A support substrate;
A first semiconductor layer deposited on the support substrate and made of a first semiconductor material;
A second semiconductor layer deposited on the first semiconductor layer and made of a second semiconductor material, wherein the band gap of the first semiconductor material and the band gap of the second semiconductor material are different (so-called Heterostructure)
A drain terminal and a source terminal embedded in at least the second semiconductor layer, the drain terminal and the source terminal being used for at least one boundary layer between the first semiconductor material and the second semiconductor material; A drain terminal and a source terminal that are electrically contactable;
A channel region between the drain terminal and the source terminal;
A gate terminal that at least partially covers the channel region;
A recess disposed on the surface of the support substrate opposite to the drain terminal and / or the source terminal and at least partially overlapping the channel region, and the side edge of the recess is covered with an insulating layer. Thus, a transistor having a concave portion is obtained.

Furthermore, the present invention provides a method for manufacturing a transistor. The method consists of the following steps:
A step of preparing a support substrate;
Depositing a first semiconductor layer made of a first semiconductor material on a support substrate and depositing a second semiconductor layer made of a second semiconductor material on the first semiconductor layer, wherein A step in which the band gap is different from the band gap of the second semiconductor material;
A step of forming a drain terminal and a source terminal, the drain terminal and the source terminal being embedded in at least the second semiconductor layer, and using the drain terminal and the source terminal between the first semiconductor material and the second semiconductor material; Electrically contactable to at least one boundary layer (140), wherein a channel region between the drain terminal and the source terminal is defined by the drain terminal and the source terminal;
Placing a gate terminal that at least partially covers the channel region;
Providing a recess in a section of the support substrate at least partially overlapping the channel region on the surface of the support substrate opposite the drain terminal and / or source terminal, the edge of the recess being an insulating layer Covered by a step.

A support substrate can be understood as a layer made of only one material or a combination of material layers. The control region can be understood as the channel of a transistor, in particular a field effect transistor. Here, a transistor called a transistor can be understood to be, for example, a field effect transistor. A recess can be understood to be a recess or an opening in at least a portion of a support substrate or support substrate. The lateral edge of the recess can be understood as the lateral edge and / or the bottom of the recess covered by an insulating layer. The insulating layer can be understood as a layer made of, for example, SiO ₂ , Si ₃ N ₄ or AlN, and these insulating layers can be produced by passivation of the formed recesses.

  The approach shown here can reduce or even prevent the substrate leakage current by providing a recess with an insulating layer on the side of the support substrate opposite the gate electrode. Based on the knowledge that it is possible. This is because the concave portion having the insulating layer can make the region of the support substrate relatively thin, so that the leakage current passing through this relatively thin region of the support substrate is subjected to a larger resistance, and this resistance Leakage current is reduced or completely prevented. In particular, by providing an insulating layer disposed on the side edge of the recess, an insulating barrier against leakage current that is generally generated can be obtained.

  With the approach shown in the present invention, the electrical characteristics of the transistor can be remarkably improved by a structure that can be easily manufactured technically. By providing a recess with an insulating layer, at the same time, the possibility of thermal coupling, which can be accompanied by heat dissipation, is also obtained, so that a comparatively large amount of heat is expected to be generated in the transistor and this heat must be expelled accordingly. The possibility of using the transistor by the approach shown here is also possible for the switching of large power.

  Furthermore, an embodiment of the invention in which an insulating layer extends from the recess to the main surface of the support substrate on the side opposite to the gate terminal is preferable. Here, the insulating layer can also extend into the region of the support substrate that no longer has a recess. An advantage of such an embodiment of the invention is that the insulating layer can particularly reliably prevent or at least reduce leakage currents in such an arrangement.

  An embodiment of the invention is also conceivable in which the filling layer is arranged at least in the region of the recesses on the side of the insulating layer opposite the support substrate, where the filling layer is thermally and / or electrically conductive. Contains sex materials. Such materials can be deposited in the form of a film or layer to allow a flat junction to the insulating layer, through which it is technically easy to drain and / or supply current to the transistor elements. Will be possible. In such an embodiment of the invention, this filling layer provides the advantage of a particularly efficient heat sink and / or electrical contact connection.

  According to another embodiment of the invention, the filling layer comprises at least in the region of the recesses a metal material, in particular copper, polysilicon, in particular doped polysilicon, and / or SiC, in particular highly doped SiC. Can have. The advantages afforded by such embodiments of the present invention are particularly good material selections that have been found to be cost-effective, for example, over thermally conductive and / or conductive materials for packed beds. It is obtained.

  In order to ensure that the original electrical function of the transistor is not impaired too much, in one embodiment of the present invention, the recess has a predetermined depth, whereby the first semiconductor layer and the insulating layer A partial layer of the support substrate is disposed between them. Such a partial layer of the support substrate can comprise a uniform material, for example it can be a buffer layer, which consists of silicon dioxide, silicon nitride or aluminum nitride, or these Material at least partially.

  Embodiments of the present invention in which another support substrate is provided that covers the second semiconductor layer, the source terminal, the drain terminal and / or the gate terminal are particularly stable. Such an embodiment of the present invention provides the advantage that the reduction in the holding force of the support substrate caused by the recess in the support substrate can be compensated by the additional holding force of the other support substrate.

  According to another embodiment of the present invention, it is possible to provide another recess for discharging heat from the region of the terminal or for electrical contact connection. The another recess extends from the surface of the support substrate opposite to the gate terminal to the first or second semiconductor layer, and in particular, the another recess does not overlap the channel region. It is arranged in the section of. For example, this other recess can be arranged laterally alongside the drain or source terminal and outside the channel or channel region.

  In order to prevent leakage current from flowing laterally or laterally from the terminal to the opposite side of the channel region, according to another embodiment of the present invention, at least partially on the edge of another recess. An insulating layer or another insulating layer can be arranged. A recess or another implementation edge is, for example, the side wall and / or the bottom of this other recess with respect to the support substrate.

  In order to provide a particularly good conductive connection or to allow good heat dissipation by means of this further recess, according to another embodiment of the present invention, this further recess has said filling layer or another filling layer Place. These filling layers have a thermally conductive and / or conductive material, and in particular, the further filling layer is electrically connected to a source terminal, a drain terminal or a boundary layer.

  According to another embodiment of the invention, the first and second semiconductor materials can form a III / V compound semiconductor combination. The advantage afforded by such an embodiment of the present invention is a particularly good and very high electron mobility at the boundary between the first and second semiconductor materials. As a result, a transistor that switches at a particularly high speed can be realized.

  Furthermore, embodiments of the present invention in which the first semiconductor material contains AlGaN and the second semiconductor material contains GaN or the first semiconductor material GaN and the second semiconductor material contains AlGaN are advantageous. . The advantage obtained by such an embodiment of the present invention is that it is possible to use a semiconductor material that is particularly good and easy to process in the technology for the transistor, which in addition to good switching properties, is also very cost-effective. It can be manufactured.

  According to another embodiment of the invention, the support substrate can have a holding layer made of a holding material, which is different from the main material of the support substrate. Here, in particular, the main material of the support substrate has silicon, and the first semiconductor material is arranged in this holding layer. An advantage obtained by this embodiment of the present invention is that the formation of the retention layer can embody good and stable fixation of the first semiconductor material in the retention layer.

  According to a particularly advantageous embodiment of the invention, the gate terminal can be electrically isolated and separated from the channel region by a gate oxide layer or a gate dielectric layer, in particular here a gate oxide layer. Alternatively, at least one predetermined type of charge carrier is embedded in the gate dielectric layer, and / or the gate oxide layer or gate dielectric layer has a predetermined concentration of charge carriers. Such an embodiment of the present invention provides the advantage that the transistor output type can be set, and in particular the transistor can be characterized as normally off or normally on. Depending on the thickness of the gate oxide layer (gate dielectric layer) and / or a predetermined charge carrier concentration in the gate oxide layer (gate dielectric layer), the breakdown voltage or the activation voltage can be set.

  Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a cross-sectional view of a transistor according to an embodiment of the present invention. FIG. 3 is a diagram illustrating a cross-sectional view of a transistor according to an embodiment of the present invention at various manufacturing stages. It is sectional drawing of the transistor by another one Example of this invention. It is sectional drawing of the transistor by another one Example of this invention. It is sectional drawing of the transistor by another one Example of this invention. 3 is a flowchart of a method according to an embodiment of the present invention.

  In the following description of the preferred embodiment of the present invention, the same or similar reference numerals are used for elements that are shown in different drawings but have similar functions. A repeated description of these elements is omitted.

  FIG. 1 shows a cross-sectional view of a transistor 100 according to one embodiment of the present invention. The transistor 100 includes a semiconductor substrate or support substrate 110, which includes a main component 115 (for example, a silicon crystal having a 111 lattice structure) and a buffer deposited on the main component 115. Layer 120 is included. The buffer layer 120 can be composed of, for example, an aluminum nitride layer followed by a plurality of rows of AlGaN layers with a low concentration of Al, whereby the lattice structure of the layer to be deposited on the support substrate Is optimally adapted to. The buffer layer 120 is used as a very good adhesion base for the semiconductor heterostructure 125 disposed on the buffer layer 120.

  The semiconductor heterostructure 125 can be, for example, a stack of two layers of different semiconductor materials. For example, these different semiconductor materials can be composed of or include semiconductor materials with different band gaps or forbidden bands. The semiconductor material of the heterostructure 125 may be arranged as the first semiconductor layer 130 (made of the first semiconductor material) and as the second semiconductor layer 135 (made of the second semiconductor material) arranged in the first semiconductor layer. And can constitute a III-V semiconductor combination or a III-V semiconductor combination system. This means that the semiconductor material of the first semiconductor layer 130 can be a group III material (that is, a material belonging to the third typical element group of the periodic table), whereas the second semiconductor layer 135 The semiconductor material can be a group V material (that is, a material belonging to the fifth typical element group of the periodic table). The first semiconductor material may be a group V material, and the second semiconductor material may be a group III material. In particular, the first semiconductor material can be AlGaN and the second semiconductor material can be GaN (or correspondingly contain these materials) or vice versa.

  A boundary layer 140 is formed between these two semiconductor materials, in which electrons have a particularly high mobility. The boundary layer 140 acts as a two-dimensional electron gas (2DEG) and can perform very good switching for high power, i.e., high current and / or high voltage. A drain terminal 145 and a source terminal 150 are provided in order to make electrical contact connection to the boundary layer 140, and these terminals pass through the second semiconductor layer 135 to the boundary layer 140 to the first semiconductor layer. Has reached. A lateral insulating layer 153 is provided on the side of the drain terminal 145 to the source terminal 150, that is, toward the side opposite to the other terminal, and the insulating layer includes the drain terminal 145 and the source terminal. Electron outflow from the channel region 160 between 150 is prevented.

  A gate oxide layer 165 is further disposed on the surface 160 of the second semiconductor layer 135 as a gate dielectric. Since the gate terminal 170 is provided in the region of the channel region 155 on the gate oxide layer 165, the transistor 100 is configured as a field effect transistor. In this respect, the channel region 155 can be understood as a channel of a field effect transistor.

  In order to obtain a particularly good setting of the cutoff voltage of the transistor 100, the gate oxide layer 165 is "contaminated" or doped with charge carriers. Thereby, in the channel region 155 and / or the boundary layer 140, the influence of the voltage applied to the gate terminal 170 on the charge carrier mobility can be changed.

In order to prevent leakage current particularly well (for example, from the source terminal 150 to the drain terminal 145), the recess 180 can be disposed in the support substrate 110. The recess 180 is disposed or formed particularly in the main material 115 of the support substrate 110, and the buffer layer 120 remains between the first semiconductor layer 130 and the recess. The side walls or edges 182 and bottom 183 of the recess 180 are covered with an insulating layer 185 made of an electrically insulating material such as SiO ₂ , Si ₃ N ₄ or AlN. Further, the insulating layer 185 also extends over the main component 115 of the support substrate 110, that is, the main surface 186 of the main material, which does not include the recess 180. Thereby, particularly good electrical insulation can be obtained. Further, a filling layer 187 can be applied to the surface of the insulating layer opposite to the support substrate 110. This fill layer 187 can comprise or consist of a thermally and / or electrically conductive material such as, for example, copper, doped polysilicon or heavily doped SiC. . The filling layer 187 fills, for example, the recesses of the recesses 180 that remain even though the insulating layer 185 is provided, so that the insulating layer 185 has a bottom 183 and a plurality of edges of the recesses 180. 182 and the packed bed 187 are arranged in a sandwich shape.

  By providing the recess 180 and the insulating layer 185 on the edge 182 and the bottom 183 of the recess 180, leakage current passing through the support substrate 110 to a part of the support substrate 110 (for example, the main component 115) is completely prevented. If not, it can be reduced at least. To this end, a recess is disposed in at least a portion 190 of the support substrate 110 that at least partially overlaps the channel region 155. According to one embodiment, the insulating layer 185 is not made smaller than, for example, 0.1 μm in order to ensure sufficient electrical insulation. However, the insulating layer 185 should not have a thickness greater than 10 μm to ensure sufficiently high thermal conductivity through the insulating layer 185. Thus, heat generated during operation of the transistor 100 can be discharged through the support substrate 110, the insulating layer 185, and the filling layer 187. In this respect, the deposition of the insulating layer 185 shown in FIG. 1 and the filling of the trenches remaining after placing the recesses 180 to 185 with the thermally conductive and / or conductive (filled) layer 187 are as follows. It helps to improve the characteristics of the transistor 100 compared to the conventional transistor.

  In addition, the (optional) gate oxide layer 165 (which can also be configured as a gate dielectric), the drain terminal 150, the source terminal 145, and / or the gate terminal 170 may be protected by a protective layer 195. Is possible. The protective layer 195 can be formed as a protective paint, for example. A protective layer 195 can be applied directly to the gate oxide layer 165 and the gate terminal 170 and can cover these elements. Thus, the surface of the transistor 100 to the transistor 100 can be reliably protected from damage or the effect of the surrounding environment.

The structure described above for transistor 100 can be referred to as a standard HEMT structure with a gate dielectric. Viewed from the structure, this HEMT transistor is composed of layers of different semiconductor materials having different band gaps (so-called heterostructures). For this purpose, in particular, compound semiconductors composed of III / V group elements of the periodic table are targeted. For example, the material system GaN / AlGaN can be used. When these materials are separated from each other, a two-dimensional electron gas is formed that can be used as a conductive channel on both sides of the GaN at the interface of these materials. This is because the electron mobility is extremely high here (generally 2000 cm ² / Vs).

  Such a GaN HEMT transistor can be manufactured by epitaxially growing a GaN / AlGaN heterostructure on a Si, SiC or sapphire substrate. These elements are always normally on due to the presence of highly conductive channels. However, in many application fields, for example, in the automobile field, normally-off type elements are desired from the viewpoint of safety and switching. In order to implement a normally-off GaN device, it is therefore necessary to locally destroy the 2DEG in the boundary layer 140 by an appropriate method in the channel region. For example, it seems that several methods have already been successful, such as locally thinning the AlGaN barrier, implanting phosphors, or inversion channel devices, but these generally have significant performance degradation and / or There is a problem with reliability. The approach presented here deals with this problem and proposes a structure that allows the realization of a GaN-based high performance normally-off transistor.

  Furthermore, in the GaN / HEMT transistor, the Si substrate, the SiC substrate, or the sapphire substrate. In addition to this, Si becomes mechanically uneasy at a general growth temperature (1000 to 1200 ° C.) for GaN. . Thus, for the above growth, a doped Si (111) substrate is advantageously selected due to the relatively good mechanical and thermal properties.

  In particular, in the present invention, an approach to a manufacturing method is also proposed. By this approach, charge carriers can be put into the gate dielectric 165 as expected, and thereby, a cut-off voltage of the GaN / HEMT is set. By doing so, a normally-off type element having a plurality of advantages over the conventional concept can be realized by a simple method.

  With the approach proposed here, for example, in a GaN / AlGaN material system, a device in which charge carriers move along the two-dimensional heterostructure interface 140 can be produced. The heterostructure 125 can be contacted laterally by a source terminal 150 and a drain terminal 145, and the channel region 155 between the source 155 and the drain 145 is controlled by the gate electrode 170. The gate electrode 170 is separated from the channel region 155 by the gate dielectric 165, and stable charge carriers that set the cut-off voltage of the transistor 100 can be placed in the gate electrode as desired.

  One approach of such a method for device fabrication may have the following steps described in detail in connection with FIG. 2A. First, the buffer layer 120 and the GaN / AlGaN heterostructure 125 can be deposited on the main component 115 of the support substrate 110. This deposition can be performed by depositing the MOCVD GaN / GaN layer 125 on the heavily doped Si (111) substrate which is the main component 115. GaN / AlGaN heterostructure 125, first semiconductor layer 130 made of, for example, GaN or made of a first semiconductor material containing this material, and second semiconductor made of, for example, AlGaN, or made of a second semiconductor material containing this material A boundary layer 140 can be formed by the layer 135, and this boundary layer has a so-called two-dimensional electron gas, and the two-dimensional electron gas provides very good conductivity of the element to be manufactured, that is, the transistor 100. be able to.

  Thereafter, as shown in FIG. 2B, lateral element isolation in the region 153 can be performed. This separation can be performed, for example, by ion implantation in the lateral separation layer 153 of the transistor 100 in FIG. This is followed by an optional deposition of gate dielectric 165 that can contain charge carriers as desired. These charge carriers shift the electrical properties of the HEMT transistor 100 according to polarity, surface concentration, and distribution. In particular, a normally-off element can be manufactured as the transistor 100, for example. Subsequently, the gate electrode 170 can be deposited and structured, after which the 2DEG (ie, boundary layer 140) contact connection by the source terminal 150 and the drain terminal 145 is made. In this regard, the cross-sectional view of FIG. 2B shows a semi-finished product that allows standard HEMT manufacturing by lateral separation by implantation, optimal gate dielectric, and deposition of substrate leakage current paths. To do.

  With the approach presented here, it is possible to improve the yield characteristics, where this improvement is embodied, for example, by preventing (or at least reducing) the leakage current (of the substrate) that would otherwise occur. Is done. At the same time, improved thermal characteristics and additional functions can be realized as compared to conventional GaN devices.

  Here, in order to keep the leakage current 200 as small as possible or completely blocked, here, as shown in FIG. 2C, the front side of the transistor prepared according to the above steps (ie, the side where the gate electrode 170 is located). First, a protective layer 195, for example, a protective layer made of a protective coating is applied. Thereafter, the support substrate 110 is thinned, and the support substrate 110 or a part of the support substrate 110 is locally removed. Here, this portion corresponds to the main component 115 of the support substrate 110 in the portion 190 below the active transistor region, ie below the channel region 155. This means that the recess 180 in the support substrate is obtained by removing the main component 115 in the portion 190, where the portion 190 at least partially overlaps the channel region 155.

  Subsequently, an insulating layer is deposited on the edge 182 and bottom 183 of the recess 180, whereby the transistor 100 shown in FIG. 1 is obtained.

In order to better align the local removal during the process and to obtain better mechanical stability, an alternative process for preparing the manufacture of the transistor 100 can be performed. Here, according to FIG. 3, first, a mesa etching step is performed on the front surface (that is, the surface on which the gate terminal 170 is disposed) to form a trench 300 (or trench) on or from the front surface of the transistor 100. Make it. The trench 310 penetrates from the gate oxide layer 165 to the main component 115 of the support substrate 110 and constitutes an opening of the support substrate 110 to the entire transistor 100. Subsequently, a passivation layer 310 is deposited on the front surface of the transistor 100 on the front surface of the transistor 100. This passivation layer is made of SiO ₂ or contains SiO ₂ at least partially. Here, another support substrate 320 is adhered to the passivation layer 310, which stabilizes the transistor 100 against subsequent manufacturing steps. The trench 300 can be used for electrical and / or thermal contact connection of the drain terminal 150 from the rear surface (ie, the surface on which the main component 115 of the support substrate 110 is disposed). This will be described in more detail later.

  If the recess 180 is provided in the structure prepared as described above according to FIG. 3, and then the insulating layer 185 and the filling layer 187 are deposited, the transistor 100 corresponding to FIG. 4 can be realized. Here, the trench 300 in which the insulating layer 185 is disposed at the edge and the bottom (that is, the boundary with the passivation layer 310) itself and is filled with the filling layer 187, causes the drain terminal 150 from the rear surface of the transistor 100. Thermal bonding is performed. Accordingly, the structure of the front side of the transistor 100 is deposited by depositing the insulating layer 185 and filling the (remaining) trench 300 with a filling layer 18, ie a thermally and / or electrically conductive layer such as copper. Thermal and / or electrical contact connections can be made. Thus, the trench 300 can be considered as another recess (similar to the recess 180). However, this other recess is made from the front surface of the transistor 100, unlike the recess 180 from the rear surface of the transistor 100. However, this does not matter for the function of the other recess 300.

  This additional recess 300 not only allows contact connection of the drain terminal 150, as shown in FIG. 4, but rather, by properly selecting the location of the trench 300 in the transistor 100 through the support substrate 110, almost all Any structure or any terminal, such as gate terminal 170 and / or source terminal 145, can also be thermally and / or electrically contacted by trench 300 filled as described above. However, it should be noted when making electrical contact connections that the insulating layer 185 has a corresponding opening or at least electrically transmissive, so that, for example, the drain terminal 150 is connected to the rear surface of the transistor 100. It is also possible to contact contact from. Therefore, the filling layer can be used as an optional back gate electrode or back drain electrode.

  An embodiment in which the insulating layer 185 is not deposited on the trench 300 or another recess 300 is also conceivable. Such an embodiment is shown in cross-section in FIG. In this case, by omitting the insulating layer 185 in the other recess 300, for example, the electrical material of the terminal such as the drain terminal 150 is formed by the conductive material of the filling layer 187 (arranged in the other recess 300). Contact connection is possible. A particularly good thermal contact connection of the structure on the front side of the transistor 100 can also be made from the rear side.

  Therefore, according to another embodiment shown in FIG. 5 of the present invention, the insulating layer 185 is opened in another recessed portion 300 on the lower side of the source terminal 150 (or the deposition of the insulating layer 185 is omitted). This makes it possible to use a filler layer 187 (eg, containing metal) (eg, containing copper or made of copper) as a source electrode from the rear surface of the transistor 100. This allows the transistor 100 to be embodied as a vertical element, which allows the option of contact connection through a support substrate.

  In summary, it can be seen that the yield characteristics can be significantly improved and the reliability of the GaN power transistor can be improved by the manufacturing methods shown in the different embodiments. Furthermore, the manufacturing methods shown here in the different embodiments allow for improved thermal properties and additional functions.

  In particular, some aspects of the embodiments of the transistor 100 shown here will be pointed out. In particular, the transistor 100 can be provided as an element having a feature that charge carriers move along a two-dimensional heterostructure interface in, for example, a GaN / AlGaN material system. Further, the heterostructure can be contact-connected from the side by the source terminal 145 and the drain terminal 150, and the channel region 155 between the source terminal 145 and the drain terminal 150 is controlled by the gate electrode 170. After the pre-stage of the transistor is fabricated, the (support) substrate 110 can be thinned by anisotropic ion etching to remove the back of the active transistor region. The resulting holes 300 or 180 (forming recesses) are filled, for example, with a metal with high thermal conductivity, for example coated with copper, using electroplating or electroplating, optionally with additional electrodes Used as.

  In another embodiment, a second etching process is used to contact the drain metallization from the back surface (ie, from the back surface of the support substrate 110). This allows source or drain metallization to be placed on the rear surface of the chip or transistor 100, advantageously in construction and connection technology, thereby saving area and enabling better heat removal or heat dissipation. .

According to one embodiment, the present invention also describes a method for manufacturing a device, in particular a transistor, according to the embodiment described herein. This method comprises, for example, the following steps:
Providing a substrate having a GaN / AlGaN heterostructure;
Making a HEMT with a source terminal / drain terminal / gate terminal with an optional gate dielectric;
Applying a protective layer, for example a protective paint;
-Thinning the substrate from the back, for example by dry etching;
Removing the silicon substrate from the back side under the active transistor region;
Depositing (matching) an insulating layer having a thickness between 0.1 μm and 10 μm in the trench, for example using CVD or sputtering, where, for example, AlN having a high thermal conductivity is deposited Depositable steps,
Filling the trench with a metal layer, for example with copper deposition by electroplating, in an alternative implementation, for example, a highly doped amorphous SiC can be deposited, for example by PECVD; ,
And a step of contacting and packaging the front and rear surfaces.

  The approach presented here has several advantages. For example, a compromise between substrate doping for a sufficiently simple epitaxy process and a small substrate leakage current can be avoided. As a result, the breakdown voltage of the element can be increased, and as a result, the same epitaxy thickness can be maintained and the reliability can be increased. Furthermore, the possibility of reducing costs can be obtained. This is because a high breakdown voltage is generally obtained only by providing a thick and expensive GaN buffer layer. Here, when a rear space filled with metal is used simultaneously as an additional electrode (back gate), an additional function can be realized (for example, setting of a cutoff voltage). Thereby, for example, a normally-on element can be operated as a normally-off element, which is a great advantage in many applications. Furthermore, the thermal characteristics can be improved thanks to the heat sink under the active transistor region. The alternative embodiments shown in FIGS. 3 and 4 can also provide the possibility of implementing vertical transistors at the same time and therefore area-efficient vertical transistors with comparable processing costs. Finally, the proposed structure makes it possible to implement a multiple, in particular periodic arrangement, which makes it possible to produce elements with a large current load capacity.

  The approach presented here further enables a method 600 for manufacturing a transistor, where the method 600 comprises a step 610 of preparing a support substrate. The method 600 further includes depositing a first semiconductor layer 130 of a first semiconductor material on the support substrate 110 and depositing a second semiconductor layer 135 of a second semiconductor material on the first semiconductor layer. Here, the band gap of the first semiconductor material is different from the band gap of the second semiconductor material. The method 600 includes a step 630 of forming a drain terminal 145 and a source terminal 150 that are embedded in the second semiconductor layer 135 and using the drain terminal 145 and the source terminal 150 to form the first semiconductor. A channel region between the drain terminal 145 and the source terminal 150 is electrically connectable to at least one boundary layer 140 between the material and the second semiconductor material, and the drain terminal 145 and the source terminal 150 155 is defined. The method 600 further includes a step 640 of placing a gate terminal 170 that at least partially covers the channel region 155. Finally, the method 600 includes providing a recess 180 in a section of the support substrate 110 that at least partially overlaps the channel region 155 on the surface of the support substrate 100 opposite the drain terminal 145 and / or the source terminal 150. 650 is included, where the edge of the recess is covered by an insulating layer.

  The embodiments described above and shown in the drawings are merely exemplary selections. Different embodiments can be combined with each other completely or for individual characteristic configurations. It is also possible to supplement one embodiment with the characteristic configuration of another embodiment.

  Furthermore, the steps according to the invention can be performed repeatedly and in an order different from the order described above.

  If an example includes a “and / or” combination word between the first characteristic configuration and the second characteristic configuration, this means that the example, in one embodiment, And the second characteristic configuration, and in another embodiment, should be interpreted as having either the first characteristic configuration or the second characteristic configuration.

In order to prevent leakage current from flowing laterally or laterally from the terminal to the opposite side of the channel region, according to another embodiment of the present invention, at least partially on the edge of another recess. An insulating layer or another insulating layer can be arranged. The edge of a recess or another recess is, for example, the side wall and / or the bottom of this other recess with respect to the support substrate.

In order to better align the local removal during the process and to obtain better mechanical stability, an alternative process for preparing the manufacture of the transistor 100 can be performed. Here, according to FIG. 3, first, a mesa etching step is performed on the front surface (that is, the surface on which the gate terminal 170 is disposed) to form a trench 300 (or trench) on or from the front surface of the transistor 100. Make it. The trench 300 penetrates from the gate oxide layer 165 to the main component 115 of the support substrate 110, and constitutes an opening of the support substrate 110 to the entire transistor 100. Subsequently, a passivation layer 310 is deposited on the front surface of the transistor 100 on the front surface of the transistor 100. This passivation layer is made of SiO ₂ or contains SiO ₂ at least partially. Here, another support substrate 320 is adhered to the passivation layer 310, which stabilizes the transistor 100 against subsequent manufacturing steps. The trench 300 can be used for electrical and / or thermal contact connection of the drain terminal 150 from the rear surface (ie, the surface on which the main component 115 of the support substrate 110 is disposed). This will be described in more detail later.

Claims (11)

A support substrate (110);
A first semiconductor layer (130) deposited on the support substrate (110) and made of a first semiconductor material;
A second semiconductor layer (135) deposited on the first semiconductor layer (130, 135) and made of a second semiconductor material, the band gap of the first semiconductor material and the band gap of the second semiconductor material; A second semiconductor layer (135) different from
A drain terminal (145) and a source terminal (150) embedded in at least the second semiconductor layer (135), and using the drain terminal (145) and the source terminal (150), the first terminal A drain terminal (145) and a source terminal (150) in electrical contact connection with at least one boundary layer (140) between a semiconductor material and the second semiconductor material;
A channel region (155) between the drain terminal (145) and the source terminal (150);
A gate terminal (170) that at least partially covers the channel region (155);
A recess (on the side of the support substrate (100) opposite to the drain terminal (145) and / or the source terminal (150) and at least partially overlapping the channel region (155) 180), the lateral edge (182) and / or bottom (183) of the recess (180) having a recess (180) covered with an insulating layer (185).
A transistor (100) characterized by that. The insulating layer extends from the recess (180) on the main surface (186) of the support substrate (100) on the side opposite to the gate terminal (170).
The transistor (100) of claim 1. On the surface of the insulating layer (185) opposite to the support substrate (110), a filling layer (187) containing a thermally conductive and / or conductive material is provided at least in the region of the recess (180). Arranged,
The transistor (100) according to claim 1 or 2. The filling layer (187) has at least in the region of the recess (180) a metal material, in particular copper, polysilicon, in particular doped polysilicon, and / or SiC, in particular highly doped SiC, and / Or including aluminum nitride,
4. The transistor (100) according to any one of claims 1 to 3. The insulating layer (185) has a thickness of at least 0.1 μm and / or at most 10 μm;
A transistor (100) according to any one of the preceding claims. The recess (180) has a predetermined depth, whereby a partial layer of the support substrate (110) is disposed between the first semiconductor layer (130) and the insulating layer (185). ing,
A transistor (100) according to any one of the preceding claims. Another support substrate (320) covering the second semiconductor layer (135), the source terminal (145), the drain terminal (150) and / or the gate terminal (170);
A transistor (100) according to any one of the preceding claims. Another recess (300) extending from the surface of the support substrate (110) opposite to the gate terminal (170) to the first semiconductor layer (130) and / or the second semiconductor layer (135). In particular, the other recess (300) is disposed in a section of the support substrate (110) that does not overlap the channel region (155).
A transistor (100) according to any one of the preceding claims. The insulating layer (185) or another insulating layer is disposed at least partially on the edge of the another recess (300),
The transistor (100) of claim 8. The filling layer (187) or another filling layer comprising a thermally conductive and / or conductive material is arranged in the further recess (300), in particular the filling layer (187) or the other filling. A layer is conductively connected to the source terminal (145), the drain terminal (150), the gate terminal (170) or the boundary layer (140);
The transistor (100) according to claim 8 or 9. In the manufacturing method (200) of the transistor (100),
The method (200) comprises the following steps:
Providing a support substrate (110) (110) (210);
A first semiconductor layer (130) made of a first semiconductor material is deposited on the support substrate (110), and a second semiconductor layer (135) made of a second semiconductor material is deposited on the first semiconductor layer. Step (220), wherein a band gap of the first semiconductor material is different from a band gap of the second semiconductor material;
A step (230) of forming a drain terminal (145) and a source terminal (150), wherein the drain terminal (145) and the source terminal (150) are embedded in at least the second semiconductor layer (135); The drain terminal (145) and the source terminal (150) can be electrically contacted to at least one boundary layer (140) between the first semiconductor material and the second semiconductor material, and A channel region (155) between a drain terminal (145) and the source terminal (150) is defined by the drain terminal (145) and the source terminal (150);
Disposing (240) a gate terminal (170) that at least partially covers the channel region (155);
The supporting substrate substrate (at least partially overlapping the channel region (155) on the surface of the supporting substrate (110) opposite the drain terminal (145) and / or the source terminal (150); 110) in which a recess (180) is provided in the compartment, the edge of the recess (180) being covered by an insulating layer (185);
Having
A method (200) for manufacturing a transistor (100), characterized in that

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