JP2008159842A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve withstand voltage characteristics by making the arrangement of a gate electrode into outside of the right above region of an insulative mask pattern. <P>SOLUTION: The semiconductor device 10 includes: a semi-insulative single crystal substrate 20 in which an element forming region 11 is prepared in a first main surface 20a; a buffer layer 30 prepared on the first main surface; an insulative mask pattern 40 prepared on the buffer layer, an electron transit layer 50 having a first region 50a and a second region 50b; a barrier layer 60 prepared on the electron transit layer; a gate electrode 72 prepared on the barrier layer which is outside of the first layer and the second layer; a drain electrode 76 prepared ranging over the first region crossing over the top of a border plane 52 from the top of the second region; and a source electrode 74 prepared so as to be opposed to the drain electrode. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a field effect semiconductor transistor having a configuration capable of realizing higher breakdown voltage characteristics or reverse breakdown voltage characteristics and a manufacturing method thereof.

  Conventionally, in the manufacturing process of a GaN-based field effect semiconductor transistor such as GaN-HEMT, the surface of a single crystal substrate made of a material different from GaN such as a GaAs substrate due to various restrictions such as difficulty in obtaining a large-diameter GaN single crystal substrate. On the buffer layer, for example, a GaN single crystal layer is formed, and a GaN layer is further epitaxially grown on the buffer layer.

  However, in such a buffer layer, so-called threading dislocations, which are defects due to lattice mismatch, occur.

  The threading dislocation generated in the buffer layer inevitably propagates to, for example, the GaN layer formed immediately above it.

  In order to prevent the breakdown voltage characteristics of the field-effect semiconductor transistor from being deteriorated due to the threading dislocation, a GaN-based field-effect semiconductor transistor in which the GaN layer is formed by a selective lateral growth (ELO) method is used. A manufacturing method is known (for example, refer to Patent Document 1).

  In addition, a Cat-CVD (Catalytic Chemical Vapor Deposition) method is applied when forming the protective film, so that a trap at the semiconductor / protective film interface is reduced, current collapse is suppressed, and a high breakdown voltage is realized. An electron mobility transistor) is known (for example, see Non-Patent Document 1).

  Furthermore, a GaAs MESFET having a field modulating plate (FP) is known (for example, see Non-Patent Document 2). This Non-Patent Document 2 describes that the electric field concentration distribution between the gate electrode and the drain electrode becomes denser on the drain side, and the electric field concentration is not so much directly under the gate electrode.

Furthermore, a film forming method for forming a GaN film having a reduced dislocation density by a selective lateral growth method is known (see, for example, Non-Patent Document 3). In Non-Patent Document 3, a low-angle grain boundary having a c-axis inclination of about 1 ° is formed at a boundary surface formed by combining films grown from two different directions by selective lateral growth. It is described that it is done.
JP 2001-230410 A Journal of Applied Electronic Properties, Vol. 12, No. 1, pages 4-8 Y. Hori, M. Kuzuhara and M. Mizuta: Extended Abstracts of 1998 Int. Conf. On SSDM pp. 394-395 Applied Physics, Vol. 68, No. 7, pp. 774-779 (1998)

  For example, according to the configuration of the semiconductor device disclosed in Patent Document 1 described above, the gate electrode of the transistor is provided immediately above the mask made of a silicon oxide film.

  If a GaN layer is formed on such a mask by a selective lateral growth method, as disclosed in Non-Patent Document 3, the c-axis of the crystal is formed on the boundary surface formed by combining films grown from two different directions. Since a low-inclination grain boundary having an inclination of about 1 ° is formed, if a source electrode and a drain electrode are present across the small-inclination grain boundary, a region where a sheet carrier exists between them Is divided into small tilt regions, and the traveling of electron carriers is hindered.

  In this case, in particular, when the gate electrode is provided on the low-inclined grain boundary, the leakage current may increase and the controllability of the transistor may be impaired.

  Here, according to the disclosure of Non-Patent Document 2, it is clear that the electric field concentration distribution is denser on the drain side, and thus it is understood that it is not necessary to have a mask directly under the gate electrode.

  In order to solve the above-described problems, the semiconductor device of the present invention has the following structural features.

  That is, the semiconductor device of the present invention has a first main surface and a second main surface opposite to the first main surface, and a semi-insulating single unit in which an element formation region is provided on the first main surface. The crystal substrate, the buffer layer provided on the first main surface, the insulating mask pattern provided on the buffer layer, and the insulating mask pattern and the buffer layer exposed from the insulating mask pattern are integrated. An electron carrier traveling layer that covers the first region, the first region defined by the boundary surface within the region on the insulating mask pattern, and the second region adjacent to the first region The carrier traveling layer, the barrier layer provided on the electron carrier traveling layer, and the barrier layer outside the first and second regions, wherein the extending direction of the gate width is along the edge of the first region The gate is provided as A drain electrode provided on the barrier layer spaced apart from the electrode and the gate electrode, and provided over the first region from the second region of the electron carrier traveling layer to the boundary surface. A drain electrode and a source electrode provided apart from the drain electrode with the gate electrode interposed therebetween are provided.

  The drain electrode and the source electrode are preferably provided in a groove that penetrates the barrier layer and reaches the thickness of the electron carrier transit layer.

  If it does in this way, since a source electrode and a drain electrode will contact a sheet carrier directly, contact resistance can be reduced more. As a result, the maximum operating frequency can be increased.

  The single crystal substrate is preferably a silicon carbide substrate, for example.

  The buffer layer is preferably an aluminum nitride film, for example.

  The insulating mask pattern is preferably, for example, either a silicon oxide film or a silicon nitride film.

  The electron carrier transit layer is preferably a gallium nitride film, for example, and the barrier layer is preferably an AlGaN film, for example.

  The film thickness of the electron carrier transit layer immediately above the insulating mask pattern is preferably 2 μm at the maximum.

  In this way, since the resistance value can be further increased, the breakdown voltage of the semiconductor device can be further improved.

  The main steps of the semiconductor device manufacturing method of the present invention are as follows.

  That is, the manufacturing method has a first main surface and a second main surface facing the first main surface, and a semi-insulating single crystal substrate in which a plurality of element formation regions are set on the first main surface. Preparing a buffer layer on the first main surface of the single crystal substrate, forming an insulating mask layer on the buffer layer, patterning the insulating mask layer, A step of forming an insulating mask pattern, and an electron carrier traveling layer that integrally covers the insulating mask pattern and the buffer layer exposed from the insulating mask pattern, which are grown from different directions by a selective lateral growth method. A step of forming an electron carrier traveling layer having a first region partitioned by a boundary surface in a region on the insulating mask pattern and a second region adjacent to the first region; A step of forming a barrier layer on the traveling layer; a step of forming an element isolation region to electrically isolate a plurality of element formation regions; and a barrier layer outside the first and second regions. A step of forming a gate electrode so that the extending direction of the gate width is along the edge of the first region, and a drain electrode provided on the barrier layer apart from the gate electrode, the electron carrier A step of forming a drain electrode provided over the first region from the second region of the traveling layer over the boundary surface, and a source electrode provided apart from the drain electrode with the gate electrode interposed therebetween Including.

  The step of forming the drain electrode and the source electrode is preferably a step of forming a groove portion that penetrates the barrier layer and reaches the thickness of the electron carrier traveling layer, and forms the groove portion in the groove portion.

  The buffer layer is preferably formed as an aluminum nitride film, for example.

  The insulating mask pattern is preferably formed, for example, as either a silicon oxide film or a silicon nitride film.

  The electron carrier traveling layer is preferably formed of, for example, a gallium nitride film, and the barrier layer is preferably formed of, for example, an AlGaN film.

  The film thickness of the electron carrier traveling layer immediately above the insulating mask pattern is preferably 2 μm at the maximum.

  According to the configuration of the semiconductor device of the present invention, the gate electrode is disposed outside the region immediately above the insulating mask pattern, that is, the gate electrode does not exist on the low-angle grain boundary, so that the transistor electrical characteristics such as an increase in leakage current are generated. It is possible to effectively prevent deterioration of characteristics.

  In addition, according to the configuration of the semiconductor device of the present invention, since the drain electrode faces the gate electrode across the low-angle grain boundary, the region where the sheet carrier exists is not divided by the low-angle grain boundary. Therefore, the electrical characteristics can be further improved.

  The semiconductor device of the present invention can realize extremely high breakdown voltage characteristics due to the combination of these configurations.

  Moreover, according to the method for manufacturing a semiconductor device of the present invention, a semiconductor device having the above-described configuration and exhibiting the above-described effects can be manufactured more efficiently.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, only the shapes, sizes, and arrangement relationships of the respective constituent components are schematically shown to such an extent that the present invention can be understood, and the present invention is not particularly limited thereby. In the following description, specific materials, conditions, numerical conditions, and the like may be used. However, these are merely preferred examples, and are not limited to these. In addition, it should be understood that the same constituent components are denoted by the same reference numerals in the drawings used for the following description, and redundant description thereof may be omitted.

(First embodiment)
1. Configuration Example of Semiconductor Device With reference to FIG. 1, an embodiment of a semiconductor device of this example will be described.

  FIG. 1A is a schematic plan view as viewed from the top for explaining the structure of the semiconductor device, and FIG. 1B is cut at a position corresponding to the dashed line II ′ in FIG. It is the schematic which shows the cut surface which carried out.

  The semiconductor device of the present invention, that is, the transistor, has a configuration in which the gate electrode is disposed so as not to be directly above the insulating mask pattern, and the drain electrode has no low-angle grain boundary between the drain electrode and the source electrode. It has the characteristic in the point arranged so.

  Hereinafter, a configuration example of a high electron mobility transistor will be described as the transistor of the present invention. The present invention is not limited to this, and can be applied to transistors such as MESFET (Metal Semiconductor Field Effect Transistor) and JFET (Junction Field Effect Transistor) whose gate electrode has a pn junction.

  As shown in FIGS. 1A and 1B, a semiconductor device 10 of the present invention includes a single crystal substrate 20. For example, a semi-insulating silicon carbide (SiC) substrate is preferably used as the single crystal substrate 20.

  The single crystal substrate 20 has a parallel plate shape, and has a first main surface 20a and a second main surface 20b opposite to the first main surface 20a.

  On the first main surface 20a side, in this example, a rectangular element forming region 11 in which a functional element as a transistor is formed is set.

  A buffer layer 30 is provided on the entire first main surface including the element formation region 11. In this example, the buffer layer 30 is an aluminum nitride (AlN) film.

  The aluminum nitride film has a larger band gap (about 6.2 eV) than that of gallium nitride (GaN), for example (about 3.4 eV).

  Therefore, the use of an aluminum nitride film as the buffer layer 30 can more effectively prevent leakage current.

  An insulating mask pattern 40 is provided on the buffer layer 30. The insulating mask pattern 40 is provided in the element formation region 11. In this example, the insulating mask pattern is provided as a rectangular pattern.

  The insulating mask pattern 40 is preferably a silicon oxide film or a silicon nitride film, for example.

  On the insulating mask pattern 40 and the buffer layer 30 exposed from the insulating mask pattern 40, an electron carrier traveling layer 50 is provided so as to integrally cover them.

  The electron carrier transit layer 50 is preferably configured as a gallium nitride film, for example.

  The electron carrier transit layer 50 is preferably provided with a film thickness immediately above the insulating mask pattern 40 at a maximum of 2 μm.

  Thus, if the electron carrier transit layer 50 is made thinner, the resistance value can be further increased, so that the breakdown voltage of the transistor can be further improved.

  Although the details will be described later, the electron carrier transit layer 50 is caused by the manufacturing method of the electron carrier transit layer 50, and at least two regions within the region immediately above the insulating mask pattern 40, that is, the first region 50a and the first region 50a. The boundary area 52 inevitably partitions the second area 50b adjacent to the area 50a.

  This boundary surface 52 is a portion where a so-called low-angle grain boundary is generated, in which the c-axis of the GaN unit cell is inclined at a small angle of about 1 ° due to the manufacturing method of the electron carrier traveling layer 50.

  That is, the low-inclination grain boundary is formed in a linear shape on the insulating mask pattern 40 and constitutes the boundary surface 52.

  On the electron carrier traveling layer 50, a barrier layer 60 covering the entire exposed surface is provided.

  The barrier layer 60 can be of any suitable structure known in the art, but is preferably composed of, for example, an AlGaN film.

At this time, the AlGaN film is preferably an Al _0.25 Ga _0.75 N film, for example, but the Al composition may be 0.3 or more.

  The barrier layer 60 may be a doped layer doped with, for example, silicon (Si).

In this case, for example, silicon is preferably doped at a concentration of about 1 × 10 ¹⁸ ions / cm ³ .

  Furthermore, the barrier layer 60 may have a laminated structure of such a doped layer and an undoped layer.

  Note that the boundary surface 52 of the electron carrier traveling layer 50 described above also reaches the barrier layer 60.

  The semiconductor device 10 of the present invention includes a plurality of element formation regions 11. A plurality of adjacent element formation regions 11 are electrically isolated from each other by an element isolation region 80 that reaches the element formation region 11 and surrounds it.

  A gate electrode 72 is provided on the barrier layer 60. In this example, the gate electrode 72 has a rod-like shape extending linearly, and the gate width direction extends in the vertical direction of the drawing.

  The gate electrode 72 is provided directly above the first region 50 a and the second region 50 b of the electron carrier transit layer 50.

  The gate electrode 72 may have any conventionally known suitable shape and configuration, but preferably has a laminated structure in which, for example, nickel (Ni) and gold (Au) are laminated in this order.

  The gate electrode 72 may be a so-called MIS (Metal Insulator Semiconductor) configured with an insulating film such as aluminum nitride (AlN) interposed therebetween.

  In this example, the gate electrode 72 is provided so that the extending direction of the gate width is along the edge of the first region 50a.

  The gate electrode 72 and the insulating mask pattern 40 are not completely overlapped with each other when viewed from the upper surface side, that is, the insulating mask pattern 40 exists outside the region directly below the gate electrode 72. Is provided.

  Therefore, since the boundary surface 52 does not exist immediately below the gate electrode 72, an increase in leakage current due to the boundary surface 52 can be effectively prevented.

  A drain electrode 76 is provided on the barrier layer 60 so as to be opposed to the gate electrode 72 while being spaced apart.

  The drain electrode 76 is provided on the side where the insulating mask pattern 40 exists, that is, the side where the boundary surface 52 exists.

  The drain electrode 76 is provided from the second region 50b of the electron carrier traveling layer 50 to the first region 50a beyond the boundary surface 52, that is, over the first region 50a and the second region 50b. ing.

  The source electrode 74 is provided so as to be separated from the drain electrode 76 with the gate electrode 72 interposed therebetween. That is, the source electrode 74 is provided to face the side surface opposite to the side surface forming the gate width opposed to the drain electrode 76 of the gate electrode 72.

  A plurality of transistors of the present invention are integrated on the same substrate. The plurality of transistors are electrically isolated from each other by the element isolation region 80.

  The element isolation region 80 may have any conventionally known and suitable configuration. Preferably, for example, as shown in the drawing, a plurality of transistors are connected to each other as an ion implantation region into which, for example, argon (Ar) is implanted. It is better to separate them electrically.

  In this example, the element isolation region 80 is provided at a depth from the surface of the barrier layer 60 to the middle of the thickness of the electron carrier traveling layer 50.

  The element isolation region 80 may have a configuration different from the illustrated example, for example, a configuration in which the element isolation region 80 is structurally isolated by a mesa structure.

  A suitable transistor size to which the structure of the present invention is applied can be arbitrarily determined depending on an intended electrical characteristic and an applied technology node.

  Here, referring to FIG. 1A, when the size of the above-described transistor of the present invention is exemplified as a general technical level at present, the gate electrode length Lg is about 1 μm. The gate electrode-drain electrode distance Lgd is about 5 μm. The distance Lsg between the source electrode and the gate electrode is about 5 μm. The source electrode length Ls and the drain electrode length Ld are both about 5 μm. The width of each electrode (length in the vertical direction in the drawing) is about 100 μm.

  The gate electrode length Lg may be 1 μm or less. The width of each electrode, that is, the total length of the length extending in the vertical direction of the drawing can be about 200 μm.

  The transistor of the present invention having the above-described configuration has particularly high reverse breakdown voltage characteristics. Therefore, the semiconductor device of the present invention is suitable for use in applications where high breakdown voltage characteristics are required, such as high power switching elements for power or high power high frequency elements.

2. Manufacturing Method Example Next, with reference to FIGS. 2, 3, 4, 5, 6, and 7, a manufacturing method of the semiconductor device of this example will be described.

  FIG. 2 is a manufacturing process diagram schematically showing a part focused on the constituent components corresponding to FIGS. 1 (A) and 1 (B) already described.

  3 to 7 are process diagrams schematically showing a series of manufacturing steps subsequent to FIG.

  Each process described below proceeds at the wafer level, but only a part of the process will be described in order to facilitate understanding of the characteristic part.

  As shown in FIGS. 2A and 2B, first, a semi-insulating single crystal substrate 20 is prepared. The single crystal substrate 20 is preferably a silicon carbide substrate, for example.

  The single crystal substrate 20 has a first main surface 20a and a second main surface 20b opposite to the first main surface 20a.

  A plurality of element formation regions 11 are set in advance on the first main surface 20a in accordance with a desired layout design of the semiconductor device. In the figure, only one element formation region 11 is shown as a representative.

  Next, buffer layer 30 is formed on first main surface 20 a of single crystal substrate 20.

  The buffer layer 30 is preferably formed of an aluminum nitride film, for example, with a film thickness of about 100 nm by a conventionally known MOCVD (Metal Organic Chemical Vapor Deposition) method or MBE (Molecular Beam Epitaxy) method.

  Specifically, when the MOCVD method is applied, the film formation temperature is about 1200 ° C., the pressure is about 6666 Pascal (50 Torr), and the growth rate is about 200 nm / hour (h). It is preferable to form a film.

  Next, as shown in FIGS. 3A and 3B, an insulating mask layer 40 </ b> X is formed on the formed buffer layer 30.

As the insulating mask layer 40X, for example, a silicon oxide film (SiO ₂ ) is preferably formed with a film thickness of about 100 nm by a conventionally known plasma CVD method.

  Next, as shown in FIGS. 4A and 4B, the insulating mask layer 40X is patterned by a photolithography process and an etching process according to a conventional method to form the insulating mask pattern 40. The insulating mask pattern 40 is formed as a rectangular pattern in the element formation region 11.

  As shown in FIGS. 5A and 5B, an electron carrier traveling layer 50 is formed.

  The electron carrier transit layer 50 is formed so as to integrally cover the insulating mask pattern 40 and the buffer layer 30 exposed from the insulating mask pattern 40.

  The electron carrier transit layer 50 is formed by an epitaxial selective lateral growth method. That is, the electron carrier traveling layer 50 is integrally formed by growing from a plurality of different directions and combining them.

  At this time, the electron carrier transit layer 50 is first grown on the buffer layer 30. On the buffer layer 30 outside the insulating mask pattern 40, the electron carrier traveling layer 50 grows in the vertical direction of FIG. 5A, that is, the white arrow A direction or the B direction.

  The electron carrier transit layer 50 grown to almost the same thickness as the insulating mask pattern 40 is laterally on the insulating mask pattern 40, that is, the first region 50a is from the direction of the white arrow C in the drawing, and the second region 50b is From the direction of the white arrow D, the insulating mask pattern 40 is grown toward the center line that bisects in the vertical direction of the drawing.

  In this manner, the electron carrier transit layer 50 is adjacent to the first region 50a and the first region 50a, which are partitioned in the region on the insulating mask pattern 40 by being substantially divided into two by the boundary surface 52 in the illustrated example. The second region 50b is provided.

  The electron carrier transit layer 50 preferably uses, for example, trimethyl gallium as a gallium source, the film forming conditions are such that the amount of trimethyl gallium is about 88 μmol / min, the concentration ratio (V / III ratio) is about 2500, and the pressure is about 6666 Pascals. It is preferable to form the film at a temperature of about (50 Torr) and a growth temperature of about 1070 ° C.

  Forming the electron carrier traveling layer 50 under such film formation conditions is preferable because the regrowth rate ratio between the direction perpendicular to the substrate and the horizontal direction can be about 5.7 times.

  As described above, the first region 50a on the insulating mask pattern 40 is formed of the gallium nitride film (GaN) that has grown from the outside of the insulating mask pattern 40, that is, on the buffer layer 30, as shown in FIG. The insulating mask pattern 40 is covered by growing in the direction of the white arrow C from the left edge of 40.

  The second region 50b on the insulating mask pattern 40 is covered with a film that grows in the direction of the white arrow D from the right edge of the illustrated insulating mask pattern 40.

  The first region 50a and the second region 50b are combined with each other along a line that substantially divides the surface area of the insulating mask pattern 40, and are integrated while forming a low-angle grain boundary, that is, a boundary surface 52.

  So-called threading dislocations inevitably occur in the regions outside the first region 50 a and the second region 50 b outside the insulating mask pattern 40 of the electron carrier transit layer 50.

  Further, threading dislocations are inevitably concentrated along the boundary surface 52 in the regions in the first region 50 a and the second region 50 b of the electron carrier traveling layer 50. However, since the electron carrier transit layer 50 is formed by the lateral selective growth method, there are very few threading dislocations in the region excluding the boundary surface 52.

  At this time, the film thickness of the electron carrier traveling layer 50 immediately above the insulating mask pattern 40, that is, the first region 50a and the second region 50b is preferably set to 2 μm at the maximum as described above.

  Next, the barrier layer 60 is formed on the electron carrier traveling layer 50. The barrier layer 60 is preferably formed by, for example, an AlGaN film according to a conventional method.

  The threading dislocations forming the boundary surface 52 generated in the electron carrier traveling layer 50 inevitably propagates to the barrier layer 60 immediately above it because the same growth orientation is maintained when the barrier layer 60 is formed. .

  As shown in FIGS. 6A and 6B, an element isolation region 80 is formed to electrically isolate a plurality of element formation regions 11 from each other.

  The element isolation region 80 may be formed by masking with a silicon oxide film having a pattern exposing the formation region of the element isolation region 80, for example, by implanting argon (Ar). Good.

  Next, as shown in FIGS. 7A and 7B, a gate electrode 72 is formed. The gate electrode 72 is formed on the barrier layer 60 outside the upper side of the first region 50a and the upper side of the second region 50b of the electron carrier traveling layer 50, that is, when viewed from the upper side, the gate electrode 72 forms the insulating mask pattern 40. It is formed so that it does not overlap with the formation position, and the extending direction of the gate width Wg is along the edge of the first region 50a.

  The formation of the gate electrode 72 is performed according to a conventional method, preferably, for example, a mask pattern forming step for opening a gate electrode formation region by a photolithography step, a metal film forming step by an electron beam evaporation step, a lift-off step for removing the mask pattern, and It can be formed by a heat treatment at about 400 ° C., that is, an annealing step.

  Next, the source electrode 74 and the drain electrode 76 are formed according to a conventional method. The source electrode 74 and the drain electrode 76 are preferably formed at the same time. Specifically, in the same manner as the gate electrode 72 already described, for example, a mask pattern forming step for opening an electrode forming region by a photolithography step, a metal film forming step by an electron beam vapor deposition step, and a lift-off for removing the mask pattern Perform the process. Next, an electrode having ohmic characteristics is formed by a heat treatment at about 600 ° C., that is, a sintering process.

  The drain electrode 76 is formed on the barrier layer 60 so as to be separated from the gate electrode 72. At this time, the drain electrode 76 is formed so as to extend from the upper side of the second region 50 b of the electron carrier transit layer 50 to the upper side of the first region 50 a beyond the boundary surface 52.

  The source electrode 74 is formed so as to be separated from the gate electrode 72 and to face the drain electrode 76 with the gate electrode 72 interposed therebetween.

(Second Embodiment)
1. Configuration Example of Semiconductor Device With reference to FIG. 8, an embodiment of a semiconductor device of this example will be described.

  FIG. 8A is a schematic plan view seen from the upper surface for explaining the structure of the semiconductor device, and FIG. 8B is cut at a position corresponding to the dashed line II ′ in FIG. It is the schematic which shows the cut surface which carried out.

  As shown in FIGS. 8A and 8B, the semiconductor device 10 of this example is characterized in that the source electrode 74 and the drain electrode 76 have a so-called recess structure.

  The other constituent elements are the same as those in the first embodiment described above, and are therefore assigned the same reference numerals and will not be described in detail.

  That is, in the semiconductor device 10 of this example, the source electrode 74 and the drain electrode 76 penetrate the barrier layer 60 and reach the thickness of the electron carrier traveling layer 50 in the configuration example of the first embodiment already described. It is provided in the groove portion 78, that is, by embedding the recess groove. The source electrode 74 and the drain electrode 76 are preferably formed so as to be in contact with the carrier traveling layer 50 in consideration of the contact resistance, but the barrier layer 60 immediately below the source electrode 74 and the drain electrode 76 is also made thinner. Since the contact resistance can be further reduced, the source electrode 74 and the drain electrode 76 may be provided so as to be embedded with a groove portion 78 that fits within the thickness of the barrier layer 60.

  In this example, the source electrode 74 and the drain electrode 76 are provided in a groove 78 having a depth shallower than the thickness of each of the source electrode 74 and the drain electrode 76 so that a part of the thickness protrudes from the barrier layer 60. It has been.

  The source electrode 74 and the drain electrode 76 are not limited to this, and may be configured to be embedded in the groove portion 78 without protruding from the barrier layer 60.

  If the source electrode 74 and the drain electrode 76 are formed in a recess structure in this way, the source electrode 74 and the drain electrode 76 are in direct contact with the sheet carrier, so that the contact resistance can be further reduced. As a result, the maximum operating frequency can be increased.

2. Manufacturing Method Example Next, with reference to FIG. 9, a manufacturing method of the semiconductor device of this example will be described.

  FIGS. 9A and 9B are partial schematic manufacturing process diagrams showing a cut surface cut at the same position as each of the drawings already described.

  Since the steps from FIG. 2 to FIG. 6 and FIG. 7 which are already described in the first embodiment are the same, detailed description thereof will be omitted.

  As shown in FIGS. 9A and 9B, after the element isolation region 80 is formed, a groove 78 which is a recess groove is formed by a conventionally known photolithography process and etching process, preferably, for example, ICP-RIE etching. .

  Next, as already described, the mask pattern forming step for opening the electrode forming region by the photolithography step, the metal film forming step by the electron beam vapor deposition step, the lift-off step for removing the mask pattern, and the heat treatment (sinter) step A source electrode 74 and a drain electrode 76 that fill the groove 78 are formed.

FIG. 1A is a schematic plan view as viewed from the top for explaining the structure of the semiconductor device, and FIG. 1B is cut at a position corresponding to the dashed line II ′ in FIG. It is the schematic which shows the cut surface which carried out. FIG. 2 is a partial schematic manufacturing process diagram shown in the same positions as those of FIGS. 1A and 1B described above. FIG. 3 is a manufacturing process diagram following FIG. FIG. 4 is a manufacturing process diagram following FIG. 3. FIG. 5 is a manufacturing process diagram following FIG. FIG. 6 is a manufacturing process diagram following FIG. 5. FIG. 7 is a manufacturing process diagram following FIG. 6. FIG. 8A is a schematic plan view seen from the upper surface for explaining the structure of the semiconductor device, and FIG. 8B is cut at a position corresponding to the dashed line II ′ in FIG. It is the schematic which shows the cut surface which carried out. FIGS. 9A and 9B are partial schematic manufacturing process diagrams showing a cut surface cut at the same position as each of the drawings already described.

Explanation of symbols

10: Semiconductor device 11: Element formation region 20: Single crystal substrate 20a: First main surface 20b: Second main surface 30: Buffer layer 40: Insulating mask pattern 40X: Insulating mask layer 50: Electron carrier traveling layer 50a: 1st area | region 50b: 2nd area | region 52: Interface 60: Barrier layer 72: Gate electrode 74: Source electrode 76: Drain electrode 78: Groove part 80: Element isolation region

Claims (13)

A semi-insulating single crystal substrate having a first main surface and a second main surface opposite to the first main surface, wherein an element formation region is provided on the first main surface;
A buffer layer provided on the first main surface;
An insulating mask pattern provided on the buffer layer;
An electron carrier traveling layer that integrally covers the insulating mask pattern and a buffer layer exposed from the insulating mask pattern, and is defined by a boundary surface in a region on the insulating mask pattern. The electron carrier transit layer having a region and a second region adjacent to the first region;
A barrier layer provided on the electron carrier transit layer;
A gate electrode provided on the barrier layer outside the first and second regions, the gate electrode extending in a direction along the edge of the first region; and
A drain electrode provided on the barrier layer apart from the gate electrode, and provided over the first region from the second region of the electron carrier transit layer to beyond the boundary surface; Said drain electrode, and
A semiconductor device comprising a source electrode spaced apart from the drain electrode with the gate electrode interposed therebetween.   The semiconductor device according to claim 1, wherein the drain electrode and the source electrode are provided in a groove portion that penetrates the barrier layer and reaches the thickness of the electron carrier traveling layer.   The semiconductor device according to claim 1, wherein the single crystal substrate is a silicon carbide substrate.   The semiconductor device according to claim 3, wherein the buffer layer is an aluminum nitride film.   5. The semiconductor device according to claim 4, wherein the insulating mask pattern is one of a silicon oxide film and a silicon nitride film.   6. The semiconductor device according to claim 5, wherein the electron carrier traveling layer is a gallium nitride film, and the barrier layer is an AlGaN film.   The semiconductor device according to claim 6, wherein a film thickness of the electron carrier traveling layer immediately above the insulating mask pattern is 2 μm at the maximum. A step of preparing a semi-insulating single crystal substrate having a first main surface and a second main surface opposite to the first main surface, wherein a plurality of element formation regions are set on the first main surface. When,
Forming a buffer layer on the first main surface of the single crystal substrate;
Forming an insulating mask layer on the buffer layer;
Patterning the insulating mask layer to form an insulating mask pattern;
An electron carrier traveling layer that integrally covers the insulating mask pattern and a buffer layer exposed from the insulating mask pattern, and is grown from different directions by a selective lateral growth method, and is formed on the insulating mask pattern. Forming the electron carrier traveling layer having a first region partitioned by a boundary surface in the region and a second region adjacent to the first region;
Forming a barrier layer on the electron carrier transit layer;
Forming an element isolation region to electrically isolate a plurality of the element formation regions;
Forming a gate electrode on the barrier layer outside the first and second regions so that the extending direction of the gate width is along the edge of the first region;
A drain electrode provided on the barrier layer apart from the gate electrode, and provided over the first region from the second region of the electron carrier transit layer to beyond the boundary surface; Forming a drain electrode, and forming a source electrode spaced apart from the drain electrode with the gate electrode interposed therebetween.   The step of forming the drain electrode and the source electrode is a step of forming a groove portion penetrating the barrier layer and reaching the thickness of the electron carrier traveling layer, and forming the groove portion in the groove portion. Item 9. A method for manufacturing a semiconductor device according to Item 8.   10. The method for manufacturing a semiconductor device according to claim 8, wherein the buffer layer is formed as an aluminum nitride film.   11. The method of manufacturing a semiconductor device according to claim 10, wherein the insulating mask pattern is formed as either a silicon oxide film or a silicon nitride film.   12. The method of manufacturing a semiconductor device according to claim 11, wherein the electron carrier traveling layer is formed of a gallium nitride film, and the barrier layer is formed of an AlGaN film.   13. The method of manufacturing a semiconductor device according to claim 12, wherein the thickness of the electron carrier transit layer immediately above the insulating mask pattern is set to 2 [mu] m at the maximum.

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