JP2013069772A - Semiconductor device and semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and a semiconductor device manufacturing method, which can inhibit variation in a current and ensure pinch-off characteristics.SOLUTION: A HEMT 100 comprises: a substrate 10 of SiC; a buffer layer 12 of AIN provided on the substrate 10; a channel layer 14 of GaN provided on the buffer layer 12; an electron supply layer 16 of AlGaN provided on the channel layer 14; and a source electrode 20, a drain electrode 22 and a gate electrode 24 which are formed on the electron supply layer 16. A concentration of C in a region 14b on the side of the electron supply layer 16 of the channel layer 14 is higher than a concentration of C in a region 14a on the side of the buffer layer 12 of the channel layer 14. A manufacturing method of the HEMT 100 is provided.

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

  A HEMT (High Electron Mobility Transistor) using a nitride semiconductor is sometimes used as a high-frequency output amplification element. In the HEMT, a two-dimensional electron gas (2DEG) generated at the interface between the channel layer and the electron supply layer is used as a carrier. When electrical stress or the like is applied, 2DEG electrons may be trapped in traps in the nitride semiconductor layer. Due to electron trapping, the current flowing in the HEMT, such as the drain current, may vary with time. Patent Document 1 discloses an invention that suppresses fluctuations in current by increasing the quality of a gallium nitride (GaN) layer.

JP 2006-147663 A

  However, the technique described in Patent Document 1 may not sufficiently suppress current fluctuation. In addition, it may be difficult to achieve both suppression of current fluctuation and securing pinch-off characteristics. In view of the above problems, an object of the present invention is to provide a semiconductor device capable of suppressing current fluctuation and ensuring pinch-off characteristics, and a method for manufacturing the semiconductor device.

  The present invention includes a substrate made of silicon carbide, a buffer layer made of aluminum nitride provided on the substrate, a channel layer made of gallium nitride provided on the buffer layer, and provided on the channel layer. An electron supply layer made of a nitride semiconductor, and a source electrode, a drain electrode, and a gate electrode provided on the electron supply layer, and the concentration of carbon in a region of the channel layer on the electron supply layer side is: The semiconductor device has a higher concentration of carbon in a region of the channel layer on the buffer layer side. According to the present invention, it is possible to suppress fluctuations in current and ensure pinch-off characteristics.

In the above configuration, the concentration of carbon in the region on the electron supply layer side of the channel layer is 4 × 10 ¹⁶ atoms / cm ³ or more, and the concentration of carbon in the region on the buffer layer side of the channel layer is 2 × 10 10. ^The configuration may be ¹⁶ atoms / cm ³ or less. According to this configuration, it is possible to suppress current fluctuation and to secure pinch-off characteristics.

  The present invention includes a substrate made of silicon carbide, a buffer layer made of aluminum nitride provided on the substrate, a channel layer made of gallium nitride provided on the buffer layer, and provided on the channel layer. An electron supply layer made of a nitride semiconductor; and a source electrode, a drain electrode, and a gate electrode provided on the electron supply layer, and the concentration of silicon and oxygen in the region of the channel layer on the electron supply layer side The semiconductor device is a semiconductor device that has a total value smaller than the total value of the silicon concentration and the oxygen concentration in the region on the buffer layer side of the channel layer. According to the present invention, it is possible to suppress fluctuations in current and ensure pinch-off characteristics.

In the above structure, the total value of the silicon concentration and the oxygen concentration in the region on the electron supply layer side of the channel layer is 1 × 10 ¹⁶ atoms / cm ³ or less, and the region on the buffer layer side of the channel layer The total value of the silicon concentration and the oxygen concentration in can be configured to be 2 × 10 ¹⁶ atoms / cm ³ or more. According to this configuration, it is possible to suppress current fluctuation and to secure pinch-off characteristics.

The present invention includes a substrate made of silicon carbide, a buffer layer made of aluminum nitride provided on the substrate, a channel layer made of gallium nitride provided on the buffer layer, and provided on the channel layer. An electron supply layer made of a nitride semiconductor; and a source electrode, a drain electrode, and a gate electrode provided on the electron supply layer, wherein the buffer layer has a carbon concentration of 2 × 10 ¹⁹ atoms / cm ³ or less. This is a semiconductor device. According to the present invention, it is possible to suppress fluctuations in current and ensure pinch-off characteristics.

The present invention includes a substrate made of silicon carbide, a buffer layer made of aluminum nitride provided on the substrate, a channel layer made of gallium nitride provided on the buffer layer, and provided on the channel layer. An electron supply layer made of a nitride semiconductor; and a source electrode, a drain electrode, and a gate electrode provided on the electron supply layer, and a total value of oxygen concentration and silicon concentration of the buffer layer is 2 It is a semiconductor device having × 10 ¹⁷ atoms / cm ³ or more. According to the present invention, it is possible to suppress fluctuations in current and ensure pinch-off characteristics.

  The present invention includes a step of providing a buffer layer made of aluminum nitride on a substrate made of silicon nitride, a step of providing a channel layer made of gallium nitride on the buffer layer by MOCVD, and on the channel layer. A step of providing an electron supply layer made of a nitride semiconductor, and a step of providing a source electrode, a drain electrode, and a gate electrode on the electron supply layer, and a growth temperature of a region on the buffer layer side of the channel layer Is a method for manufacturing a semiconductor device, which is higher than the growth temperature of the region on the electron supply layer side of the channel layer. According to the present invention, it is possible to suppress fluctuations in current and ensure pinch-off characteristics.

  In the above configuration, the growth temperature of the channel layer on the buffer layer side may be 40 ° C. or higher than the growth temperature of the channel layer on the electron supply layer side. According to this configuration, it is possible to suppress current fluctuation and to secure pinch-off characteristics.

  The present invention includes a step of providing a buffer layer made of aluminum nitride on a substrate made of silicon nitride, a step of providing a channel layer made of gallium nitride on the buffer layer by MOCVD, and on the channel layer. A step of providing an electron supply layer made of a nitride semiconductor, and a step of providing a source electrode, a drain electrode, and a gate electrode on the electron supply layer, and growing a region on the electron supply layer side of the channel layer The rate is a method for manufacturing a semiconductor device that is larger than the growth rate of the region on the buffer layer side of the channel layer. According to the present invention, it is possible to suppress fluctuations in current and ensure pinch-off characteristics.

  In the above configuration, the growth rate of the region on the electron supply layer side of the channel layer may be 1.5 times or more the growth rate of the region on the buffer layer side of the channel layer. According to this configuration, it is possible to suppress current fluctuation and to secure pinch-off characteristics.

  The present invention includes a step of providing a buffer layer made of aluminum nitride on a substrate made of silicon nitride, a step of providing a channel layer made of gallium nitride on the buffer layer by MOCVD, and on the channel layer. A step of providing an electron supply layer made of a nitride semiconductor; and a step of providing a source electrode, a drain electrode, and a gate electrode on the electron supply layer, and a growth pressure of a region of the channel layer on the buffer layer side Is a method for growing a semiconductor device that is higher than the growth pressure of the region on the electron supply layer side of the channel layer. According to the present invention, it is possible to suppress fluctuations in current and ensure pinch-off characteristics.

  In the above-described configuration, the growth pressure of the channel layer on the buffer layer side may be higher than the growth pressure of the channel layer on the electron supply layer side by 13.33 kPa or more. According to this configuration, it is possible to suppress current fluctuation and to secure pinch-off characteristics.

  The present invention includes a step of providing a buffer layer made of aluminum nitride on a substrate made of silicon nitride, a step of providing a channel layer made of gallium nitride on the buffer layer by MOCVD including ammonia as a raw material, A step of providing an electron supply layer made of a nitride semiconductor on the channel layer; and a step of providing a source electrode, a drain electrode, and a gate electrode on the electron supply layer, and the buffer layer side of the channel layer The ammonia flow rate ratio in the step of providing the region is a growth method of a semiconductor device larger than the ammonia flow rate ratio in the step of providing the region on the electron supply layer side of the channel layer. According to the present invention, it is possible to suppress fluctuations in current and ensure pinch-off characteristics.

  The present invention includes a step of providing a buffer layer made of aluminum nitride on a substrate made of silicon nitride by a MOCVD method using a source gas containing silicon, and a step of providing a channel layer made of gallium nitride on the buffer layer. A method for manufacturing a semiconductor device, comprising: providing an electron supply layer made of a nitride semiconductor on the channel layer; and providing a source electrode, a drain electrode, and a gate electrode on the electron supply layer. According to the present invention, it is possible to suppress fluctuations in current and ensure pinch-off characteristics.

  The present invention includes a step of providing a buffer layer made of aluminum nitride on a substrate made of silicon nitride by a MOCVD method, a step of providing a channel layer made of gallium nitride on the buffer layer, and on the channel layer. A step of providing an electron supply layer made of a nitride semiconductor and a step of providing a source electrode, a drain electrode, and a gate electrode on the electron supply layer, and the growth rate of the buffer layer is 0.5 μm / h or less. This is a method for manufacturing a semiconductor device. According to the present invention, it is possible to suppress fluctuations in current and ensure pinch-off characteristics.

  ADVANTAGE OF THE INVENTION According to this invention, the semiconductor device which can suppress the fluctuation | variation of an electric current and can ensure a pinch-off characteristic, and the manufacturing method of a semiconductor device can be provided.

FIG. 1 is a cross-sectional view illustrating a HEMT according to Comparative Example 1. FIG. 2A is a schematic view illustrating the band structure of the HEMT according to Comparative Example 1. FIG. 2B is a schematic view illustrating the band structure of the HEMT according to Comparative Example 2. FIG. 3A is a schematic view illustrating a sample for buffer leak evaluation. FIG. 3B is a schematic view illustrating a sample for pinch freak evaluation. FIG. 4A is a schematic diagram illustrating the field strength dependence of the buffer leakage current in Comparative Example 1. FIG. 4B is a schematic view illustrating the field strength dependence of the buffer leakage current in Comparative Example 2. FIG. 5A is a schematic view illustrating the electric field strength dependence of the pinch freak current in Comparative Example 1. FIG. FIG. 5B is a schematic view illustrating the electric field strength dependence of the pinch freak current in Comparative Example 2. FIG. 6A is a cross-sectional view illustrating a HEMT according to the first embodiment. FIG. 6B is a schematic view illustrating the band structure of the HEMT according to the first embodiment. FIG. 7A is a schematic view illustrating a sample for buffer leak evaluation. FIG. 7B is a schematic view illustrating a sample for pinch freak evaluation. FIG. 8A is a schematic view illustrating the field strength dependence of the buffer leakage current in the first embodiment. FIG. 8B is a schematic view illustrating the electric field strength dependence of the pinch freak current in the first embodiment. FIG. 9A to FIG. 9C are cross-sectional views illustrating a method for manufacturing the HEMT according to the first embodiment. FIG. 10A and FIG. 10B are cross-sectional views illustrating a method for manufacturing the HEMT according to the first embodiment. FIG. 11A is a cross-sectional view illustrating a HEMT according to the second embodiment. FIG. 11B is a schematic view illustrating the band structure of the HEMT according to the second embodiment. FIG. 12A and FIG. 12B are cross-sectional views illustrating a method for manufacturing the HEMT according to the second embodiment.

  First, a comparative example will be described. FIG. 1 is a cross-sectional view illustrating a HEMT according to Comparative Example 1.

  As shown in FIG. 1, the HEMT 100R according to Comparative Example 1 includes a substrate 110, a buffer layer 112, a channel layer 114, an electron supply layer 116, a source electrode 120, a drain electrode 122, a gate electrode 124, and a protective layer 126.

  The substrate 110 is made of silicon carbide (SiC). The buffer layer 112 is made of, for example, aluminum nitride (AlN) having a thickness of 25 nm. The buffer layer 112 is provided on the substrate 110. The channel layer 114 is made of, for example, gallium nitride (GaN) having a thickness of 1200 nm. The channel layer 114 is provided on the buffer layer 112. The electron supply layer 116 is made of, for example, aluminum gallium nitride (AlGaN) having a thickness of 20 nm. The electron supply layer 116 is provided on the channel layer 114. The source electrode 120 and the drain electrode 122 are formed by, for example, laminating a titanium layer and an aluminum layer (Ti / Al), or a metal such as tantalum / aluminum (Ta / Al) in order from the side closer to the electron supply layer 116. Electrode. The gate electrode 124 is formed by laminating a metal such as nickel / aluminum (Ni / Al) in order from the side closer to the electron supply layer 116, for example. The gate electrode 124 is located between the source electrode 120 and the drain electrode 122. For example, a wiring made of a metal such as gold (Au) is connected to the source electrode 120 and the drain electrode 122. The wiring is not shown. A protective layer 126 made of an insulator such as silicon nitride (SiN) is provided on the electron supply layer 116.

  For example, when the source electrode 120 is grounded and a positive potential is applied to the drain electrode 122 and a negative potential is applied to the gate electrode 124, 2DEG is generated at the interface between the channel layer 114 and the electron supply layer 116. 2DEG becomes a carrier, and a current flows between the source and the drain. When an electrical stress is applied, electrons constituting 2DEG are trapped in the trap, and the drain current may fluctuate, for example. The electrical stress is, for example, a DC signal or a high-power high-frequency signal. The current fluctuation will be described later with reference to FIGS. 2 (a) and 2 (b).

  Next, the HEMT according to Comparative Example 2 will be described. In Comparative Example 2, the quality of GaN constituting the channel layer 114 is increased. That is, the concentration of impurities such as carbon (C) contained in GaN in Comparative Example 2 is lower than that in Comparative Example 1. Other configurations are the same as those shown in FIG. In order to reduce the concentration of impurities, for example, there is a method of increasing the growth temperature in an MOCVD method (Metal Organic Chemical Vapor Deposition) for growing the channel layer 114. For example, in Comparative Example 1, the growth temperature is 1100 ° C., and in Comparative Example 2, the growth temperature is 1200 ° C. Next, the band structure will be described.

  FIG. 2A is a schematic view illustrating the band structure of the HEMT according to Comparative Example 1. FIG. 2B is a schematic view illustrating the band structure of the HEMT according to Comparative Example 2. Ef indicated by a broken line represents Fermi energy. Ec indicated by a solid line represents the energy at the bottom of the conduction band. Et indicated by a dotted line represents the energy of a deep level (trap) below the conduction band. In FIG. 2A and FIG. 2B, regions corresponding to the respective portions of the HEMT are denoted by the same reference numerals as those in FIG. The hatched area indicates 2DEG. As described above, 2DEG becomes a carrier and a drain current flows. However, when an electrical stress is applied, the drain current may fluctuate with time.

  As shown in FIG. 2A, Ec in the channel layer 114 is high. For example, the energy difference Ec−Ef in the vicinity of the interface between the channel layer 114 and the buffer layer 112 is about 1.5 eV. In the region on the buffer layer 112 side of the channel layer 114, the trap energy Et is higher than the Fermi energy Ef. Since the trap is ionized, electrons that have become high energy due to electrical stress or the like can be captured. That is, 2DEG electrons may be trapped in the trap. Due to electron capture, the concentration of 2DEG decreases. As the concentration of 2DEG decreases, the HEMT drain current decreases. In addition, trapped electrons may be emitted. Thus, the drain current may vary with time.

  As shown in FIG. 2B, in Comparative Example 2, the energy Ec of the conduction band of the channel layer 114 is lower than Ec in Comparative Example 1. This is because the quality of GaN forming the channel layer 114 is improved, and the contribution of impurities such as C, which become acceptors, is reduced. Thereby, the resistance of the channel layer 114 is reduced. The energy difference Ec−Ef in the vicinity of the interface between the channel layer 114 and the buffer layer 112 is, for example, about 0.4 to 0.6 eV. The trap energy Et is lower than the Fermi energy Ef. Since the trap is occupied by electrons, capture of 2DEG electrons in the trap is suppressed. As a result, the fluctuation of the drain current is suppressed.

  However, in FIG. 2B, the energy Ec decreases over the entire channel layer 114. For this reason, even in the vicinity of 2DEG, the energy Ec decreases and the energy difference Ec−Ef decreases. As a result, the gradient of energy Ec becomes gentle from the channel layer 114 to the buffer layer 112. In other words, the barrier near 2DEG is lowered. Therefore, when a voltage is applied between the source and the drain, the 2DEG electrons easily get over the barrier. As a result, in Comparative Example 2, there is a possibility that the leakage current increases and the pinch-off characteristic is deteriorated.

  Due to the difference in band structure as described above, a difference occurs in the IV characteristic. The influence of the band structure on the IV characteristics will be described. As an evaluation of the IV characteristics, buffer leak and pinch freak were evaluated.

  The evaluation of the buffer leak is to evaluate the electric field strength dependence of the current flowing through the region on the electron supply layer 116 side of the channel layer 114 (hereinafter referred to as “buffer leak current”). The behavior of electrons in the region near the electron supply layer 116 of the channel layer 114 affects the buffer leak. The evaluation of the pinch freak is to evaluate the electric field strength dependence of the current flowing through the region on the buffer layer 112 side of the channel layer 114 (referred to as “pinch freak current”). The behavior of electrons in a region near the buffer layer 112 of the channel layer 114 affects the pinch freak.

  A sample will be described. FIG. 3A is a schematic view illustrating a sample for buffer leak evaluation. Arrows represent the flow of electrons.

  As shown in FIG. 3A, a sample 100A for buffer leak evaluation includes a substrate 110, a buffer layer 112, a channel layer 114, an electron supply layer 116, a source electrode 120, and a drain electrode 122. The gate electrode 124 is not provided. The material and dimensions of the substrate 110 and each layer are the same as those illustrated in FIG. The source electrode 120 and the drain electrode 122 are formed by stacking Ti / Al from the side closer to the electron supply layer 116. Part of the channel layer 114 and the electron supply layer 116 is removed by, for example, etching. Etching is, for example, RIE (Reactive Ion Etching) using a chlorine-based etchant. By etching, a recess 114 c that penetrates the electron supply layer 116 is formed on the upper surface of the channel layer 114. The recess 114c is located between the source electrode 120 and the drain electrode 122, and has a width W of 2000 nm and a depth D of 100 nm. The width direction is the left-right direction in FIG. The depth direction is the vertical direction of FIG.

  By applying a voltage between the source electrode 120 and the drain electrode 122 of the sample 100A, a buffer leak current flows between the source and the drain. As shown by arrows in FIG. 3A, electrons mainly flow in a region on the electron supply layer 116 side of the channel layer 114.

  Using the sample 100A having the channel layer 114 formed of GaN that has not been improved in quality, the electric field strength dependence of the buffer leakage current in Comparative Example 1 was evaluated. Using the sample 100A having the channel layer 114 made of high quality GaN, the electric field strength dependence of the buffer leakage current in Comparative Example 2 was evaluated.

  FIG. 3B is a schematic view illustrating a sample for pinch freak evaluation. The lattice diagonal line in FIG. 3B represents a depletion layer.

  As shown in FIG. 3B, HEMT 100R was used as a sample 100B for pinch freak evaluation. The materials and dimensions are the same as those illustrated in FIG. The source electrode 120 and the drain electrode 122 are formed by stacking Ti / Al from the side closer to the electron supply layer 116. The gate electrode 124 is formed by stacking Ni / Au from the side closer to the electron supply layer 116. The length L of the gate electrode 124 is 1 μm. The length direction is the left-right direction in FIG. By applying a voltage of −3 V to the gate electrode 124, the depletion layer 118 is formed up to a deep position of the channel layer 114. By applying a voltage between the source electrode 120 and the drain electrode 122 of the sample 100B, a drain current flows. As indicated by arrows in FIG. 3B, electrons mainly flow in a region on the buffer layer 112 side of the channel layer 114. As shown in FIG. 3B, the pinch freak is evaluated by evaluating the IV characteristics in a state where the depletion layer 118 is formed.

  Using the sample 100B having the channel layer 114 formed of GaN that has not been improved in quality, the electric field strength dependence of the pinch freak current in Comparative Example 1 was evaluated. Using the sample 100B having the channel layer 114 formed of high quality GaN, the electric field strength dependence of the pinch freak current in Comparative Example 2 was evaluated.

  First, the buffer leak will be described. FIG. 4A is a schematic diagram illustrating the field strength dependence of the buffer leakage current in Comparative Example 1. FIG. 4B is a schematic view illustrating the field strength dependence of the buffer leakage current in Comparative Example 2. The horizontal axis represents the electric field intensity, and the vertical axis represents the buffer leakage current. The electric field strength is the strength of the electric field between the source and the drain, and depends on the source-drain voltage.

  As shown in FIG. 4A and FIG. 4B, the buffer leakage current increases as the electric field strength increases. The increase in the buffer leakage current is larger in Comparative Example 2 than in Comparative Example 1. For example, in Comparative Example 1, when the electric field strength is E1, the buffer leakage current is I1. In Comparative Example 2, when the electric field strength is E1, the buffer leakage current becomes I2 larger than I1.

  As shown in FIG. 2A, in Comparative Example 1, it is difficult for electrons to get over the barrier in the channel layer 14 between the source and the drain. For this reason, as shown in FIG. 4A, the buffer leak current is smaller in the first comparative example than in the second comparative example. As shown in FIG. 2B, the energy difference Ec−Ef in the vicinity of 2DEG in Comparative Example 2 is smaller than that in Comparative Example 1. Therefore, 2DEG electrons easily get over the barrier in the channel layer 14 between the source and drain. In other words, a buffer leak current tends to flow through the channel layer 114. As a result, as shown in FIG. 4B, the buffer leakage current increases in the comparative example 2.

  Next, pinch freaks will be described. FIG. 5A is a schematic view illustrating the electric field strength dependence of the pinch freak current in Comparative Example 1. FIG. FIG. 5B is a schematic view illustrating the electric field strength dependence of the pinch freak current in Comparative Example 2. The vertical axis represents the pinch freak current.

  As shown in FIG. 5A and FIG. 5B, the pinch freak current increases as the electric field strength between the source and the drain increases. The increase in pinch freak current is greater in Comparative Example 2 than in Comparative Example 1. For example, in the comparative example 1, when the electric field strength is E2, the pinch freak current is I3. In Comparative Example 2, when the electric field strength is E2, the pinch freak current is I4 larger than I3.

  As shown in FIG. 2A, Ec is high in the region near the buffer layer 112 of the channel layer 114 in the first comparative example. For this reason, pinch freak current is suppressed. As shown in FIG.2 (b), in the comparative example 2, since Ec-Ef is small, pinch freak current increases.

  As described above, in Comparative Example 1, since the energy difference Ec−Ef in the region on the electron supply layer 116 side of the channel layer 114 is high, the buffer leak current and the pinch freak current are small. However, a trap in which electrons are not captured is formed in a region of the channel layer 114 on the buffer layer 112 side. Since electrons having high energy are trapped in the trap, the drain current varies.

  In Comparative Example 2, the trap energy Et decreases in the region of the channel layer 114 on the buffer layer 112 side. Accordingly, fluctuations in the drain current due to electron capture are suppressed. However, the energy difference Ec−Ef in the region on the electron supply layer 116 side of the channel layer 114 is low. Due to the source-drain voltage, high energy electrons overcome the barrier in the channel layer 114. Thereby, the pinch-off characteristic is deteriorated. Thus, in the HEMT, it has been difficult to achieve both suppression of current fluctuation and ensuring pinch-off characteristics.

  Embodiments of the present invention will be described with reference to the drawings.

  FIG. 6A is a cross-sectional view illustrating a HEMT according to the first embodiment. The description of the same configuration as that already described in FIG. 1 is omitted.

  As shown in FIG. 6A, the HEMT 100 according to the first embodiment includes a substrate 10, a buffer layer 12, a channel layer 14, an electron supply layer 16, a source electrode 20, a drain electrode 22, a gate electrode 24, and a protective layer 26. Prepare. The buffer layer 12 is in contact with the upper surface of the substrate 10, for example. For example, the channel layer 14 is in contact with the upper surface of the buffer layer 12. The electron supply layer 16 is in contact with the upper surface of the channel layer 14, for example. The source electrode 20, the drain electrode 22, and the gate electrode 24 are in contact with, for example, the upper surface of the electron supply layer 16.

As indicated by a broken line in FIG. 6A, the channel layer 14 includes two regions 14a and 14b. A region on the buffer layer 12 side of the channel layer 14 is a region 14a, and a region on the electron supply layer 16 side is a region 14b. The concentration of C in the region 14b is, for example, 4 × 10 ¹⁶ atoms / cm ³ or more. The concentration of C in the region 14a is, for example, 2 × 10 ¹⁶ atoms / cm ³ or less. Thus, the concentration of C in the region 14b is higher than the concentration of C in the region 14a. The total value of the concentration of silicon (Si) and the concentration of oxygen (O) in the region 14b is, for example, 1 × 10 ¹⁶ atoms / cm ³ or less. The total value of the Si concentration and the O concentration in the region 14a is, for example, 2 × 10 ¹⁶ atoms / cm ³ or more. Thus, the total value of the Si concentration and the O concentration in the region 14b is smaller than the total value of the Si concentration and the O concentration in the region 14a. The thickness of each of the region 14a and the region 14b is, for example, 600 nm. Next, the band structure will be described.

  FIG. 6B is a schematic view illustrating the band structure of the HEMT according to the first embodiment. When FIG. 6B is compared with FIG. 2A, Ec decreases in the region 14a. On the other hand, Ec hardly decreases in the region 14b. In other words, Ec-Ef is kept high in the region 14b. The energy of the conduction band on the channel layer 14 side of the buffer layer 12 is Eb1. The energy of the buffer layer 12 will be described later in Example 2.

  The concentration of C in the region 14b is high. In other words, the concentration of acceptor impurities (acceptor concentration) is high. Further, the total value of the Si concentration and the O concentration is small. In other words, the impurity concentration (donor concentration) serving as a donor is low. The resistivity depends on the acceptor concentration-donor concentration, which is the difference between the acceptor concentration and the donor concentration. In the region 14b, the acceptor concentration-donor concentration is high. As a result, the region 14b has a high resistance. In other words, Ec increases. For this reason, a steep barrier is formed in the vicinity of 2DEG. Therefore, it becomes difficult for 2DEG electrons to cross the barrier.

  In the region 14a, Ec-Ef is small. Ec-Ef in the vicinity of the interface between the channel layer 14 and the buffer layer 12 is, for example, about 0.4 to 0.6 eV. The concentration of C in the region 14a is low. In other words, the concentration of impurities serving as acceptors is low. The total value of the Si concentration and the O concentration in the region 14a is large. In other words, the concentration of impurities serving as donors is high. As a result, the resistance of the region 14a is reduced. Thus, Ec-Ef becomes small. As Ec−Ef becomes smaller, the trap energy Et becomes smaller than the Fermi energy Ef. The trap is occupied by electrons. As a result, trapping of electrons having high energy in the trap is suppressed.

  The buffer leak and the pinch freak in Example 1 will be described. First, a sample will be described. FIG. 7A is a schematic view illustrating a sample for buffer leak evaluation. As shown in FIG. 7A, a recess 14 c is formed in the channel layer 14. As shown by arrows in FIG. 7A, in the sample 100C, electrons mainly flow through the region 14b of the channel layer 14.

  FIG. 7B is a schematic view illustrating a sample for pinch freak evaluation. The description of the configuration already described in FIGS. 3B and 6A is omitted. As shown in FIG. 6B, a depletion layer 18 is formed. As indicated by the arrows, in the sample 100D, electrons mainly flow through the region 14a of the channel layer 14.

  FIG. 8A is a schematic view illustrating the field strength dependence of the buffer leakage current in the first embodiment. As shown in FIG. 8A, when the electric field strength is E1, the buffer leakage current is I5. I5 is smaller than I2 shown in FIG. 4B, and is about the same size as I1 shown in FIG. 4A, for example. This is because, as shown in FIG. 6B, a high barrier is formed in the region 14b and it is difficult for electrons to get over the barrier between the source and the drain.

  FIG. 8B is a schematic view illustrating the electric field strength dependence of the pinch freak current in the first embodiment. As shown in FIG. 8B, when the electric field strength is E2, the pinch freak current is I6. I6 is larger than I3 shown in FIG. 5A, and is about the same size as I4 shown in FIG. 5B, for example.

  Next, a method for manufacturing the HEMT 100 according to the first embodiment will be described. FIG. 9A to FIG. 10B are cross-sectional views illustrating a method for manufacturing the HEMT according to the first embodiment.

As shown in FIG. 9A, first, the buffer layer 12 made of AlN having a thickness of, for example, 25 nm is epitaxially grown on the substrate 10 made of SiC by using the MOCVD method. The growth conditions of the buffer layer 12 are shown below. The growth temperature is the temperature of the substrate during growth. The growth pressure is the pressure in the furnace used for the MOCVD method.
Growth temperature: 1100 ° C
Growth pressure: 20 kPa
Ingredients: trimethylaluminum (TMA: Tri Methyl Aluminum), ammonia _(NH 3)

As shown in FIG. 9B, the region 14a of the channel layer 14 made of GaN having a thickness of, for example, 600 nm is epitaxially grown on the buffer layer 12 by MOCVD. The growth conditions are shown below.
Growth temperature: 1200 ° C
Growth pressure: 20 kPa
Growth rate: 0.3 nm / sec
Raw material: Trimethyl Gallium (TMG), NH ₃
TMG flow rate: 90 μmol / min
NH ₃ flow rate: 0.9 mol / min

As shown in FIG. 9C, a GaN region 14b having a thickness of 600 nm, for example, is epitaxially grown on the region 14a by MOCVD. The growth conditions are shown below.
Growth temperature: 1100 ° C
Other growth conditions are the same as the growth conditions of the region 14a. Thus, the growth temperature of the region 14a is higher than the growth temperature of the region 14b. Region 14 a and region 14 b form channel layer 14. The step of providing the channel layer 14 includes a step of providing the region 14a and a step of providing the region 14b.

As shown in FIG. 10A, an electron supply layer 16 made of, for example, AlGaN having a thickness of 20 nm is epitaxially grown on the channel layer 14 by MOCVD. The growth conditions are shown below.
Growth temperature: 1100 ° C
Growth pressure: 20 kPa
Raw materials: TMA, TMG, NH ₃

  As shown in FIG. 10B, a first SiN layer is provided on the electron supply layer 16 by using, for example, a plasma CVD method (Plasma Chemical Vapor Deposition). The first SiN layer is patterned to expose the electron supply layer 16. An ohmic electrode made of a metal such as Ti / Al is formed on the exposed electron supply layer 16 by, for example, vapor deposition. The ohmic electrode functions as the source electrode 20 and the drain electrode 22. Further, the first SiN layer is patterned to expose the electron supply layer 16. For example, the gate electrode 24 made of a metal such as Ni / Au is formed on the electron supply layer 16 by vapor deposition or the like. A second SiN layer is provided on the first SiN layer. The protective layer 26 is formed by the first SiN layer and the second SiN layer. Through the above steps, the HEMT 100 according to the first embodiment is formed.

  The HEMT 100 according to the first embodiment includes a substrate 10 made of SiC, a buffer layer 12 made of AlN, a channel layer 14 made of GaN, an electron supply layer 16 made of AlGaN, a source electrode 20, a drain electrode 22, A gate electrode 24. The C concentration in the region 14b of the channel layer 14 on the electron supply layer 16 side is higher than the C concentration in the region 14a of the channel layer 14 on the buffer layer 12 side. Therefore, a high barrier is formed in the vicinity of 2DEG. In the region 14a, Ec-Ef decreases, and the trap energy Et becomes lower than the Fermi energy Ef. In other words, the resistance of the region 14a is reduced and the resistance of the region 14b is increased. Therefore, according to the first embodiment, the fluctuation of the drain current can be suppressed and the pinch-off characteristics can be ensured.

  The total value of the Si concentration and the O concentration in the region 14b is smaller than the total value of the Si concentration and the O concentration in the region 14a. For this reason, the region 14a has a low resistance, and the region 14b has a high resistance. Therefore, according to the first embodiment, it is possible to suppress the fluctuation of the current and secure the pinch-off characteristics.

The concentration of C in the region 14a is 2 × 10 ¹⁶ atoms / cm ³ or less, but may be, for example, 1.5 × 10 ¹⁶ atoms / cm ³ or less, or 1 × 10 ¹⁶ atoms / cm ³ or less. The total value of the concentration of Si and the concentration of O in the region 14a is 2 × 10 ¹⁶ atoms / cm ³ or more. For example, it is 2.5 × 10 ¹⁶ atoms / cm ³ or more, or 3 × 10 ¹⁶ atoms / cm ^3. It is good also as above. As described above, in the region 14a, it is preferable to reduce the concentration of impurities such as C serving as an acceptor and increase the concentration of impurities such as Si and O serving as donors.

The concentration of C in the region 14b is set to 4 × 10 ¹⁶ atoms / cm ³ or more, but may be set to 4.5 × 10 ¹⁶ atoms / cm ³ or more, or 5 × 10 ¹⁶ atoms / cm ³ or more, for example. The total value of the Si concentration and the O concentration in the region 14b is set to 1 × 10 ¹⁶ atoms / cm ³ or less, for example, 0.8 × 10 ¹⁶ atoms / cm ³ or less, or 0.5 × 10 ¹⁶ atoms / cm ^3. It is good also as cm < ³ > or less. Thus, in the region 14b, it is preferable to increase the concentration of impurities such as C serving as an acceptor and to decrease the concentration of impurities such as Si and O serving as donors. The difference between the acceptor concentration and the donor concentration in the region 14b is preferably larger than the difference between the acceptor concentration and the donor concentration in the region 14a.

The concentration of C in the region 14a may be, for example, less than 2 × 10 ¹⁶ atoms / cm ^3, less than 1.5 × 10 ¹⁶ atoms / cm ³ , or less than 1 × 10 ¹⁶ atoms / cm ³ . The total value of the Si concentration and the O concentration in the region 14a is larger than, for example, 2 × 10 ¹⁶ atoms / cm ³ , 2.5 × 10 ¹⁶ atoms / cm ³ , or 3 × 10 ¹⁶ atoms / cm ³ , respectively. May be. The concentration of C in the region 14b may be larger than each of 4 × 10 ¹⁶ atoms / cm ³ , 4.5 × 10 ¹⁶ atoms / cm ³ , or 5 × 10 ¹⁶ atoms / cm ³ , for example. The total value of the Si concentration and the O concentration in the region 14b is, for example, less than 1 × 10 ¹⁶ atoms / cm ^3, less than 0.8 × 10 ¹⁶ atoms / cm ³ , or 0.5 × 10 ¹⁶ atoms / cm ^3. It may be less.

  In order to manufacture the channel layer 14 having the impurity concentration as described above, the growth conditions may be adjusted. For example, as described in FIGS. 9A and 9B, the growth temperature of the region 14a is preferably higher than the growth temperature of the region 14b. Increasing the growth temperature can suppress the incorporation of C into GaN. Further, incorporation of Si and O into GaN is promoted. Although the growth temperature of the region 14a is 1200 ° C. and the growth temperature of the region 14b is 1100 ° C., the growth temperature can be changed. The growth temperature of the region 14a is preferably 40 ° C. or higher than the growth temperature of the region 14b. The difference in growth temperature may be, for example, 50 ° C. or higher, 100 ° C. or higher, or 120 ° C. or higher.

In order to make the regions 14a and 14b have a desired composition, in addition to the growth temperature, for example, the growth rate, the growth pressure, or the amount of the raw material may be changed. An example of the growth rate is shown.
Growth rate of region 14a: 1.0 μm / h
Growth rate of region 14b: 2.0 μm / h
Thus, the growth rate of the region 14b is larger than the growth rate of the region 14a. Thereby, the C concentration in the region 14b can be made higher than the C concentration in the region 14a. Further, the total value of the Si concentration and the O concentration in the region 14b can be made lower than the total value of the Si concentration and the O concentration in the region 14a. In particular, the growth rate of the region 14b is preferably 1.5 times or more the growth rate of the region 14a. The ratio of the growth rates may be, for example, 1.8 times or more or 2 times or more.

An example of growth pressure is shown.
Growth pressure of region 14a: 300 torr (39.99 kPa)
Growth pressure of region 14b: 150 torr (19.99 kPa)
Thus, the growth pressure in the region 14a is higher than the growth pressure in the region 14b. Thereby, the C concentration in the region 14b can be made higher than the C concentration in the region 14a. In particular, the growth pressure in the region 14a is preferably higher than the growth pressure in the region 14b by 13.33 kPa (100 torr) or more. The difference in growth pressure may be, for example, 150 torr or more, or 200 torr or more.

An example of the flow rate ratio of NH ₃ is shown. The flow rate ratio is the ratio of the flow rate of NH _{3 to} the flow rate of all gases that are raw materials.
NH ₃ flow rate ratio in the step of providing the region 14a: 2000
NH ₃ flow rate ratio in the step of providing the region 14b: 4000
Thus, the flow rate ratio of NH _{3 in} the step of providing the region 14a is made larger than the flow rate ratio of NH _{3 in} the step of providing the region 14b. Thereby, the C concentration in the region 14b can be made higher than the C concentration in the region 14a. The flow rate ratio of NH _{3 in} the step of providing the region 14a is preferably 1.5 times or more than the flow rate ratio of NH _{3 in} the step of providing the region 14b.

In Example 1, both the C concentration and the total value of the Si concentration and the O concentration were made different between the region 14a and the region 14b. The configuration is not limited to this. For example, in the channel layer 14, the C concentration in the region 14b is higher than the C concentration in the region 14a, and the sum of the Si concentration and the O concentration in the region 14b is the sum of the Si concentration and the O concentration in the region 14a. You may have at least one structure of smaller than a total value. In the first embodiment, the example in which the growth temperature, the growth rate, the growth pressure, and the flow rate ratio of NH ₃ are independently adjusted has been described. The channel layer 14 may be grown by changing all of the growth temperature, the growth rate, the growth pressure, and the NH ₃ flow ratio, or two or more conditions. For example, a cap layer made of a nitride semiconductor such as GaN may be provided on the electron supply layer 16, and each electrode may be provided on the cap layer.

  Further, although the example in which the composition of the channel layer 14 changes discretely between the region 14a and the region 14b has been described, the configuration is not limited thereto. For example, the composition of the channel layer 14 may change continuously. Specifically, even if the concentration of C is continuously increased from the buffer layer 12 side to the electron supply layer 16 side of the channel layer 14 and the total value of the Si concentration and the O concentration is continuously decreased. Good. The composition may be different between the region 14a and the region 14b, and the composition may continuously change in the vicinity of the boundary between the region 14a and the region 14b. The channel layer 14 may include three or more regions having different compositions. In the step of providing the channel layer 14, the channel layer 14 may be grown while continuously changing the growth conditions. The channel layer 14 may be grown using three or more different growth conditions.

  Example 2 is an example in which the impurity concentration of the buffer layer 12 is changed. FIG. 11A is a cross-sectional view illustrating a HEMT according to the second embodiment. The description of the configuration described above with reference to FIGS. 1A and 6A is omitted.

  As shown in FIG. 11A, the HEMT 200 according to the second embodiment includes a substrate 10, a buffer layer 12, a channel layer 14, an electron supply layer 16, a source electrode 20, a drain electrode 22, a gate electrode 24, and a protective layer 26. Prepare.

The buffer layer 12 is made of AlN. The concentration of C in the buffer layer 12 is 2 × 10 ¹⁹ atoms / cm ³ or less. The concentration of Si in the buffer layer 12 is, for example, 5 × 10 ¹⁷ atoms / cm ³ . The total value of the Si concentration and the O concentration in the buffer layer 12 is 2 × 10 ¹⁷ atoms / cm ³ or more. Thus, in the buffer layer 12, the concentration of the impurity serving as an acceptor is low and the concentration of the impurity serving as a donor is high. Therefore, the resistance of the buffer layer 12 is reduced.

  The band structure will be described. FIG. 11B is a schematic view illustrating the band structure of the HEMT according to the second embodiment.

  As shown in FIG. 11B, the energy of the conduction band of the buffer layer 12 is Eb2. Eb2 is lower than the energy Eb1 in the first embodiment. Due to the reduction in energy of the buffer layer 12, the conduction band is lowered in the region 14a on the buffer layer 12 side of the channel layer 14. In other words, Ec-Ef becomes small in the region 14a. For this reason, the trap energy Et is smaller than the Fermi energy Ec. As a result, the trapping of electrons in the trap is suppressed. On the other hand, Ec-Ef is kept high in the region 14b. For this reason, it is suppressed that an electron gets over a barrier.

  Next, a method for manufacturing the HEMT 200 according to the second embodiment will be described. FIG. 12A and FIG. 12B are cross-sectional views illustrating a method for manufacturing the HEMT according to the second embodiment. The description of the configuration already described in the first embodiment is omitted.

As shown in FIG. 12A, a buffer layer 12 made of AlN having a thickness of 25 nm is epitaxially grown on the substrate 10 by MOCVD. The growth conditions are shown below.
Growth temperature: 1100 ° C
Growth pressure: 20 kPa
Growth rate: 0.5 μm / h or less Raw materials: TMA, TMG, NH ₃ , SiH ₄ (silane)
The buffer layer 12 made of AlN doped with SiH ₄ contained in the raw material is formed as a dopant. The concentration of Si in the buffer layer 12 is, for example, 5 × 10 ¹⁷ atoms / cm ³ .

As shown in FIG. 12B, a channel layer 14 made of GaN having a thickness of 1200 nm is epitaxially grown on the buffer layer 12 by MOCVD. The step of providing the channel layer 14 does not use different growth conditions depending on the region, but uses the same growth conditions in the entire channel layer 14. The growth conditions are shown below.
Growth temperature: 1100 ° C
Growth pressure: 20 kPa
Growth rate: 0.3 μm / sec
Ingredients: TMG, NH ₃
TMG flow rate: 90 μmol / min
NH ₃ flow rate: 0.9 mol / min

The HEMT 200 according to the second embodiment includes a substrate 10 made of SiC, a buffer layer 12 made of AlN, a channel layer 14 made of GaN, an electron supply layer 16 made of AlGaN, a source electrode 20, a drain electrode 22, A gate electrode 24. The concentration of C in the buffer layer 12 is 2 × 10 ¹⁹ atoms / cm ³ or less. The total value of the Si concentration and the O concentration in the buffer layer 12 is 2 × 10 ¹⁷ atoms / cm ³ or more. In the buffer layer 12, the acceptor concentration-donor concentration is small. Therefore, the resistance of the buffer layer 12 is reduced. For this reason, the energy of the conduction band of the buffer layer 12 is reduced to Eb2. In the region 14a of the channel layer 14, Ec-Ef decreases. For this reason, the capture of electrons is suppressed. Further, a high barrier is formed in the region 14b. For this reason, according to Example 2, the fluctuation | variation of an electric current can be suppressed and pinch-off characteristics can be ensured.

C concentration in the buffer layer 12 is, for example, 1.5 × ¹⁰ 19 atoms / cm ³ or less, or 1 × ¹⁰ 19 atoms / cm ³ or below. The concentration of C in the buffer layer 12 may be less than 2 × 10 ¹⁹ atoms / cm ^3, less than 1.5 × 10 ¹⁹ atoms / cm ³ , or less than 1 × 10 ¹⁹ atoms / cm ³ . The total value of the Si concentration and the O concentration in the buffer layer 12 may be, for example, 2.5 × 10 ¹⁷ atoms / cm ³ or more, or 3 × 10 ¹⁷ atoms / cm ³ or more. The total value of the Si concentration and the O concentration in the buffer layer 12 is 2 × 10 ¹⁷ atoms / cm ³ , 2.5 × 10 ¹⁷ atoms / cm ³ , or 3 × 10 ¹⁷ atoms / cm ³ , respectively. It can be large. The buffer layer 12 has at least one of, for example, a C concentration of 2 × 10 ¹⁹ atoms / cm ³ or less and a total value of the Si concentration and the O concentration of 2 × 10 ¹⁷ atoms / cm ³ or more. May be.

In order to form the buffer layer 12 with reduced resistance, the growth conditions of the buffer layer 12 may be adjusted. When the growth temperature is higher, the incorporation of C into AlN is suppressed. Also, the smaller the growth rate, the more C uptake into AlN is suppressed. The growth temperature may be 1100 ° C., the growth rate may be 0.5 μm / h or less, and SiH ₄ may be included in the raw material. A source gas containing Si other than SiH ₄ such as disilane (Si ₂ H ₆ ) may be used. The growth temperature can be 1050 ° C. or higher, for example, 1150 ° C. or higher and 1200 ° C. or higher. The growth temperature may be higher than 1050 ° C, 1100 ° C, 1150 ° C, or 1200 ° C. Although the growth rate is 0.5 μm / h or less, it may be 0.4 μm / h or less, or 0.3 μm / h or less. The growth rate may be less than 0.5 μm / h, less than 0.4 μm / h, or less than 0.3 μm / h.

  The first embodiment and the second embodiment may be combined. That is, the resistance of the region 14a of the channel layer 14 may be increased, the resistance of the region 14b may be decreased, and the resistance of the buffer layer 12 may be decreased. In the HEMT manufacturing process, the buffer layer 12 is provided according to the growth conditions described in FIG. 10A, and the regions 14a and 14b are provided according to the growth conditions described in FIGS. 9B and 9C. May be.

  The electron supply layer 16 is made of AlGaN, but may be made of a nitride semiconductor other than AlGaN. A nitride semiconductor is a semiconductor containing nitrogen (N), such as indium aluminum nitride (InAlN), indium gallium nitride (InGaN), indium nitride (InN), and aluminum indium gallium nitride (AlInGaN). The electron supply layer 16 may be made of InAlN, AlInGaN, or the like among nitride semiconductors.

  Although the embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and changes can be made within the scope of the gist of the present invention described in the claims. It can be changed.

10 substrate 12 buffer layer 14 channel layer 14a, 14b region 16 electron supply layer 20 source electrode 22 drain electrode 24 gate electrode 100, 200 HEMT

Claims (15)

A substrate made of silicon carbide;
A buffer layer provided on the substrate and made of aluminum nitride;
A channel layer provided on the buffer layer and made of gallium nitride;
An electron supply layer provided on the channel layer and made of a nitride semiconductor;
A source electrode, a drain electrode and a gate electrode provided on the electron supply layer,
The semiconductor device, wherein a concentration of carbon in a region on the electron supply layer side of the channel layer is higher than a concentration of carbon in a region on the buffer layer side of the channel layer. The concentration of carbon in the region on the electron supply layer side of the channel layer is 4 × 10 ¹⁶ atoms / cm ³ or more, and the concentration of carbon in the region on the buffer layer side of the channel layer is 2 × 10 ¹⁶ atoms / cm 3. The semiconductor device according to claim 1, wherein the semiconductor device is ³ or less. A substrate made of silicon carbide;
A buffer layer provided on the substrate and made of aluminum nitride;
A channel layer provided on the buffer layer and made of gallium nitride;
An electron supply layer provided on the channel layer and made of a nitride semiconductor;
A source electrode, a drain electrode and a gate electrode provided on the electron supply layer,
The total value of the silicon concentration and the oxygen concentration in the region on the electron supply layer side of the channel layer is smaller than the total value of the silicon concentration and the oxygen concentration in the buffer layer side region of the channel layer. A semiconductor device characterized by the above. The total value of the silicon concentration and the oxygen concentration in the region on the electron supply layer side of the channel layer is 1 × 10 ¹⁶ atoms / cm ³ or less, and the silicon concentration in the region on the buffer layer side of the channel layer 4. The semiconductor device according to claim 3, wherein a total value of the concentration of oxygen and oxygen is 2 × 10 ¹⁶ atoms / cm ³ or more. A substrate made of silicon carbide;
A buffer layer provided on the substrate and made of aluminum nitride;
A channel layer provided on the buffer layer and made of gallium nitride;
An electron supply layer provided on the channel layer and made of a nitride semiconductor;
A source electrode, a drain electrode and a gate electrode provided on the electron supply layer,
The semiconductor device according to claim 1, wherein the buffer layer has a carbon concentration of 2 × 10 ¹⁹ atoms / cm ³ or less. A substrate made of silicon carbide;
A buffer layer provided on the substrate and made of aluminum nitride;
A channel layer provided on the buffer layer and made of gallium nitride;
An electron supply layer provided on the channel layer and made of a nitride semiconductor;
A source electrode, a drain electrode and a gate electrode provided on the electron supply layer,
2. A semiconductor device according to claim 1, wherein a total value of oxygen concentration and silicon concentration in the buffer layer is 2 × 10 ¹⁷ atoms / cm ³ or more. Providing a buffer layer made of aluminum nitride on a substrate made of silicon nitride;
Providing a channel layer made of gallium nitride on the buffer layer by MOCVD;
Providing an electron supply layer made of a nitride semiconductor on the channel layer;
Providing a source electrode, a drain electrode, and a gate electrode on the electron supply layer,
A growth method of a region of the channel layer on the buffer layer side is higher than a growth temperature of a region of the channel layer on the electron supply layer side.   8. The method of manufacturing a semiconductor device according to claim 7, wherein the growth temperature of the region on the buffer layer side of the channel layer is 40 ° C. or more higher than the growth temperature of the region on the electron supply layer side of the channel layer. . Providing a buffer layer made of aluminum nitride on a substrate made of silicon nitride;
Providing a channel layer made of gallium nitride on the buffer layer by MOCVD;
Providing an electron supply layer made of a nitride semiconductor on the channel layer;
Providing a source electrode, a drain electrode, and a gate electrode on the electron supply layer,
A method for manufacturing a semiconductor device, wherein a growth rate of a region of the channel layer on the electron supply layer side is higher than a growth rate of a region of the channel layer on the buffer layer side.   10. The semiconductor device according to claim 9, wherein a growth rate of a region of the channel layer on the electron supply layer side is 1.5 times or more a growth rate of a region of the channel layer on the buffer layer side. Growth method. Providing a buffer layer made of aluminum nitride on a substrate made of silicon nitride;
Providing a channel layer made of gallium nitride on the buffer layer by MOCVD;
Providing an electron supply layer made of a nitride semiconductor on the channel layer;
Providing a source electrode, a drain electrode, and a gate electrode on the electron supply layer,
A growth method of a semiconductor device, wherein a growth pressure of a region of the channel layer on the buffer layer side is higher than a growth pressure of a region of the channel layer on the electron supply layer side.   12. The method for growing a semiconductor device according to claim 11, wherein the growth pressure of the region on the buffer layer side of the channel layer is 13.33 kPa or more higher than the growth pressure of the region on the electron supply layer side of the channel layer. . Providing a buffer layer made of aluminum nitride on a substrate made of silicon nitride;
A step of providing a channel layer made of gallium nitride on the buffer layer by MOCVD using ammonia as a raw material;
Providing an electron supply layer made of a nitride semiconductor on the channel layer;
Providing a source electrode, a drain electrode, and a gate electrode on the electron supply layer,
The growth rate of the semiconductor device is characterized in that the flow rate ratio of ammonia in the step of providing the region on the buffer layer side of the channel layer is larger than the flow rate ratio of ammonia in the step of providing the region on the electron supply layer side of the channel layer. Method. Providing a buffer layer made of aluminum nitride on a substrate made of silicon nitride by MOCVD using a source gas containing silicon;
Providing a channel layer made of gallium nitride on the buffer layer;
Providing an electron supply layer made of a nitride semiconductor on the channel layer;
And a step of providing a source electrode, a drain electrode and a gate electrode on the electron supply layer. Providing a buffer layer made of aluminum nitride on a substrate made of silicon nitride by MOCVD;
Providing a channel layer made of gallium nitride on the buffer layer;
Providing an electron supply layer made of a nitride semiconductor on the channel layer;
Providing a source electrode, a drain electrode, and a gate electrode on the electron supply layer,
A method for manufacturing a semiconductor device, wherein the growth rate of the buffer layer is 0.5 μm / h or less.

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