JP5664262B2 - Field effect transistor and epitaxial wafer for field effect transistor - Google Patents

Description

  The present invention relates to a field effect transistor using a nitride semiconductor.

  Nitride semiconductors composed of indium, gallium, aluminum, and nitrogen are materials such as innovative high-efficiency light-emitting devices that cover most regions from ultraviolet to visible light by controlling the composition ratio of group III elements. Is being developed (see, for example, Patent Document 1).

  Since this type of nitride semiconductor has a high saturation electron velocity and a high breakdown voltage, it is very promising as a material for electronic devices that realizes orders of magnitude higher efficiency and higher output in the high frequency region.

JP 2009-231561 A

  An object of the present invention is to provide a field effect transistor with improved breakdown voltage.

  The inventors of the present invention conducted an enthusiastic examination on the improvement of the withstand voltage of the field effect transistor, and as a result, surprisingly, the nitride compound semiconductor layer is not doped with a transition metal such as iron in claims 1 to 3 of the present invention. It has been found that this invention can be achieved effectively.

[1] That is, the present invention is formed on a substrate, a first nitride semiconductor layer formed on the substrate and functioning as a nucleation layer, and the first nitride semiconductor layer. A second nitride semiconductor layer having a higher electron affinity than the nitride semiconductor layer, and a third nitride semiconductor layer formed on the second nitride semiconductor layer and having a lower electron affinity than the second nitride semiconductor layer. A nitride semiconductor layer; a source electrode and a drain electrode formed on the third nitride semiconductor layer directly or via an intermediate layer; and a gate electrode formed between the source electrode and the drain electrode. A field effect transistor is provided, wherein the first nitride semiconductor layer contains boron as an impurity.

[2] In the invention described in [1] above, the substrate is silicon carbide, the first nitride semiconductor layer is aluminum nitride, and the second nitride semiconductor layer is gallium nitride, The third nitride semiconductor layer is characterized by being aluminum gallium nitride.

[3] In the invention described in [1] or [2] above, the boron concentration of the first nitride semiconductor layer is in the range of 5E16 to 5E19 [/ cm ³ ].

  According to the present invention, the breakdown voltage of a field effect transistor can be improved.

It is a cross-sectional schematic diagram which shows one structural example of the field effect type nitride transistor which is typical embodiment which concerns on this invention. (A) is a graph which shows a leakage current by making the voltage between electrodes of the nitride transistor which is an Example which concerns on this invention into a variable, (b) is a leak by making the voltage between electrodes of the conventional undoped nitride transistor a variable. It is a graph which shows an electric current. It is a graph which shows an example of the correlation of the leakage current of the nitride transistor which is an Example which concerns on this invention, and the boron doping density | concentration to the 1st nitride semiconductor layer which functions as a nucleation layer. It is an optical microscope photograph of the epitaxial wafer surface for nitride transistors which is an Example which concerns on this invention, (a) is boron doping concentration 5E18 [/ cm < ³ >], (b) is boron doping concentration 7E19 [/ cm < ³ >. ] Is an example. It is the figure which analyzed the depth direction distribution of the gallium, aluminum, and boron in the epitaxial wafer for nitride transistors which is an Example which concerns on this invention by SIMS.

  Preferred embodiments of the present invention will be specifically described below with reference to the accompanying drawings.

(Configuration of nitride transistor)
In FIG. 1, reference numeral 101 denotes a polytype 4H or polytype 6H semi-insulating silicon carbide substrate (SiC substrate) in a field effect transistor (hereinafter referred to as “nitride transistor”) using a group III nitride semiconductor. ).

  On the SiC substrate 101, an aluminum nitride nucleation layer (B-AlN) 102, which is a first nitride semiconductor layer doped with boron, is formed. On the aluminum nitride nucleation layer 102, an undoped gallium nitride layer (un-GaN) 103, which is a second nitride semiconductor layer, is formed. On the undoped gallium nitride layer 103, an aluminum gallium nitride electron supply layer (un-AlGaN) 104, which is a third nitride semiconductor layer, is formed.

  The undoped gallium nitride layer 103 is made of a material having a higher electron affinity than the aluminum nitride nucleation layer 102. The aluminum gallium nitride electron supply layer 104 is made of a material having a lower electron affinity than the undoped gallium nitride layer 103. On the aluminum gallium nitride electron supply layer 104, a silicon-doped gallium nitride intermediate layer (Si-GaN) 106 is formed. The aluminum nitride nucleation layer 102, the undoped gallium nitride layer 103, the aluminum gallium nitride electron supply layer 104, and the gallium nitride intermediate layer 106 constitute a GaN-HEMT (High Electron Mobility Transistor) structure.

  Due to the lattice constant difference between the undoped gallium nitride layer 103 and the undoped aluminum gallium nitride electron supply layer 104, the two-dimensional electron gas layer 105 generated by the piezoelectric effect in the undoped aluminum gallium nitride electron supply layer 104 is undoped. It is formed in the vicinity of the interface (near the junction surface) with the undoped aluminum gallium nitride electron supply layer 104 in the gallium nitride layer 103.

  A source electrode 107, a drain electrode 108, and a gate electrode 109 are disposed on the surface of the gallium nitride intermediate layer 106. The source electrode 107 and the drain electrode 108 have a multilayer structure of titanium and aluminum. The gate electrode 109 is formed between the source electrode 107 and the drain electrode 108 and has a multilayer structure of nickel and gold.

  By the way, in the nitride transistor structure, for example, if there is any current leakage path in the nitride transistor structure in a cut-off state, a leakage current is generated between electrodes or elements, and the breakdown voltage of the device is significantly reduced. Resulting in.

  This current leak path is considered to occur frequently near the interface between the nitride epitaxial layer and the substrate. The reason for this is that the substrate before the epitaxial layer is grown is generally introduced into the epitaxial apparatus after being exposed to the atmosphere unless it is subjected to very special pretreatment. This is because a large amount of impurities such as silicon that become a leak source as a donor adhere to the substrate surface. That is, the current leak path is in the vicinity of the interface between the substrate surface to which impurities serving as a leak source adhere and the initial growth layer of the epitaxial layer.

  A common technique used in a nitride transistor structure to suppress the occurrence of this current leakage path is iron doping into gallium nitride. It is known that when a gallium nitride-based or indium phosphide-based compound semiconductor is doped with a transition metal such as iron, the resistance of the compound semiconductor is increased. This is because the doped transition metal forms a deep trapping level in the band cap of the compound semiconductor, and this level traps free carriers.

  By doping iron into gallium nitride, which occupies most of the film thickness in the epitaxial layer, the current leakage path and the two-dimensional electron gas generation region which is the device active layer are separated. As a result, although iron doping into gallium nitride having a high electric affinity has disadvantages, there is an advantage that the breakdown voltage of a gallium nitride-based device can be improved.

  As described above, a transition metal such as iron forms a deep trapping level in the band cap of the compound semiconductor. For this reason, it is preferable from the viewpoint of withstand voltage that iron is mixed in a portion of the compound semiconductor structure that does not directly contribute to the transistor operation. However, on the other hand, if iron is mixed in the channel portion which is the core of the transistor operation, there is a disadvantage that the conductivity is lowered.

  In particular, it has been pointed out that in a nitride transistor, a carrier traveling in a channel portion is trapped in a trapping level, thereby causing a so-called current collapse phenomenon in which a drain current is significantly reduced during high-frequency operation. That is, it can be said that the iron mixed in the channel part causes the current collapse phenomenon.

  The configuration according to this embodiment has a main feature in the configuration that improves the breakdown voltage of the field-effect nitride transistor structure without using iron doping. It is important that the aluminum nitride layer functioning as a nucleation layer that forms the interface between the SiC substrate 101 and the nitride epitaxial layer is doped with boron as an impurity. According to the illustrated example, an aluminum nitride nucleation layer 102 containing boron as an impurity is formed on a SiC substrate 101.

  By doping boron, the resistance of aluminum nitride can be increased, and the leakage current at the interface between SiC substrate 101 and aluminum nitride nucleation layer 102 can be greatly reduced. The fact that the boron nitride becomes almost an insulator greatly affects the conductivity of the aluminum nitride nucleation layer 102.

The concentration of boron doped as an impurity in the aluminum nitride nucleation layer 102 is set within the range of 5E16 to 1E19 [/ cm ³ ]. The film thickness of the aluminum nitride nucleation layer 102 is preferably 10 nm or more and 1000 nm or less in consideration of the boron concentration.

When the film thickness of the aluminum nitride nucleation layer 102 is less than 10 nm, even if the boron concentration is in the range of 5E16 to 1E19 [/ cm ³ ], it is effective for the result of the boron concentration and pressure resistance of less than 5E16 [/ cm ³ ]. Difference cannot be obtained. If the film thickness of the aluminum nitride nucleation layer 102 exceeds 1000 nm, the surface morphology of the nitride epitaxial layer is remarkably deteriorated even if the boron concentration is in the range of 5E16 to 1E19 [/ cm ³ ]. For leakage current control, the Si concentration of the aluminum nitride nucleation layer 102 is preferably in the range of 5E16 to 3E17.

In order to control variations in device characteristics, the undoped gallium nitride layer 103 is formed such that the C concentration and the Si concentration are 7E16 [/ cm ³ ] or less. The thickness of the undoped gallium nitride layer 103 is preferably in the range of 200 nm to 2000 nm, and more preferably in the range of 550 nm to 1200 nm.

  Hereinafter, examples will be described in detail as specific embodiments of the present invention with reference to FIGS. In this example, a typical example of the above embodiment is given, and the present invention is of course not limited to this example.

[Example 1]
(Manufacturing method of nitride transistor structure)
The nitride transistor according to the above embodiment can be effectively obtained by the following manufacturing method. In manufacturing the main part of the nitride transistor, first, a polytype 4H or polytype 6H semi-insulating SiC substrate (JUST substrate) 101 is prepared as a substrate.

  Next, for example, by using MOVPE (Metal Organic Chemical Vapor Deposition) apparatus and supplying ammonia gas, TMA (Tri Methyl Aluminum), and TEB (Tri Ethyl Boron) as raw material gas, the film thickness is 800 nm on the SiC substrate 101. The aluminum nitride nucleation layer 102 (hereinafter also referred to as “boron-doped aluminum nitride nucleation layer 102”) is formed. The reaction temperature for forming the boron-doped aluminum nitride nucleation layer 102 is most preferably 1200 ° C. as described in Japanese Patent Application Laid-Open No. 2005-32823 previously proposed by the present applicant.

  Next, using the same MOVPE apparatus, by supplying ammonia gas and TMG (Tri Methyl Gallium) as source gases, an undoped gallium nitride layer 103 having a thickness of 1200 nm is formed on the boron-doped aluminum nitride nucleation layer 102. Form. The reaction temperature at this time is set to 1020 ° C.

  Next, by using the same MOVPE apparatus and supplying ammonia gas, TMA, and TMG as source gases, an aluminum gallium nitride electron supply layer 104 having a thickness of 30 nm is formed on the undoped gallium nitride layer 103.

Next, using the same MOVPE apparatus, by supplying ammonia gas and TMG as source gases, an gallium nitride intermediate layer (Si-GaN) 106 having a thickness of 8 nm is formed on the aluminum gallium nitride electron supply layer 104. To do. The gallium nitride intermediate layer 106 is formed so that the Si concentration is in the range of 1E17 to 1E19 [/ cm ³ ].

  Here, an epitaxial multilayer film in which a boron-doped aluminum nitride nucleation layer 102, an undoped gallium nitride layer 103, and an aluminum gallium nitride electron supply layer 104 are sequentially laminated on the SiC substrate 101 is formed by SIMS (Secondary Ion Mass Spectroscopy). As a result of analysis, the distribution in the depth direction of gallium, aluminum, and boron in the epitaxial multilayer film as shown in FIG. 5 was obtained.

  As can be understood from FIG. 5, the boron-doped aluminum nitride nucleation layer 102 is sequentially formed from the bottom so as to satisfy the initial target concentration range with a total thickness of about 2.0 μm on the surface of the SiC substrate 101. It was confirmed that a three-layer structure of the undoped gallium nitride layer 103 and the aluminum gallium nitride electron supply layer 104 was formed.

Both the C concentration and Si concentration of the aluminum nitride nucleation layer 102 and the C concentration and Si concentration of the undoped gallium nitride layer 103 were in the range of 5E16 to 7E16 [/ cm ³ ]. As a result, the leakage current was further effectively reduced, and variations in element characteristics were suppressed. The boron concentration of the undoped gallium nitride layer 103 was not more than the lower limit of detection by SIMS except for the vicinity of the interface of the aluminum nitride nucleation layer 102 (range from the aluminum nitride nucleation layer 102 to 20 nm). Of course, since iron was not doped in Example 1, iron was below the lower limit of detection.

  Then, according to a conventional method, each of the source electrode 107, the drain electrode 108, and the gate electrode 109 is formed on the surface of the gallium nitride intermediate layer 106 by using a general photolithography technique.

  Through the above manufacturing process, the main part of the nitride transistor using the unique group III nitride semiconductor according to the first embodiment can be manufactured.

  Referring to FIG. 2, FIG. 2 (a) shows the leakage current value during DC driving with the voltage between the source electrode 107 and the drain electrode 108 of the nitride transistor according to the first embodiment as variables. Yes. FIG. 2B shows a leakage current value at the time of DC driving of the conventional nitride transistor.

  It can be said that the larger the value of the leakage current, the greater the adverse effect on the transistor characteristics. As can be understood from FIG. 2, it was confirmed that the nitride transistor according to Example 1 has the leakage current value suppressed (reduced) by one digit or more than the conventional nitride transistor.

Referring to FIGS. 3 and 4, FIG. 3 shows a leakage current at an applied voltage of 50 V of the nitride transistor according to Example 1, and an aluminum nitride nucleus that is a first nitride semiconductor layer functioning as a nucleation layer. A correlation with the boron doping concentration in the generation layer 102 is shown. On the other hand, FIG. 4 shows the surface of a nitride transistor epitaxial wafer doped with boron on the aluminum nitride nucleation layer 102. 4A illustrates an example when the boron doping concentration is 5E18 [/ cm ³ ], and FIG. 4B illustrates an example when the boron doping concentration is 7E19 [/ cm ³ ]. doing.

  Using the above manufacturing method, Samples 1 to 9 were respectively prototyped under the boron doping concentration conditions shown in Table 1 below, and nine GaN-HEMT structures were obtained. The correlation between the boron doping concentration and the leakage current shown in Table 1 is plotted on the graph of FIG.

As can be seen from FIG. 3, the higher the boron doping concentration, the higher the effect of suppressing leakage current. This suppression effect of leakage current occurs after the boron doping concentration in the aluminum nitride nucleation layer 102 exceeds 5E16 [/ cm ³ ], and as the boron doping concentration increases, the leakage current is reduced and the leakage current is suppressed. It can be understood that the effect is increasing.

On the other hand, when the boron doping concentration exceeds 5E19 [/ cm ³ ], the surface morphology of the epitaxial wafer for nitride transistors is significantly deteriorated, as shown in FIG. Deterioration of the surface morphology is not preferable because it adversely affects the formation of electrodes.

From these results, it can be said that the concentration of boron doped as an impurity in the aluminum nitride nucleation layer 102 is preferably set in the range of 5E16 to 5E19 [/ cm ³ ].

[Example 2]
In Example 1 described above, a configuration example of a nitride transistor obtained by using a semi-insulating SiC substrate (JUST substrate) 101 to which Si was unintentionally attached was illustrated, but in Example 2, An example of using a substrate on which Si is intentionally attached will be described.

In the second embodiment, the substrate is set in the furnace as in the first embodiment. Tetraethylsilane is allowed to flow into the furnace to deposit 1E12 [/ cm ³ ] Si per unit area on the substrate. With respect to this Si-adhered substrate, the boron concentration of the boron-doped aluminum nitride nucleation layer 102 was 2E18 [/ cm ³ ], and the same structure as in Example 1 was formed. As a result, a low leakage current and a good withstand voltage were obtained.

[Example 3]
By controlling the carbon concentration of the undoped gallium nitride layer 103, the pressure resistance can be improved. In Example 3, the boron concentration of the boron-doped aluminum nitride nucleation layer 102 was controlled, and the carbon concentration of the undoped gallium nitride layer 103 was controlled to improve the pressure resistance.

As a result of enthusiastically examining the breakdown voltage improvement of the field effect transistor, the present inventors have set the carbon concentration of the undoped gallium nitride layer 103 to 8E16 in addition to controlling the boron concentration of the boron-doped aluminum nitride nucleation layer 102. It has been found that by setting it to [/ cm ³ ] or more, it is effective in improving pressure resistance. On the other hand, in the upper layer portion of the undoped gallium nitride layer 103, for example, in the vicinity of the aluminum gallium nitride electron supply layer 104 (range from the interface between the aluminum gallium nitride electron supply layer 104 and the undoped gallium nitride layer 103 to the substrate 101 side up to 50 nm). It was confirmed that when the carbon concentration exceeded 1E17 [/ cm ³ ], the transistor characteristics deteriorated.

Therefore, the growth temperature on the lower layer side of the undoped gallium nitride layer 103 is set to 980 ° C., the pressure in the furnace is controlled to 50 Torr (about 13,332 Pa), and carbon contamination on the upper layer side of the undoped gallium nitride layer 103 is controlled. Controlled. Specifically, the carbon concentration in the lower portion of the undoped gallium nitride layer 103 (from the boron-doped aluminum nitride nucleation layer 102 side to the vicinity of the aluminum gallium nitride electron supply layer 104) is in the range of 8E16 or more and 15E16 [/ cm ³ ] or less. Thus, the lower layer portion of the undoped gallium nitride layer 103 was at least 250 nm, and was formed to have a thickness in the range of 250 nm to 550 nm.

The upper layer portion of the undoped gallium nitride layer 103 was formed so that the carbon concentration in the vicinity of the aluminum gallium nitride electron supply layer 104 did not exceed 1E17 [/ cm ³ ]. Preferably, it is possible to suppress deterioration in transistor characteristics by forming the film so as to be equal to or less than 7E16 [/ cm ³ ]. Depending on the thickness of the undoped gallium nitride layer 103, a layer corresponding to an intervening layer exists between the upper layer portion and the lower layer portion. The carbon concentration of the intervening layer was set within the range of the concentration in the upper layer portion to the concentration in the lower layer portion. The undoped gallium nitride layer 103 was formed to have a Si concentration in a range of 5E16 to 7E16 [/ cm ³ ].

  As a result, it was confirmed that the drain breakdown voltage can be improved and the leakage between elements can be suppressed. The present inventors considered that carbon plays a role of trapping and inactivating free n-type carriers caused by point defects (for example, nitrogen vacancies) or n-type impurities in the nitride semiconductor. . In addition to the leakage current control by controlling the boron concentration of the boron-doped aluminum nitride nucleation layer 102, the addition of carbon to the undoped gallium nitride layer 103 using the growth condition control improves the durability without deteriorating the transistor characteristics. Was realized.

  As is apparent from the above description, the nitride transistor of the present invention has been described based on the above-described embodiment and examples, but the present invention is limited to the above-described embodiment, examples, and illustrated examples. However, the present invention can be implemented in various modes without departing from the scope of the invention. In the present invention, the following modifications are possible.

[Modification]
(1) Although the SiC substrate 101 is illustrated in the illustrated example, the material of the substrate is not particularly limited as long as it is a material capable of forming a nitride semiconductor layer. For example, sapphire or silicon is used for the substrate. Can do.
(2) In the illustrated example, the aluminum nitride nucleation layer (B-AlN) 102 is exemplified as the first nitride semiconductor layer doped with boron. However, the present invention is not limited to this. For example, boron such as AlGaN is used. Doped nitride semiconductor layers can be used.
(3) In the illustrated example, the undoped gallium nitride layer (un-GaN) 103 is exemplified as the second nitride semiconductor layer. However, the present invention is not limited to this, and the electron affinity is higher than that of the first nitride semiconductor layer. A large nitride semiconductor layer such as AlGaN, InGaN, or AlInGaN may be used.
(4) In the illustrated example, the aluminum gallium nitride electron supply layer (un-AlGaN) 104 is illustrated as the third nitride semiconductor layer, but is not limited thereto. Instead of the aluminum gallium nitride electron supply layer, a nitride semiconductor layer such as InAlN having a lower electron affinity than the second nitride semiconductor layer can be used.
(5) In the illustrated example, the gallium nitride intermediate layer (Si—GaN) 106 is illustrated as the intermediate layer, but the present invention is not limited to this, and a nitride semiconductor layer such as Si—AlGaN may be used.
(6) In the illustrated example, a configuration example in which the source electrode 107, the drain electrode 108, and the gate electrode 109 are arranged on the surface of the gallium nitride intermediate layer 106 is illustrated, but the present invention is not limited to this. Alternatively, the drain electrode 108 and the gate electrode 109 may be formed on the undoped aluminum gallium nitride layer 104.

  As mentioned above, although embodiment and the Example of this invention were described, the said embodiment and Example do not limit the invention based on a claim. It should be noted that not all the combinations of features described in the embodiments and examples are essential to the means for solving the problems of the invention.

101 substrate 102 first nitride semiconductor layer 103 second nitride semiconductor layer 104 third nitride semiconductor layer 105 two-dimensional electron gas layer 106 intermediate layer 107 source electrode 108 drain electrode 109 gate electrode

Claims (5)

A silicon carbide substrate;
An aluminum nitride nucleation layer formed on the silicon carbide substrate;
The formed aluminum nitride nucleation layer, a second nitride semiconductor layer having a large electron affinity than the aluminum nitride nucleation layer,
A third nitride semiconductor layer formed on the second nitride semiconductor layer and having a lower electron affinity than the second nitride semiconductor layer;
A source electrode and a drain electrode formed directly or via an intermediate layer on the third nitride semiconductor layer;
A gate electrode formed between the source electrode and the drain electrode,
A field effect transistor characterized in that the aluminum nitride nucleation layer contains boron as an impurity. Before Stories second nitride semiconductor layer is gallium nitride,
2. The field effect transistor according to claim 1, wherein the third nitride semiconductor layer is aluminum gallium nitride. ^3. The field effect transistor according to claim 1, wherein a concentration of boron in the aluminum nitride nucleation layer is in a range of 5E16 to 5E19 [/ cm ³ ]. A silicon carbide substrate;
An aluminum nitride nucleation layer formed on the silicon carbide substrate;
A second nitride semiconductor layer formed on the aluminum nitride nucleation layer and having a higher electron affinity than the aluminum nitride nucleation layer;
A third nitride semiconductor layer formed on the second nitride semiconductor layer and having a lower electron affinity than the second nitride semiconductor layer;
At least,
An epitaxial wafer for a field effect transistor, wherein the aluminum nitride nucleation layer contains boron as an impurity. The boron concentration of the aluminum nitride nucleation layer is 5E16 to 5E19 [/ cm. ³ The epitaxial wafer for a field effect transistor according to claim 4, wherein