CN117133802A

CN117133802A - Semiconductor device, manufacturing method thereof, packaging device and electronic equipment

Info

Publication number: CN117133802A
Application number: CN202310365696.7A
Authority: CN
Inventors: 刘璋成; 张璁雨
Original assignee: Honor Device Co Ltd
Current assignee: Honor Device Co Ltd
Priority date: 2023-03-30
Filing date: 2023-03-30
Publication date: 2023-11-28

Abstract

The application provides a semiconductor device, a manufacturing method thereof, a packaging device and electronic equipment, and relates to the technical field of semiconductors. The self-heating device is used for solving the problems that the self-heating effect of the traditional semiconductor device is serious, the performance of the device is limited, and the risk of burning the device exists. The semiconductor device includes a substrate, a channel layer, a barrier layer, and a thermally conductive portion. The substrate is provided with a heat dissipation hole. The channel layer is stacked on the substrate, and the heat dissipation holes penetrate through the substrate and extend to the channel layer. The barrier stack is disposed on a surface of the channel layer remote from the substrate. The heat conduction part is filled in the heat dissipation hole. The semiconductor device provided by the application can improve the heat dissipation effect and is beneficial to improving the performance of the device.

Description

Semiconductor device, manufacturing method thereof, packaging device and electronic equipment

Technical Field

The present application relates to the field of semiconductor technologies, and in particular, to a semiconductor device, a manufacturing method thereof, a packaging device, and an electronic apparatus.

Background

Semiconductor devices are indispensable devices in electronic products. For example, gallium nitride (GaN) high electron mobility transistors (high electron mobility transistor, HEMT) have high power density and high operating frequency. However, because of the low thermal conductivity of gallium nitride materials, the self-heating effect of the device is severe when operating at high frequency and high power, limiting the improvement of the device performance and risking burning out the device.

Disclosure of Invention

The embodiment of the application provides a semiconductor device, a manufacturing method thereof, a packaging device and electronic equipment, which are used for solving the problems that the self-heating effect of the semiconductor device is serious, the performance of the device is limited to be improved, and the risk of burning the device exists.

In order to achieve the above purpose, the embodiment of the present application adopts the following technical scheme:

in a first aspect, a semiconductor device is provided that includes a substrate, a channel layer, a barrier layer, and a thermally conductive portion. The substrate is provided with a heat dissipation hole. The channel layer is stacked on the substrate, and the heat dissipation holes penetrate through the substrate and extend to the channel layer. The barrier stack is disposed on a side of the channel layer remote from the substrate. The heat conduction part is filled in the heat dissipation hole.

According to the semiconductor device provided by the first aspect of the application, the radiating holes for leading out heat are formed in the substrate, and extend to the channel layer, namely, the radiating holes do not penetrate through the channel layer and do not extend to the barrier layer, so that a heterojunction structure formed between the channel layer and the barrier layer is not damaged, and the performance of the semiconductor device is guaranteed. And the heat conducting part is filled in the heat radiating hole so as to conduct heat on the channel layer to the substrate rapidly, thereby realizing efficient heat radiation and being beneficial to improving the heat radiation effect of the semiconductor device.

In one possible implementation of the first aspect, the substrate includes a first substrate and a second substrate. The channel layer is disposed on the first substrate. The second substrate is arranged on one side of the first substrate far away from the channel layer; the heat dissipation hole is arranged on the surface of the second substrate far away from the first substrate, penetrates through the second substrate and the first substrate and extends to the channel layer. Wherein the thermal conductivity of the second substrate is higher than the thermal conductivity of the first substrate. In this way, a layer of second substrate is further arranged on the basis of the first substrate, and the heat of the channel layer is transferred to the second substrate through the heat dissipation holes and the heat conduction part, so that heat dissipation is realized through the second substrate.

In one possible implementation of the first aspect, the material of the second substrate comprises diamond material. The diamond material has good heat conduction performance, so the diamond material is used as the second substrate, and the heat dissipation effect of the semiconductor device is improved.

In a possible implementation manner of the first aspect, the substrate further includes a transition layer, and the transition layer is disposed between the second substrate and the first substrate. Therefore, the matching degree between the first substrate and the second substrate can be improved, and the processing difficulty is reduced.

In a possible implementation manner of the first aspect, the material of the heat conducting part includes metallic copper or metallic silver. Since copper or silver has good heat conduction performance, heat of the channel layer can be transferred to the second substrate, so that heat dissipation performance of the semiconductor device is improved.

In a possible implementation manner of the first aspect, a side of the channel layer away from the first substrate is provided with a source motor, a gate electrode and a drain electrode, and the gate electrode is disposed between the source electrode and the drain electrode. The radiating hole is arranged on one side of the gate electrode, which is close to the drain electrode, along the direction parallel to the substrate. Because the region with larger heating value of the semiconductor device is the region of one side of the gate electrode, which is close to the drain electrode, the heat dissipation holes are formed at the corresponding positions of the region, so that the heat generated by the region is transferred to the second substrate, and the performance of the semiconductor device is improved.

In a possible implementation manner of the first aspect, the plurality of heat dissipation holes are formed, and the plurality of heat dissipation holes are distributed at intervals between the gate electrode and the drain electrode along a direction parallel to the substrate. Under this structure, through a plurality of louvres and heat conduction portion, be favorable to promoting heat conduction ability to can further promote the radiating effect.

In a possible implementation manner of the first aspect, a vertical projection of an edge of the gate electrode, which is close to the drain electrode, on the first substrate sequentially passes through a vertical projection of a portion of the plurality of heat dissipation holes, which is close to the gate electrode, on the first substrate. Under this structure, set up the part in a plurality of louvres in the gate electrode be close to one side of substrate, the more position of calorific capacity promptly to can in time transfer the heat of this position department to the second substrate, with the temperature of reduction gate electrode, further guarantee the performance of semiconductor device.

In a possible implementation manner of the first aspect, the source electrode and the drain electrode are disposed on a surface of the channel layer remote from the first substrate, the barrier layer is disposed between the source electrode and the drain electrode, and the gate electrode is disposed on a surface of the barrier layer remote from the channel layer.

In a possible implementation manner of the first aspect, the semiconductor device further includes a semiconductor layer disposed between the gate electrode and the barrier layer. The semiconductor layer can be a P-type semiconductor layer, which is beneficial to forming an enhanced device.

In a possible implementation manner of the first aspect, the semiconductor device further includes a thermally conductive insulating layer disposed on a surface of the second substrate remote from the first substrate. For example, the heat conducting insulating layer can be made of diamond-like material, which has high heat conducting property, and is beneficial to further improving the heat radiating effect; and the heat dissipation holes can be electrically isolated, so that the structural reliability of the semiconductor device is improved.

In one possible implementation of the first aspect, the material of the thermally conductive insulating layer comprises a diamond-like material.

In one possible implementation manner of the first aspect, the semiconductor device is a GaN HEMT device.

In a second aspect, a package device is provided, including a substrate and the semiconductor device according to any of the above claims, where the semiconductor device is disposed on the substrate.

In a third aspect, an electronic device is provided, including a circuit board and a package device according to the above technical solution, where the package device is disposed on the circuit board.

In a fourth aspect, a method for manufacturing a semiconductor device is provided, the method comprising: forming a channel layer on the surface of the substrate; forming a barrier layer on a surface of the channel layer remote from the substrate; a heat dissipation hole is formed in the surface, far away from the channel layer, of the substrate, and extends to the channel layer; and the heat conducting part is filled in the heat radiating hole.

In the method for manufacturing a semiconductor device according to the fourth aspect of the present application, the heat dissipation hole is formed in the surface of the substrate away from the channel layer, the heat dissipation hole extends to the channel layer, and the heat conduction portion is filled in the heat dissipation hole. On the one hand, the heat dissipation hole and the heat conduction part do not extend to the barrier layer, so that a heterojunction structure formed between the channel layer and the barrier layer is not damaged, and the performance of the semiconductor device is not affected. On the other hand, through the heat conduction part filled in the heat dissipation hole, the heat of the channel layer can be transferred to one side of the substrate far away from the channel layer, so that the heat dissipation is realized more quickly, the temperature of the semiconductor device is reduced, and the performance of the semiconductor device is improved.

In a possible implementation manner of the fourth aspect, the substrate includes a first substrate and a second substrate, and the method for manufacturing the substrate includes: activating the first surface of the first substrate and the second surface of the second substrate; and pressing the first substrate and the second substrate, wherein the first surface is opposite to the second surface, and bonding of the first substrate and the second substrate is realized to form the substrate. In this way, the second substrate is arranged on one side, far away from the channel layer, of the first substrate, and heat of the channel layer can be transferred to the second substrate through the heat conducting part in the heat radiating hole, so that the heat radiating effect is further improved.

In a possible implementation manner of the fourth aspect, the substrate includes a first substrate, a transition layer, and a second substrate, the transition layer is disposed between the first substrate and the second substrate, and the channel layer is formed on a surface of the first substrate away from the second substrate; the manufacturing method of the substrate comprises the following steps: forming a first sub-transition layer on a first surface of a first substrate; forming a second sub-transition layer on a second surface of the second substrate; activating the first sub-transition layer and the second sub-transition layer; and pressing the first sub-transition layer and the second sub-transition layer to form a transition layer between the first sub-transition layer and the second sub-transition layer, and bonding the first substrate and the second substrate to form the substrate. In this way, the transition layer is arranged between the first substrate and the second substrate, so that the lattice matching degree between the hierarchical structures can be improved, the process difficulty is reduced, and the yield of products is improved.

In a possible implementation manner of the fourth aspect, the method for manufacturing the heat dissipation hole includes: punching holes on the surface of the second substrate far away from the first substrate and extending to the first substrate; and carrying out an etching process on the bottom of the sub-hole, penetrating through the first substrate and extending to the channel layer to form a heat dissipation hole. Firstly, punching a second substrate through a punching process, and then etching the first substrate and the channel layer; in this way, the aperture is controlled by the punching process, and then the opening of the radiating holes is completed by the etching process, so that the overlarge aperture of the radiating holes is avoided.

Illustratively, the second substrate may be made of a diamond material, and the diamond material has a high hardness, so that the second substrate may be perforated by using a femtosecond laser technology, which has advantages of high precision, high speed, high efficiency, and the like. Thereby, the sub-holes can be rapidly opened on the second substrate made of diamond material, and the aperture precision of the sub-holes can be ensured.

In a possible implementation manner of the fourth aspect, the method for filling the heat conducting part in the heat dissipation hole includes: depositing a layer of material of the heat conducting part on the inner wall of the heat radiating hole to form a material layer of the heat conducting part; and filling a heat conducting part material layer with a heat conducting part material layer to form a heat conducting part. Therefore, a layer of heat conducting part material is deposited on the inner wall of the heat dissipation hole, and then the heat conducting part material is filled, so that the bonding degree between the heat conducting part and the inner wall of the heat dissipation hole is improved, the heat conducting efficiency is guaranteed, and the heat dissipation effect is improved.

In a possible implementation manner of the fourth aspect, after the heat conducting portion is filled in the heat dissipation hole, the method for manufacturing the semiconductor device further includes: a thermally conductive insulating layer is formed on a surface of the substrate remote from the channel layer. In this way, the heat-conducting insulating layer can electrically isolate the heat dissipation holes, which is beneficial to improving the structural reliability of the semiconductor device.

In a possible implementation manner of the fourth aspect, before the heat dissipation hole is formed on the surface of the substrate away from the channel layer, the method for manufacturing the semiconductor device further includes: etching a local region of the barrier layer at one side of the barrier layer away from the channel layer to expose the channel layer, forming a source electrode mounting region and a drain electrode mounting region, wherein the barrier layer is positioned between the source electrode mounting region and the drain electrode mounting region; manufacturing a source electrode in a source mounting area and manufacturing a drain electrode in a drain mounting area; a gate electrode is fabricated on a surface of the barrier layer remote from the channel layer.

Drawings

Fig. 1 is a block diagram of an electronic device according to an embodiment of the present application;

fig. 2 is an exploded view of an electronic device according to an embodiment of the present application;

fig. 3 is a structural diagram of a packaged device according to an embodiment of the present application;

fig. 4 is a block diagram of a semiconductor device according to an embodiment of the present application;

fig. 5 is a block diagram of another semiconductor device according to an embodiment of the present application;

fig. 6 is a cross-sectional view of the semiconductor device provided in fig. 5;

fig. 7 is a block diagram of still another semiconductor device according to an embodiment of the present application;

fig. 8 is a cross-sectional view of the semiconductor device provided in fig. 7;

Fig. 9 is a bottom view of the semiconductor device provided in fig. 7 and 8 with a plurality of evenly distributed heat dissipation holes;

fig. 10 is a bottom view of a non-uniform distribution of a plurality of heat dissipation holes formed in the semiconductor device provided in fig. 7 and 8;

fig. 11 is a block diagram of still another semiconductor device according to an embodiment of the present application;

fig. 12 is a cross-sectional view of the semiconductor device provided in fig. 11;

fig. 13 is a block diagram of another substrate of the semiconductor device according to the embodiment of the present application;

fig. 14 is a block diagram of still another semiconductor device according to an embodiment of the present application;

fig. 15 is a cross-sectional view of the semiconductor device provided in fig. 14;

fig. 16 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present application;

fig. 17 is a block diagram of a first substrate and an epitaxial structure according to an embodiment of the present application;

fig. 18 is a block diagram of a first substrate and another epitaxial structure according to an embodiment of the present application;

FIG. 19 is a diagram showing a structure of a first substrate and a second substrate before direct bonding according to an embodiment of the present application;

FIG. 20 is a diagram of a structure of a first substrate and a second substrate directly bonded according to an embodiment of the present application;

fig. 21 is a diagram illustrating a structure before a first substrate and a second substrate are indirectly bonded according to an embodiment of the present application;

FIG. 22 is a diagram illustrating a structure of a first substrate and a second substrate indirectly bonded according to an embodiment of the present application;

fig. 23 is a structural diagram of forming a source electrode, a drain electrode, and a gate electrode on an epitaxial structure according to an embodiment of the present application;

fig. 24 is a block diagram of a semiconductor device provided in fig. 23 with sub-holes formed therein;

fig. 25 is a view showing a structure of a semiconductor device provided in fig. 24, in which a heat dissipation hole is formed;

fig. 26 is a structural view of a thermally conductive metal layer formed in a heat dissipation hole of the semiconductor device provided in fig. 25.

Reference numerals: 01-an electronic device; 10-a housing; 101-a rear cover; 102-frame; 103-middle plate; 20-a display module; 201-a light-transmitting cover plate; -202-a display screen; 30-a circuit board; 40-packaging the device; 401-a substrate; 402-packaging structure; 403-semiconductor devices; 400-epitaxial structure; 410-a substrate; 411-heat dissipation holes; 411 a-sub-aperture; 412-a first substrate; 412 a-a first surface; 413-a second substrate; 413 a-a second surface; 414-a transition layer; 414 a-a first sub-transition layer; 414 b-a second sub-transition layer; 420-a channel layer; 430-a barrier layer; 440-a thermally conductive section; 450-source electrode; 451-gate electrode; 452-drain electrode; 460-a semiconductor layer; 470-a thermally conductive insulating layer; 471-a thermally conductive metal layer; 480-a nucleation layer; 490-buffer layer.

Detailed Description

The following description of the technical solutions according to the embodiments of the present application will be given with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, but not all embodiments.

Hereinafter, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first", "a second", etc. may explicitly or implicitly include one or more such feature.

Furthermore, in the present application, directional terms "upper", "lower", etc. are defined with respect to the orientation in which the components are schematically disposed in the drawings, and it should be understood that these directional terms are relative concepts, which are used for description and clarity with respect thereto, and which may be changed accordingly in accordance with the change in the orientation in which the components are disposed in the drawings.

In the present application, unless explicitly specified and limited otherwise, the term "connected" is to be construed broadly, and for example, "connected" may be either fixedly connected, detachably connected, or integrally formed; can be directly connected or indirectly connected through an intermediate medium.

Embodiments of the present application provide an electronic device that may include a communication device (e.g., a cell phone, a base station, etc.), a wireless charging device, a medical device, a radar, a navigation device, a Radio Frequency (RF) plasma lighting device, an RF induction and microwave heating device, etc. The embodiment of the application does not particularly limit the specific form of the electronic device. For convenience of explanation, the following will take an electronic device as an example of a mobile phone.

Referring to fig. 1 and fig. 2, fig. 1 is a block diagram of an electronic device 01 according to an embodiment of the present application, and fig. 2 is an exploded view of the electronic device 01 according to the embodiment of the present application. The electronic apparatus 01 may include a housing 10, a display module 20, a circuit board 30, and a package device 40.

The display module 20 is used for displaying images, videos, and the like. The display module 20 may include a light-transmitting cover 201 and a display screen 202, and the light-transmitting cover 201 and the display screen 202 are stacked. The transparent cover plate 201 can adopt a common transparent cover plate 201 for protecting the display screen 202, so as to avoid damage of the display screen 202 caused by collision of external force, and can play a role in dust prevention; the light-transmitting cover plate 201 with the touch function can also be adopted, so that the electronic device 01 has the touch function, and the use of a user is more convenient. Therefore, the specific material of the light-transmitting cover plate 201 is not particularly limited in the present application.

Further, the display 202 may be a flexible display 202 or a rigid display 202. For example, the display 202 may be an organic light-emitting diode (OLED) display 202, an active-matrix organic light-emitting diode (AMOLED) display 202, a mini-led (mini organic light-emitting diode) display 202, a micro-led (micro organic light-emitting diode) display 202, a micro-organic light-emitting diode (micro organic light-emitting diode) display 202, a quantum dot light-emitting diode (quantum dot light emitting diode, QLED) display 202, a liquid crystal display 202 (liquid crystal display, LCD).

The above-described case 10 is used to protect electronic components inside the electronic apparatus 01. The housing 10 includes a rear cover 101 and a frame 102, the rear cover 101 is located at a side of the display screen 202 away from the transparent cover 201, and is stacked with the transparent cover 201 and the display screen 202, and the frame 102 is located between the transparent cover 201 and the rear cover 101. The frame 102 is fixed on the rear cover 101, and the frame 102 may be fixed on the rear cover 101 by bonding, welding, clamping or screwing; alternatively, the frame 102 and the rear cover 101 may be integrally formed, i.e., the frame 102 and the rear cover 101 are integrally formed. The transparent cover 201 may be adhered to the frame 102 by glue, so that the transparent cover 201, the rear cover 101 and the frame 102 enclose an internal accommodating space of the electronic device 01. The display 202, the circuit board 30 and the packaging device 40 are all disposed in the internal accommodating space.

In some embodiments, the housing 10 may further include a middle plate 103. The middle plate 103 is disposed in the above-mentioned inner accommodation space, and the middle plate 103 is located at a side of the display screen 202 remote from the light-transmitting cover plate 201. The middle plate 103 is fixedly connected with the frame 102, and the middle plate 103 and the frame 102 can be fixedly connected in a gluing, welding, clamping or threaded connection mode, etc. by way of example; alternatively, the middle plate 103 and the frame 102 may be formed as an integral structure, that is, the middle plate 103 and the frame 102 enclose a structural member. The middle plate 103 divides the internal accommodating space into two mutually independent spaces. One of the spaces is located between the light-transmitting cover plate 201 and the middle plate 103, and the display screen 202 is located in the space. Another space is located between the middle plate 103 and the rear cover 101, and the circuit board 30 and the package device 40 are disposed in the space.

The circuit board 30 is used for disposing electronic components of the electronic apparatus 01 and for electrically connecting the electronic components. The electronic component may be, for example, the package device 40 described above or a headset, a flash module, etc.

Referring to fig. 3, fig. 3 is a block diagram of a package device 40 according to an embodiment of the present application, where the package device 40 may include a substrate 401, a semiconductor device 403, and a package structure 402. The semiconductor device 403 is disposed on the substrate 401, and the package structure 402 encapsulates the semiconductor device 403 to form an effective protection for the semiconductor device 403.

With the development of the fourth generation mobile communication technology (4th generation of wireless communications technologies,4G) toward the fifth generation mobile communication technology (5th generation of wireless communications technologies,5G), the functional requirements of the above-mentioned semiconductor device 403 are also increasing, for example, higher frequencies, higher voltages, higher output power and efficiency, and the like.

Among the semiconductor materials that can be selected, gallium nitride (GaN) is a key material for fabricating the semiconductor device 403 because it has characteristics of high breakdown field strength, high saturated electron mobility, and the like. Referring to fig. 4, fig. 4 is a schematic diagram illustrating a semiconductor device 403 according to an embodiment of the present application, in which a gallium nitride (GaN) -based high electron mobility transistor (high electron mobility transistor, HEMT) is fabricated from a GaN epitaxial single crystal thin film (epitaxial structure 400) grown on a single crystal substrate 410. The single crystal substrate 410 may be made of a material such as Sapphire (Sapphire), silicon carbide (SiC), or silicon (Si) single crystal, for example, when the substrate 410 is made of a silicon single crystal material, the HEMT fabricated may be referred to as a gallium nitride on silicon (GaN-on-Si) HEMT device.

However, since the semiconductor device 403 generates a large amount of heat when operating under high frequency and high power conditions, the temperature of the device itself is high, and thus further improvement of the frequency and power of the semiconductor device 403 is seriously affected, i.e. further improvement of the performance of the semiconductor device 403 is restricted.

Based on this, another semiconductor device 403 is provided in the embodiments of the present application, which can improve the heat dissipation performance of the semiconductor device 403, so that the semiconductor device 403 can dissipate heat rapidly when operating under high-frequency and high-power conditions, thereby being beneficial to reducing the temperature of the semiconductor device 403, and further being beneficial to further improving the performance of the semiconductor device 403.

In one possible example, the semiconductor device provided by the embodiment of the present application may be a GaN HEMT device. The following embodiments are all exemplified by taking the semiconductor device 403 as a GaN HEMT device.

Specifically, referring to fig. 5 and 6, fig. 5 is a block diagram of another semiconductor device 403 according to an embodiment of the present application, and fig. 6 is a cross-sectional view of the semiconductor device 403 according to fig. 5. The semiconductor device 403 may include a substrate 410, a channel layer 420, a barrier layer 430, and a heat conductive portion 440. The channel layer 420 is stacked on the substrate 410, and the barrier layer 430 is stacked on a surface of the channel layer 420 remote from the substrate 410. The surface of the substrate 410 away from the channel layer 420 is provided with a heat dissipation hole 411, the heat dissipation hole 411 extends to the channel layer 420, and the heat conduction portion 440 is filled in the heat dissipation hole 411.

It is to be understood that the heat dissipation hole 411 extends to the channel layer 420, and the heat dissipation hole 411 may penetrate through the substrate 410 to expose the surface of the channel layer 420 facing the substrate 410, but a recess structure is not formed on the channel layer 420. The heat dissipation hole 411 may extend to the channel layer 420, and a recess structure may be formed on the channel layer 420, but does not penetrate the channel layer 420. For example, the thickness of the channel layer 420 may be 2 μm, the heat sink 411 extends to the channel layer 420, and a recess structure of 1 μm is formed on the surface of the channel layer 420 facing the substrate 410, i.e., the heat sink 411 does not penetrate the channel layer 420.

The channel layer 420 is further provided with a source electrode 450, a gate electrode 451, and a drain electrode 452 on a side away from the substrate 410. Illustratively, the source electrode 450 and the drain electrode 452 may be disposed on a surface of the channel layer 420 remote from the substrate 410, the barrier layer 430 disposed between the source electrode 450 and the drain electrode 452, and the gate electrode 451 disposed on a surface of the barrier layer 430 remote from the channel layer 420.

In addition, in order to further improve the performance of the semiconductor device 403, referring to fig. 7 and 8, fig. 7 is a structural diagram of another semiconductor device 403 according to an embodiment of the present application, and fig. 8 is a cross-sectional view of the semiconductor device 403 provided in fig. 7. A semiconductor layer 460 may be further disposed on a surface of the barrier layer 430 away from the channel layer 420, where the semiconductor layer 460 is a P-type semiconductor layer 460, such as a P-type NaG layer.

The gate electrode 451 is provided on the semiconductor layer 460. Thus, the semiconductor layer 460 can neutralize the two-dimensional electron gas formed between the channel layer 420 and the barrier layer 430, so that the semiconductor device 403 is in a normally-off state, which is beneficial to improving the reliability of the semiconductor device 403 and forming an enhanced device.

When the semiconductor device 403 generates heat, a region having a serious heat generation amount is located at an edge of the gate power supply adjacent to the drain power supply, that is, a position on the channel layer 420 corresponding to the region has a large heat generation amount. Therefore, the heat dissipation hole 411 may be formed on a side of the gate power supply, which is close to the drain power supply, along a direction parallel to the substrate 410. So that the heat in the region with higher heat on the channel layer 420 is quickly conducted to the side of the substrate 410 away from the channel layer 420 through the heat conducting portion 440 in the heat dissipating hole 411, thereby realizing efficient heat dissipation and reducing the temperature of the semiconductor device 403.

In order to further enhance the heat dissipation capability of the semiconductor device 403, referring to fig. 7 and 8, a plurality of heat dissipation holes 411 may be formed, and the plurality of heat dissipation holes 411 are distributed at intervals on one side of the gate electrode 451 near the drain electrode 452. And each of the heat dissipation holes 411 is filled with the heat conductive part 440. That is, a plurality of heat dissipation holes 411 are provided in a region where the amount of heat generation is serious, and each heat dissipation hole 411 is filled with a heat conduction portion 440, so that the heat conduction efficiency is further improved, and the heat dissipation effect of the semiconductor device 403 can be improved.

In some examples, referring to fig. 9, fig. 9 is a bottom view of the semiconductor device 403 provided in fig. 7 and 8 with a plurality of evenly distributed heat dissipation holes 411. The plurality of heat dissipation holes 411 may be uniformly distributed at a side of the gate electrode 451 near the drain electrode 452. For example, the plurality of heat dissipation holes 411 may form an array of m×n, where M > 0 and N > 0, and thus are uniformly distributed on the side of the gate electrode 451 near the drain electrode 452.

Alternatively, referring to fig. 10, fig. 10 is a bottom view of the semiconductor device 403 provided in fig. 7 and 8 with unevenly distributed heat dissipation holes 411. The plurality of heat dissipation holes 411 may be unevenly distributed. For example, a plurality of groups of heat dissipation holes 411 are distributed along the direction of the gate electrode 451 toward the drain electrode 452, and the number of heat dissipation holes 411 included in each group of heat dissipation holes 411 may gradually decrease along the direction of the gate electrode 451 toward the drain electrode 452, i.e., the heat generation amount of the region close to the gate electrode 451 is serious, so that more heat dissipation holes 411 are provided; the region near the drain electrode 452 generates less heat, and therefore, the heat dissipation holes 411 are provided less. The number and distribution of the heat radiation holes 411 are not particularly limited.

In addition, a vertical projection of an edge of the gate electrode 451 adjacent to the drain electrode 452 on the substrate 410 may pass through a vertical projection of a portion of the heat dissipation holes 411, which is close to the gate electrode 451, of the plurality of heat dissipation holes 411 on the substrate 410. I.e. the vertical projection of the heat sink 411 near the gate electrode 451 onto the substrate 410 coincides with the vertical projection of the gate electrode 451 onto the substrate 410.

Note that the above-mentioned heat dissipation hole 411 being disposed on the side of the gate electrode 451 near the drain electrode 452 means that the heat dissipation hole 411 is disposed on the side of the gate electrode 451 near the drain electrode 452 in the direction parallel to the substrate 410. That is, the heat radiation hole 411 is not located between the gate electrode 451 and the drain electrode 452 in the three-dimensional space.

In summary, in the semiconductor device 403 provided by the embodiment of the present application, the heat dissipation hole 411 is formed on the substrate 410, and the heat conduction portion 440 is filled in the heat dissipation hole 411, so that the heat on the channel layer 420 can be quickly transferred to the substrate 410, so as to achieve efficient heat dissipation, and improve the heat dissipation effect of the semiconductor device 403.

In addition, the heat dissipation hole 411 extends only to the channel layer 420 and does not extend to the barrier layer 430, that is, the heat dissipation hole 411 does not penetrate through the channel layer 420, so that the heat dissipation hole 411 and the heat conduction portion 440 do not damage the heterojunction structure formed between the channel layer 420 and the barrier layer 430, which is beneficial to ensuring the formation of the semiconductor device 403.

On this basis, the heat dissipation performance of the semiconductor device 403 is further improved. Referring to fig. 11 and 12, fig. 11 is a block diagram of a semiconductor device 403 according to another embodiment of the present application, and fig. 12 is a cross-sectional view of the semiconductor device 403 shown in fig. 11. The substrate 410 may include a first substrate 412 and a second substrate 413, and the second substrate 413 is disposed on a side of the first substrate 412 away from the channel layer 420. The heat dissipation hole 411 is disposed on a surface of the second substrate 413 away from the first substrate 412, and extends through the second substrate 413 and the first substrate 412 to the channel layer 420. And, the thermal conductivity of the second substrate 413 is higher than that of the first substrate 412.

Illustratively, the first substrate 412 may be made of sapphire, silicon carbide, silicon single crystal, gallium nitride, or the like. The second substrate 413 may be made of a diamond material, which has a high thermal conductivity due to its excellent thermal conductivity, and is higher than the thermal conductivity of the above-mentioned materials such as sapphire, silicon carbide, silicon single crystal, and gallium nitride. Therefore, the use of the diamond material as the second substrate 413 is advantageous in further improving the heat dissipation effect of the semiconductor device 403.

In addition, referring to fig. 13, fig. 13 is a schematic diagram of another substrate 410 of a semiconductor device 403 according to an embodiment of the present application. The substrate 410 of the semiconductor device 403 may further include a transition layer 414, where the transition layer 414 is disposed between the second substrate 413 and the first substrate 412. In this way, the lattice matching between the second substrate 413 and the first substrate 412 made of diamond material is advantageously improved. I.e., by growing a transition layer 414 on a second substrate 413 of diamond material and then growing a first substrate 412 on the transition layer 414, the process difficulty is advantageously reduced.

In some embodiments, referring to fig. 14 and 15, fig. 14 is a block diagram of a semiconductor device 403 according to another embodiment of the present application, and fig. 15 is a cross-sectional view of the semiconductor device 403 provided in fig. 14. The semiconductor device 403 may further include a thermally conductive insulating layer 470, where the thermally conductive insulating layer 470 is disposed on a surface of the second substrate 413 remote from the first substrate 412. The heat conducting insulating layer 470 has better heat conducting property, so that the heat transferred by the heat conducting part 440 is transferred to the heat conducting insulating layer 470, thereby being beneficial to further improving the heat dissipation effect. And, the heat conductive insulating layer 470 may electrically isolate the heat dissipation hole 411, thereby facilitating the improvement of the reliability of the semiconductor device 403.

The above is a description of the structure of the semiconductor device 403 provided in the embodiment of the present application. Referring to fig. 16, fig. 16 is a flowchart illustrating a method for fabricating a semiconductor device 403 according to an embodiment of the present application, the method may include steps S101-S106:

s101, an epitaxial structure 400 is formed on a first substrate 412.

Referring to fig. 17, fig. 17 is a block diagram of a first substrate 412 and an epitaxial structure 400 according to an embodiment of the present application. A channel layer 420, a barrier layer 430, and a semiconductor layer 460 are epitaxially grown in this order on the surface of the first substrate 412. The channel layer 420, the barrier layer 430 and the semiconductor layer 460 form the epitaxial structure 400. The barrier layer 430 is used to form a heterojunction structure with the channel layer 420, so that a two-dimensional electron gas (two-dimensional electron gas,2 DEG) is generated between the channel layer 420 and the barrier layer 430 by polarization, thereby conducting a current. The semiconductor layer 460 may be a P-type semiconductor layer 460, which is used to neutralize two-dimensional electron gas between the channel layer 420 and the barrier layer 430, so that the semiconductor device 403 is in a normally-off state, which is beneficial to improving the reliability of the semiconductor device 403. And can form an enhanced device.

Illustratively, the first substrate 412 may include Sapphire (Sapphire), silicon carbide (SiC), silicon single crystal (Si), al ₂ O ₃ Or gallium nitride (GaN) or the like, the thickness of the first substrate 412 may be 10 μm to 30 μm.

The channel layer 420 may include a gallium nitride (GaN) material, and the thickness of the channel layer 420 may be 2 μm to 5 μm.

The barrier layer 430 may include an aluminum gallium nitride (AlGaN) material, or may include at least one of aluminum indium nitride (AlInN) or aluminum indium gallium nitride (AlInGaN) in combination with AlGaN. The barrier layer 430 may have a thickness of 10nm-50nm.

The semiconductor layer 460 may be a P-type semiconductor layer 460, which may include a GaN material. The thickness of the semiconductor layer 460 may be 10nm-500nm.

The manner in which the epitaxial structure is epitaxially grown on the first substrate 412 may be selected from, but is not limited to, thin film deposition processes such as chemical vapor deposition (Chemical Vapor Deposition, CVD), physical vapor deposition (Physical Vapor Deposition, PVD), or atomic layer deposition (Atomic Layer Deposition, ALD). Alternatively, molecular beam epitaxy and other processes may be used.

In some examples, referring to fig. 18, fig. 18 is a block diagram of a first substrate 412 and another epitaxial structure 400 according to an embodiment of the present application. When the first substrate 412 is made of sapphire, silicon carbide, or silicon single crystal, in order to buffer lattice mismatch between the first substrate 412 and the channel layer 420, a nucleation layer 480 and a buffer layer 490, that is, the nucleation layer 480, the buffer layer 490, the channel layer 420, the barrier layer 430, and the semiconductor layer 460, may be formed together to form the epitaxial structure 400, thereby being beneficial to improving the yield of products.

Of course, more semiconductor functional layers may be added or some semiconductor functional layers may be removed based on the above embodiments. The present application is not particularly limited to these semiconductor functional layers integrated on the substrate 410.

S102, a second substrate 413 is formed on the first substrate 412.

Specifically, referring to fig. 19, fig. 19 is a structural diagram of the first substrate 412 and the second substrate 413 before being directly bonded according to an embodiment of the present application. The surface of the first substrate 412 away from the channel layer 420 is a first surface 412a, and the surface of the second substrate 413 facing the first substrate 412 is a second surface 413a. The first surface 412a of the first substrate 412 and the second surface 413a of the second substrate 413 are subjected to activation treatments, respectively. Then, the first surface 412a of the first substrate 412 is opposed to the second surface 413a of the second substrate 413, and pressure bonding is applied, thereby realizing direct bonding of the first substrate 412 and the second substrate 413. Referring to fig. 20, fig. 20 is a schematic diagram of a structure in which a first substrate 412 and a second substrate 413 are directly bonded according to an embodiment of the present application.

The second substrate 413 may be made of a diamond material, and the thickness of the second substrate 413 may be 80 μm to 100 μm. Alternatively, the second substrate 413 may be made of other materials having higher thermal conductivity than the first substrate 412. Therefore, the present application is not particularly limited thereto.

Illustratively, the first substrate 412 is thinned to 20 μm, the second substrate 413 is thinned to 100 μm, and the first surface 412a of the first substrate 412 and the second surface 413a of the second substrate 413 are polished to a roughness of less than 0.5nm.

Then, the first substrate 412 and the second substrate 413 were placed in a vacuum bonding apparatus, respectively, and the first surface 412a of the first substrate 412 and the second surface 413a of the second substrate 413 were bombarded with an Ar (argon element) ion beam for 2min for activation.

Finally, the activated first surface 412a of the first substrate 412 is bonded to the activated second surface 413a of the second substrate 413, and a pressure is applied to bond the first substrate 412 and the second substrate 413.

In some embodiments, indirect bonding between the second substrate 413 and the first substrate 412 may also be used.

Specifically, referring to fig. 21, fig. 21 is a schematic diagram of a structure before the first substrate 412 and the second substrate 413 are indirectly bonded according to an embodiment of the present application. A first sub-transition layer 414a is deposited on the first surface 412a of the first substrate 412 and a second sub-transition layer 414b is deposited on the second surface 413a of the second substrate 413. The first sub-transition layer 414a and the second sub-transition layer 414b are then activated. The first sub-transition layer 414a and the second sub-transition layer 414b are then laminated together to form the transition layer 414, thereby achieving indirect bonding of the first substrate 412 and the second substrate 413. Referring to fig. 22, fig. 22 is a schematic diagram of a structure in which a first substrate 412 and a second substrate 413 are indirectly bonded according to an embodiment of the present application.

Illustratively, the first substrate 412 is thinned to 10 μm, the second substrate 413 is thinned to 80 μm, and the first surface 412a of the first substrate 412 and the second surface 413a of the second substrate 413 are polished to a roughness of less than 5nm.

Then, a 2nmTi (titanium element) film, or a 5nmAu (gold element) film is deposited on the first surface 412a of the first substrate 412 to form a first sub-transition layer 414a; and, a 2nmTi (titanium element) film, or a 5nmAu (gold element) film is deposited on the second surface 413a of the second substrate 413 to form a second sub-transition layer 414b.

Next, the first substrate 412 and the second substrate 413 were placed in a vacuum bonding apparatus, and the first sub-transition layer 414a and the second sub-transition layer 414b were bombarded with an Ar ion beam for 2min for activation.

Finally, the first sub-transition layer 414a and the second sub-transition layer 414b are attached, and pressure is applied to press the first sub-transition layer and the second sub-transition layer together to form the transition layer 414, so that the first substrate 412 and the second substrate 413 are indirectly bonded.

S103, a source electrode 450, a gate electrode 451, and a drain electrode 452 are formed on a side of the channel layer 420 away from the first substrate 412.

Specifically, referring to fig. 23, fig. 23 is a block diagram illustrating formation of a source electrode 450, a drain electrode 452 and a gate electrode 451 on an epitaxial structure 400 according to an embodiment of the present application. An etching process is performed on a side of the epitaxial structure 400 formed in step S101 away from the first substrate 412, exposing the channel layer 420, forming a source mounting region and a drain mounting region, and the barrier layer 430 and the semiconductor layer 460 are located between the source mounting region and the drain mounting region. Then, a source electrode 450 and a drain electrode 452 are formed in the source and drain mounting regions by a thin film deposition technique, and high temperature annealing is performed to form ohmic contacts. Finally, a gate electrode 451 is formed on the surface of the barrier layer 430 remote from the channel layer 420 by thin film deposition technique, and low temperature annealing is performed to density the gate defect.

Wherein, the etching process comprises, but is not limited to, normal temperature (20-80 ℃) etching process, low temperature (less than-30 ℃) etching process, dry etching process or wet etching process, etc.

Illustratively, the external structure is etched to expose the channel layer 420 and the semiconductor layer 460 of the active region, the exposed channel layer 420 forming a source mounting region and a drain mounting region; and ammonia water is used for 30min to reduce etching defects.

Then, source and drain electrodes 450 and 452 are formed on the channel layer 420 through a thin film deposition process, and rapidly annealed at a high temperature of 950 ℃ in an argon atmosphere to form ohmic contacts. The source electrode 450 and the drain electrode 452 may be formed using Ti or Au materials, and the materials of the source electrode 450 and the drain electrode 452 may be the same or different. For example, the source electrode 450 and the drain electrode 452 formed of Ti metal having a thickness of 500nm, or the source electrode 450 and the drain electrode 452 formed of Au metal having a thickness of 20nm may be prepared.

Finally, a gate electrode 451 is formed on the surface of the semiconductor layer 460 remote from the barrier layer 430, and annealed at 300 ℃ for 30min under a nitrogen atmosphere. The gate electrode 451 may be made of Ni or Au material. For example, the gate electrode 451 formed of Ni metal having a thickness of 20nm, or the gate electrode 451 formed of Au metal having a thickness of 200nm may be prepared.

S104, a heat dissipation hole 411 is formed in the second substrate 413.

Specifically, referring to fig. 24, fig. 24 is a structural diagram of a semiconductor device 403 provided in fig. 23 with a sub-hole 411a formed therein. A sub-hole 411a is formed by punching a surface of the second substrate 413 away from the first substrate 412. The sub-aperture 411a extends to the first substrate 412. Next, referring to fig. 25, fig. 25 is a structural diagram of a semiconductor device 403 provided in fig. 24 in which a heat dissipation hole 411 is formed. The heat dissipation hole 411 is formed by penetrating the first substrate 412 through an etching process on the bottom surface of the sub-hole 411a and extending to the channel layer 420.

In some embodiments, the second substrate 413 is supported by a diamond material, and since the diamond material has a high hardness, a femtosecond laser technique may be used so that the second substrate 413 is perforated away from the surface of the first substrate 412 and extends to the first substrate 412, thereby forming the sub-holes 411a. For example, the sub-holes 411a may extend to the first substrate 4125 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm, and the aperture may be 20 μm.

Then, an etching process may be performed on the bottom surface of the sub-hole 411a, penetrating the first substrate 412, and extending to the channel layer 420. For example, when the thickness of the channel layer 420 is 2 μm, it may be etched to the channel layer 4201 μm, i.e., a recess structure having a depth of 1 μm is formed on the channel layer 420. Alternatively, when the thickness of the channel layer 420 is 5 μm, it may be etched to the channel layer 4204 μm, i.e., a recess structure having a depth of 4 μm is formed on the channel layer 420. Thereby forming the above-described heat dissipation hole 411.

In other embodiments, when the semiconductor device 403 includes the nucleation layer 480 and the buffer layer 490, the bottom surface of the sub-hole 411a is etched through the first substrate 412, the nucleation layer 480 and the buffer layer 490 sequentially, so as to extend to the channel layer 420.

When the second substrate 413 is perforated away from the surface of the first substrate 412, the femtosecond laser technique is used to perform the perforation, which has advantages of high precision and high speed. In addition, in addition to the femtosecond laser technology, other high-precision punching processes can be adopted. Therefore, the present application is not particularly limited thereto.

S105, the heat conduction portion 440 is filled in the heat dissipation hole 411.

In some embodiments, the heat conductive portion 440 may be made of a metal material with better heat conductivity, such as metallic copper (Cu) or metallic silver (Ag).

For example, referring to fig. 26, fig. 26 is a structural diagram of a heat conductive metal layer 471 formed in a heat dissipation hole 411 of the semiconductor device 403 provided in fig. 25. A layer of thermally conductive metal 471 may be formed within the heat sink 411 by a thin film deposition process. Then, a metal material is filled in the heat dissipation hole 411 to form the heat conduction portion 440 shown in fig. 12. In this way, the heat conductive metal layer 471 is formed by the thin film deposition process, so that the adhesion degree between the heat conductive metal layer 471 and the inner wall of the heat dissipation hole 411 can be ensured, and the heat conduction portion 440 can conduct heat better.

In addition, the heat dissipation hole 411 may be directly filled with a metal material, or the heat conduction portion 440 may be formed in the heat dissipation hole 411 by other processes. The present application is not particularly limited thereto.

S106, forming a heat conductive insulating layer 470.

A heat conductive insulating layer 470 is formed on a surface of the above-described second substrate 413 remote from the first substrate 412, thereby forming the semiconductor device 403 shown in fig. 15. On the one hand, the heat can be transferred to the second substrate 413 and the heat conducting insulating layer 470 through the heat conducting portion 440, which is beneficial to further improving the heat dissipation effect. On the other hand, the heat conductive insulating layer 470 can form electrical isolation to the heat dissipation hole 411 to improve the overall structure reliability.

In some embodiments, the thermally conductive and insulating layer 470 may comprise diamond-like material, and the thermally conductive and insulating layer 470 may have a thickness of 100nm-1 μm. The diamond-like carbon material has better heat conduction performance and insulating performance. Therefore, the heat dissipation effect of the semiconductor device 403 is advantageously improved.

Illustratively, a thermally conductive insulating layer 470 having a thickness of 100nm, 200nm, 300nm, or 500nm may be formed on a surface of the second substrate 413 remote from the first substrate 412 by a thin film deposition process.

It will be appreciated that other materials having good thermal conductivity and insulation properties may be used for the thermally conductive and insulating layer 470 in embodiments of the present application in addition to the diamond-like materials described above. Therefore, the present application is not particularly limited thereto.

Based on this, the semiconductor device 403 manufactured by the above manufacturing method can quickly transfer the heat generated during the operation of the semiconductor device 403 to the second substrate 413, so as to improve the heat dissipation performance of the semiconductor device 403, thereby reducing the temperature of the semiconductor device 403, and being beneficial to further improving the frequency and power of the semiconductor device 403, that is, improving the performance of the semiconductor device 403.

In the description of the present specification, a particular feature, structure, material, or characteristic may be combined in any suitable manner in one or more embodiments or examples.

The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A semiconductor device, comprising:

a substrate, wherein a heat dissipation hole is formed in the substrate;

the channel layer is overlapped on the substrate, and the radiating holes penetrate through the substrate and extend to the channel layer;

a barrier layer stacked on a side of the channel layer away from the substrate;

and the heat conducting part is filled in the heat dissipation hole.

2. The semiconductor device of claim 1, wherein the substrate comprises:

a first substrate, the channel layer being disposed on the first substrate;

a second substrate arranged on one side of the first substrate away from the channel layer; the radiating holes are formed in the surface, far away from the first substrate, of the second substrate, penetrate through the second substrate and the first substrate, and extend to the channel layer;

wherein the thermal conductivity of the second substrate is higher than the thermal conductivity of the first substrate.

3. The semiconductor device of claim 2, wherein the material of the second substrate comprises a diamond material.

4. The semiconductor device according to claim 2, wherein the substrate further comprises a transition layer disposed between the second substrate and the first substrate.

5. The semiconductor device according to any one of claims 1 to 4, wherein a material of the heat conductive portion includes at least one of metallic copper or metallic silver.

6. The semiconductor device according to any one of claims 1 to 5, wherein a source electrode, a gate electrode, and a drain electrode are provided on a side of the channel layer away from the first substrate, the gate electrode being provided between the source electrode and the drain electrode; and the radiating hole is arranged on one side of the gate electrode, which is close to the drain electrode, along the direction parallel to the substrate.

7. The semiconductor device according to claim 6, wherein a plurality of the heat dissipation holes are formed, and the plurality of the heat dissipation holes are distributed at intervals on a side of the gate electrode close to the drain electrode.

8. The semiconductor device according to claim 7, wherein a vertical projection of an edge of the gate electrode, which is close to the drain electrode, on the first substrate sequentially passes through a vertical projection of a portion of the plurality of heat dissipation holes, which is close to the gate electrode, on the first substrate.

9. The semiconductor device according to claim 6, wherein the source electrode and the drain electrode are provided on a surface of the channel layer remote from the first substrate, wherein the barrier layer is provided between the source electrode and the drain electrode, and wherein the gate electrode is provided on a surface of the barrier layer remote from the channel layer.

10. The semiconductor device according to claim 9, further comprising a semiconductor layer disposed between the gate electrode and the barrier layer.

11. The semiconductor device according to any one of claims 1 to 10, further comprising a thermally conductive insulating layer provided on a surface of the substrate remote from the channel layer.

12. The semiconductor device of claim 11, wherein the material of the thermally conductive insulating layer comprises a diamond-like material.

13. The semiconductor device according to any one of claims 1 to 12, wherein the semiconductor device is a GaN HEMT device.

14. A packaged device comprising a substrate and the semiconductor device of any one of claims 1-13 disposed on the substrate.

15. An electronic device comprising a circuit board and the packaged device of claim 14, the packaged device disposed on the circuit board.

16. A method of fabricating a semiconductor device, comprising:

Forming a channel layer on one side of a substrate;

forming a barrier layer on one side of the channel layer away from the substrate;

a heat dissipation hole is formed in the surface, far away from the channel layer, of the substrate, and the heat dissipation hole extends to the channel layer;

and the heat conducting part is filled in the heat radiating hole.

17. The method of manufacturing of claim 16, wherein the substrate comprises a first substrate and a second substrate, the channel layer being formed on a surface of the first substrate remote from the second substrate; the manufacturing method of the substrate comprises the following steps:

activating the first surface of the first substrate and the second surface of the second substrate;

and pressing the first substrate and the second substrate, wherein the first surface is opposite to the second surface, and bonding of the first substrate and the second substrate is realized to form the substrate.

18. The method of claim 16, wherein the substrate comprises a first substrate, a transition layer, and a second substrate, the transition layer being disposed between the first substrate and the second substrate, the channel layer being formed on a surface of the first substrate remote from the second substrate, the method of fabricating the substrate comprising:

Forming a first sub-transition layer on a first surface of the first substrate;

forming a second sub-transition layer on a second surface of the second substrate;

activating the first sub-transition layer and the second sub-transition layer;

and pressing the first sub-transition layer and the second sub-transition layer to form the transition layer by the first sub-transition layer and the second sub-transition layer, and bonding the first substrate and the second substrate to form the substrate.

19. The manufacturing method according to claim 17 or 18, wherein the manufacturing method of the heat dissipation holes includes:

punching the surface of the second substrate far away from the first substrate and extending to the first substrate to form sub-holes;

and carrying out an etching process on the bottom of the sub-hole, penetrating through the first substrate and extending to the channel layer to form the heat dissipation hole.

20. The method according to any one of claims 16 to 19, wherein the method for filling the heat-conducting portion in the heat-dissipating hole includes:

depositing a layer of material of the heat conducting part on the inner wall of the heat radiating hole to form a material layer of the heat conducting part;

And filling the heat conducting part material layer with the heat conducting part material layer to form the heat conducting part.

21. The manufacturing method according to any one of claims 16 to 20, wherein after the heat conduction portion is filled in the heat dissipation hole, the manufacturing method further comprises:

a thermally conductive insulating layer is formed on a surface of the substrate remote from the channel layer.

22. The method according to any one of claims 16 to 21, wherein before the heat dissipation holes are formed in the surface of the substrate away from the channel layer, the method further comprises:

etching a local area of the barrier layer on one side of the barrier layer far away from the channel layer to expose the channel layer, forming a source electrode mounting area and a drain electrode mounting area, wherein the barrier layer is positioned between the source electrode mounting area and the drain electrode mounting area;

manufacturing a source electrode in the source mounting region and manufacturing a drain electrode in the drain mounting region;

a gate electrode is fabricated on a surface of the barrier layer remote from the channel layer.