JP2016524819A - トランジスタ、及び、トランジスタの製造方法 - Google Patents

トランジスタ、及び、トランジスタの製造方法 Download PDF

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Publication number
JP2016524819A
JP2016524819A JP2016520370A JP2016520370A JP2016524819A JP 2016524819 A JP2016524819 A JP 2016524819A JP 2016520370 A JP2016520370 A JP 2016520370A JP 2016520370 A JP2016520370 A JP 2016520370A JP 2016524819 A JP2016524819 A JP 2016524819A
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layer
transistor
terminal
recess
support substrate
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Pending
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JP2016520370A
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Japanese (ja)
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ダヴェス ワルテル
ダヴェス ワルテル
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Robert Bosch GmbH
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Robert Bosch GmbH
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/778Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481Internal lead connections, e.g. via connections, feedthrough structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367Cooling facilitated by shape of device
    • H01L23/3677Wire-like or pin-like cooling fins or heat sinks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642Isolation within the component, i.e. internal isolation
    • H01L29/0649Dielectric regions, e.g. SiO2 regions, air gaps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003Nitride compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402Field plates
    • H01L29/407Recessed field plates, e.g. trench field plates, buried field plates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725Source or drain electrodes for field effect devices
    • H01L29/4175Source or drain electrodes for field effect devices for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
JP2016520370A 2013-06-18 2014-06-06 トランジスタ、及び、トランジスタの製造方法 Pending JP2016524819A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE102013211374.9A DE102013211374A1 (de) 2013-06-18 2013-06-18 Transistor und Verfahren zur Herstellung eines Transistors
DE102013211374.9 2013-06-18
PCT/EP2014/061800 WO2014202409A1 (de) 2013-06-18 2014-06-06 Transistor und verfahren zur herstellung eines transistors

Publications (1)

Publication Number Publication Date
JP2016524819A true JP2016524819A (ja) 2016-08-18

Family

ID=50942676

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2016520370A Pending JP2016524819A (ja) 2013-06-18 2014-06-06 トランジスタ、及び、トランジスタの製造方法

Country Status (5)

Country Link
EP (1) EP3011598A1 (de)
JP (1) JP2016524819A (de)
CN (1) CN105283959A (de)
DE (1) DE102013211374A1 (de)
WO (1) WO2014202409A1 (de)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018157100A (ja) * 2017-03-17 2018-10-04 株式会社東芝 窒化物半導体装置
JP2019125600A (ja) * 2018-01-11 2019-07-25 富士通株式会社 化合物半導体装置及びその製造方法
JP2019169551A (ja) * 2018-03-22 2019-10-03 ローム株式会社 窒化物半導体装置
JP2021114590A (ja) * 2020-01-21 2021-08-05 富士通株式会社 半導体装置、半導体装置の製造方法及び電子装置

Families Citing this family (13)

* Cited by examiner, † Cited by third party
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DE102015208150A1 (de) * 2015-05-04 2016-11-10 Robert Bosch Gmbh Verfahren zum Herstellen einer elektronischen Schaltungsvorrichtung und elektronische Schaltungsvorrichtung
CN105140281A (zh) * 2015-05-27 2015-12-09 苏州能讯高能半导体有限公司 一种半导体器件及其制造方法
DE102015212048A1 (de) * 2015-06-29 2016-12-29 Robert Bosch Gmbh Transistor mit hoher Elektronenbeweglichkeit
DE102016200825A1 (de) 2016-01-21 2017-07-27 Robert Bosch Gmbh Vorrichtung und Verfahren zur Herstellung eines lateralen HEMTs
CN107230718A (zh) * 2016-03-25 2017-10-03 北京大学 半导体器件及制造方法
US10217827B2 (en) * 2016-05-11 2019-02-26 Rfhic Corporation High electron mobility transistor (HEMT)
TWI624872B (zh) * 2017-07-20 2018-05-21 新唐科技股份有限公司 氮化物半導體元件
CN110212028B (zh) * 2019-05-22 2023-03-31 山东建筑大学 一种集成反向二极管和内嵌漏极场板的横向扩散eGaN HEMT器件
TWI692039B (zh) * 2019-05-28 2020-04-21 大陸商聚力成半導體(重慶)有限公司 半導體裝置的製作方法
US11411099B2 (en) 2019-05-28 2022-08-09 Glc Semiconductor Group (Cq) Co., Ltd. Semiconductor device
EP4283667A4 (de) * 2021-02-26 2024-04-10 Huawei Tech Co Ltd Halbleiterbauelement, elektronische vorrichtung und herstellungsverfahren für halbleiterbauelement
US20230420326A1 (en) * 2022-06-22 2023-12-28 Globalfoundries U.S. Inc. High-mobility-electron transistors having heat dissipating structures
CN117133802A (zh) * 2023-03-30 2023-11-28 荣耀终端有限公司 一种半导体器件及其制作方法、封装器件、电子设备

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JP2010067662A (ja) * 2008-09-09 2010-03-25 Nec Corp 半導体装置及びその製造方法
JP2010103236A (ja) * 2008-10-22 2010-05-06 Panasonic Corp 窒化物半導体装置
US7745848B1 (en) * 2007-08-15 2010-06-29 Nitronex Corporation Gallium nitride material devices and thermal designs thereof
JP2011014789A (ja) * 2009-07-03 2011-01-20 Furukawa Electric Co Ltd:The 窒化物系半導体電界効果トランジスタ
JP2011205071A (ja) * 2010-02-12 2011-10-13 Internatl Rectifier Corp 単一ゲートの誘電体構造を有するエンハンスメントモードのiii族窒化物トランジスタ
US20120193677A1 (en) * 2011-02-02 2012-08-02 Transphorm Inc. III-N Device Structures and Methods

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JP2001093914A (ja) * 1999-09-20 2001-04-06 Toshiba Corp 半導体能動素子及び半導体集積回路
FR2842832B1 (fr) 2002-07-24 2006-01-20 Lumilog Procede de realisation par epitaxie en phase vapeur d'un film de nitrure de gallium a faible densite de defaut
DE102004044141A1 (de) * 2004-09-13 2006-03-30 Robert Bosch Gmbh Halbleiteranordnung zur Spannungsbegrenzung
US8519438B2 (en) * 2008-04-23 2013-08-27 Transphorm Inc. Enhancement mode III-N HEMTs
US9112009B2 (en) * 2008-09-16 2015-08-18 International Rectifier Corporation III-nitride device with back-gate and field plate for improving transconductance
US20120019284A1 (en) * 2010-07-26 2012-01-26 Infineon Technologies Austria Ag Normally-Off Field Effect Transistor, a Manufacturing Method Therefor and a Method for Programming a Power Field Effect Transistor

Patent Citations (6)

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Publication number Priority date Publication date Assignee Title
US7745848B1 (en) * 2007-08-15 2010-06-29 Nitronex Corporation Gallium nitride material devices and thermal designs thereof
JP2010067662A (ja) * 2008-09-09 2010-03-25 Nec Corp 半導体装置及びその製造方法
JP2010103236A (ja) * 2008-10-22 2010-05-06 Panasonic Corp 窒化物半導体装置
JP2011014789A (ja) * 2009-07-03 2011-01-20 Furukawa Electric Co Ltd:The 窒化物系半導体電界効果トランジスタ
JP2011205071A (ja) * 2010-02-12 2011-10-13 Internatl Rectifier Corp 単一ゲートの誘電体構造を有するエンハンスメントモードのiii族窒化物トランジスタ
US20120193677A1 (en) * 2011-02-02 2012-08-02 Transphorm Inc. III-N Device Structures and Methods

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018157100A (ja) * 2017-03-17 2018-10-04 株式会社東芝 窒化物半導体装置
JP2019125600A (ja) * 2018-01-11 2019-07-25 富士通株式会社 化合物半導体装置及びその製造方法
JP7032641B2 (ja) 2018-01-11 2022-03-09 富士通株式会社 化合物半導体装置及びその製造方法
JP2019169551A (ja) * 2018-03-22 2019-10-03 ローム株式会社 窒化物半導体装置
JP7137947B2 (ja) 2018-03-22 2022-09-15 ローム株式会社 窒化物半導体装置
JP2021114590A (ja) * 2020-01-21 2021-08-05 富士通株式会社 半導体装置、半導体装置の製造方法及び電子装置

Also Published As

Publication number Publication date
DE102013211374A1 (de) 2014-12-18
EP3011598A1 (de) 2016-04-27
CN105283959A (zh) 2016-01-27
WO2014202409A1 (de) 2014-12-24

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