JP2016522994A - 絶縁ゲートバイポーラトランジスタ増幅回路 - Google Patents
絶縁ゲートバイポーラトランジスタ増幅回路 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 claims abstract description 43
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- 239000010703 silicon Substances 0.000 description 6
- 229910019001 CoSi Inorganic materials 0.000 description 4
- 229910005883 NiSi Inorganic materials 0.000 description 4
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- 230000005693 optoelectronics Effects 0.000 description 1
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Abstract
Description
絶縁層の一部分上に配置され、半導体基板の上面に延在して、バイポーラpnpトランジスタのコレクタを形成するp型コレクタ層と、
p型コレクタ層内に配置され、半導体基板の上面に延在して、バイポーラpnpトランジスタのベースを形成するn型ベース層と、
n型ベース層内に配置され、半導体基板の上面に延在して、バイポーラpnpトランジスタのエミッタを形成するp型エミッタ層と、
を備える。
半導体基板の上面から半導体基板内に延在するpウェルと、
半導体基板の上面の近傍にあり、ゲート構造の下に配置されるチャネル層と、
nチャネルIGFETのソースを形成するn型ソース層と、
nチャネルIGFETのドレインを形成するn型ドレイン層と、
を備える。
nチャネルIGFETのpウェルおよびバイポーラpnpトランジスタのコレクタ層に隣接するnウェル層であって、n型ベース層がコレクタ層により包囲され、nウェル層がコレクタ層を取り囲み、絶縁層と接触しており、バイポーラpnpトランジスタのデバイス絶縁分離を提供する、nウェル層と、
ドレイン層からベース層に延在して、低抵抗相互接続を形成すると同時にベース層にオーミック接触を提供する低抵抗相互接続層であって、低抵抗相互接続層が、pウェルの上に少なくとも部分的に、コレクタ層の上に少なくとも部分的に、およびnウェル層の上に少なくとも部分的に配置される、低抵抗相互接続層と、
を備える。
埋込n層の一部分および半導体基板の上面に延在する一部分の上に配置されて、バイポーラnpnトランジスタのコレクタを形成するn型コレクタ層と、
n型コレクタ層内に配置され、半導体基板の上面に延在して、バイポーラnpnトランジスタのベースを形成するp型ベース層と、
ベース層内に配置され、上側半導体基板に延在して、バイポーラnpnトランジスタのエミッタを形成するn型エミッタ層と、
を備える。
半導体基板の上面から半導体基板内に延在するnウェルと、
半導体基板の上面の近傍にあり、ゲート構造の下に配置されるチャネル層と、
pチャネルIGFETのソースを形成するp型ソース層と、
pチャネルIGFETのドレインを形成するp型ドレイン層と、
を備える。
pチャネルIGFETのpウェルおよびバイポーラnpnランジスタのコレクタ層に隣接するpウェル層であって、p型ベース層がコレクタ層により包囲され、pウェル層がコレクタ層を取り囲み、埋込n層と接続しており、IGFTとnpnバイポーラトランジスタとの間にデバイス絶縁分離を提供する、pウェル層と、
ドレイン層からベース層まで延在して、低抵抗相互接続を形成すると同時にベース層にオーミック接触を提供する、低抵抗相互接続層と、
を備える。
Claims (14)
- バイポーラトランジスタおよびIGFETを備え、前記IGFETが従来型または拡張ドレイン型である、ラテラルIGBTトランジスタであって、
前記IGFETの前記ドレインと前記バイポーラトランジスタのベースとの間の低抵抗接続と、
前記IGFETと前記バイポーラトランジスタとの間に配置された絶縁分離層と、
を備え、これによって、ラッチ免疫性を提供することを特徴とするラテラルIGBTトランジスタ。 - 前記ラテラルIGBTトランジスタは、バイポーラPNPトランジスタ(102)およびnチャネルIGFET(101)を備えたラテラルnチャネルIGBTトランジスタ(100)であり、前記ラテラルnチャネルIGBTトランジスタ(100)は、
半導体基板(115)と、
前記半導体基板に埋め込まれ、前記バイポーラPNPトランジスタおよび前記IGFETのドレイン層(136a)の少なくとも一部分を少なくともカバーしている絶縁層(120)と、
を備え、
前記バイポーラPNPトランジスタ(102)は、
絶縁層(120)の一部分上に配置され、前記半導体基板(115)の上面に延在して、前記バイポーラPNPトランジスタのコレクタを形成するp型コレクタ層(125b)と、
前記p型コレクタ層(125b)内に配置され、前記半導体基板(115)の上面に延在して、前記バイポーラPNPトランジスタのベースを形成するn型ベース層(127b)と、
n型ベース層(127b)内に配置され、前記半導体基板(115)の上面に延在して、前記バイポーラPNPトランジスタのエミッタを形成するp型エミッタ層(145)と、を備え、
前記nチャネルIGFETは、
前記半導体基板(115)の上面から前記半導体基板(115)内に延在するpウェル(125a)と、
前記半導体基板(115)の上面の近傍にあり、およびゲート構造(156)の下に配置されたチャネル層(126)と、
前記nチャネルIGFET(101)のソースを形成するn型ソース層(135)と、
前記nチャネルIGFET(101)のドレインを形成するn型ドレイン層(136a)と、を備え、
前記ラテラルnチャネルIGBTトランジスタ(100)は、
前記nチャネルIGFET(101)の前記pウェル(125a)および前記バイポーラPNPトランジスタ(102)のコレクタ層(125b)に隣接するnウェル層(130)であって、前記n型ベース層(127b)はコレクタ層(125b)により包囲され、前記nウェル層(130)はコレクタ層(125b)を取り囲み、および前記絶縁層(120)と接触しており、前記バイポーラPNPトランジスタ(102)のデバイス絶縁分離を提供する、該nウェル層(130)と、
前記ドレイン層(136a)からベース層(136b)まで延在して、低抵抗相互接続を形成すると同時にベース層(136b)にオーミック接触を提供する低抵抗相互接続層(136c)であって、前記pウェル(125a)の上に少なくとも部分的に、コレクタ層(125b)の上に少なくとも部分的に、および前記nウェル層(130)の上に少なくとも部分的に配置される、該低抵抗相互接続層(136c)と、
を備えたことを特徴とする請求項1に記載のラテラルIGBTトランジスタ。 - 前記半導体基板(115)が埋込酸化物層を備え、前記絶縁層(120)が前記基板全体にわたって延在する前記酸化物層によって形成されたことを特徴とする請求項2に記載のラテラルNチャネルIGBTトランジスタ(100)。
- 前記相互接続層(136c)が開口部を備え、コレクタ層(125b)への接触を可能にすることを特徴とする請求項2に記載のラテラルNチャネルIGBTトランジスタ(100)。
- 少なくとも前記相互接続層(136c)が低抵抗率のシリサイド層によって分路されることを特徴とする請求項2に記載のラテラルNチャネルIGBTトランジスタ(100)。
- 前記相互接続層(136c)がドレイン層(136a)からベース層(136b)にまたがる金属ブリッジによって分路されることを特徴とする請求項2に記載のラテラルNチャネルIGBTトランジスタ(100)。
- p型層(125b)と接触しているp型コレクタ接触層(150)と、前記エミッタ(145)および前記コレクタ接触層(150)を取り囲む酸化物絶縁分離層(310)と、
を更に備え、前記相互接続層(136c)およびベース層(136b)がnウェル層(130)によって置き換えられたことを特徴とする請求項2に記載のラテラルNチャネルIGBTトランジスタ(100)。 - 前記IGBT構造が前記エミッタを通過する仮想垂直面(122)に相対して投影されることを特徴とすることを特徴とする請求項2に記載のラテラルNチャネルIGBTトランジスタ(100)。
- 前記ラテラルIGBTトランジスタは、バイポーラNPNトランジスタ(202)およびpチャネルIGFET(201)を備えたラテラルpチャネルIGBTトランジスタ(200)であり、前記ラテラルpチャネルIGBTトランジスタ(200)は、
半導体基板(115)と、
前記バイポーラNPNトランジスタ(202)および前記IGFETのドレイン層(241a)の少なくとも一部分を少なくともカバーしている前記半導体基板(115)に配置される埋込n層(220)と、
を備え、
前記バイポーラNPNトランジスタ(202)は、
前記埋込n層(220)の一部分および前記半導体基板(115)の上面に延在する一部分の上に配置されて、前記バイポーラNPNトランジスタ(202)のコレクタを形成するn型コレクタ層(230b)と、
前記n型コレクタ層(230b)内に配置され、前記半導体基板(115)の上面に延在して、前記バイポーラNPNトランジスタ(202)のベースを形成するp型ベース層(227b)と、
ベース層(227b)内に配置され、前記半導体基板(115)の上方に延在して、前記バイポーラNPNトランジスタのエミッタを形成するn型エミッタ層(245)と、
を備え、
前記pチャネルIGFET(201)は、
前記半導体基板(115)の上面から前記半導体基板内に延在するnウェル(230a)と、
前記半導体基板(115)の上面の近傍にあり、およびゲート構造(256)の下に配置されたチャネル層(226)と、
前記pチャネルIGFET(201)のソースを形成するp型ソース層(240)と、
前記PチャネルIGFET(201)のドレインを形成するp型ドレイン層(241a)と、を備え、
前記ラテラルpチャネルIGBTトランジスタ(200)は、
前記PチャネルIGFET(201)の前記pウェル(230a)および前記バイポーラNPNトランジスタ(202)のコレクタ層(230b)に隣接するpウェル層(225)であって、前記p型ベース層(227b)はコレクタ層(230b)により包囲され、前記pウェル層(225)はコレクタ層(230b)を取り囲み、および前記埋込n層(220)と接触しており、IGFET(201)と前記NPNバイポーラトランジスタ(202)との間にデバイス絶縁分離を提供する、該pウェル層(225)と、
前記ドレイン層(241a)から前記ベース層(241b)まで延在して、低抵抗相互接続を形成すると同時に前記ベース層(227b)にオーミック接触を提供する低抵抗相互接続層(241c)であって、前記nウェル(230a)上に少なくとも部分的に、コレクタ層(230b)上に少なくとも部分的に、および前記pウェル層(225)上に少なくとも部分的に配置された、該低抵抗相互接続層(241c)と、
を備えたことを特徴とする請求項1に記載のラテラルIGBTトランジスタ。 - 前記半導体基板(115)が前記基板全体にわたって延在する絶縁層(220)を形成する埋込酸化物層を備えたことを特徴とする請求項9に記載のラテラルPチャネルIGBTトランジスタ(200)。
- 前記相互接続層(241c)が開口部を備え、コレクタ層(230b)への接触を可能にすることを特徴とする請求項9に記載のラテラルPチャネルIGBTトランジスタ(200)。
- 少なくとも前記相互接続層(241c)が低抵抗率のシリサイド層によって分路されることを特徴とする請求項9に記載のラテラルPチャネルIGBTトランジスタ(200)。
- 前記相互接続層(241c)がドレイン層(241a)からベース層(241b)にまたがる金属ブリッジによって分路されたことを特徴とする請求項9に記載のラテラルPチャネルIGBTトランジスタ(100)。
- n型層(230b)と接触しているn型コレクタ接触層(250)と、前記エミッタ(145)および前記コレクタ接触層(250)を取り囲む酸化物絶縁分離層(310)と、を更に備え、前記相互接続層(241c)およびベース層(241b)がpウェル層(225)によって置き換えられたことを特徴とする請求項9に記載のラテラルPチャネルIGBTトランジスタ(100)。
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