JP2016515274A5 - - Google Patents

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Publication number
JP2016515274A5
JP2016515274A5 JP2016502013A JP2016502013A JP2016515274A5 JP 2016515274 A5 JP2016515274 A5 JP 2016515274A5 JP 2016502013 A JP2016502013 A JP 2016502013A JP 2016502013 A JP2016502013 A JP 2016502013A JP 2016515274 A5 JP2016515274 A5 JP 2016515274A5
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JP
Japan
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memory
type
cached information
cache
storing
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JP2016502013A
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English (en)
Japanese (ja)
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JP6154060B2 (ja
JP2016515274A (ja
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Priority claimed from US13/843,190 external-priority patent/US9304913B2/en
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Publication of JP2016515274A publication Critical patent/JP2016515274A/ja
Publication of JP2016515274A5 publication Critical patent/JP2016515274A5/ja
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Publication of JP6154060B2 publication Critical patent/JP6154060B2/ja
Expired - Fee Related legal-status Critical Current
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JP2016502013A 2013-03-15 2014-03-13 混載メモリタイプハイブリッドキャッシュ Expired - Fee Related JP6154060B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/843,190 US9304913B2 (en) 2013-03-15 2013-03-15 Mixed memory type hybrid cache
US13/843,190 2013-03-15
PCT/US2014/025971 WO2014151548A1 (en) 2013-03-15 2014-03-13 Mixed memory type hybrid cache

Publications (3)

Publication Number Publication Date
JP2016515274A JP2016515274A (ja) 2016-05-26
JP2016515274A5 true JP2016515274A5 (enExample) 2016-07-07
JP6154060B2 JP6154060B2 (ja) 2017-06-28

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ID=50628954

Family Applications (1)

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JP2016502013A Expired - Fee Related JP6154060B2 (ja) 2013-03-15 2014-03-13 混載メモリタイプハイブリッドキャッシュ

Country Status (6)

Country Link
US (1) US9304913B2 (enExample)
EP (1) EP2972892B1 (enExample)
JP (1) JP6154060B2 (enExample)
KR (1) KR20150132360A (enExample)
CN (1) CN105009095B (enExample)
WO (1) WO2014151548A1 (enExample)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5520747B2 (ja) * 2010-08-25 2014-06-11 株式会社日立製作所 キャッシュを搭載した情報装置及びコンピュータ読み取り可能な記憶媒体
CN107533459B (zh) 2016-03-31 2020-11-20 慧与发展有限责任合伙企业 使用电阻存储器阵列的数据处理方法和单元
US10474557B2 (en) 2016-07-19 2019-11-12 Sap Se Source code profiling for line-level latency and energy consumption estimation
US10437798B2 (en) 2016-07-19 2019-10-08 Sap Se Full system simulator and memory-aware splay tree for in-memory databases in hybrid memory systems
US10783146B2 (en) 2016-07-19 2020-09-22 Sap Se Join operations in hybrid main memory systems
US10387127B2 (en) * 2016-07-19 2019-08-20 Sap Se Detecting sequential access data and random access data for placement on hybrid main memory for in-memory databases
US10452539B2 (en) 2016-07-19 2019-10-22 Sap Se Simulator for enterprise-scale simulations on hybrid main memory systems
US10540098B2 (en) 2016-07-19 2020-01-21 Sap Se Workload-aware page management for in-memory databases in hybrid main memory systems
US11977484B2 (en) 2016-07-19 2024-05-07 Sap Se Adapting in-memory database in hybrid memory systems and operating system interface
US10698732B2 (en) 2016-07-19 2020-06-30 Sap Se Page ranking in operating system virtual pages in hybrid memory systems
KR102835585B1 (ko) * 2016-11-07 2025-07-18 삼성전자주식회사 데이터 처리 방법 및 디바이스
US10235299B2 (en) 2016-11-07 2019-03-19 Samsung Electronics Co., Ltd. Method and device for processing data
US20180374893A1 (en) * 2017-06-22 2018-12-27 Globalfoundries Singapore Pte. Ltd. Differential sensing cell design for stt mram
US11010379B2 (en) 2017-08-15 2021-05-18 Sap Se Increasing performance of in-memory databases using re-ordered query execution plans
WO2019212466A1 (en) * 2018-04-30 2019-11-07 Hewlett Packard Enterprise Development Lp Resistive and digital processing cores
US10896707B2 (en) * 2018-12-17 2021-01-19 Arm Limited Selective clock adjustment during read and/or write memory operations
CN118732924B (zh) * 2023-03-28 2025-11-11 华为技术有限公司 一种数据访存方法及片上系统

Family Cites Families (14)

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Publication number Priority date Publication date Assignee Title
JPH08328949A (ja) * 1995-06-06 1996-12-13 Mitsubishi Electric Corp 記憶装置
JP3092557B2 (ja) * 1997-09-16 2000-09-25 日本電気株式会社 半導体記憶装置
JP3604296B2 (ja) * 1998-01-22 2004-12-22 松下電器産業株式会社 半導体メモリおよびメモリシステム
JP2000339954A (ja) 1999-05-31 2000-12-08 Fujitsu Ltd 半導体記憶装置
JP2002351741A (ja) * 2001-05-30 2002-12-06 Matsushita Electric Ind Co Ltd 半導体集積回路装置
US7293141B1 (en) * 2005-02-01 2007-11-06 Advanced Micro Devices, Inc. Cache word of interest latency organization
JP4437489B2 (ja) 2006-10-25 2010-03-24 株式会社日立製作所 揮発性キャッシュメモリと不揮発性メモリとを備えたストレージシステム
US7584335B2 (en) * 2006-11-02 2009-09-01 International Business Machines Corporation Methods and arrangements for hybrid data storage
US7568068B2 (en) 2006-11-13 2009-07-28 Hitachi Global Storage Technologies Netherlands B. V. Disk drive with cache having volatile and nonvolatile memory
US7962695B2 (en) * 2007-12-04 2011-06-14 International Business Machines Corporation Method and system for integrating SRAM and DRAM architecture in set associative cache
WO2010148359A1 (en) * 2009-06-18 2010-12-23 Cypress Semiconductor Corporation Memory devices and systems including multi-speed access of memory modules
US8914568B2 (en) 2009-12-23 2014-12-16 Intel Corporation Hybrid memory architectures
JP2012190359A (ja) * 2011-03-11 2012-10-04 Toshiba Corp キャッシュシステムおよび処理装置
JP5627521B2 (ja) 2011-03-24 2014-11-19 株式会社東芝 キャッシュシステムおよび処理装置

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