JP2016513872A - ビア使用パッケージオンパッケージ - Google Patents

ビア使用パッケージオンパッケージ Download PDF

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Publication number
JP2016513872A
JP2016513872A JP2015561619A JP2015561619A JP2016513872A JP 2016513872 A JP2016513872 A JP 2016513872A JP 2015561619 A JP2015561619 A JP 2015561619A JP 2015561619 A JP2015561619 A JP 2015561619A JP 2016513872 A JP2016513872 A JP 2016513872A
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JP
Japan
Prior art keywords
package
die
substrate
integrated circuit
interposer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2015561619A
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English (en)
Japanese (ja)
Other versions
JP2016513872A5 (enExample
Inventor
デュロダミ・ジョスリン・リスク
ヴィディヤ・ラマチャンドラン
ジェ・シク・リー
Original Assignee
クアルコム，インコーポレイテッド
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by クアルコム，インコーポレイテッド filed Critical クアルコム，インコーポレイテッド
Publication of JP2016513872A publication Critical patent/JP2016513872A/ja
Publication of JP2016513872A5 publication Critical patent/JP2016513872A5/ja
Pending legal-status Critical Current

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Classifications

    • H10W70/611—
    • H10W70/635—
    • H10W90/00—
    • H10W70/60—
    • H10W72/07232—
    • H10W72/07252—
    • H10W72/07254—
    • H10W72/227—
    • H10W72/244—
    • H10W72/247—
    • H10W72/248—
    • H10W72/252—
    • H10W72/29—
    • H10W72/884—
    • H10W72/9226—
    • H10W72/923—
    • H10W72/944—
    • H10W74/15—
    • H10W90/297—
    • H10W90/722—
    • H10W90/724—
    • H10W90/732—
    • H10W90/734—
    • H10W90/754—

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Manufacturing & Machinery (AREA)
  • Micromachines (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
JP2015561619A 2013-03-08 2014-03-05 ビア使用パッケージオンパッケージ Pending JP2016513872A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/791,223 US20140252561A1 (en) 2013-03-08 2013-03-08 Via-enabled package-on-package
US13/791,223 2013-03-08
PCT/US2014/020868 WO2014138285A1 (en) 2013-03-08 2014-03-05 Via-enabled package-on-package

Publications (2)

Publication Number Publication Date
JP2016513872A true JP2016513872A (ja) 2016-05-16
JP2016513872A5 JP2016513872A5 (enExample) 2017-03-23

Family

ID=50382674

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2015561619A Pending JP2016513872A (ja) 2013-03-08 2014-03-05 ビア使用パッケージオンパッケージ

Country Status (6)

Country Link
US (1) US20140252561A1 (enExample)
EP (1) EP2965357A1 (enExample)
JP (1) JP2016513872A (enExample)
KR (1) KR20150127162A (enExample)
CN (1) CN105027282A (enExample)
WO (1) WO2014138285A1 (enExample)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9070644B2 (en) 2013-03-15 2015-06-30 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging mechanisms for dies with different sizes of connectors
US9646894B2 (en) * 2013-03-15 2017-05-09 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging mechanisms for dies with different sizes of connectors
KR102245770B1 (ko) * 2013-10-29 2021-04-28 삼성전자주식회사 반도체 패키지 장치
KR102198858B1 (ko) * 2014-07-24 2021-01-05 삼성전자 주식회사 인터포저 기판을 갖는 반도체 패키지 적층 구조체
US9859202B2 (en) * 2015-06-24 2018-01-02 Dyi-chung Hu Spacer connector
CN106672888B (zh) * 2015-11-11 2022-03-11 恩智浦美国有限公司 封装集成电路管芯的方法和器件
KR102372300B1 (ko) * 2015-11-26 2022-03-08 삼성전자주식회사 스택 패키지 및 그 제조 방법
US10181456B2 (en) * 2017-03-16 2019-01-15 Intel Corporation Multi-package integrated circuit assembly with package on package interconnects
US10438930B2 (en) * 2017-06-30 2019-10-08 Intel Corporation Package on package thermal transfer systems and methods
CN107564900B (zh) * 2017-08-29 2019-09-03 中国电子科技集团公司第五十八研究所 基于射频信号传输的扇出型封装结构及制造方法
US10636774B2 (en) 2017-09-06 2020-04-28 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming a 3D integrated system-in-package module
KR102519571B1 (ko) 2018-06-11 2023-04-10 삼성전자주식회사 반도체 패키지
KR102899838B1 (ko) * 2020-09-10 2025-12-11 삼성전기주식회사 전자부품 장치

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009141169A (ja) * 2007-12-07 2009-06-25 Shinko Electric Ind Co Ltd 半導体装置
JP2012502506A (ja) * 2008-09-11 2012-01-26 マイクロン テクノロジー， インク． 積層素子における信号送出

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100817073B1 (ko) * 2006-11-03 2008-03-26 삼성전자주식회사 휨방지용 보강부재가 기판에 연결된 반도체 칩 스택 패키지
US8063846B2 (en) * 2006-12-28 2011-11-22 Sanyo Electric Co., Ltd. Semiconductor module and mobile apparatus
US8421244B2 (en) * 2007-05-08 2013-04-16 Samsung Electronics Co., Ltd. Semiconductor package and method of forming the same
US9230898B2 (en) * 2009-08-17 2016-01-05 Stats Chippac Ltd. Integrated circuit packaging system with package-on-package and method of manufacture thereof
US8518752B2 (en) * 2009-12-02 2013-08-27 Stats Chippac Ltd. Integrated circuit packaging system with stackable package and method of manufacture thereof
US8519537B2 (en) * 2010-02-26 2013-08-27 Taiwan Semiconductor Manufacturing Company, Ltd. 3D semiconductor package interposer with die cavity
KR101695846B1 (ko) * 2010-03-02 2017-01-16 삼성전자 주식회사 적층형 반도체 패키지
US8541872B2 (en) * 2010-06-02 2013-09-24 Stats Chippac Ltd. Integrated circuit package system with package stacking and method of manufacture thereof
US8217502B2 (en) * 2010-06-08 2012-07-10 Stats Chippac Ltd. Integrated circuit packaging system with multipart conductive pillars and method of manufacture thereof
US20120193785A1 (en) * 2011-02-01 2012-08-02 Megica Corporation Multichip Packages
KR20120091691A (ko) * 2011-02-09 2012-08-20 삼성전자주식회사 휨 방지용 접합패턴을 갖는 반도체 소자 및 그 제조방법
US8716065B2 (en) * 2011-09-23 2014-05-06 Stats Chippac Ltd. Integrated circuit packaging system with encapsulation and method of manufacture thereof
JP2013077711A (ja) * 2011-09-30 2013-04-25 Sony Corp 半導体装置および半導体装置の製造方法
TWI476888B (zh) * 2011-10-31 2015-03-11 欣興電子股份有限公司 嵌埋穿孔中介層之封裝基板及其製法
KR101818507B1 (ko) * 2012-01-11 2018-01-15 삼성전자 주식회사 반도체 패키지
US8809995B2 (en) * 2012-02-29 2014-08-19 International Business Machines Corporation Through silicon via noise suppression using buried interface contacts
US9478474B2 (en) * 2012-12-28 2016-10-25 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for forming package-on-packages

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009141169A (ja) * 2007-12-07 2009-06-25 Shinko Electric Ind Co Ltd 半導体装置
JP2012502506A (ja) * 2008-09-11 2012-01-26 マイクロン テクノロジー， インク． 積層素子における信号送出

Also Published As

Publication number Publication date
EP2965357A1 (en) 2016-01-13
WO2014138285A1 (en) 2014-09-12
US20140252561A1 (en) 2014-09-11
CN105027282A (zh) 2015-11-04
KR20150127162A (ko) 2015-11-16

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