JP2016197759A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of preventing storage of electric charges in a semiconductor layer.SOLUTION: A semiconductor device comprises: a semiconductor layer that has an element formation region comprising a semiconductor element, and an element isolation region contacted with the element formation region in a plan view, comprising a first opening, and consisting of a first insulation member; a second insulation member formed so that its first surface is contacted with a principal surface of the semiconductor layer, and that comprises a second opening communicated with the first opening, and a third opening provided at a different position from the second opening; a third insulation member that comprises a second surface contacted with a rear face of the semiconductor layer opposed to the principal surface of the semiconductor layer, and a third surface opposed to the second surface, and that has a fourth opening communicated with the first opening; and a second conductive member connected with a first conductive member having a thickness smaller than a distance between the principal surface of the semiconductor layer and the third surface, and formed in the first opening, the second opening, and the fourth opening that have a continuous side wall.SELECTED DRAWING: Figure 7

Description

  The present invention relates to a semiconductor device.

  In an SOI (Silicon On Insulator) device, a silicon substrate layer and a thin film silicon layer (also referred to as SOI layer) formed thereon are insulated and separated by a buried oxide film layer (also referred to as BOX (Buried Oxide) layer). It has a structure. As a result, the isolation between adjacent elements on the thin film silicon layer can be easily performed, and a parasitic thyristor is not formed through the silicon substrate layer, thereby preventing a latch-up phenomenon. It becomes. In addition, it is effective to suppress the so-called short channel effect in which the power consumption increases with the miniaturization of the transistor, by forming the transistor in the thin silicon layer on the buried oxide film layer. Further, since the junction capacitance of the transistor formed over the SOI substrate is smaller than that of the transistor formed over the bulk substrate, high-speed operation is possible. Thus, a transistor formed over an SOI substrate has many excellent characteristics, and can achieve higher speed and lower power consumption than those formed over a conventional bulk substrate.

  In Patent Document 1, in a semiconductor device using an SOI wafer, in order to prevent the SOI wafer surface from being charged up by metal sputtering or dry etching, the edge region of the silicon substrate layer is exposed and conductive so as to include the exposed portion. A method of forming a layer is described.

JP 2005-93646 A

FIGS. 1A, 1 </ b> B, and 1 </ b> C are cross-sectional views illustrating a process of forming a contact hole in the intermediate insulator layer 30 formed on the SOI substrate 10. The SOI substrate 10 is configured by laminating a substrate layer 11, a buried oxide film layer 12, and a semiconductor layer 13. The semiconductor layer 13 has an element isolation layer 14 made of an insulator such as SiO ₂ , and the formation region of the element isolation layer 14 is an element isolation region 15, and a region other than the element isolation region 15 is an element formation region 16. Is done. After a semiconductor element (not shown) such as a MOSFET is formed on the element formation region 16, an intermediate insulator layer 30 made of an insulator such as SiO ₂ is formed so as to entirely cover the semiconductor layer 13.

  Next, as illustrated in FIG. 1A, a photoresist is formed on the surface of the intermediate insulator layer 30, and the photoresist is patterned using a photolithography technique to form a resist mask 40. The resist mask 40 has openings 41 a, 42 a, 43 a at contact hole formation positions on the element formation region 16.

  Next, as shown in FIG. 1B, dry etching is performed through the patterned resist mask 40 to form contact holes 51 a, 52 a, and 53 a in the intermediate insulator layer 30. In this dry etching, all the contact holes are not formed at a uniform etching rate, and the progress of etching has some variation between the contact holes. That is, as shown in FIG. 1B, the timing at which the contact holes reach the semiconductor layer 13 differs between the contact holes. At this time, electric charges due to plasma irradiated during dry etching are injected into the element formation region 16 of the semiconductor layer 13 through the contact holes 51a and 53a that have reached the semiconductor layer 13 earlier. Since the element formation region 16 is insulated and isolated by the buried oxide film layer 12 and the element isolation layer 14, the charge injected into the element formation region 16 is accumulated therein. Thereafter, as shown in FIG. 1C, as the etching of the contact hole 52a proceeds, the thickness of the portion immediately below the contact hole 52a of the intermediate insulator layer 30 is reduced, and the insulation of the intermediate insulator layer 30 is reduced in the portion. The pressure resistance decreases. If the intermediate insulator layer 30 thinned immediately below the contact hole 52a cannot withstand the electric field generated by the electric charge accumulated in the semiconductor layer 13, the dielectric breakdown occurs, and the influence is caused by the semiconductor layer 13 and the buried oxide film. It will also extend to layer 12.

  FIG. 2 is a cross-sectional view of the SOI substrate 10 that has been broken by the above-described mechanism in the portion immediately below the contact hole 50 and has a fracture mark X.

  The present invention has been made in view of the above-described points. In a semiconductor device having a semiconductor layer insulated from a substrate layer and an insulator layer formed on the semiconductor layer, the semiconductor device is provided on the surface of the insulator layer. An object of the present invention is to provide a semiconductor device capable of preventing charge accumulation in a semiconductor layer when a contact hole reaching the layer is formed by dry etching.

  A semiconductor device according to the present invention includes an element formation region including a semiconductor element, and an element isolation region that is in contact with the element formation region in plan view and includes a first opening and is formed of a first insulating member. And a second opening formed in contact with the first surface of the semiconductor layer and communicating with the first opening, and a third opening provided at a position different from the second opening. A second insulating member, a second surface in contact with the back surface of the semiconductor layer facing the main surface of the semiconductor layer, and a third surface facing the second surface, and in communication with the first opening. Connected to a third insulating member having a fourth opening and a first conductive member having a thickness smaller than a distance between the main surface and the third surface of the semiconductor layer, and continuous The first opening and the second opening having side walls; A second conductive member formed in the interior of the serial fourth opening, characterized in that it comprises a.

  According to the semiconductor device of the present invention, when a contact hole reaching the semiconductor layer from the surface of the insulator layer is formed by dry etching, charge accumulation in the semiconductor layer can be prevented. Therefore, the insulator layer and the semiconductor layer can be prevented from being destroyed due to etching.

FIG. 1 is a cross-sectional view showing a conventional method for forming a contact hole. FIG. 2 is a cross-sectional view showing the state of the semiconductor layer and the buried oxide film layer destroyed in the portion immediately below the contact hole. 3 (a), 3 (c), and 3 (e) are plan views showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention, and FIG. 3 (b) and FIG. 3 (d). FIG. 3F is a cross-sectional view taken along lines 3b-3b, 3d-3d, and 3f-3f in FIGS. 3A, 3C, and 3E, respectively. 4 (a), 4 (c), and 4 (e) are plan views showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention, and FIG. 4 (b) and FIG. 4 (d). FIG. 4F is a cross-sectional view taken along lines 4b-4b, 4d-4d, and 4f-4f in FIGS. 4A, 4C, and 4E, respectively. 5 (a), 5 (c), and 5 (e) are plan views showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention, and FIG. 5 (b) and FIG. 5 (d). FIG. 5F is a cross-sectional view taken along lines 5b-5b, 5d-5d, and 5f-5f in FIGS. 5A, 5C, and 5E, respectively. 6A is a plan view showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention, and FIG. 6B is a cross-sectional view taken along the line 6b-6b in FIG. 6A. is there. FIG. 7 is a cross-sectional view showing the flow of charges injected into the semiconductor layer during dry etching when forming contact holes. 8 (a), 8 (c), and 8 (e) are plan views showing a method for manufacturing a semiconductor device according to the second embodiment of the present invention, and FIG. 8 (b) and FIG. 8 (d). FIG. 8F is a cross-sectional view taken along lines 8b-8b, 8d-8d, and 8f-8f in FIGS. 8A, 8C, and 8E, respectively. 9 (a), 9 (c), and 9 (e) are plan views showing a method for manufacturing a semiconductor device according to the second embodiment of the present invention, and FIG. 9 (b) and FIG. 9 (d). 9F is a cross-sectional view taken along lines 9b-9b, 9d-9d, and 9f-9f in FIGS. 9A, 9C, and 9E, respectively.

  Embodiments of the present invention will be described below with reference to the drawings. In the drawings, substantially the same or equivalent components or parts are denoted by the same reference numerals.

<First Embodiment>
3 to 6 are a cross-sectional view and a plan view showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention. 3 (a), 3 (c), 3 (e), 4 (a), 4 (c), 4 (e), 5 (a), 5 (c), 5 FIG. 6E and FIG. 6A are plan views for each process step of the method for manufacturing a semiconductor device according to the embodiment of the present invention. FIG. 3B, FIG. 3D, and FIG. 4 (b), FIG. 4 (d), FIG. 4 (f), FIG. 5 (b), FIG. 5 (d), FIG. 5 (f) and FIG. 6 (b) are respectively shown in FIG. 3), FIG. 3C, FIG. 3E, FIG. 4A, FIG. 4C, FIG. 4E, FIG. 5A, FIG. 5C, FIG. 3b-3b line, 3d-3d line, 3f-3f, 4b-4b line, 4d-4d line, 4f-4f, 5b-5b line, 5d-5d line, 5f-5f, 6b- in FIG. FIG. 6 is a cross-sectional view taken along line 6b. That is, in each drawing, a plan view and a sectional view corresponding to each process step are shown.

(Preparation of SOI substrate)
First, an SOI substrate 10 comprising a substrate layer 11, a buried oxide film layer (BOX layer) 12, and a semiconductor layer (SOI layer) 13 as shown in FIGS. 3A and 3B is prepared. To do. The substrate layer 11 can be made of a semiconductor material such as silicon, but is not limited to this, and may be made of a conductor material or the like. The semiconductor layer 13 can be made of a semiconductor material such as silicon, but is not limited to this, and may be made of a semiconductor material other than silicon. The SOI substrate 10 may be formed by any method such as a bonding method or a SIMOX (Silicon Implanted Oxide) method. Incidentally, in the SIMOX method, high-energy and high-concentration oxygen is ion-implanted from the prime wafer surface, and then the implanted oxygen and silicon are reacted by heat treatment to form a buried oxide film layer composed of a SiO ₂ film inside the wafer surface. Thus, an SOI substrate is produced. On the other hand, in the bonding method, a silicon wafer having a SiO ₂ film formed on the surface and another silicon wafer are bonded with heat and pressure, and the silicon wafer on one side is ground and removed so as to leave only a predetermined thickness. An SOI substrate is created. The substrate layer 11 corresponds to the substrate layer of the present invention, the buried oxide film layer 12 corresponds to the first insulator layer of the present invention, and the semiconductor layer 13 corresponds to the semiconductor layer of the present invention. In the manufacturing method according to the embodiment of the present invention, the semiconductor layer 13 has p-type conductivity.

Next, as shown in FIGS. 3C and 3D, buried oxidation is performed by a known local oxidation of silicon (LOCOS) method, shallow trench isolation (STI) method, deep trench isolation (DTI) method, or the like. An element isolation layer 14 made of, for example, SiO ₂ is formed on the film layer 12 so as to electrically isolate the semiconductor layer 13 into a plurality of regions. The element isolation layer 14 is for insulating and isolating adjacent semiconductor elements formed on the semiconductor layer 13. In the semiconductor layer 13, a region where the element isolation layer 14 is formed is an element isolation region (inactive region) 15, and a region other than the element isolation region 15 is an element formation region (active region) 16. The element isolation region 15 is formed, for example, so as to surround the element formation region 16. Although each element forming region 16 is shown in each drawing, the semiconductor layer 13 may have a plurality of element forming regions 16 that are insulated and separated by the element isolation layer 14. When a p-channel MOSFET is formed in the semiconductor layer 13, an n-well region having an n-type conductivity is formed in the semiconductor layer 13 before forming the element isolation layer 14.

(Formation of semiconductor elements)
Next, as shown in FIGS. 3E and 3F, a semiconductor element 20 such as a MOSFET is formed in the element formation region 16 of the semiconductor layer 13. Specifically, a gate oxide film 21 made of SiO ₂ is formed on the surface of the semiconductor layer 13 by thermal oxidation treatment. Subsequently, for example, a silane (SiH ₄ ) gas is thermally decomposed in nitrogen (N ₂ ) gas by CVD (chemical vapor deposition) or the like to form a polysilicon film on the gate oxide film 21. The gate electrode 22 is formed by patterning. Next, using the gate electrode 22 as a mask, for example, phosphorus is ion-implanted into the semiconductor layer 13 to form an n-type source region 23 and drain region 24 in a self-aligned manner with respect to the gate electrode 22 in the element formation region 16. To do. As a result, the semiconductor element 20 is formed in the element formation region 16 of the semiconductor layer 13. In the above description, the case where an n-channel MOSFET is formed as a semiconductor element is illustrated, but other semiconductor elements such as a p-channel MOSFET, a bipolar transistor, a resistance element, and a capacitor may be formed.

(Formation of intermediate insulator layer)
Next, as shown in FIGS. 4A and 4B, an intermediate insulator layer 30 is formed so as to entirely cover the surface of the semiconductor layer 13 on which the semiconductor element 20 is formed. The intermediate insulator layer 30 is formed by covering the entire surface of the semiconductor layer 13 with a SiO ₂ film by a CVD method using, for example, silane (SiH ₄ ) gas and oxygen (O ₂ ) gas as material gases. However, it is not limited to such a method. In addition, the intermediate insulator layer 30 can be made of an insulator other than SiO ₂ . The intermediate insulator layer 30 corresponds to the second insulator layer in the present invention.

(Formation of first layer resist mask)
Next, as shown in FIGS. 4C and 4D, a first-layer resist mask 40 for forming contact holes is formed on the intermediate insulator layer 30. Specifically, a photosensitive resin generally used as a photoresist material is formed on the intermediate insulator layer 30 by a spin coat method or the like. Thereafter, a heat treatment is applied to the coated photoresist material (pre-baking). Next, openings 41 and 42 are formed in the photoresist material by exposure and development processing. Thereby, a resist mask 40 is formed on the intermediate insulator layer 30. The resist mask 40 has at least one opening 41 provided on the element isolation region 15 and at least one opening 42 provided on the element formation region 16. The resist mask 40 corresponds to the first mask layer of the present invention.

(Contact hole formation: 1st time)
Next, as shown in FIGS. 4E and 4F, a plasma dry etching process is performed through the resist mask 40 so that the surface of the intermediate insulator layer 30 passes through the element isolation layer 14. At least one contact hole 51 reaching the substrate layer 11 is formed, and at least one contact hole 52 reaching the element formation region 16 of the semiconductor layer 13 from the surface of the intermediate insulator layer 30 is formed. In the present embodiment, the contact hole 52 is formed so as to reach the source region of the semiconductor element 20. In this dry etching, the etching rate for SiO ₂ constituting the intermediate insulator layer 30, the element isolation layer 14, and the buried oxide film layer 12 is the etching rate for Si constituting the semiconductor layer 13 in the element formation region 16 of the semiconductor layer 13. Higher etching gas is used. That is, an etching gas having a relatively high selectivity between Si and SiO ₂ is used. Examples of such an etching gas include a mixed gas of CH ₄ and H ₂ , CHF ₃ , C ₂ F ₆ , and the like. When the contact hole 52 reaches the element formation region 16 of the semiconductor layer 13 made of Si having a low etching rate by dry etching using an etching gas having such etching selectivity, the progress of the etching is substantially stopped. On the other hand, the intermediate insulator layer 30, the element isolation layer 14, and the buried oxide film layer 12 are each made of SiO ₂ having a high etching rate, so that the contact hole 51 reaches the substrate layer 11. That is, in this step, the contact hole 51 reaching the substrate layer 11 through the intermediate insulator layer 30, the element isolation layer 14 and the buried oxide film layer 12, and the semiconductor layer 13 through the intermediate insulator layer 30. A contact hole 52 reaching the element formation region 16 is formed at the same time. In addition, the progress of the etching in the contact hole 51 can be easily stopped by forming an alloy layer on the surface of the gate electrode, the source region, and the drain region of the semiconductor element 20 by the salicide process. The contact hole 51 corresponds to the first contact hole in the present invention, and the contact hole 52 corresponds to the second contact hole in the present invention.
In general, in the plasma dry etching process, a reaction product generated by etching is deposited on the side wall of the etching portion or the surface of the resist mask. The deposited layer made of this reaction product usually contains carbon (C), oxygen (O), fluorine (F), hydrogen (H), etc. contained in the resist material or etching gas. ) Due to the presence of). This deposited layer is generally called a “deposited film”. Also in the manufacturing method according to the embodiment of the present invention, the bottom and side surfaces of the contact holes 51 and 52 and the surface and side surfaces of the resist mask 40 are covered with the deposited layer 60 made of a reaction product generated during dry etching. Is called. Since the deposited layer 60 has conductivity, the element formation region 16 of the semiconductor layer 13 and the substrate layer 11 are electrically connected via the deposited layer 60.

  In a general semiconductor device manufacturing process, the resist mask and the deposited layer (deposition film) are removed by ashing and chemical treatment after the contact holes are formed. However, in the manufacturing method according to the embodiment of the present invention, the resist mask 40 and the deposited layer 60 are not removed even after the contact holes 51 and 52 are formed, and the process proceeds to the next process while leaving them.

  In the manufacturing method according to the embodiment of the present invention, the contact hole 52 is for forming a source contact of the semiconductor element 20, for example. However, in this step, the contact hole formed on the element formation region 16 may be formed for a purpose other than the source contact, for example, for forming a drain contact or a gate contact. Alternatively, a so-called dummy contact that does not contact the semiconductor element may be formed. However, since the gate oxide film 21 exists immediately below the gate electrode 22, when the contact hole 52 is connected to the gate electrode, the third contact hole is formed in a later step. There is a possibility that the charge injected into the element formation region 16 due to the dry etching is insufficiently eliminated. Therefore, the contact hole 52 is preferably connected to the source or drain. The contact hole 52 may be connected to a region of the element formation region 16 other than the gate, source, and drain.

In this step, the contact hole 52 formed on the element formation region 16 and the contact hole 51 formed on the element isolation region 15 and reaching the substrate layer 11 are preferably arranged close to each other. By bringing the contact hole 51 and the contact hole 52 close to each other, the electrical resistance on the conductive path by the deposited layer 60 from the element formation region 16 of the semiconductor layer 13 to the substrate layer 11 can be reduced. This is advantageous in eliminating the charge injected into the element formation region 16 due to the dry etching when the third contact hole is formed in a later process. Therefore, the contact hole 52 is preferably formed corresponding to, for example, one of the drain and source constituting the semiconductor element 20 that is disposed closest to the contact hole 51.
In this step, the number of contact holes 52 formed on one element formation region 16 is preferably small, and more preferably one. By reducing the number of contact holes reaching the element formation region 16 of the semiconductor layer 13, the amount of charge accumulated in the element formation region 16 can be reduced. If only one contact hole 52 is formed in one element formation region 16, the dielectric breakdown of the intermediate insulator layer 30 as described above does not occur.

(Formation of second layer resist mask)
Next, as shown in FIGS. 5A and 5B, a second-layer resist mask 70 is formed on the first-layer resist mask 40 formed previously. Specifically, a photosensitive resin generally used as a photoresist material is formed on the first resist mask 40 by spin coating or the like. Thereafter, a heat treatment is applied to the coated photoresist material (pre-baking). Next, openings 71 and 72 are formed in the photoresist material by exposure and development processing. As a result, a second-layer resist mask 70 is formed on the first-layer resist mask 40. The openings 71 and 72 are disposed on the element formation region 16 of the semiconductor layer 13 and are disposed at positions different from the formation positions of the contact holes 52 formed previously.

(Contact hole formation: 2nd)
Next, as shown in FIGS. 5C and 5D, a plasma dry etching process is performed through the resist mask 70, whereby the deposited layer 60, the first resist mask 40, and the intermediate insulator are processed. Contact holes 81 and 82 that penetrate the layer 30 and reach the element formation region 16 are formed. The contact hole 81 is for forming a gate contact of the semiconductor element 20, for example, and the contact hole 82 is for forming a drain contact of the semiconductor element 20, for example. However, the contact hole formed in this step may be formed for purposes other than the drain contact and the gate contact. Further, the number of contact holes formed in this step can be appropriately changed as necessary. That is, a plurality of contacts may be formed with respect to the gate, source, drain, or the like. Further, the contact hole 52 formed in advance is used for forming a source contact or a drain contact which is necessary for the function, so that a contact hole for a source contact or a drain contact is separately formed in this step. This eliminates the need for the element area. The contact holes 81 and 82 correspond to the third contact hole of the present invention.

  In this step, as shown in FIG. 7, the charge e due to the plasma irradiated during dry etching is injected into the element formation region 16 of the semiconductor layer 13 through the contact hole 82, and then the previous contact hole 51. Then, it flows into the substrate layer 11 through the conductive deposited layer 60 formed by dry etching to form the first and second layers 52. Thereby, charge accumulation in the semiconductor layer 13 is avoided, and it is possible to prevent the dielectric breakdown of the intermediate insulator layer 30 and the breakdown of the semiconductor layer 13 and the buried oxide film layer 12 due to this. In the previous step, the contact hole 52 reaching the element formation region 16 of the semiconductor layer 13 and the contact hole 51 reaching the substrate layer 11 are arranged close to each other, so that the deposited layer extending from the element formation region 16 to the substrate layer 11 is disposed. The electrical resistance of the conductive path by 60 can be reduced, and the effect of extracting the charge e injected into the element formation region 16 into the substrate layer 11 can be promoted. That is, the distance between the contact hole 52 and the contact hole 51 in the main surface direction of the SOI substrate 10 is preferably smaller than the distance between the contact holes 81 and 82 and the contact hole 51 in the main surface direction of the SOI substrate 10.

(Removal of resist mask and deposited layer)
Next, as shown in FIGS. 5E and 5F, the second-layer resist mask 70, the first deposited layer 60, and the first-layer resist mask 40 are removed. Specifically, after removing the resist masks 40 and 70 and the deposited layer 60 by plasma ashing using O ₂ plasma, the resist residue is removed using a resist stripping solution. Through the above steps, contact holes 52, 81 and 82 corresponding to the source region 23, gate electrode 22 and drain region 24 of the semiconductor element 20 are completed.

(Wiring formation)
Next, as shown in FIGS. 6A and 6B, a wiring material such as Al is embedded in the contact holes 51, 52, 81, and 82 by using a sputtering method or the like, and on the intermediate insulator layer 30. A wiring material is formed. Next, the wiring material formed on the intermediate insulator layer 30 is patterned using a photolithography technique and a dry etching technique. Thereby, the source wiring 91 connected to the source region 23 of the semiconductor element 20, the gate wiring 92 connected to the gate electrode 22, the drain wiring 93 connected to the drain region 24, and the substrate wiring 94 connected to the substrate layer 11. Are separated from each other. The patterning of the wiring material can be appropriately changed according to the circuit configuration or the like, but it is desirable that the substrate wiring 94 be separated from the other wirings 91, 92 and 93. The substrate wiring 94 is preferably connected to a ground potential (ground potential). By fixing the potential of the substrate layer 11 to the ground potential, it becomes possible to ensure the stability of the circuit operation and the like as compared with the case of floating. Thereafter, heat treatment is performed in a mixed gas atmosphere of H ₂ and N ₂ as necessary to perform source wiring 91, gate wiring 92, drain wiring 93, silicon (source region 23 and drain region 24), and polysilicon (gate electrode). 22) is secured.

  As is clear from the above description, in the method for manufacturing a semiconductor device according to the embodiment of the present invention, the intermediate insulator layer 30, the element isolation layer 14, and the element are separated by dry etching through the first resist mask 40. A first contact hole 51 that reaches the substrate layer 11 through the buried oxide film layer 12 and a second contact hole 52 that reaches the element formation region 16 of the semiconductor layer 13 through the intermediate insulator layer 30 are formed. To do. At this time, the deposited layer 60 made of a reaction product having conductivity generated by dry etching covers the entire inner wall surfaces of the contact holes 51 and 52 and the entire surface of the resist mask 40. Thereby, a conductive path from the element formation region 16 of the semiconductor layer 13 to the substrate layer 11 is formed.

  Thereafter, the second resist mask 70 is formed while leaving the first resist mask 40 and the deposited layer 60, and the intermediate insulator layer 30 is formed by dry etching through the second resist mask. The third contact holes 81 and 82 are formed so as to penetrate the semiconductor device 13 and reach the element formation region 16 of the semiconductor layer 13. The charge injected into the element formation region 16 of the semiconductor layer 13 by the plasma irradiation during the dry etching flows through the conductive deposition layer 60 to the substrate layer 11. Therefore, charge accumulation in the semiconductor layer 13 is avoided.

  That is, according to the method for manufacturing a semiconductor device according to the embodiment of the present invention, since charge accumulation in the semiconductor layer 13 during dry etching is avoided, the intermediate insulator is made thinner as the dry etching progresses. It becomes possible to prevent the dielectric breakdown of the layer 30 and also prevent the semiconductor layer 13 and the buried oxide film layer 12 from being broken.

<Second Embodiment>
In the semiconductor device manufacturing method according to the first embodiment of the present invention described above, the same photosensitive resin is used for the first-layer resist mask 40 and the second-layer resist mask 70. In this case, the mask material (second-layer resist mask 70) and the film to be etched (first-layer resist mask 40) are the same in the dry etching process for forming the contact holes 81 and 82 in the second time. Since it becomes a material, when the resist mask 40 is removed by etching, the resist mask 70 is also removed to some extent, and when the resist mask 40 is etched, the openings 71 and 72 are gradually etched. Since the diameter of the contact holes 81 and 82 may increase, it becomes difficult to set dry etching conditions. Therefore, in the method of manufacturing a semiconductor device according to the second embodiment of the present invention, the first-layer mask material is different from the second-layer mask material, so that the contact holes are formed in the second time. This makes it easy to set the dry etching conditions.

  A method for manufacturing a semiconductor device according to the second embodiment of the present invention will be described below with reference to the drawings. Note that the steps up to the step of forming the intermediate insulator layer 30 on the SOI substrate 10 are the same as those in the manufacturing method according to the first embodiment described above, and thus the description thereof is omitted.

  8 and 10 are a cross-sectional view and a plan view showing a method for manufacturing a semiconductor device according to the second embodiment of the present invention. 8 (a), FIG. 8 (c), FIG. 8 (e), FIG. 9 (a), FIG. 9 (c), and FIG. 9 (e) are views of the manufacturing method according to the second embodiment of the present invention. FIG. 8B is a plan view for each process step. FIG. 8B, FIG. 8D, FIG. 8F, FIG. 9B, FIG. 9D, and FIG. (A), FIG. 8 (c), FIG. 8 (e), FIG. 9 (a), FIG. 9 (c), FIG. 9 (e), 8b-8b line, 8d-8d line, 8f-8f, 9b- It is sectional drawing along a 9b line, 9d-9d line, and 9f-9f line. That is, in each drawing, a plan view and a sectional view corresponding to each process step are shown.

(Hard mask formation)
An SOI substrate is prepared, an element isolation layer is formed, a semiconductor element is formed, and an intermediate insulator layer is formed by a method similar to the manufacturing method according to the first embodiment described above.
Next, as shown in FIGS. 8A and 8B, a hard mask 40 a for forming contact holes is formed on the intermediate insulator layer 30. The hard mask 40a is made of a material different from a photosensitive resin used as a general photoresist material, for example, a silicon nitride film (Si ₃ N ₄ ), and is formed by, for example, a CVD method. Thereafter, openings 41 and 42 are formed in the silicon nitride film by a known photolithography technique and dry etching technique. As a result, a hard mask 40 a is formed on the intermediate insulator layer 30. The hard mask 40 a is patterned so as to have at least one opening 41 provided on the element isolation region 15 and at least one opening 42 provided on the element formation region 15.

(Contact hole formation: 1st time)
Next, as shown in FIGS. 8C and 8D, a plasma dry etching process is performed through the hard mask 40a, so that the surface of the intermediate insulator layer 30 is routed through the element isolation layer. At least one contact hole (first contact hole) 51 reaching the substrate layer 11 is formed, and at least one contact hole (second contact hole) 52 reaching the element formation region 16 from the surface of the intermediate insulator layer 30. Form. In this dry etching, the etching rate for SiO ₂ constituting the intermediate insulator layer 30, the element isolation layer 14 and the buried oxide film layer 12 is higher than the etching rate for Si constituting the element forming region 16 of the semiconductor layer 13. Use gas. That is, an etching gas having a relatively high selectivity between Si and SiO ₂ is used. Examples of such an etching gas include a mixed gas of CF ₄ and H ₂ , CHF ₃ , C ₂ F ₆ , and the like. When the contact hole 52 reaches the element formation region 16 composed of Si having a low etching rate by the dry etching process using the etching gas having such etching selectivity, the progress of the etching is almost stopped. On the other hand, the intermediate insulator layer 30, the element isolation layer 14, and the buried oxide film layer 12 are each made of SiO ₂ having a high etching rate, so that the contact hole 51 reaches the substrate layer 11. That is, the contact hole 51 reaching the substrate layer 11 through the intermediate insulator layer 30, the element isolation layer 14 and the buried oxide film layer 12, and the element formation region 16 of the semiconductor layer 13 through the intermediate insulator layer 30. A contact hole 52 that reaches is simultaneously formed. Further, the bottom and side surfaces of the contact holes 51 and 52 and the surface and side surfaces of the hard mask 40a are covered with a deposited layer 60 made of a reaction product during dry etching. Since the deposited layer 60 has conductivity, the element formation region 16 of the semiconductor layer 13 and the substrate layer 11 are electrically connected via the deposited layer 60.

  In a general semiconductor device manufacturing process, the resist mask and the deposited layer (deposition film) are removed by ashing and chemical treatment after the contact holes are formed. However, in the manufacturing method according to the embodiment of the present invention, the hard mask 40a and the deposited layer 60 are not removed even after the contact holes 51 and 52 are formed, and the process proceeds to the next step while leaving them.

  In the manufacturing method according to the embodiment of the present invention, the contact hole 52 is for forming a source contact of the semiconductor element 20, for example. However, the contact hole formed in this step may be formed for a purpose other than the source contact, for example, for forming a drain contact or a gate contact, It may be for forming a so-called dummy contact that does not contact.

(Formation of resist mask)
Next, as shown in FIGS. 8E and 8F, a resist mask 70 is formed on the previously formed hard mask 40a. Specifically, a photosensitive resin generally used as a photoresist material is formed on the hard mask 40a by spin coating or the like. Thereafter, a heat treatment is applied to the resist material formed by coating (pre-baking). Next, openings 71 and 72 are formed in the resist material by exposure and development processing. As a result, a resist mask 70 is formed on the hard mask 40a. The resist mask 70 has openings 71 and 72 provided on the element formation region 16. Openings 71 and 72 are arranged at a position different from the formation position of contact hole 52 formed previously.

(Contact hole formation: 2nd)
Next, as shown in FIGS. 9A and 9B, plasma dry etching is performed through the resist mask 70 to penetrate the deposited layer 60, the hard mask 40a, and the intermediate insulator layer 30. Contact holes (third contact holes) 81 and 82 reaching the element formation region 16 of the semiconductor layer 13 are formed. In the present dry etching process, the resist mask 70 used as a mask material and the hard mask 40a that is a film to be etched are made of different materials, and therefore according to the first embodiment of the present invention described above. Compared with the manufacturing method, the etching conditions can be easily set. In this step, the etching gas may be switched between the step of etching the hard mask 40a made of Si ₃ N ₄ or the like and the step of etching the intermediate insulator layer 30 made of SiO ₂ or the like.

  The contact hole 81 is for forming a gate contact of the semiconductor element 20, for example, and the contact hole 82 is for forming a drain contact of the semiconductor element 20, for example. However, the contact holes formed in this step may be formed for purposes other than the drain contact and the gate contact, and the number of contact holes formed in this step is changed as appropriate. It is possible. That is, a plurality of contacts may be formed with respect to the gate, source, drain, or the like. Further, the contact hole 52 formed in advance is used for forming a source contact or a drain contact which is necessary for the function, so that a contact hole for a source contact or a drain contact is separately formed in this step. This eliminates the need for the element area.

  As in the case of the first embodiment, the charge due to the plasma irradiated during the dry etching in this step is injected into the element formation region 16 of the semiconductor layer 13 and then forms the previous contact holes 51 and 52. Therefore, it flows into the substrate layer 11 through the conductive deposition layer 60 formed by dry etching. Thereby, charge accumulation in the semiconductor layer 13 is avoided, and it is possible to prevent the dielectric breakdown of the intermediate insulator layer 30 and the breakdown of the semiconductor layer 13 and the buried oxide film layer 12 accompanying this. The contact hole 52 that reaches the element formation region 16 of the semiconductor layer 13 and the contact hole 51 that reaches the substrate layer 11 are arranged close to each other, whereby the deposited layer 60 extending from the element formation region 16 of the semiconductor layer 13 to the substrate layer 11. It is possible to reduce the electrical resistance on the conductive path due to the above, and to promote the effect of extracting the charge injected into the element formation region 16 of the semiconductor layer 13 into the substrate layer 11.

(Removal of resist mask, hard mask and deposited layer)
Next, as shown in FIGS. 9C and 9D, the resist mask 70 and the deposited layer 60 are removed. Specifically, the resist mask 70 and the deposited layer 60 are removed by plasma ashing using O ₂ plasma. The hard mask 40a is preferably left from the viewpoint of reducing the number of steps. However, the hard mask 40a may be removed. When the hard mask 40a is made of, for example, a silicon nitride film, it can be removed by wet processing using, for example, phosphoric acid (H ₃ PO ₄ ). Through the above steps, contact holes 52, 81 and 82 corresponding to the source region 23, gate electrode 22 and drain region 24 of the semiconductor element 20 are completed.

(Wiring formation)
Next, as shown in FIGS. 9E and 9F, a wiring material such as Al is embedded in the contact holes 51, 52, 81, and 82 by using a sputtering method or the like, and on the intermediate insulator layer 30. A wiring material is formed. Next, the wiring material formed on the intermediate insulator layer 30 is patterned using a photolithography technique and a dry etching technique. Thereby, the source wiring 91 connected to the source region 23 of the semiconductor element 20, the gate wiring 92 connected to the gate electrode 22, the drain wiring 93 connected to the drain region 24, and the substrate wiring 94 connected to the substrate layer 11. Are separated from each other. The patterning of the wiring material can be appropriately changed according to the circuit configuration or the like, but it is desirable that the substrate wiring 94 be separated from the other wirings 91, 92 and 93. The substrate wiring 94 is preferably connected to a ground potential (ground potential). Thus, by fixing the potential of the substrate layer 11 to the ground potential, it becomes possible to ensure the stability of the circuit operation as compared with the floating state. Thereafter, heat treatment is performed in a mixed gas atmosphere of H ₂ and N ₂ as necessary to perform source wiring 91, gate wiring 92, drain wiring 93, silicon (source region 23 and drain region 24), and polysilicon (gate electrode). 22) is secured.

  Thus, according to the manufacturing method of the semiconductor device according to the second embodiment of the present invention, as in the manufacturing method according to the first embodiment of the present invention described above, the semiconductor layer 13 is subjected to dry etching. Since charge accumulation is avoided, it is possible to prevent the dielectric breakdown of the intermediate insulator layer 30 and to prevent the semiconductor layer 13 and the buried oxide film layer 12 from being broken. Further, since the mask material used in the dry etching for forming the contact hole in the first time and the mask material used in the dry etching for forming the contact hole in the second time are different, In the dry etching for forming the contact hole at the second time, the mask material and the material to be etched are different, and it becomes possible to easily set the conditions for the dry etching.

DESCRIPTION OF SYMBOLS 10 SOI substrate 11 Substrate layer 12 Embedded oxide film layer 13 Semiconductor layer 14 Element isolation layer 15 Element isolation region 16 Element formation region 20 Semiconductor device 30 Intermediate insulator layer 40 Resist mask 40a Hard mask 51, 52 Contact hole 60 Deposition layer 70 Resist Mask 81, 82 Contact hole

Claims (4)

A semiconductor layer having an element formation region including a semiconductor element, and an element isolation region that is in contact with the element formation region in plan view and includes a first opening and made of a first insulating member;
A second opening formed in contact with the first surface of the main surface of the semiconductor layer and communicating with the first opening; and a third opening provided at a position different from the second opening. A second insulating member;
A second surface contacting the back surface of the semiconductor layer facing the main surface of the semiconductor layer; and a third surface facing the second surface; and a fourth opening communicating with the first opening. A third insulating member;
The first opening and the second opening are connected to a first conductive member having a thickness smaller than a distance between the main surface and the third surface of the semiconductor layer and have continuous side walls. A second conductive member formed inside the portion and the fourth opening,
A semiconductor device comprising:   The semiconductor device according to claim 1, wherein the first conductive member is formed in contact with the third surface.   The semiconductor device according to claim 1, further comprising a third conductive member connected to the semiconductor element in the third opening. 4. The semiconductor device according to claim 1, wherein the semiconductor layer, the third insulating member, and the first conductive member are SOI substrates. 5.

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