CN108878528B - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN108878528B CN108878528B CN201710343140.2A CN201710343140A CN108878528B CN 108878528 B CN108878528 B CN 108878528B CN 201710343140 A CN201710343140 A CN 201710343140A CN 108878528 B CN108878528 B CN 108878528B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
Abstract
A semiconductor structure and a method of forming the same, the method comprising: the substrate is provided with a first grid structure and a second grid structure, a spacer area is arranged between the first grid structure and the second grid structure, dielectric layers are arranged on the substrate, on the side wall and the top of the first grid structure and on the side wall and the top of the second grid structure, and a stop layer is arranged on the dielectric layers; removing the stop layer and part of the dielectric layer on the spacer region, forming a first opening in the stop layer and the dielectric layer, and exposing the spacer region dielectric layer at the bottom of the first opening; removing the stop layer on the second grid structure until the top of the dielectric layer on the second grid structure is exposed, and forming a second opening in the stop layer on the second grid structure, wherein the second opening is communicated with the first opening; and etching the dielectric layers at the bottoms of the first opening and the second opening by taking the stop layer as a mask until the spacer area substrate and the surface of the second grid structure are exposed, and forming a third opening in the dielectric layer. The formed device has better performance.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
With the continuous development of semiconductor process technology, such as the introduction of high-K gate dielectric layers, stress engineering techniques, pocket region ion implantation, and the continuous optimization of materials and device structures, the size of semiconductor devices is continuously reduced. As the feature size of the devices is further reduced, however, planar transistors face significant challenges due to increasingly significant short channel effects, manufacturing variations, and reduced reliability. Fin field effect transistors have a fully depleted fin, lower dopant ion concentration fluctuation, higher carrier mobility, lower parasitic capacitance, and higher area usage efficiency than planar transistors, and thus have received much attention.
In the integrated circuit manufacturing process, for example, after a semiconductor device structure is formed on a substrate, a plurality of metallization layers are used to connect the semiconductor devices together to form a circuit, and each metallization layer includes an interconnection line and a metal plug formed in a contact hole, the metal plug in the contact hole connects the semiconductor devices, and the interconnection line connects the metal plugs on different semiconductor devices to form a circuit. The contact holes formed on the transistor include a contact hole on the surface of the gate electrode, and a contact hole to which the source region is connected.
However, in the process of forming the contact hole connected with the source region, other devices are damaged, and the performance of the formed semiconductor device is poor.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which are used for improving the performance of a semiconductor device.
To solve the above technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate is provided with a first gate structure and a second gate structure, the substrate between the first gate structure and the second gate structure is provided with a spacing area, the substrate, the side wall and the top of the first gate structure and the side wall and the top surface of the second gate structure are provided with dielectric layers, and the dielectric layers are provided with stop layers; removing the stop layer and part of the dielectric layer on the spacer region, forming a first opening in the stop layer and the dielectric layer, and exposing the dielectric layer on the spacer region at the bottom of the first opening; after the first opening is formed, removing the stop layer on the second grid structure until the surface of the dielectric layer on the second grid structure is exposed, and forming a second opening in the stop layer on the second grid structure, wherein the second opening is communicated with the first opening; and etching the dielectric layers at the bottoms of the first opening and the second opening by taking the stop layer as a mask until the substrate of the spacer region and the top surface of the second gate structure are exposed, and forming a third opening in the dielectric layer.
Optionally, the material of the stop layer includes: silicon nitride or boron nitride.
Optionally, the thickness of the stop layer is: 100 to 800 angstroms.
Optionally, the step of forming the first opening includes: forming a mask layer on part of the stop layer of the interval area, wherein the mask layer spans from the first grid structure to the second grid structure; after the mask layer is formed, forming a first graphic layer on the stop layer, wherein the first graphic layer exposes the mask layer and the top surface of the stop layer; and etching the stop layer and part of the dielectric layer on the spacer region by taking the mask layer and the first pattern layer as masks to form the first opening.
Optionally, with the mask layer and the first pattern layer as masks, the process for etching the stop layer includes: an anisotropic dry etching process; the process for etching the partial dielectric layer by taking the mask layer and the first pattern layer as masks comprises the following steps: and (3) an anisotropic dry etching process.
Optionally, the step of forming the first opening includes: forming a mask layer on the stop layer, wherein the mask layer exposes the top surface of the stop layer of part or all of the spacers; and etching the stop layer and part of the dielectric layer of the spacer region by taking the mask layer as a mask, and forming the first opening in the stop layer and the dielectric layer.
Optionally, the material of the mask layer includes silicon nitride.
Optionally, the aspect ratio of the first opening is: 2/1-15/1.
Optionally, the step of forming the second opening includes: forming a sacrificial layer in the first opening and on the stop layer, wherein the top surface of the sacrificial layer is provided with a second graphic layer which exposes the top surface of the sacrificial layer on the second gate structure; and etching the sacrificial layer and the stop layer on the second gate structure by taking the second graphic layer as a mask to form the second opening.
Optionally, the material of the sacrificial layer includes: and an organic medium layer.
Optionally, after forming the second opening and before forming the third opening, the method further includes: removing the sacrificial layer; removing sacrificial objectsThe technology of the animal layer comprises the following steps: ashing process; the parameters of the ashing process include: using oxygen-containing plasma or N2Plasma of gas combined with hydrogen.
Optionally, the forming process of the third opening includes: an anisotropic dry process; the parameters of the anisotropic dry etching process comprise: the main etching gas comprises C-F-based plasma, the flow rate of the main etching gas is 50-2000 standard milliliters/minute, the pressure is 50-1 Torr, and the power is 100-2000 Watts.
Optionally, the substrate, the sidewalls of the first gate structure and the second gate structure have a first protection layer; the tops of the first gate structure and the second gate structure are respectively provided with a second protective layer; the material of the first protective layer comprises: silicon nitride; the material of the second protective layer comprises: silicon nitride.
Optionally, the dielectric layer includes a first dielectric layer and a second dielectric layer; the first dielectric layer is positioned on the first protective layer, and the top surface of the first dielectric layer is exposed out of the top surface of the second protective layer; the second dielectric layer is positioned on the first dielectric layer and the second protective layer.
Optionally, the bottom of the third opening in the spacer exposes the top surface of the first protection layer; the bottom of the third opening on the second gate structure exposes the top surface of the second passivation layer.
Optionally, after forming the third opening, the method further includes: removing the first protective layer at the bottom of the third opening to expose the top surface of the spacer substrate; removing the second protective layer at the bottom of the third opening to expose the top surface of the second gate structure; after removing the first protective layer and the second protective layer at the bottom of the third opening, forming a metal silicide layer in the third opening; and forming a conductive plug on the metal silicide layer in the third opening.
Correspondingly, the invention also provides a semiconductor structure formed by adopting the method.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
in the method for forming a semiconductor structure provided by the technical scheme of the invention, the second opening is formed after the first opening is formed. Because the substrate at the bottom of the first opening is covered with a part of the dielectric layer, the damage to the substrate at the bottom of the first opening is reduced in the process of forming the second opening. And subsequently, removing the dielectric layers at the bottoms of the first opening and the second opening to form a third opening. In the process of forming the third opening, because the dielectric layers at the bottoms of the first opening and the second opening are removed simultaneously, the substrate at the bottom of the first opening or the top of the second gate structure can be prevented from being exposed prematurely, and the substrate surface at the bottom of the first opening and the top of the second gate structure are less damaged after the third opening is formed. The damage on the substrate surface of the spacer region is small, so that the electric leakage between the bottom of the second grid structure and the substrate of the spacer region is reduced, and the performance of the formed semiconductor device is optimized.
Further, in the process of forming the second opening, a sacrificial layer is formed within the first opening. After the second opening is formed and before the third opening is formed, removing the sacrificial layer in the first opening. The process of removing the sacrificial layer includes an ashing process. Since the aspect ratio of the first opening is small, the ashing gas easily reaches the bottom of the first opening, so that the sacrificial layer in the first opening is removed more thoroughly, that is: after the sacrificial layer is removed, fewer by-products remain in the first opening. And the first opening is used for forming a third opening subsequently, so that by-products in the third opening are less, and the performance of the semiconductor device is improved.
Drawings
FIGS. 1-3 are schematic structural diagrams illustrating steps of a method for forming a semiconductor structure;
fig. 4 to 21 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Detailed Description
As described in the background, the performance of the semiconductor device is poor.
Fig. 1 to 3 are schematic structural diagrams of steps of a method for forming a semiconductor structure.
Referring to fig. 1, a substrate 100 is provided, the substrate 100 has a first gate structure 101 and a second gate structure 102, the substrate 100 between the first gate structure 101 and the second gate structure 102 has a spacer a, a first protection layer 103 is disposed on the substrate 100 and on sidewalls of the first gate structure 101 and the second gate structure 102, a first dielectric layer 104 is disposed on the first protection layer 103, and top portions of the first dielectric layer 104 expose top surfaces of the first gate structure 101 and the second gate structure 102; removing part of the first gate structure 101 to form a first protection opening; removing part of the second gate structure 102 to form a second protection opening; forming a second protection layer (not shown) in the first protection opening and the second protection opening; a second dielectric layer 105 is formed on the first dielectric layer 104 and the second protective layer.
With reference to fig. 1, the first dielectric layer 104 and the second dielectric layer 105 of the spacer a are removed, a first opening 106 is formed in the first dielectric layer 104 and the second dielectric layer 105, and a bottom of the first opening 106 is exposed on a top surface of the first protection layer 103 on the spacer a.
Referring to fig. 2, a sacrificial layer 107 is formed in the first opening 106 (see fig. 1) and on the second dielectric layer 105, a top surface of the sacrificial layer 107 has a patterned photoresist (not shown), and the patterned photoresist exposes a top surface of the sacrificial layer 107 on the second gate structure 102.
Referring to fig. 3, the sacrificial layer 107 and the second dielectric layer 105 on the second gate structure 102 are etched by using the patterned photoresist as a mask until the top surface of the second protective layer on the second gate structure 102 is exposed, a second opening 108 is formed in the second dielectric layer 105 on the second gate structure 102, and the second opening 108 is communicated with the first opening 106.
However, the performance of the semiconductor device manufactured by the above method is poor because:
in the above method, after the first opening 106 is formed, the second opening 108 is formed. The step of forming the second opening 108 includes: and etching the sacrificial layer 107 and the second dielectric layer 105 on the second gate structure 102 by using the patterned photoresist as a mask until the top surface of the second protective layer on the second gate structure 102 is exposed, forming a second opening 108 in the second dielectric layer 105 on the second gate structure 102, wherein the second opening 108 is communicated with the first opening 106. The process of etching the sacrificial layer 107 on the second gate structure 102 includes: and (3) an anisotropic dry etching process. The process for etching the second dielectric layer 105 on the second gate structure 102 includes: and (3) an anisotropic dry etching process.
However, the thickness of the sacrificial layer 107 and the second dielectric layer 105 on the second gate structure 102 is relatively thick, so that the etching time required for forming the second opening 108 is relatively long. The sacrificial layer 107 covering the first opening 106 and the second dielectric layer 105 is relatively soft, so that during the process of forming the second opening 108, a portion of the sacrificial layer 107 located in the spacer a is also removed, and even a portion of the first protection layer 103 located in the spacer a and close to the second gate structure 102 is etched through, so as to cause a first damage to the substrate 100 located in the spacer a and close to the second gate structure 102.
After the second opening 108 is formed, the sacrificial layer 107 located in the first opening 106 and on the second dielectric layer 105 is removed. The process of removing the sacrificial layer 107 located in the first opening 106 and on the second dielectric layer 105 includes: and (5) ashing. Since the aspect ratio of the first opening 106 is large, it is difficult for the ashing gas to reach the bottom of the first opening 106, so that the sacrificial layer 107 located in the first opening 106 is difficult to be removed cleanly. The sacrificial layer 107 remaining in the first opening 106 will affect the electrical performance of the conductive plug formed subsequently, which is not favorable for improving the performance of the semiconductor structure.
Moreover, during the process of removing the sacrificial layer 107 by using the ashing process, the ashing gas damages the first protective layer 103 at the bottom of the first opening 106. The damage includes a second damage of the ashing gas to the substrate 100 of the spacer a close to the second gate structure 102, so that the substrate 100 of the spacer a close to the second gate structure 102 is damaged too severely, which results in a severe leakage of the device and is not beneficial to improving the performance of the semiconductor device.
To solve the above technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: forming the first opening in the stop layer and part of the dielectric layer on the spacer region; forming the second opening in a stop layer on the second gate structure after forming the first opening; and etching the dielectric layers at the bottoms of the first opening and the second opening, and forming the third opening in the dielectric layer. The method can protect the substrate surface of the spacer region, and is beneficial to improving the performance of the semiconductor device.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 4 to 21 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Referring to fig. 4, a substrate 200 is provided, and the substrate 200 has a first dummy gate structure 201 and a second dummy gate structure 202.
In this embodiment, the substrate 200 includes: a substrate 203 and a fin 204 on the substrate 203. In other embodiments, the base is a planar substrate.
The forming step of the substrate 200 includes: providing an initial substrate; the initial substrate is patterned to form a substrate 203 and a fin 204 on the substrate 203.
In this embodiment, the initial substrate is made of silicon. In other embodiments, the initial substrate may also be a semiconductor substrate such as a germanium substrate, a silicon-on-insulator or a germanium-on-insulator.
The substrate 200 further comprises isolation structures (not shown) for electrically isolating the different devices of the semiconductor.
The first dummy gate structure 201 crosses the fin portion 204 and covers a portion of the sidewall and the top surface of the fin portion 204. The first dummy gate structure 201 includes: a first dummy gate dielectric layer (not shown) on the surface of the substrate 200 and a first dummy gate layer (not shown) on the first dummy gate dielectric layer.
The material of the first dummy gate dielectric layer comprises: silicon oxide. The material of the first dummy gate layer comprises: silicon.
In this embodiment, the first dummy gate dielectric layer and the first dummy gate layer have first sidewalls (not shown in the figure) on sidewalls thereof. The first sidewall is used to protect the first dummy gate structure 201. The first side wall is made of materials including: silicon nitride.
The second dummy gate structure 202 crosses over the fin 204 and covers a portion of the sidewalls and the top surface of the fin 204. The second dummy gate structure 202 includes: a second dummy gate dielectric layer (not shown) on the surface of the substrate 200 and a second dummy gate layer (not shown) on the second dummy gate dielectric layer.
The material of the second dummy gate dielectric layer comprises: silicon oxide. The material of the second dummy gate layer comprises: silicon.
In this embodiment, the sidewalls of the second dummy gate dielectric layer and the second dummy gate layer have second sidewalls (not shown). The second sidewall is used to protect the second dummy gate structure 202. The second side wall is made of materials including: silicon nitride.
Subsequently, with the first dummy gate structure 201, the first sidewall, the second dummy gate structure 202, and the second sidewall as masks, source-drain doped regions (not shown in the figure) are respectively formed in the fin portions 204 at two sides of the first dummy gate structure 201 and the first sidewall, and at two sides of the second dummy gate structure 202 and the second sidewall.
Referring to fig. 5, a first protective layer 205 is formed on the substrate 200, the source-drain doped region, the first sidewall and the second sidewall; a first dielectric layer 206 is formed on the first protection layer 205, and the top surface of the first dielectric layer 206 exposes the top surfaces of the first dummy gate structure 201 and the second dummy gate structure 202.
The forming process of the first protection layer 205 includes: chemical vapor deposition process. The material of the first protective layer 205 includes: silicon nitride.
The first protection layer 205 is used to protect the substrate 200 and the top surface of the source/drain doped region.
The thickness of the first protection layer 205 is: 30 to 100 angstroms, the thickness of the first protective layer 205 being chosen in the sense that: if the thickness of the first protection layer 205 is less than 30 angstroms, the protection strength of the first protection layer 205 on the top surfaces of the substrate 200 and the source-drain doped region is not enough, so that the surfaces of the substrate 200 and the source-drain doped region are easily damaged, which is not beneficial to improving the performance of the semiconductor structure; if the thickness of the first protection layer 205 is greater than 100 angstroms, it is difficult to remove the first protection layer 205 on the substrate 200 between the first dummy gate structure 201 and the second dummy gate structure 202.
The substrate 200 between the first dummy gate structure 201 and the second dummy gate structure 202 has a spacer i.
The source-drain doped region is located in the substrate 200 of the spacer region i, and the first dummy gate structure 201 and the second dummy gate structure 202 share the same source-drain doped region in the substrate 200 of the spacer region i.
The material of the first dielectric layer 206 includes: silicon oxide. The forming process of the first dielectric layer 206 comprises the following steps: a fluid chemical vapor deposition process.
Referring to fig. 6, the first dummy gate structure 201 (as shown in fig. 5) is removed, and a first dummy gate opening 220 is formed in the first dielectric layer 206; the second dummy gate structure 202 is removed (as shown in fig. 5), and a second dummy gate opening 221 is formed in the first dielectric layer 206.
Removing the first dummy gate structure 201 includes: removing the first dummy gate layer; and removing the first dummy gate dielectric layer after removing the first dummy gate layer. The process for removing the first dummy gate layer comprises the following steps: and (3) an anisotropic dry etching process. The process for removing the first dummy gate dielectric layer comprises the following steps: and (3) an anisotropic dry etching process.
The first dummy gate opening 220 is used for subsequently forming a first gate structure 222.
Removing the second dummy gate structure 202 includes: removing the second dummy gate layer; and removing the second dummy gate dielectric layer after removing the second dummy gate layer. The process for removing the second dummy gate layer comprises the following steps: and (3) an anisotropic dry etching process. The process for removing the second pseudo gate dielectric layer comprises the following steps: and (3) an anisotropic dry etching process.
The second dummy gate opening 221 is used for forming a second gate structure later.
Referring to fig. 7, a first gate structure 222 is formed in the first dummy gate opening 220; a second gate structure 223 is formed within the second dummy gate opening 221.
The first gate structure 222 includes: a first gate dielectric layer (not shown), and a first gate layer (not shown) on the first gate dielectric layer. The material of the first gate dielectric layer comprises: and (3) hafnium oxide. The material of the first gate layer is metal, such as: tungsten.
The second gate structure 223 includes: a second gate dielectric layer (not shown), and a second gate layer (not shown) on the second gate dielectric layer. The material of the second gate dielectric layer comprises: and (3) hafnium oxide. The material of the second gate layer is metal, such as: tungsten.
Referring to fig. 8, a portion of the first gate layer is removed to form a first protection opening (not shown); removing a portion of the second gate layer to form a second protection opening (not shown); forming a second protection layer 207 in the first protection opening and the second protection opening; a second dielectric layer 208 is formed on the first dielectric layer 206 and on the second protective layer 207.
The process for removing part of the first gate layer comprises the following steps: an anisotropic dry etching process or a wet etching process. The process for removing part of the second gate layer comprises the following steps: an anisotropic dry etching process or a wet etching process.
The material of the second protective layer 207 includes: silicon oxide. The forming process of the second protective layer 207 includes: chemical vapor deposition process.
The second protection layer 207 is used to protect the top surfaces of the first gate structure 222 and the second gate structure 223 when a conductive plug is formed on the first gate structure 222 and the second gate structure 223.
The material of the second dielectric layer 208 includes: silicon oxide. The forming process of the second dielectric layer 208 comprises the following steps: chemical vapor deposition process.
The dielectric layer 220 includes: a first dielectric layer 206 and a second dielectric layer 208.
The dielectric layer 220 is used to electrically isolate different devices of the semiconductor.
A stop layer is subsequently formed on the second dielectric layer 208.
In this embodiment, the stop layer and a portion of the dielectric layer 220 on the spacer i are subsequently removed, a first opening is formed in the stop layer and the dielectric layer 220, and the dielectric layer 220 on the spacer i is exposed at the bottom of the first opening. Please refer to fig. 9 to 14.
Referring to fig. 9, a stop layer 209 is formed on the second dielectric layer 208; a layer of masking material 210 is formed on the stop layer 209.
The material of the stop layer 209 includes: silicon nitride or boron nitride, and the materials of the first dielectric layer 206 and the second dielectric layer 208 include: and oxidizing silicon so that when the stop layer 209 and part of the dielectric layer 220 of the spacer I are etched subsequently, the stop layer 209 and the dielectric layer 220 have different etching selection ratios.
The forming process of the stop layer 209 comprises the following steps: chemical vapor deposition process.
The thickness of the stop layer 209 is: 100 to 800 angstroms, the thickness of the stop layer 209 being chosen in the sense that: if the thickness of the stop layer 209 is less than 100 angstroms, when a part of the dielectric layer 220 and the stop layer 209 of the spacer i are etched later, the time for etching the stop layer 209 of the spacer i is too short, so that the removal amount of the dielectric layer 220 on the spacer i is difficult to control, and thus the first protection layer 205 of the spacer i may suffer damage, and even may damage the fin portion 204 below the first protection layer 205 in the spacer i; if the thickness of the stop layer 209 is greater than 800 angstroms, the difficulty of subsequently removing the stop layer 209 is increased.
The material of the masking material layer 210 includes: titanium nitride. The masking material layer 210 is used to subsequently form a masking layer. The mask material layer 208 has high etching resistance, so that the mask layer is not completely consumed when the mask layer is subsequently used as a mask to form the first opening.
Referring to fig. 10 and fig. 11, fig. 10 is a schematic structural view based on fig. 9, fig. 10 is a schematic cross-sectional view taken along line CC1 of fig. 11, in which a portion of the masking material layer 210 is removed, and a masking layer 211 is formed on a portion of the stop layer 209 above the spacer i, the masking layer 211 crosses from the first gate structure 222 to the second gate structure 223; after the mask layer 211 is formed, a first pattern layer 230 is formed on the second dielectric layer 208, and the top surfaces of the mask layer 211 and the stop layer 209 are exposed by the first pattern layer 230.
The forming step of the mask layer 211 includes: forming a third pattern layer on the mask material layer 210, wherein the third pattern layer exposes a part of the top surface of the mask material layer 210 of the spacer region i; and etching the mask material layer 210 of the spacer I by taking the third pattern layer as a mask until the top surface of the stop layer 209 is exposed to form a mask layer 211.
The material of the mask layer 211 includes: titanium nitride.
The mask layer 211 and the first pattern layer 230 are used as masks for forming a first opening later.
Referring to fig. 12, 13 and 14, fig. 13 and 14 are schematic structural diagrams based on fig. 10, fig. 13 is a schematic cross-sectional diagram of fig. 12 along line AA1, fig. 14 is a schematic cross-sectional diagram of fig. 12 along line BB1, the mask layer 211 and the first pattern layer 230 are used as masks, the stop layer 209 (see fig. 11) of the spacer i and a part of the dielectric layer 220 are etched, a first opening 212 is formed in the stop layer 209 and the dielectric layer 220, and the bottom of the first opening 212 exposes the dielectric layer 220 of the spacer i.
The process for etching the stop layer 209 on the spacer region i by using the mask layer 211 and the first pattern layer 230 as masks includes: and (3) an anisotropic dry etching process.
The process for etching the partial dielectric layer 220 by using the mask layer 211 and the first pattern layer 230 as masks comprises the following steps: and (3) an anisotropic dry etching process.
In this embodiment, the part of the dielectric layer 220 not etched under the mask layer 211 in the spacer i serves as an isolation structure between the subsequently formed conductive plugs.
In other embodiments, the portion of the dielectric layer 220 not etched under the mask layer 211 in the spacer i is removed.
The aspect ratio of the first opening 212 is: 2/1-15/1, the aspect ratio of the first opening 212 is selected to have the following meaning: in the process of forming the first opening 212, if the aspect ratio of the first opening 212 is smaller than 2/1, the removal amount of the spacer i dielectric layer 220 is too small, so that the difficulty in subsequently removing the residual dielectric layer 220 of the spacer i is large; if the aspect ratio of the first opening 212 is greater than 15/1, the amount of the dielectric layer 220 covered on the substrate 200 of the spacer i is small, so that the substrate 200 of the spacer i is easily damaged when a second opening is formed subsequently, which is not favorable for improving the performance of the semiconductor device.
A sacrificial layer is formed in the first opening 212 in the following step, and due to the small aspect ratio of the first opening 212, the sacrificial layer in the first opening 212 can be removed easily and completely in the following step, so that the sacrificial layer does not remain in the first opening 212, thereby effectively avoiding the influence of the remaining sacrificial layer on the following process, and further improving the performance of the semiconductor structure.
Moreover, since the dielectric layer 220 of the spacer i is exposed at the bottom of the first opening 212, when a second opening is formed in the stop layer 209 on the second gate structure 223, the dielectric layer 220 at the bottom of the first opening 212 and the first protection layer 205 below the dielectric layer 220 can protect the fin portion 204 of the spacer i, so that the fin portion 204 of the spacer i is protected from being damaged, which is beneficial to improving the performance of the semiconductor device.
In other embodiments, the forming of the first opening includes: removing part of the mask material layer, and forming a mask layer on the stop layer, wherein the mask layer exposes the top surface of the stop layer of part or all of the spacers; and etching the stop layer and part of the dielectric layer of the spacer region by taking the mask layer as a mask, and forming the first opening in the stop layer and the dielectric layer.
After the first opening 212 is formed, the stop layer 209 on the second gate structure 223 is removed until the surface of the second dielectric layer 208 on the second gate structure 223 is exposed, and a second opening is formed in the stop layer 209 on the second gate structure 223, wherein the second opening is communicated with the first opening 212. Please refer to fig. 15 to fig. 16.
Referring to fig. 15, the mask layer 211 is removed (as shown in fig. 14); after removing the mask layer 211, forming a sacrificial layer 213 in the first opening 212 and on the stop layer 209; a second pattern layer (not shown) is formed on the sacrificial layer 213, the second pattern layer having a mask opening 214, the mask opening 214 exposing a top surface of the sacrificial layer 213 on the second gate structure 223.
The process for removing the mask layer 211 includes: a dry etching process or a wet etching process.
The material of the sacrificial layer 213 includes: and an organic medium layer.
The mask opening 214 is used to define the size and topography of a second opening subsequently formed in the stop layer 209 over the second gate structure 223.
Referring to fig. 16, the sidewalls of the mask opening 214 are used as a mask to etch the second gate structure 223 and the sacrificial layer 213 and the stop layer 209 on the first protection layer 205 on the sidewalls of the second gate structure 223 until the top surface of the second dielectric layer 208 on the second gate structure 223 is exposed, a second opening 215 is formed in the stop layer 209 on the second gate structure 223, and the second opening 215 is communicated with the first opening 212 (see fig. 14).
The depth of the second opening 215 is determined by the thickness of the stop layer 209, and the second opening 215 penetrates the stop layer 209, i.e.: the depth of the second opening 215 corresponds to the thickness of the stop layer 209. The depth of the second opening 215 is: 100 to 500 angstroms.
In the process of forming the second opening 215, the substrate 200 of the spacer i is covered with a part of the dielectric layer 220 and the first protective layer 203, so that the substrate 200 of the spacer i is prevented from being damaged, and the performance of a semiconductor device is improved.
Referring to fig. 17, after the second opening 215, the sacrificial layer 213 is removed (as shown in fig. 16), exposing the sidewalls and the top surface of the first opening 212.
The process of removing the sacrificial layer 213 includes: an ashing process, the parameters of the ashing process comprising: using oxygen-containing plasma or N2And H2A plasma of the combined gases.
In the process of removing the sacrificial layer 213, a part of the dielectric layer 220 and the first protective layer 205 are covered on the fin portion 204 at the bottom of the first opening 212, so that the part of the dielectric layer 220 and the first protective layer 205 at the bottom of the first opening 212 can protect the fin portion 204 at the bottom of the first opening 212, and the fin portion 204 at the bottom of the first opening 212 is not damaged, which is beneficial to improving the performance of the semiconductor device.
In addition, since the aspect ratio of the first opening 212 is small, the ashing process is used to remove the sacrificial layer 213 at the bottom of the first opening 212 more easily and completely, so that no sacrificial layer 213 remains in the first opening 212, thereby effectively preventing the residual sacrificial layer 213 from affecting the electrical properties of the subsequently formed conductive plug, and further improving the performance of the semiconductor structure.
Referring to fig. 18, after removing the sacrificial layer 213, the stop layer 209 is used as a mask to etch the dielectric layer 220 at the bottom of the first opening 212 and the second dielectric layer 208 at the bottom of the second opening 215 until the first protection layer 205 of the spacer i and the second protection layer 207 on the top surface of the second gate structure 223 are exposed, and a third opening 216 is formed in the dielectric layer 220.
The process of etching dielectric layer 220 at the bottom of first opening 212 and second dielectric layer 208 at the bottom of second opening 215 includes: the anisotropic dry etching process comprises the following parameters: the main etching gas comprises C-F-based plasma, the flow rate of the main etching gas is 50-2000 standard milliliters/minute, the pressure is 50-1 Torr, and the power is 100-2000 Watts.
In the process of forming the third opening 216, since the dielectric layer 220 at the bottom of the first opening 212 and the second dielectric layer 208 at the bottom of the second opening 215 are removed at the same time, the substrate 200 at the bottom of the first opening 212 or the top of the second gate structure 223 can be prevented from being exposed prematurely, and the surface of the substrate 200 at the bottom of the first opening 212 and the top of the second gate structure 223 are damaged less after the third opening 216 is formed. The damage on the surface of the substrate 200 of the spacer i is small, which is beneficial to reducing the electric leakage between the bottom of the second gate structure 223 and the substrate 200 of the spacer i and optimizing the performance of the formed semiconductor device.
Referring to fig. 19, after the third opening 216 is formed, the stop layer 209 and the first and second protection layers 205 and 207 at the bottom of the third opening 216 are removed to expose the top surfaces of the substrate 200 and the second gate structure 202 of the spacer i.
The process of removing the stop layer 209 and the first protection layer 205 and the second protection layer 207 at the bottom of the third opening 216 includes: a dry etching process or a wet etching process.
After the third opening 216 is formed, the stop layer 209 and the first protection layer 205 and the second protection layer 207 at the bottom of the third opening 216 are removed at the same time, so that the top of the substrate 200 or the top of the second gate structure 223 at the bottom of the first opening 212 can be protected from being exposed prematurely, and the damage to the top of the substrate 200 or the top of the second gate structure 223 at the bottom of the first opening 212 is small. The damage on the surface of the substrate 200 of the spacer i is small, which is beneficial to reducing the electric leakage between the bottom of the second gate structure 223 and the substrate 200 of the spacer i and optimizing the performance of the formed semiconductor device.
Referring to fig. 20, a metal silicide layer 217 is formed at the bottom of the third opening 216.
The metal silicide layer 217 is used to reduce the contact resistance between the conductive plug and the source/drain doped region formed on the metal silicide layer 217.
The forming step of the metal silicide layer 217 includes: forming a metal layer in the third opening 216 and on the second dielectric layer 208; annealing the metal layer to form a metal silicide layer 217 on the substrate 200 of the spacer I; after the metal silicide layer 217 is formed, the unreacted metal layer is removed.
The material of the metal layer comprises: titanium, aluminum, zinc and nickel.
The metal layer is annealed so that the metal layer reacts with the top surface of the substrate 200 of the spacer i to form a metal silicide layer 217.
The process for removing the unreacted metal layer comprises the following steps: and (5) wet etching process. The etching liquid adopted by the wet etching process comprises: a mixed aqueous solution of phosphoric acid, nitric acid and acetic acid.
The material of the metal silicide layer 217 includes: nickel silicide.
Referring to fig. 21, after the metal silicide layer 217 is formed, a conductive plug 218 is formed in the third opening 216 (see fig. 20).
The step of forming the conductive plug 218 includes: forming a material layer in the third opening 216 and on the dielectric layer 220; the material layer is planarized until the top surface of the second dielectric layer 208 is exposed, forming a conductive plug 218 within the third opening 216.
In this embodiment, the material of the material layer includes: a metal, the metal comprising: tungsten.
In summary, in the present embodiment, after the first opening is formed, a second opening is formed. Because the substrate at the bottom of the first opening is covered with a part of the dielectric layer, the damage to the substrate at the bottom of the first opening is reduced in the process of forming the second opening. And subsequently, removing the dielectric layers at the bottoms of the first opening and the second opening to form a third opening. In the process of forming the third opening, because the dielectric layers at the bottoms of the first opening and the second opening are removed simultaneously, the substrate at the bottom of the first opening or the top of the second gate structure can be prevented from being exposed prematurely, and the substrate surface at the bottom of the first opening and the top of the second gate structure are less damaged after the third opening is formed. The damage on the substrate surface of the spacer region is small, so that the electric leakage between the bottom of the second grid structure and the substrate of the spacer region is reduced, and the performance of the formed semiconductor device is optimized.
Correspondingly, the invention also provides a semiconductor structure formed by adopting the method.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (17)
1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate is provided with a first gate structure and a second gate structure, the substrate between the first gate structure and the second gate structure is provided with a spacing area, the substrate, the side wall and the top of the first gate structure and the side wall and the top of the second gate structure are provided with dielectric layers, and the dielectric layers are provided with stop layers;
removing the stop layer and part of the dielectric layer on the spacer region, forming a first opening in the stop layer and the dielectric layer, and exposing the dielectric layer on the spacer region at the bottom of the first opening;
after the first opening is formed, removing the stop layer on the second gate structure until the surface of the dielectric layer on the second gate structure is exposed, and forming a second opening in the stop layer on the second gate structure, wherein the second opening is communicated with the first opening;
and etching the dielectric layers at the bottoms of the first opening and the second opening by taking the stop layer as a mask until the substrate of the spacer region and the top surface of the second gate structure are exposed, and forming a third opening in the dielectric layer.
2. The method of forming a semiconductor structure of claim 1, wherein the material of the stop layer comprises: silicon nitride or boron nitride.
3. The method of forming a semiconductor structure of claim 1, wherein the stop layer has a thickness of: 100 to 800 angstroms.
4. The method of forming a semiconductor structure of claim 1, wherein the step of forming the first opening comprises: forming a mask layer on part of the stop layer of the interval area, wherein the mask layer spans from the first grid structure to the second grid structure; after the mask layer is formed, forming a first graphic layer on the stop layer, wherein the first graphic layer exposes the mask layer and the top surface of the stop layer; and etching the stop layer and part of the dielectric layer on the interval area by taking the mask layer and the first pattern layer as masks to form the first opening.
5. The method for forming a semiconductor structure according to claim 4, wherein the step of etching the stop layer by using the mask layer and the first pattern layer as masks comprises the steps of: an anisotropic dry etching process; the process for etching the partial dielectric layer by taking the mask layer and the first pattern layer as masks comprises the following steps: and (3) an anisotropic dry etching process.
6. The method of forming a semiconductor structure of claim 1, wherein the step of forming the first opening comprises: forming a mask layer on the stop layer, wherein the mask layer exposes the top surface of the stop layer of part or all of the spacers; and etching the stop layer and part of the dielectric layer of the spacer region by taking the mask layer as a mask, and forming the first opening in the stop layer and the dielectric layer.
7. The method of claim 4 or 6, wherein the material of the mask layer comprises titanium nitride.
8. The method of forming a semiconductor structure of claim 1, wherein an aspect ratio of the first opening is: 2/1-15/1.
9. The method of forming a semiconductor structure of claim 1, wherein the step of forming the second opening comprises: forming a sacrificial layer in the first opening and on the stop layer, wherein the top surface of the sacrificial layer is provided with a second graphic layer which exposes the top surface of the sacrificial layer on the second gate structure; and etching the sacrificial layer and the stop layer on the second gate structure by taking the second graphic layer as a mask to form the second opening.
10. The method of forming a semiconductor structure of claim 9, wherein the material of the sacrificial layer comprises: and an organic medium layer.
11. The method of forming a semiconductor structure of claim 9, wherein after forming the second opening and before forming the third opening, further comprising: removing the sacrificial layer; the process for removing the sacrificial layer comprises the following steps: ashing process; the parameters of the ashing process include: oxygen-containing plasma or plasma of a gas of nitrogen in combination with hydrogen is used.
12. The method of claim 1, wherein the forming of the third opening comprises: an anisotropic dry process; the parameters of the anisotropic dry etching process comprise: the main etching gas comprises C-F-based plasma, the flow rate of the main etching gas is 50-2000 standard milliliters/minute, the pressure is 50-1 Torr, and the power is 100-2000 Watts.
13. The method of claim 1, wherein sidewalls of the first gate structure and the second gate structure on the substrate have a first protective layer; the tops of the first gate structure and the second gate structure are respectively provided with a second protective layer; the material of the first protective layer comprises: silicon nitride; the material of the second protective layer comprises: silicon nitride.
14. The method of forming a semiconductor structure of claim 13, wherein the dielectric layer comprises a first dielectric layer and a second dielectric layer; the first dielectric layer is positioned on the first protective layer, and the top surface of the first dielectric layer is exposed out of the top surface of the second protective layer; the second dielectric layer is positioned on the first dielectric layer and the second protective layer.
15. The method of forming a semiconductor structure of claim 13, wherein a bottom of the third opening in the spacer region exposes a top surface of the first protective layer; the bottom of the third opening on the second gate structure exposes the top surface of the second passivation layer.
16. The method of forming a semiconductor structure of claim 13, wherein after forming the third opening, further comprising: removing the first protective layer at the bottom of the third opening to expose the top surface of the spacer substrate; removing the second protective layer at the bottom of the third opening to expose the top surface of the second gate structure; after removing the first protective layer and the second protective layer at the bottom of the third opening, forming a metal silicide layer in the third opening; and forming a conductive plug on the metal silicide layer in the third opening.
17. A semiconductor structure formed by the method of any of claims 1 to 16.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104617093A (en) * | 2013-11-05 | 2015-05-13 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN104867823A (en) * | 2014-02-24 | 2015-08-26 | 联华电子股份有限公司 | Method For Manufacturing Semiconductor Device And Device Manufactured Using The Same |
| CN105655288A (en) * | 2014-12-02 | 2016-06-08 | 中芯国际集成电路制造(上海)有限公司 | Formation method of semiconductor structure |
| CN105789111A (en) * | 2014-12-18 | 2016-07-20 | 中芯国际集成电路制造(上海)有限公司 | Formation method for semiconductor structure |
| US9490341B2 (en) * | 2015-04-01 | 2016-11-08 | United Microelectronics Corp. | Semiconductor device having metal gate and method for manufacturing semiconductor device having metal gate |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104617093A (en) * | 2013-11-05 | 2015-05-13 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN104867823A (en) * | 2014-02-24 | 2015-08-26 | 联华电子股份有限公司 | Method For Manufacturing Semiconductor Device And Device Manufactured Using The Same |
| CN105655288A (en) * | 2014-12-02 | 2016-06-08 | 中芯国际集成电路制造(上海)有限公司 | Formation method of semiconductor structure |
| CN105789111A (en) * | 2014-12-18 | 2016-07-20 | 中芯国际集成电路制造(上海)有限公司 | Formation method for semiconductor structure |
| US9490341B2 (en) * | 2015-04-01 | 2016-11-08 | United Microelectronics Corp. | Semiconductor device having metal gate and method for manufacturing semiconductor device having metal gate |
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