CN106206405B - Semiconductor devices and forming method thereof - Google Patents
Semiconductor devices and forming method thereof Download PDFInfo
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- CN106206405B CN106206405B CN201510214828.1A CN201510214828A CN106206405B CN 106206405 B CN106206405 B CN 106206405B CN 201510214828 A CN201510214828 A CN 201510214828A CN 106206405 B CN106206405 B CN 106206405B
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Abstract
The present invention provides a kind of semiconductor devices and forming method thereof, the forming method of the semiconductor devices includes: in removal the first barrier material layer of part, it is formed to expose and is covered on grid, and the first barrier layer of partial electroconductive layer, and filled layer is formed on the semiconductor substrate after formation metal silicide layer on the grid and conductive layer that the first barrier layer is exposed.The filled layer is filled in during removal the first barrier material layer of part, because eliminating the notch that part side wall causes to be formed between side wall and grid.The insulating properties between conductive layer and grid to improve the semiconductor devices being subsequently formed, to avoid in subsequent use process, occur because of the phenomenon that notch between side wall and grid is to cause conductive layer and grid breakdown defect, to further decrease probability breakdown between grid and conductive layer, the performance for the semiconductor devices being subsequently formed is improved.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly, to a kind of semiconductor devices and forming method thereof.
Background technique
As integrated circuit technique develops, feature sizes of semiconductor devices (Critical Dimension, CD) is increasingly
Small, the integrated level of the semiconductor devices on integrated circuit is continuously increased.It on the integrated, on a semiconductor substrate include multilayer
Semiconductor devices, and the transistor of the semiconductor devices of same layer and different layers is electrically connected by interconnection structure.
It is each if Static RAM (Static Random Access Memory, SRAM) includes multiple transistors
The grid and source electrode and drain electrode of transistor are connected according to specific circuit structure by interconnection structures such as conductive plungers, to
Transmit signal.
Fig. 1 is traditional transistor arrangement schematic diagram, and existing transistor arrangement includes: in semiconductor substrate 10
Grid 20, in the semiconductor substrate 10, source electrode and drain electrode 21 positioned at 20 two sides of grid, wherein in the grid 20
And plug 22 and 23 is respectively formed in source electrode and drain electrode 21.The plug 22 and 23 is located on the same floor or not for connecting
With other transistors of interlayer, to realize that signal transmits.
However, in actual operation, the interconnection structures such as plug need to occupy biggish space between transistor, to increase
The size of semiconductor devices, thus it is unable to satisfy the ever-reduced trend requirement of semiconductor devices.
For this purpose, there is a kind of transistor of double-layered polycrystal silicon structure in the prior art.With reference to Fig. 2, the double level polysilicon knot
The transistor arrangement of structure includes: the polysilicon gate 30 being formed in semiconductor substrate 10, and is located at the polysilicon gate
30 two sides source electrode and drain electrodes 31；It is formed with another polysilicon layer 32 in the source electrode or 31 (or on grid 30) of drain electrode, it is described
Polysilicon layer 32 is covered in the source electrode and drain electrode 33 (or polysilicon gate) of transistor (not shown) simultaneously；Exist later
Link in forming metal silicide layer 34, the polysilicon layer 32 and metal silicide layer 34 on the polysilicon layer 32 as mutual
Structure is realized to be electrically connected between different crystal pipe.
In the transistor of above-mentioned double-layered polycrystal silicon structure, taken using polysilicon layer 32 and metal silicide layer 34 as conductive layer
For interconnection structures such as conductive plungers, it is electrically connected between same layer transistor with realizing, to reduce the structure of semiconductor devices.
But it is easy to appear between polysilicon layer 32 and polysilicon gate 30 in the transistor of existing double-layered polycrystal silicon structure
It is electrically shocked and wears defect, the stability of transistor is poor.
It is those skilled in the art's urgent need to resolve for this purpose, how to improve the performance of the transistor of double-layered polycrystal silicon structure
Problem.
Summary of the invention
Problems solved by the invention is to provide a kind of semiconductor devices and forming method thereof, so that double-layered polycrystal be effectively reduced
In the transistor of silicon structure, polysilicon layer and polysilicon gate are electrically shocked and wear probability, improve transistor performance.
To solve the above problems, the forming method of semiconductor devices provided by the invention includes:
Semiconductor substrate is provided；
The grid being located in semiconductor substrate, the side wall positioned at gate lateral wall are formed, and positioned at the grid two sides
Source electrode and drain electrode in semiconductor substrate；
Conductive layer is formed on the semiconductor substrate, and the conductive layer at least covers the source electrode or drain electrode, and reveals
The part side wall of part of grid pole and grid side out forms opening between the conductive layer, grid and side wall；
The first barrier material layer is formed on the semiconductor substrate, and first barrier material layer covers the conduction
Layer, grid and side wall；
Part first barrier material layer is removed, to form the first blocking for exposing the grid and partial electroconductive layer
Layer in removal part when first barrier material layer, removes the exposed part side wall of the opening, at side wall position
Notch is formed on gate lateral wall；
Metal silicide layer is formed in the grid and conductive layer surface of exposing；
After forming the metal silicide layer, filled layer, the filled layer filling are formed on the semiconductor substrate
The notch；
Dielectric layer is formed on the semiconductor substrate, to form interconnection structure.
Optionally, the filled layer is silicon oxide layer；
The step of forming the filled layer includes: to be sunk using ethyl orthosilicate as reactant using sub- atmospheric chemical vapor
Product technique forms the silicon oxide layer.
Optionally, the step of sub- aumospheric pressure cvd technique includes: to be passed through containing ethyl orthosilicate and oxygen
Gas as reaction gas, and the flow-rate ratio of ethyl orthosilicate and oxygen is 1:5~1:10, and the air pressure of reaction gas is 300
~800Torr, reaction temperature are 400~600 DEG C.
Optionally, part first barrier material layer is removed, to form expose the grid and partial electroconductive layer the
The step of one barrier layer includes:
Dry etch step is first carried out, the first barrier material layer of part, exposed portion conductive layer are removed；
Carry out wet etching step again later.
Optionally, the dry etch step includes: to contain CF4、C4F8And O2Gas as etching gas, control
Power is 200~800W, and the air pressure of dry etching agent is 30~100mTorr.
Optionally, the wet etching step includes: using diluted hydrofluoric acid solution as wet etchant.
Optionally, the material of the side wall is silica.
Optionally, formed conductive layer the step of include: to form polysilicon layer on the semiconductor substrate, it is backward described in
Doped ions in polysilicon layer, the polysilicon layer after Doped ions is as the conductive layer.
Optionally, the step of forming metal silicide layer includes: to be formed on the grid and conductive layer surface of exposing
Metal layer carries out annealing process later, forms the metal silicide layer in the grid and conductive layer surface of exposing.
Optionally, after forming the filled layer, before forming the dielectric layer, the forming method of the semiconductor devices is also
Include:
Guarantor's type covers the second barrier layer on the semiconductor substrate.
Optionally, the step of guarantor's type covers the second barrier layer on the semiconductor substrate includes: to serve as a contrast in the semiconductor
The silicon nitride layer of guarantor's type covering doping oxygen on bottom, forms silicon nitride layer on the silicon nitride layer of the doping oxygen later, with described
The silicon nitride layer of oxygen and the lamination of silicon nitride layer are adulterated as second barrier layer.
Optionally, on the semiconductor substrate formed filled layer the step of include make the filled layer with a thickness of
The present invention also provides a kind of semiconductor devices, comprising:
Semiconductor substrate；
Grid in the semiconductor substrate, the side wall positioned at gate lateral wall, and positioned at the grid two sides
Source electrode and drain electrode, wherein formed between the side wall and grid jagged；
At least cover the conductive layer of the source electrode or drain electrode, conductive layer exposed portion grid, grid side part
Side wall and the notch；
The grid and partial electroconductive layer are exposed in the first barrier layer on the conductive layer, first barrier layer,
And the notch；
Cover the metal silicide layer of grid and conductive layer that first barrier layer is exposed；
Filled layer on the metal silicide layer, the filled layer fill the notch；
It is covered on the dielectric layer of the semiconductor substrate, is used to form interconnection structure in the dielectric layer.
Optionally, the filled layer is using ethyl orthosilicate as reactant, using sub- aumospheric pressure cvd technique
It is formed by silicon oxide layer.
Optionally, the material of the side wall is silica.
Optionally, the conductive layer is the polysilicon layer of Doped ions.
Optionally, the semiconductor devices further include: guarantor's type is covered in the second barrier layer in the semiconductor substrate.
Optionally, second barrier layer includes the silicon nitride layer for adulterating oxygen, and positioned at the silicon nitride of the doping oxygen
Silicon nitride layer on layer.
Optionally, the filled layer with a thickness of
Compared with prior art, technical solution of the present invention has the advantage that
In the forming method of semiconductor devices of the present invention, in removal the first barrier material layer of part, exposed portion is formed
Conductive layer and grid, with to behind the first barrier layer that conductive layer and gate surface form metal silicide layer, described
Filled layer is formed in semiconductor substrate, during removal the first barrier material layer of part can be filled in the filled layer, because going
Notch except part side wall to be formed on the gate lateral wall at side wall position, and then improve between the conductive layer and grid
Insulating properties occur because the notch between side wall and grid is to cause conductive layer and grid to avoid in subsequent use process
The phenomenon that extremely breakdown defect, to further decrease probability breakdown between grid and conductive layer, raising is subsequently formed
Semiconductor devices performance.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of traditional transistor；
Fig. 2 is the structural schematic diagram of the transistor of existing double-layered polycrystal silicon structure；
Fig. 3 and Fig. 4 is the structural schematic diagram in the transistor forming process of double-layered polycrystal silicon structure in Fig. 2；
Fig. 5 is in the transistor preparation process of double-layered polycrystal silicon structure shown in Fig. 2, using dry etch process removal portion
The structural schematic diagram of semiconductor devices after dividing barrier layer；
Fig. 6~Figure 14 is the knot of the semiconductor devices in each step of one embodiment of forming method of semiconductor devices of the present invention
Structure schematic diagram；
Figure 15 is that the structure of the semiconductor devices formed using one embodiment of forming method of semiconductor devices of the present invention is shown
It is intended to.
Specific embodiment
As stated in the background art, in the transistor of double-layered polycrystal silicon structure, by be formed in transistor source or drain electrode (or
On grid) on polysilicon layer, be electrically connected between different crystal pipe with realizing.However, in use, passing through existing work
In the transistor for the double-layered polycrystal silicon structure that skill is formed, the polysilicon layer as conductive layer and between the polysilicon layer as grid
Usually occur being electrically shocked the phenomenon that wearing, to influence transistor performance.
Its reason is analyzed, in conjunction with referring to figs. 2 to Fig. 4.Referring initially to Fig. 3, work is prepared in the transistor of double-layered polycrystal silicon structure
In skill, formed in 32 step of polysilicon layer on the source electrode of transistor or drain electrode (or grid), in order to avoid polysilicon layer 32
It is contacted with grid 30, the side wall 35 of the meeting of polysilicon layer 32 exposed portion.Metal silication is formed on polysilicon layer 32
In the step of nitride layer 34, with continued reference to Fig. 3, need to be formed the barrier layer 36 of covering transistor over the semiconductor substrate 10, then join
Fig. 4 is examined, after forming mask (not shown) on the barrier layer 36, using the mask as mask, using dry etching and wet process
Etching technics, to remove the part barrier layer 36, (wet etching is not shown in the figure in exposed portion grid 30 and polysilicon layer 32
After technique, it is retained in the barrier layer in the semiconductor substrate 10)；Later then at the polysilicon layer 32 of the exposing and grid 30
It is upper to form metal silicide layer 34 as shown in Figure 2.
Fig. 4 is referred to however, combining.In the actual operation process, discovery removes partial barrier step using wet etching
In, the side wall 35 that the polysilicon layer 32 exposes can be damaged, notch 351 is formed between side wall 35 and grid 30, although subsequent
Another barrier layer can be formed on transistor (not show in another barrier layer figure, another barrier layer described for partly leading
After forming the dielectric layer for covering the transistor in body substrate, the dielectric layer is etched to form the through-hole that the transistor is connected
When, over etching phenomenon is avoided the occurrence of, to cause grid or the source electrode and drain electrode damage of transistor), but another barrier layer
Filling capacity it is poor, the notch can not be filled.In use, the notch 351 can cause grid 30 and polysilicon
The breakdown phenomenon under electric field action of layer 32, to reduce the reliability of transistor.
In order to solve above-mentioned gap problem, those skilled in the art attempt only to remove the part resistance with dry etch process
Barrier 36 is to expose source electrode or the drain electrode (or grid) of transistor.But Fig. 5 is referred to, the resistance is only etched with dry etch process
After barrier 36, understand in the subsequent 32 remained on surface partial barrier 341 of polysilicon layer for needing to form metal silicide layer, even
Excessive dry etch process is still difficult to thoroughly remove the partial barrier 341, cause can not on polysilicon layer 32 shape
At metal silicide layer 34, to reduce the performance of semiconductor device being subsequently formed.
For this purpose, the present invention provides a kind of semiconductor devices and forming method thereof.Include: in the formation of semiconductor devices
Grid, the side wall positioned at gate lateral wall, and partly leading positioned at the grid two sides are formed on a semiconductor substrate
Source electrode and drain electrode in body substrate；And conductive layer (being equivalent to the polysilicon layer 32 in Fig. 2) is formed on the semiconductor substrate,
The conductive layer at least covers the source electrode or drain electrode, and exposed portion grid and the part side wall of grid side, in institute
It states and forms opening between conductive layer, grid and side wall；
The first barrier material layer is formed on the semiconductor substrate, and first barrier material layer covers the conduction
Layer, grid and side wall；
Part first barrier material layer is removed, to form the first blocking for exposing the grid and partial electroconductive layer
Layer in removal part when first barrier material layer, removes the exposed part side wall of the opening, at side wall position
Notch is formed on gate lateral wall；
Metal silicide layer is formed in the grid and conductive layer surface of exposing；
After forming the metal silicide layer, filled layer, the filled layer filling are formed on the semiconductor substrate
The notch；
Dielectric layer is formed on the semiconductor substrate, to form interconnection structure.
In the forming method of above-mentioned semiconductor devices, in removal the first barrier material layer of part, forms exposed portion and lead
Electric layer and grid, with to behind the first barrier layer that conductive layer and gate surface form metal silicide layer, described half
Filled layer is formed on conductor substrate, during removal the first barrier material layer of part can be filled in the filled layer, because of removal
Notch of the part side wall to be formed on the gate lateral wall at side wall position, and then improve between the conductive layer and grid
Insulating properties, to avoid in subsequent use process, occurring because the notch between side wall and grid is to cause conductive layer and grid
The phenomenon that breakdown defect, is improved and is subsequently formed to further decrease probability breakdown between grid and conductive layer
The performance of semiconductor devices.
In order to make the foregoing objectives, features and advantages of the present invention clearer and more comprehensible, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
Fig. 6~Figure 14 is the knot of the semiconductor devices in each step of one embodiment of forming method of semiconductor devices of the present invention
Structure schematic diagram.
The forming method of semiconductor devices provided in this embodiment includes:
Referring initially to Fig. 6, semiconductor substrate 100 is provided.
In the present embodiment, the semiconductor substrate 100 is silicon substrate.
But in the other embodiments in addition to the present embodiment, the semiconductor substrate can also be silicon-Germanium substrate, silicon carbide lining
Bottom, silicon-on-insulator (SOI) substrate, germanium on insulator (GOI) substrate, glass substrate or other III-V compound substrates.
In addition, may also include the semiconductor elements such as transistor and interconnection structure in the semiconductor substrate 100, described half
Simultaneously the scope of protection of the present invention is not limited for the structure of conductor substrate.
With continued reference to Fig. 6, grid 210 is formed in the semiconductor substrate 100, positioned at the side of 210 side wall of grid
Wall 220, and the source electrode and drain electrode 230 in the semiconductor substrate of 210 two sides of grid.
In the present embodiment, multiple grids, and side corresponding with the grid are formed in the semiconductor substrate 100
Wall and source electrode and drain electrode.
In Fig. 6, grid 210, the side on 210 side wall of grid are formed in the semiconductor substrate 100
Wall 220, the source electrode and drain electrode 230 positioned at 210 two sides of grid, and another grid (figure adjacent with the grid 210
In do not show) source electrode (or drain electrode) 310.
Half between the corresponding source electrode of the grid 210 (or drain electrode) 230 and the source electrode (or drain electrode) 310 of another grid
Fleet plough groove isolation structure (Shallow Trench Isolation, abbreviation STI) 120 is formed in conductor substrate 100, with isolation
The corresponding source electrode and drain electrode of different grids.
In the present embodiment, the grid 210 is polysilicon gate, and the material of the side wall 220 is silica.
The formation process of each grid, side wall and source-drain electrode is similar, with the grid 210, is covered on the grid 210
For side wall 220 and source electrode and drain electrode 230 on side wall, formation process includes:
Gate dielectric layer 110 is first formed in the semiconductor substrate 100, forms polysilicon on the gate dielectric layer 110
Layer, forms the first mask 240 on the polysilicon layer；
It is later to form the grid 210 after polysilicon layer described in mask etching with first mask 240；
The silicon oxide layer for covering the grid 210 is formed in the semiconductor substrate 100, and uses autoregistration dry method
Etching technics etches the silicon oxide layer and forms the side wall 220；
After forming side wall 220, then ion implantation technology is used to inject ion in the semiconductor substrate, described in being formed
The corresponding source electrode and drain electrode 230 of grid 210.The specific formation process of the grid 210, side wall 220 and source electrode and drain electrode 230
For the prior art, details are not described herein.
Referring next to Fig. 7 and Fig. 8, conductive layer is formed on the semiconductor substrate, described in the conductive layer at least covers
The corresponding source electrode of grid 210 or drain electrode 230, and conductive layer exposed portion grid and the part side wall of grid side,
Opening is formed between the conductive layer, grid and side wall.
In the present embodiment, the conductive layer includes the multiple portions such as the first conductive layer 410 and the second conductive layer 420.This reality
Apply in example, 210 surface of grid described in 410 covering part of the first conductive layer, grid 210 close to another grid source electrode (or
Drain electrode) side walls of 310 sides, the grid 210 and the source electrode (or drain electrode) 310 adjacent sides source electrode (or drain electrode) 230,
And the corresponding source electrode (or drain electrode) 310 of another grid；Second conductive layer 420 covers the grid 210 far from institute
Side wall 220, the source electrode (or drain electrode) 230 far from the source electrode (or drain electrode) 310 sides for stating source electrode (or drain electrode) 310 sides,
And other corresponding source electrodes of grid (not shown) (or drain electrode or grid).
The conductive layer is for being electrically connected the corresponding source electrode of adjacent grid, drain electrode or adjacent grid, after realizing
Signal transmitting between the continuous each semiconductor devices formed.
In the present embodiment, first conductive layer 410 and the second conductive layer 420 are the polysilicon layer doped with ion,
The specific forming step of the conductive layer includes:
Referring initially to Fig. 7, remove grid 210 described in 240 exposed portion of the first mask of part surface and the grid
Pole 210 is close to the side wall 220 of source electrode (or drain electrode) 310 sides of another grid, and the covering of guarantor's type is more in semiconductor substrate 100
Crystal silicon；Later, the polysilicon is etched, with the exposed side wall of the surface of the formation covering exposing of grid 210, grid 210, is leaned on
Source electrode (or drain electrode) 230 another grid corresponding described sources adjacent with exposed side wall of the nearly exposed side wall side of grid
First polysilicon layer of pole (or drain electrode) 310, and the remaining side of the covering grid 210 side wall 220 and with the grid
Second polysilicon layer of the 210 corresponding source electrodes of remaining side wall 220 (or drain electrode) 230；Ion implanting step, Xiang Suoshu are carried out again
Doped ions in first polysilicon layer and the second polysilicon layer, to form first conductive layer 410 and the second conductive layer 420,
First conductive layer 410 is not contacted with the grid 210.
The grid 210 is removed after forming first conductive layer 410 and the second conductive layer 420 referring next to Fig. 8
Upper remaining first mask 240, the part side wall 220 on 210 side wall of grid 210 and the grid described in exposed portion,
Opening 200 is formed between first conductive layer 410 and the second conductive layer 420, grid 210 and side wall 220.
It is worth noting that, in the present embodiment, grid 210 described in 410 covering part of the first conductive layer, in another reality
It applies in example, the side wall of 210 two sides of grid can be retained, and first conductive layer 410 is not contacted with the grid 210,
The corresponding side wall 220 of the grid 210 and source electrode (or drain electrode) are only covered, i.e., described first conductive layer, 410 structure is led with second
420 structure of electric layer is similar, these simple changes are within the scope of the invention.
Referring next to Fig. 9, the first barrier material layer 500 is formed in the semiconductor substrate 100, described first stops material
The bed of material 500 covers first conductive layer 410 and the second conductive layer 420, grid 210 and side wall 220.
In the present embodiment, the material of first barrier material layer 500 be silicon rich oxide (Silicon Rich Oxide,
Abbreviation SRO), 500 guarantor's type of the first barrier material layer is covered on the surface of the semiconductor substrate.
In conjunction with reference Figure 10, removes part first barrier material layer 500 and (do not shown in figure with forming the first barrier layer
First barrier layer), the first conductive layer 410, the second conductive layer 420 and grid 210 described in the exposed portion of first barrier layer, after
It is continuous to need to form metal silicide layer on the first conductive layer 410, the second conductive layer 420 and grid 210 of exposing.
In the present embodiment, the technique for removing first barrier material layer 500 includes:
Photoresist layer (not shown), and exposed developing process are first coated on first barrier material layer 500
Afterwards, photoresist mask is formed；Later using the photoresist mask as mask, first it is partially covered on using dry etch process removal
The first barrier material layer 500 on first conductive layer 410 and the second conductive layer 420 needs to cover metal silication with determination
First conductive layer 410 of nitride layer and the range of the second conductive layer 420；Wherein after dry etch process, need to expose in part
Remaining the first barrier material layer of part 500 on first conductive layer 410, the second conductive layer 420 and grid 210, for this purpose, continuing
Using the photoresist mask as mask, then wet-etching technology is carried out, to remove remaining first barrier material layer in this part.
In the present embodiment, the first barrier material layer being partially covered on the conductive layer is first removed with dry etch process
500 the step of includes: to contain CF4、C4F8And O2, gas as dry etching agent, control power is 200~800W, dry method
The air pressure of etching agent is 30~100mTorr.
After dry etch process, then the step of remaining first barrier material layer in this part is removed with wet-etching technology packet
It includes: using diluted hydrofluoric acid solution as wet etchant.
It recombines with reference to Figure 10, remains in need to expose first after using wet-etching technology removal dry etching
When the first barrier material layer 500 on conductive layer 410, the second conductive layer 420 and grid 210, wet etching solution can corrode institute
The side wall 220 that opening 200 is exposed is stated, forms notch 221 between side wall 220 and grid 210.
It is subsequent in use, on the conductive layer and grid 210 apply voltage after, the conductive layer and grid
Electric field is formed between 210, the notch 221 causes the conductive layer and grid 210 breakdown under electric field action, to influence
The performance of semiconductor devices.
Referring next to Figure 11, after the first conductive layer 410 described in exposed portion, the second conductive layer 420 and grid 210,
Metal silicide layer 430 is formed on the first conductive layer 410, the second conductive layer 420 and the grid 210 exposed.
The formation process of the metal silicide layer 430 includes: first to form metal layer in the semiconductor substrate 100,
The metal layer is covered on 210 surface of the first conductive layer 410, the second conductive layer 420 and grid of exposing；It anneals later
Technique, so that the metal layer and the first conductive layer 410, the second conductive layer 420 and grid 210 react, to be formed
Metal silicide layer 430；Then it is reacted again using the removal of the techniques such as wet etching not with conductive layer and not with the grid 210
Metal layer.
It is worth noting that, the metal silicide layer 430 can't fill the notch 221, and it is located at described second
Metal silicide layer on conductive layer 420 is not in contact with the metal silicide layer on the grid 210.The metal silicide
The formation process of layer 430 is the prior art, and details are not described herein.
In the present embodiment, the metal layer is cobalt (Co) layer, and forming method is physical vapour deposition (PVD) (Physical Vapor
Deposition, abbreviation PVD), the material of the metal silicide layer 430 is the silicide of cobalt.
The metal silicide layer 430 is subsequently used for forming interconnection structure.
In the present embodiment, with reference to Figure 12, after forming the metal silicide layer 430, in the semiconductor substrate 100
Upper formation filled layer 600, the filled layer 600 has good filling capacity, so that the filled layer 600 can effectively fill institute
State notch 221.
In the present embodiment, the filled layer 600 is silicon oxide layer, specifically, the filled layer 600 is with ethyl orthosilicate
(TEOS) it is used as reactant, using sub- aumospheric pressure cvd technique (Sub Atmospheric Pressure Chemical
Vapor Deposition, abbreviation SACVD) formed silicon oxide layer.
The silicon oxide layer formed using above-mentioned technique has good filling capacity to effectively fill the notch 221,
Increase the insulating properties between the grid 210 and conductive layer, reduce after applying voltage on the grid 210 and conductive layer,
The grid 210 and the breakdown probability of conductive layer.
It is that reactant is formed in the technique of silica in TEOS, passes through TEOS flow control, reaction gas in reaction gas
Air pressure and temperature control, with optimize formed silica filling capacity.
In the present embodiment, (TEOS) is made for reactant, using sub- aumospheric pressure cvd technique shape with ethyl orthosilicate
Include: at the concrete technology of silicon oxide layer
The gas for containing ethyl orthosilicate and oxygen is passed through as reaction gas, controls the flow of ethyl orthosilicate and oxygen
Than being 300~800Torr for the air pressure of 1:5~1:10, reaction gas, reaction temperature is 400~600 DEG C, to form the oxygen
SiClx layer, as filled layer 600.
In the present embodiment, the filled layer 600 covers the metal silicide layer 430 simultaneously.
Optionally, the step of forming filled layer 600 include: make the filled layer with a thickness of
Referring again to Figure 13, after forming the filled layer 600, the second resistance of guarantor's type covering in the semiconductor substrate 100
Barrier 700.
In the present embodiment, formed the second barrier layer 700 the step of include: to be formed in the semiconductor substrate 100
The silicon nitride layer (SiON) of oxygen is adulterated, silicon nitride layer (SiN) is formed on the silicon nitride layer of the doping oxygen later, is mixed with described
The silicon nitride layer of miscellaneous oxygen and the lamination of silicon nitride layer are as second barrier layer 700.
It combines later and refers to Figure 14, form dielectric layer 800 in the semiconductor substrate 100, the dielectric layer 800 covers
Second barrier layer.
Optionally, the dielectric layer 800 is silicon oxide layer.
The dielectric layer 800 is used to form interconnection structure.The forming step of the interconnection structure includes:
The dielectric layer 800 is first etched, above the formation exposing grid 210 and part in the dielectric layer 800
The through-hole of metal silicide layer 430 above first conductive layer 410, the second conductive layer 420.
Second barrier layer 700, which is used as, etches the dielectric layer 800 to form the barrier layer when through-hole, avoid because
And 800 difference in thickness of dielectric layer of 230 top of the grid 210 or source electrode (and drain electrode) and cause dielectric layer 800 locally to occur
Over etching phenomenon, thus damage gate 210 or the first conductive layer 410, the second conductive layer 420.
Later, conductive material is filled in the through-hole in the dielectric layer 800, using as interconnection structure.Above-mentioned technique with
Prior art is similar, and details are not described herein.
In the forming method of the present embodiment semiconductor devices, in removal the first barrier material layer of part, exposed portion is formed
Conductive layer and grid, with to behind the first barrier layer that conductive layer and gate surface form metal silicide layer, described half
Filled layer is formed on conductor substrate, during removal the first barrier material layer of part can be filled in the filled layer, because of removal
Notch of the part side wall to be formed on the gate lateral wall at side wall position, and then improve between the conductive layer and grid
Insulating properties, to avoid in subsequent use process, occurring because the notch between side wall and grid is to cause conductive layer and grid
The phenomenon that breakdown defect, is improved and is subsequently formed to further decrease probability breakdown between grid and conductive layer
The performance of semiconductor devices.
The present embodiment additionally provides semiconductor devices made from the forming method using above-described embodiment semiconductor devices, but
The forming method of above-described embodiment semiconductor devices does not limit the structure of the semiconductor devices.
With reference to Figure 15, the semiconductor devices includes semiconductor substrate 900.
In the present embodiment, the semiconductor substrate 900 is silicon substrate, but in the other embodiments in addition to the present embodiment, institute
Stating semiconductor substrate can also be silicon-Germanium substrate, silicon carbide substrates, silicon-on-insulator (SOI) substrate, germanium on insulator (GOI) lining
Bottom, glass substrate or other III-V compound substrates.The type of the semiconductor substrate does not limit protection model of the invention
It encloses.
It is formed with grid, the side wall on gate lateral wall in the semiconductor substrate 900, and is served as a contrast in the semiconductor
The corresponding multiple source electrode and drain electrodes of each grid are formed in bottom 900.
In the present embodiment, multiple grids are formed in semiconductor substrate 900, be formed in semiconductor substrate it is multiple with it is each
The corresponding source electrode and drain electrode of grid, and by being set to the semiconductor substrate between the different corresponding source electrode and drain electrodes of grid
Fleet plough groove isolation structure in 900 is separately.
Optionally, it is formed with gate dielectric layer 941 on 900 surface of semiconductor substrate, each grid is located at grid Jie
941 top of matter layer.
In the present embodiment, the semiconductor substrate 900 includes the region I and the region II, is distinguished in the region I and the region II
It is formed with different grids, and source electrode and drain electrode corresponding with grid.
It is formed with grid 912 on the region I, positioned at the grid 912 far from the side wall of the region II side
Side wall 913 is formed with the source electrode and drain electrode 911 positioned at 912 two sides of grid in the region I of the semiconductor substrate 900.
Jagged 950 are formed between the side wall 913 and grid 912.
In the present embodiment, the grid 912 is polysilicon gate, and the material of the side wall 920 is silica.
It is worth noting that, only show the grid positioned at the region I in Figure 15, and in the region II source electrode (or
Drain electrode) 921, the gate structure on the region I and the region II can be the same or different, and each grid is existing
Technology.The side wall and source electrode and drain electrode of the region I and grid, gate lateral wall on the region II are the prior art,
And the scope of protection of the present invention is not limited.
Conductive layer, grid 912, side wall described in the conductive layer exposed portion are formed in the semiconductor substrate 900
Notch 950 between 913 and the grid 912 and side wall 123, and the conductive layer connects the grid 912 on the region I
The corresponding source electrode of grid (or drain electrode) 921 on corresponding source electrode (or drain electrode) 911 and the region II.
In the present embodiment, the conductive layer includes the first conductive layer 943 and the second conductive layer 944.
912 surface of grid described in first conductive layer, 943 covering part, the grid 912 do not set the side wall of side wall, position
The source electrode (or drain electrode) 911 of the side wall side of side wall is not set in the grid, and another grid leans in the region II
The source electrode (or drain electrode) 921 in the nearly region I.
Second conductive layer 944 cover the side wall 913 of the grid 912, source electrode corresponding with the side wall 913 (or
Drain electrode) 911, and be located in the semiconductor substrate 900, and other grid (figures adjacent with the source electrode (or drain electrode) 911
In do not show) corresponding source electrode or drain electrode (not shown).
In the present embodiment, the conductive layer (including the first conductive layer 943 and the second conductive layer 944) is doped with ion
Polysilicon layer.
The semiconductor devices further includes (including the first conductive layer 943 and the second conductive layer of conductive layer described in covering part
944) the first barrier layer (not shown), conductive layer and the grid described in the exposed portion of first barrier layer, to
Form the metal silicide layer for being covered on the grid and conductive layer surface.
5 are continued to refer to figure 1, the conductive layer that exposes on first barrier layer (including the first conductive layer 943 and second conductive
Layer is 944) and the surface of the grid 912 is covered with metal silicide layer 945.
In the present embodiment, the material of the metal silicide layer 945 is the silicide of cobalt.
Filled layer 946 is also formed in the semiconductor substrate 900, the filled layer 946 fills the notch 950.
Optionally, the filled layer 946 is using ethyl orthosilicate as reactant, using sub- aumospheric pressure cvd work
Skill forms the silicon oxide layer.
The filled layer 946 has good filling effect and insulating properties, so as to effectively fill the grid 912 with
Notch 950 between the side wall 913 avoids subsequent used to improve the insulating properties between the conductive layer and grid 912
Cheng Zhong causes conductive layer and grid 912 breakdown based on the notch 950 between side wall 913 and grid 912, reduces grid
Breakdown probability between 912 and conductive layer, improves the performance for the semiconductor devices being subsequently formed.
Optionally, the filled layer 946 fills the notch 950, and covers the metal silicide layer 945.
In the present embodiment, the filled layer 946 with a thickness of
Also guarantor's type is covered with the second barrier layer 947 in the semiconductor substrate 100.
In the present embodiment, second barrier layer 947 is covered on 946 surface of filled layer.
In the present embodiment, second barrier layer 947 includes the silicon nitride layer of doping oxygen, and positioned at the nitrogen of the doping oxygen
Silicon nitride layer on SiClx layer.
Dielectric layer 960 is formed on second barrier layer 947, the dielectric layer 960 is used to form the connection grid
The interconnection structure of pole 912 and the corresponding source electrode and drain electrode 911 of grid 912.
It is worth noting that, in the other embodiments of semiconductor devices of the present invention, in the grid 912 and the side wall
Side wall is likewise formed on 913 corresponding other side side walls；And first conductive layer 943 is not contacted with the grid 912,
Only covering part side wall and the other side source electrode opposite with the side wall 913.Above-mentioned simple change is in guarantor of the invention
It protects in range.
In the present embodiment semiconductor devices, filled layer, the filled layer filling are formed on the grid and conductive layer
Notch between the full grid and side wall avoids subsequent use to improve the insulating properties between the conductive layer and grid
In the process, based on the notch between side wall and grid to causing conductive layer and grid breakdown, reduce grid and conductive layer it
Between breakdown probability, improve the performance for the semiconductor devices being subsequently formed.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (19)
1. a kind of forming method of semiconductor devices characterized by comprising
Semiconductor substrate is provided；
Form the grid being located in semiconductor substrate, the side wall positioned at gate lateral wall, and partly leading positioned at the grid two sides
Source electrode and drain electrode in body substrate；
Conductive layer is formed on the semiconductor substrate, and the conductive layer at least covers the source electrode or drain electrode, and exposed division
The part side wall for dividing grid and grid side forms opening between the conductive layer, grid and side wall；
The first barrier material layer is formed on the semiconductor substrate, and first barrier material layer covers the conductive layer, grid
Pole and side wall；
Part first barrier material layer is removed, to form the first barrier layer for exposing the grid and partial electroconductive layer,
When removing part first barrier material layer, the exposed part side wall of the opening, the grid at side wall position are removed
Notch is formed on side wall；
Metal silicide layer is formed in the grid and conductive layer surface of exposing；
After forming the metal silicide layer, filled layer is formed on the semiconductor substrate, described in the filled layer filling
Notch；
Dielectric layer is formed on the semiconductor substrate, to form interconnection structure.
2. the forming method of semiconductor devices as described in claim 1, which is characterized in that the filled layer is silicon oxide layer；
The step of forming the filled layer includes: using ethyl orthosilicate as reactant, using sub- aumospheric pressure cvd work
Skill forms the silicon oxide layer.
3. the forming method of semiconductor devices as claimed in claim 2, which is characterized in that the Asia aumospheric pressure cvd
The step of technique includes: to be passed through the gas that contains ethyl orthosilicate and oxygen as reaction gas, and ethyl orthosilicate and oxygen
Flow-rate ratio be 1:5~1:10, the air pressure of reaction gas is 300~800Torr, and reaction temperature is 400~600 DEG C.
4. the forming method of semiconductor devices as described in claim 1, which is characterized in that removal part described first stops material
The bed of material includes: the step of the first barrier layer for exposing the grid and partial electroconductive layer to be formed
Dry etch step is first carried out, the first barrier material layer of part, exposed portion conductive layer are removed；Carry out wet process quarter again later
Lose step.
5. the forming method of semiconductor devices as claimed in claim 4, which is characterized in that the dry etch step includes:
To contain CF4、C4F8And O2For gas as etching gas, control power is 200~800W, the air pressure of dry etching agent is 30~
100mTorr。
6. the forming method of semiconductor devices as claimed in claim 4, which is characterized in that the wet etching step includes:
Using diluted hydrofluoric acid solution as wet etchant.
7. the forming method of semiconductor devices as described in claim 1, which is characterized in that the material of the side wall is oxidation
Silicon.
8. the forming method of semiconductor devices as described in claim 1, which is characterized in that formed conductive layer the step of include:
Form polysilicon layer on the semiconductor substrate, the backward polysilicon layer in Doped ions, the polycrystalline after Doped ions
Silicon layer is as the conductive layer.
9. the forming method of semiconductor devices as described in claim 1, which is characterized in that the step of forming metal silicide layer
Include: to form metal layer on the grid and conductive layer surface of exposing, annealing process is carried out later, in the grid of exposing
Pole and conductive layer surface form the metal silicide layer.
10. the forming method of semiconductor devices as described in claim 1, which is characterized in that after forming the filled layer, shape
Before the dielectric layer, the forming method of the semiconductor devices further include: guarantor's type covering second on the semiconductor substrate
Barrier layer.
11. the forming method of semiconductor devices as claimed in claim 10, which is characterized in that protect on the semiconductor substrate
Type covers the silicon nitride layer that the step of the second barrier layer includes: guarantor's type covering doping oxygen on the semiconductor substrate, Zhi Hou
It is described doping oxygen silicon nitride layer on form silicon nitride layer, using it is described doping oxygen silicon nitride layer and silicon nitride layer lamination as
Second barrier layer.
12. the forming method of semiconductor devices as described in claim 1, which is characterized in that shape on the semiconductor substrate
At the step of filled layer include make the filled layer with a thickness of
13. a kind of semiconductor devices characterized by comprising
Semiconductor substrate；
Grid in the semiconductor substrate, the side wall positioned at gate lateral wall, and the source electrode positioned at the grid two sides
And drain electrode, wherein formed between the side wall and grid jagged；
At least cover the conductive layer of the source electrode or drain electrode, conductive layer exposed portion grid, grid side part side wall,
And the notch；
The grid and partial electroconductive layer are exposed in the first barrier layer on the conductive layer, first barrier layer, and
The notch；
Cover the metal silicide layer of grid and conductive layer that first barrier layer is exposed；
Filled layer on the metal silicide layer, the filled layer fill the notch；
It is covered on the dielectric layer of the semiconductor substrate, is used to form interconnection structure in the dielectric layer.
14. semiconductor devices as claimed in claim 13, which is characterized in that the filled layer is using ethyl orthosilicate as instead
Object is answered, silicon oxide layer is formed by using sub- aumospheric pressure cvd technique.
15. semiconductor devices as claimed in claim 13, which is characterized in that the material of the side wall is silica.
16. semiconductor devices as claimed in claim 13, which is characterized in that the conductive layer is the polysilicon of Doped ions
Layer.
17. semiconductor devices as claimed in claim 13, which is characterized in that the semiconductor devices further include: the covering of guarantor's type
In the second barrier layer in the semiconductor substrate.
18. semiconductor devices as claimed in claim 17, which is characterized in that second barrier layer includes the nitridation for adulterating oxygen
Silicon layer, and the silicon nitride layer on the silicon nitride layer of the doping oxygen.
19. semiconductor devices as claimed in claim 13, which is characterized in that the filled layer with a thickness of
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| US6274468B1 (en) * | 1998-07-06 | 2001-08-14 | United Microelectronics Corp. | Method of manufacturing borderless contact |
| CN102487048A (en) * | 2010-12-03 | 2012-06-06 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6274468B1 (en) * | 1998-07-06 | 2001-08-14 | United Microelectronics Corp. | Method of manufacturing borderless contact |
| CN102487048A (en) * | 2010-12-03 | 2012-06-06 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor device |
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