CN104752218B - The forming method of semiconductor devices - Google Patents
The forming method of semiconductor devices Download PDFInfo
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- CN104752218B CN104752218B CN201310745796.9A CN201310745796A CN104752218B CN 104752218 B CN104752218 B CN 104752218B CN 201310745796 A CN201310745796 A CN 201310745796A CN 104752218 B CN104752218 B CN 104752218B
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- 238000000034 method Methods 0.000 title claims abstract description 60
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 58
- 230000004888 barrier function Effects 0.000 claims abstract description 57
- 239000000463 material Substances 0.000 claims abstract description 56
- 238000005530 etching Methods 0.000 claims abstract description 52
- 238000002955 isolation Methods 0.000 claims abstract description 23
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 22
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 22
- 239000010703 silicon Substances 0.000 claims abstract description 22
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 9
- 239000010410 layer Substances 0.000 claims description 206
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 26
- 239000002184 metal Substances 0.000 claims description 23
- 229910052751 metal Inorganic materials 0.000 claims description 23
- 239000011229 interlayer Substances 0.000 claims description 16
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- 239000000377 silicon dioxide Substances 0.000 claims description 11
- 238000001039 wet etching Methods 0.000 claims description 9
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 8
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 6
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 6
- 230000003647 oxidation Effects 0.000 claims description 5
- 238000007254 oxidation reaction Methods 0.000 claims description 5
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- 239000003795 chemical substances by application Substances 0.000 claims description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 4
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- 238000010790 dilution Methods 0.000 claims description 3
- 239000012895 dilution Substances 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 15
- 229910052760 oxygen Inorganic materials 0.000 abstract description 15
- 239000001301 oxygen Substances 0.000 abstract description 15
- 230000008054 signal transmission Effects 0.000 abstract description 6
- 239000002699 waste material Substances 0.000 abstract description 4
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- 238000006243 chemical reaction Methods 0.000 description 3
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- 229920002120 photoresistant polymer Polymers 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 206010054949 Metaplasia Diseases 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A kind of forming method of semiconductor devices, including：Substrate is provided, substrate includes core space and external zones, shallow groove isolation layer and multiple fins higher than shallow groove isolation layer are formed with substrate；Cap layers material layer, cap layers material layer covering substrate, fin portion surface are formed in substrate；The cap layers layer material sections of external zones are removed, the remaining cap layers material layer of core space is used as cap layers；After cap layers are formed, using thermal oxide growth technique, in fin portion surface the first etching barrier layer of formation of external zones.In core space, oxygen, to the stop that diffuses to form of fin portion surface, the silicon waste very little of the fin portion surface of core space or will not be lost cap layers substantially.Compared with prior art, the fin line width of core space is more or less the same or of substantially equal with expected line width, it is ensured that carrier higher carrier mobility in the fin of core circuit, core circuit has higher signal transmission rate.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly to a kind of forming method of semiconductor devices.
Background technology
Integrated circuit in technical field of semiconductors, usual wafer includes the I/O around core circuit and core circuit
Circuit.The advantages of fin formula field effect transistor is with its less size, larger driving current, applied to IC manufacturing work
Skill.
Prior art is using rear grid technique formation fin formula field effect transistor.Fin formula field effect transistor includes：It is located at
Fin in substrate；Across the metal gates of fin；The fin part of the grid both sides has heavy doping, respectively as source
Pole, drain electrode.
Reference picture 1, is used self-alignment duplex pattern (Self-aligned Double patterning, abbreviation SADP)
Method, in multiple finned pieces 2 of the formation laid out in parallel of substrate 1.Core space I finned piece 2 and external zones II finned piece 2 be
Formed in same step, wherein core space I is used to form core circuit, and external zones II is used to form I/O circuits.
Reference picture 2, forms shallow groove isolation layer 3 on the base 1, the covering substrate 1 of shallow groove isolation layer 3 and by finned piece 2
It is spaced from each other, the thickness of shallow groove isolation layer 3 is less than the height of finned piece 2, the finned piece part higher than shallow groove isolation layer 3 is made
For fin 4.
Reference picture 3, using thermal oxide growth technique, makes the silicon on the surface of fin 4 be combined with the oxygen in reaction chamber, in fin 4
Surface forms silicon oxide layer 5, and silicon oxide layer 5 is used as etching barrier layer.The gold of fin is subsequently being developed across using rear grid technique
When belonging to grid, etching barrier layer plays etch stopper effect during etching removes dummy grid, it is to avoid the fin under dummy grid
By over etching.After dummy grid is removed, etching removes silicon oxide layer 5, under conditions of etching oxidation silicon layer 5, silicon oxide layer 5
There is larger etching selection ratio to the silicon of fin, substantially will not over etching correspondence dummy grid fin part.
For core space I core circuit, if the fin 4 of fin formula field effect transistor is perpendicular to fin length direction
On line width it is larger when, carrier mobility is larger, then the signal transmission speed in core circuit is also bigger.But, in heat
During oxidation growth, the silicon on the surface of fin 4 is lost.Reference picture 2, Fig. 3, carry out the line of fin 4 after thermal oxide growth
Wide W2Less than the line width W of fin 4 not carried out before thermal oxide growth1, the core space I surface loss of fin 4 subtracts the line width of fin 4
Small, this can reduce the signal transmission speed of core circuit.
The content of the invention
The problem of present invention is solved is that the fin line width of the fin formula field effect transistor of prior art core circuit is smaller,
Reduce the signal transmission rate of core circuit.
To solve the above problems, the present invention provides a kind of forming method of semiconductor devices, the formation of the semiconductor devices
Method includes：
There is provided substrate, the substrate include core space and external zones, be formed with the substrate shallow groove isolation layer and
Higher than multiple fins of the shallow groove isolation layer；
Cap layers material layer, the cap layers material layer covering substrate, fin portion surface are formed on the substrate；
The cap layers layer material sections of the external zones are removed, the remaining cap layers material layer of core space is used as cap layers；
After the cap layers are formed, using thermal oxide growth technique, at fin portion surface the first quarter of formation of the external zones
Lose barrier layer.
Alternatively, in thermal oxide growth technique, formed between the fin of the core space and the cap layers of fin portion surface
Second etching barrier layer.
Alternatively, also include：
It is developed across the dummy grid of the fin；
Form interlayer dielectric layer, the interlayer dielectric layer covering cap layers and the first etching barrier layer, dummy grid, inter-level dielectric
The upper surface and dummy grid upper surface of layer maintain an equal level；
Etching removes the dummy grid and forms pseudo- gate groove, to exposing the cap layers and the first etching barrier layer；
The first etching barrier layer in the cap layers and the pseudo- gate groove of external zones in the pseudo- gate groove of the core space is removed, it
Afterwards, metal gates are formed in pseudo- gate groove.
Alternatively, the forming method of the shallow groove isolation layer and fin includes：
Substrate to segment thickness is patterned to form multiple finned pieces；
Insulating barrier, the insulating barrier covering substrate and all finned pieces, and the insulation in substrate are formed on the substrate
Layer segment is higher than finned piece；
It is etched back to remove the insulating barrier of segment thickness, the finned piece is higher than remaining insulating barrier, the residue in substrate
Insulated part as shallow groove isolation layer, the finned piece part higher than shallow groove isolation layer is used as fin.
Alternatively, the substrate of segment thickness is patterned and forms the methods of multiple finned pieces and include：
Strip piece is formed on the substrate, and the strip piece defines the position in space between adjacent two finned piece；
In the side wall formation side wall of the strip piece bearing of trend, the side wall defines the position of finned piece；
Using the side wall as mask, segment thickness substrate, the shape under the side wall under the strip piece and strip piece are etched
Into finned piece；
Remove the side wall.
Alternatively, the material of the strip piece is silica, and the material of the side wall is silicon nitride.
Alternatively, the forming method of the shallow groove isolation layer and fin includes：
Insulating barrier and the top silicon layer on insulating barrier are formed on the substrate, and the insulating barrier is used as shallow trench
Separation layer；
The top silicon layer of full depth is patterned to form multiple fins.
Alternatively, the method for removing the cap layers layer material sections of the external zones is wet etching.
Alternatively, the cap layers material is silica or silicon nitride.
Alternatively, the cap layers material is silica, and the etching agent that the wet etching process is used is dilute hydrofluoric acid
Solution.
Alternatively, the cap layers material is silicon nitride, and the etching agent that the wet etching process is used is molten for dilution phosphoric acid
Liquid.
Alternatively, before the interlayer dielectric layer is formed, ion implanting is carried out to the dummy grid both sides fin part,
Source electrode, drain electrode are formed respectively.
Alternatively, the pseudo- gate trench sidewall of covering and the high-K gate dielectric layer of bottom, the gold are formed in the pseudo- gate groove
Belong to grid covering high-K gate dielectric layer.
Alternatively, the forming method of the high-K gate dielectric layer and metal gates includes：
Form high K dielectric material layer and the metal gate material layer in high K dielectric material layer, the high K dielectric material
The bed of material covers the interlayer dielectric layer, pseudo- gate trench sidewall and bottom, the full pseudo- gate groove of metal gate material layer filling；
Remove the high K dielectric material layer for being higher by interlayer dielectric layer upper surface and metal gate material layer, the pseudo- gate groove
In remaining high K dielectric material layer as high-K gate dielectric layer, remaining metal gate material layer is used as metal gates.
Compared with prior art, technical scheme has advantages below：
During thermal oxide growth, in external zones, oxygen is directly contacted with fin portion surface.And in core space, cap layers are to oxygen
To the stop that diffuses to form of fin portion surface, the oxygen that the oxygen content of external zones fin portion surface is significantly more than the fin portion surface of core space contains
Amount, makes the fin portion surface thermal oxide growth speed of external zones very big, the silicon waste very little of the fin portion surface of core space or basic
It will not be lost.Therefore, after thermal oxide growth, the fin line width of core space is more than the fin line width of external zones.With showing
There is technology to compare, the fin line width of core space is more or less the same or of substantially equal with expected line width, it is ensured that the fin of core circuit
Middle carrier higher carrier mobility, core circuit has higher signal transmission rate.
Brief description of the drawings
Fig. 1~Fig. 3 is cross-sectional view of the existing fin formula field effect transistor in forming process；
Fig. 4~Figure 10 is that cross-section structure of the fin formula field effect transistor of the specific embodiment of the invention in forming process shows
It is intended to；
Figure 11~Figure 12 is that the fin and shallow groove isolation layer of the fin formula field effect transistor of another embodiment of the present invention exist
Cross-sectional view in forming process.
Embodiment
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
Reference picture 4 includes core space I and external zones II there is provided substrate 100, substrate 100, and core space I will be used to form core
Electrocardio road, external zones II will be used to form I/O circuits.
In a particular embodiment, substrate 100 can be silicon base or germanium, germanium silicon, GaAs substrate or insulator
Upper silicon base.Those skilled in the art can select substrate as needed, therefore the type of substrate should not limit the present invention's
Protection domain.The selection silicon base of substrate 100 in the present embodiment, because implementing the technical program on a silicon substrate than above-mentioned
Implement the low cost of the technical program in other substrates.
Reference picture 5, the substrate to segment thickness is patterned to form multiple finned pieces 101.
In a particular embodiment, using self-alignment duplex pattern method, segment thickness substrate is patterned to be formed
Multiple finned pieces 101, specifically, including：
Strip piece (not shown) is formed in substrate 100, the material of the strip piece is silica, and strip piece is used for
Define the position in space between adjacent two finned piece；
In the side wall formation side wall of strip piece bearing of trend, the material of side wall is silicon nitride, and the side wall defines finned piece
Position；
Using side wall as mask, the substrate of segment thickness, finned piece is formed under side wall under etching strip piece and strip piece
101；
Finally, side wall is removed.
Reference picture 6, forms insulating barrier 102, insulating barrier covering substrate 100 and all finned pieces 101 in substrate 100, and
Insulation layer segment in substrate 100 is higher than finned piece 101.The material of insulating barrier 102 is silica, specifically used chemical vapor deposition
Product is formed.
Reference picture 7, is etched back to remove the insulating barrier of segment thickness, finned piece 101 is higher than remaining insulation in substrate 100
Layer, the remaining insulated part is as shallow groove isolation layer 103, and the finned piece part higher than shallow groove isolation layer 103 is used as fin
Portion 104.
Reference picture 8, forms cap layers material layer 105, the covering of cap layers material layer 105 substrate 100, fin 104 in substrate 100
Surface.In a particular embodiment, cap layers material is silica or silicon nitride, and usable chemical vapor deposition method is formed.
Reference picture 9, is removing external zones II cap layers layer material sections, the remaining cap layers layer material sections of core space I are made
For cap layers 106.
In a particular embodiment, removing the method for external zones II cap layers layer material sections includes：
Patterned mask layer is formed in cap layers material layer 105, the patterned mask layer material can for photoresist or
Other mask materials, in the present embodiment, the material of patterned mask layer is photoresist, patterned mask layer definition periphery
Area II position；
Using patterned mask layer as mask, wet etching removes external zones II cap layers layer material sections, according to cap layers
Material, when cap layers material is silica, can be used dilute hydrofluoric acid solution during wet etching, when cap layers material is nitridation
Dilution phosphoric acid solution can be used during silicon, during wet etching；
Remove patterned mask layer.
Reference picture 10, using thermal oxide growth technique, the external zones II surface of fin 104 forms the first etching barrier layer
111.During the first etching barrier layer 111 is formed, the second etching barrier layer is also formed on the core space I surface of fin 104
112, the second etching barrier layer 112 is located between fin and the cap layers part of fin portion surface.
In a particular embodiment, the thermal oxide growth process is carried out in boiler tube, therefore, and thermal oxide growth is also known as boiler tube oxygen
Metaplasia is long.Oxygen and the pasc reaction generation silica on external zones II surfaces, the silica are attached to the surface of fin 104 as the first etching
Barrier layer 111.In boiler tube, oxygen is also possible to reach the surface of core space I fins 104 through cap layers 106, and with pasc reaction generation the
Two etching barrier layers 112.
But, it is contemplated that external zones II oxygen is directly contacted with the surface of fin 104, and cap layers 106 diffuse to form resistance to oxygen
Gear, the oxygen content on the core space I surface of fin 104 is less than the oxygen content on the surface of external zones II fins 104, and core space I fin
The Film by Thermal Oxidation speed of portion 104 is less than the Film by Thermal Oxidation speed of external zones II fins 104 so that core space I fin
The silicon waste on the surface of portion 104 is less than the silicon waste on the external zones II surface of fin 104, finally, the second etching barrier layer 112
Thickness H1Less than the thickness H of the first etching barrier layer 1112.In a particular embodiment, if the thickness of cap layers 106 is thicker, or
Oxygen content in person's boiler tube is less, and the silicon on the core space I surface of fin 104 may also will not touch oxygen, the surface of fin 104
Silicon will not be lost, and would not also form the second etching barrier layer.
Therefore, after thermal oxide growth, core space I fin line width W1Fin line width W more than external zones II2.With it is existing
Technology is compared, and core space I fin line width is more or less the same or of substantially equal with expected line width, it is ensured that in the fin of core circuit
Carrier higher carrier mobility, core circuit has higher signal transmission rate.
In a particular embodiment, thermal oxide growth is formed after the first etching barrier layer 111 and the second etching barrier layer 112,
The metal gates (not shown) of fin 104 is developed across using rear grid technique.
Specifically, the rear grid technique is：
It is cap layers and the second quarter between the fin and dummy grid that are developed across under the dummy grid of fin, the dummy grid of core space
It is the first etch stopper layer segment to lose between fin and dummy grid under barrier layer portions, the dummy grid of external zones, dummy grid
Material is polysilicon or non-crystalline silicon；
Ion implanting is carried out in the fin part of the dummy grid both sides, source electrode, drain electrode is formed respectively, in this process,
Inject ion can through the cap layers and the second etch stopper layer segment of core space dummy grid both sides, external zones dummy grid both sides the
One etching barrier layer portions are diffused in fin, and form heavy doping in the fin, in other embodiments, also can carry out from
Before son injection, the cap layers and the second etch stopper layer segment, the first etch stopper layer segment of dummy grid both sides are removed；
Interlayer dielectric layer, interlayer dielectric layer covering cap layers and the first etching barrier layer, dummy grid are formed, interlayer dielectric layer
Upper surface and dummy grid upper surface are remained basically stable；
Etching removes dummy grid and forms pseudo- gate groove, to cap layers and the first etching barrier layer are exposed, in this process, pseudo- grid
Cap layers and the second etching barrier layer under extremely, the first etching barrier layer can play etch stopper effect, it is to avoid etching dummy grid mistake
Journey causes over etching to the fin part under dummy grid；
Remove the first etching in the pseudo- gate groove of cap layers, the second etching barrier layer and external zones in the pseudo- gate groove of core space
Barrier layer, under conditions of the first etching barrier layer and the second etching barrier layer is etched, the first etching barrier layer and the second etching
Barrier layer has a higher etching selection ratio compared to fin, substantially will not the pseudo- gate groove bottom of over etching fin part；
Afterwards, metal gates are formed in pseudo- gate groove.
In a particular embodiment, the pseudo- gate trench sidewall of covering and the high-K gate dielectric layer of bottom, gold are formed in pseudo- gate groove
Belong to grid covering high-K gate dielectric layer.
In a particular embodiment, the forming method of high-K gate dielectric layer and metal gates includes：
Form high K dielectric material layer and the metal gate material layer in high K dielectric material layer, high K dielectric material layer
Cover interlayer dielectric layer, pseudo- gate trench sidewall and bottom, the full pseudo- gate groove of metal gate material layer filling；
Remove the high K dielectric material layer for being higher by interlayer dielectric layer upper surface and metal gate material layer, the pseudo- gate groove
In remaining high K dielectric material layer as high-K gate dielectric layer, remaining metal gate material layer is used as metal gates.
So, multiple fin formula field effect transistors are formed in core space I and external zones II, interconnection is formed subsequently in substrate
Structure, interconnection structure will be electrically connected between corresponding fin formula field effect transistor.
The present invention also provides the forming method of another semiconductor devices.
In the present embodiment, the forming method of shallow groove isolation layer and fin is different from previous embodiment.
Reference picture 11, forms insulating barrier 301 and the top silicon layer 302 on insulating barrier 301, insulation in substrate 300
Layer 301 will include core space I and external zones II as shallow groove isolation layer, substrate 300.
Reference picture 12, is patterned to form multiple fins 303 to the top silicon layer 302 (reference picture 11) of full depth,
Self-alignment duplex pattern method specifically can be used.Multiple fins 303 are respectively formed in core space I and external zones II.
In addition to shallow groove isolation layer is different with fin forming method, the step of other are not described in detail and technical scheme are with before
State embodiment identical, corresponding reference can be made, be will not be described in detail herein.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, are not departing from this
In the spirit and scope of invention, it can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
The scope of restriction is defined.
Claims (14)
1. a kind of forming method of semiconductor devices, it is characterised in that including：
Substrate is provided, the substrate includes core space and external zones, shallow groove isolation layer is formed with the substrate and is higher than
Multiple fins of the shallow groove isolation layer；
Cap layers material layer, the cap layers material layer covering substrate, fin portion surface are formed on the substrate；
The cap layers layer material sections of the external zones are removed, the remaining cap layers material layer of core space is used as cap layers；
After the cap layers are formed, using thermal oxide growth technique, in fin portion surface formation the first etching resistance of the external zones
Barrier.
2. the forming method of semiconductor devices as claimed in claim 1, it is characterised in that in thermal oxide growth
In technique, the second etching barrier layer is formed between the fin of the core space and the cap layers of fin portion surface.
3. the forming method of semiconductor devices as claimed in claim 1, it is characterised in that also include：
It is developed across the dummy grid of the fin；
Interlayer dielectric layer, the interlayer dielectric layer covering cap layers and the first etching barrier layer, dummy grid are formed, interlayer dielectric layer
Upper surface and dummy grid upper surface maintain an equal level；
Etching removes the dummy grid and forms pseudo- gate groove, to exposing the cap layers and the first etching barrier layer；
The first etching barrier layer in the cap layers and the pseudo- gate groove of external zones in the pseudo- gate groove of the core space is removed, afterwards,
Metal gates are formed in pseudo- gate groove.
4. the forming method of semiconductor devices as claimed in claim 1, it is characterised in that the shallow trench every
The forming method of absciss layer and fin includes：
Substrate to segment thickness is patterned to form multiple finned pieces；
Insulating barrier, the insulating barrier covering substrate and all finned pieces, and the insulating barrier portion in substrate are formed on the substrate
Divide and be higher than finned piece；
It is etched back to remove the insulating barrier of segment thickness, the finned piece is described remaining exhausted higher than remaining insulating barrier in substrate
Edge is allocated as shallow groove isolation layer, and the finned piece part higher than shallow groove isolation layer is used as fin.
5. the forming method of semiconductor devices as claimed in claim 4, it is characterised in that the substrate to segment thickness is schemed
The method that shape forms multiple finned pieces includes：
Strip piece is formed on the substrate, and the strip piece defines the position in space between adjacent two finned piece；
In the side wall formation side wall of the strip piece bearing of trend, the side wall defines the position of finned piece；
Using the side wall as mask, segment thickness substrate under the strip piece and strip piece is etched, fin is formed under the side wall
Shape part；
Remove the side wall.
6. the forming method of semiconductor devices as claimed in claim 5, it is characterised in that the material of the strip piece is oxidation
Silicon, the material of the side wall is silicon nitride.
7. the forming method of semiconductor devices as claimed in claim 1, it is characterised in that the shallow groove isolation layer and fin
Forming method include：
Insulating barrier and the top silicon layer on insulating barrier are formed on the substrate, and the insulating barrier is isolated as shallow trench
Layer；
The top silicon layer of full depth is patterned to form multiple fins.
8. the forming method of semiconductor devices as claimed in claim 1, it is characterised in that remove the cap layers material of the external zones
The method of bed of material part is wet etching.
9. the forming method of semiconductor devices as claimed in claim 1, it is characterised in that the cap layers material be silica or
Silicon nitride.
10. the forming method of semiconductor devices as claimed in claim 8, it is characterised in that the cap layers material is silica,
The etching agent that the wet etching process is used is dilute hydrofluoric acid solution.
11. the forming method of semiconductor devices as claimed in claim 8, it is characterised in that the cap layers material is silicon nitride,
The etching agent that the wet etching process is used is dilution phosphoric acid solution.
12. the forming method of semiconductor devices as claimed in claim 3, it is characterised in that forming the interlayer dielectric layer
Before, ion implanting is carried out to the dummy grid both sides fin part, forms source electrode, drain electrode respectively.
13. the forming method of semiconductor devices as claimed in claim 3, it is characterised in that formed in the pseudo- gate groove
The pseudo- gate trench sidewall of covering and the high-K gate dielectric layer of bottom, the metal gates cover high-K gate dielectric layer.
14. the forming method of semiconductor devices as claimed in claim 13, it is characterised in that the high-K gate dielectric layer and gold
The forming method of category grid includes：
Form high K dielectric material layer and the metal gate material layer in high K dielectric material layer, the high K dielectric material layer
Cover the interlayer dielectric layer, pseudo- gate trench sidewall and bottom, the full pseudo- gate groove of metal gate material layer filling；
Remove and remained in the high K dielectric material layer for being higher by interlayer dielectric layer upper surface and metal gate material layer, the pseudo- gate groove
Remaining high K dielectric material layer is as high-K gate dielectric layer, and remaining metal gate material layer is used as metal gates.
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| US9666692B2 (en) * | 2015-07-31 | 2017-05-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming FinFET gate oxide |
| CN106952815A (en) * | 2016-01-06 | 2017-07-14 | 中芯国际集成电路制造(上海)有限公司 | The forming method of fin transistor |
| CN107316856B (en) * | 2016-04-26 | 2020-02-07 | 中芯国际集成电路制造(上海)有限公司 | Structure for detecting ion implantation abnormality, method for manufacturing same, and method for detecting ion implantation abnormality |
| CN108933105B (en) * | 2017-05-24 | 2020-11-03 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN109390397B (en) * | 2017-08-03 | 2023-03-10 | 联华电子股份有限公司 | Semiconductor element and manufacturing method thereof |
| CN109686702B (en) * | 2017-10-19 | 2021-02-02 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN110718465B (en) * | 2018-07-12 | 2023-03-14 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN115241132A (en) * | 2021-04-23 | 2022-10-25 | 长鑫存储技术有限公司 | Semiconductor structure and forming method thereof |
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