JP2016181674A - Semiconductor light-emitting device and apparatus including the same - Google Patents

Semiconductor light-emitting device and apparatus including the same Download PDF

Info

Publication number
JP2016181674A
JP2016181674A JP2015237732A JP2015237732A JP2016181674A JP 2016181674 A JP2016181674 A JP 2016181674A JP 2015237732 A JP2015237732 A JP 2015237732A JP 2015237732 A JP2015237732 A JP 2015237732A JP 2016181674 A JP2016181674 A JP 2016181674A
Authority
JP
Japan
Prior art keywords
light emitting
semiconductor
semiconductor light
emitting device
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2015237732A
Other languages
Japanese (ja)
Inventor
朋浩 森下
Tomohiro Morishita
朋浩 森下
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Asahi Kasei Corp
Original Assignee
Asahi Kasei Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Asahi Kasei Corp filed Critical Asahi Kasei Corp
Publication of JP2016181674A publication Critical patent/JP2016181674A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor light-emitting device with high operation reliability while preventing the decrease in luminous efficiency.SOLUTION: The semiconductor light-emitting device includes: a semiconductor light-emitting element 10 emitting a deep UV light and including an element substrate 11 and a semiconductor stack portion 12 with a mesa structure formed by stacking an n-type semiconductor layer 121, a light-emitting layer 122, and a p-type semiconductor layer 123 on the element substrate 11 in this order from the element substrate 11 side; and a sub-mount substrate 20 electrically connected to the semiconductor light-emitting element 10 through a plurality of adhesion portions 22. In the plan view, the adhesion portions 22 are disposed so that the total area of the plural adhesion portions 22 on the top surface of the mesa structure of the semiconductor stack portion 12 is 10% or more and 50% or less of the light-emitting area of the light-emitting layer 122, and so that the edge of each of the adhesion portions 22 on the top surface of the mesa structure of the semiconductor stack portion 12 comes on the inside relative to the edge of the top surface of the mesa structure.SELECTED DRAWING: Figure 1

Description

本発明は半導体発光装置及びそれを備えた装置に関する。   The present invention relates to a semiconductor light emitting device and a device including the same.

従来から、半導体素子は、様々な電子機器に用いられており、発光素子や受光素子等の光学デバイス及び各種センサ等に応用されている。例えば、発光素子に着目すると、発光波長が320nm以下の紫外領域(以下、UVBという。)や発光波長が280nm以下の紫外領域(以下、UVCという。)の半導体発光素子の開発が期待されている。
UVCの半導体発光素子は、サファイア基板や窒化アルミニウム(AlN)基板等の基板上に、n型半導体層と、発光層と、p型半導体層とが、基板側からこの順に積層された構造となっている。紫外線半導体発光素子では、光取出し効率の観点から、基板側から光を取り出す形態をとることが多い。
Conventionally, semiconductor elements have been used in various electronic devices and applied to optical devices such as light emitting elements and light receiving elements, various sensors, and the like. For example, when attention is paid to a light emitting element, development of a semiconductor light emitting element in an ultraviolet region (hereinafter referred to as UVB) having an emission wavelength of 320 nm or less and an ultraviolet region (hereinafter referred to as UVC) having an emission wavelength of 280 nm or less is expected. .
The UVC semiconductor light-emitting element has a structure in which an n-type semiconductor layer, a light-emitting layer, and a p-type semiconductor layer are stacked in this order from the substrate side on a substrate such as a sapphire substrate or an aluminum nitride (AlN) substrate. ing. Ultraviolet semiconductor light emitting elements often take the form of extracting light from the substrate side from the viewpoint of light extraction efficiency.

ところで、高強度の発光素子では、電流印加時に発生する熱の放熱が重要である。特に紫外線半導体発光素子では発光効率が約1%と非常に低いため、放熱が不十分であると発光素子の劣化が早いという問題がある。この問題に対して、例えば特許文献1には、発光素子半導体層を基板から剥離し、放熱性の高い支持基板に接着することが提案されている。   By the way, in a high-intensity light-emitting element, it is important to dissipate heat generated when a current is applied. In particular, an ultraviolet semiconductor light emitting device has a very low luminous efficiency of about 1%, and therefore there is a problem that the light emitting device is quickly deteriorated if heat radiation is insufficient. For this problem, for example, Patent Document 1 proposes that the light-emitting element semiconductor layer is peeled from the substrate and bonded to a support substrate having high heat dissipation.

特開2007−81312号公報JP 2007-83112 A

特許文献1記載の半導体発光素子では、放熱性を向上させるため、熱伝導性の低い基板から発光素子を剥離し、熱伝導性の高い基板に接着している。しかしながら、特許文献1記載の発明のように発光素子を基板から剥離する場合、発光素子の作製手順が複雑となり、収率低下の要因となったり、剥離する際のダメージにより発光効率が低下したりする可能性がある。また発光素子が不具合なく長時間動作するためには、高い放熱性を実現して熱の影響を除去することに加え、外的な振動に対しても耐え得るように発光素子と支持基板とが接着されている必要もある。
本発明は、このような問題に鑑みてなされたもので、その目的とするところは、発光効率の低下を防ぎながら、動作信頼性の高い半導体発光装置及びそれを備えた装置を提供することを目的としている。
In the semiconductor light emitting device described in Patent Document 1, in order to improve heat dissipation, the light emitting device is peeled off from a substrate having low thermal conductivity and bonded to a substrate having high thermal conductivity. However, when the light-emitting element is peeled off from the substrate as in the invention described in Patent Document 1, the manufacturing procedure of the light-emitting element is complicated, which may cause a decrease in yield, or light emission efficiency may be reduced due to damage at the time of peeling. there's a possibility that. In addition, in order for the light-emitting element to operate for a long time without any trouble, in addition to realizing high heat dissipation and removing the influence of heat, the light-emitting element and the support substrate must be able to withstand external vibration. It must also be glued.
The present invention has been made in view of such problems, and an object of the present invention is to provide a semiconductor light emitting device with high operational reliability and a device including the same while preventing a decrease in light emission efficiency. It is aimed.

本発明の一態様による半導体発光装置は、素子基板と、当該素子基板側からn型半導体層、発光層及びp型半導体層がこの順に前記素子基板上に積層されてなるメサ型構造を有する半導体積層部とを備えた深紫外領域の光を発光する半導体発光素子と、複数の接着部を介して前記半導体発光素子と電気的に接続されたサブマウント基板と、を備え、平面視で、前記メサ型構造の上面に配置された前記複数の接着部の総面積が、前記発光層の発光面積の10%以上50%以下であり、且つ前記メサ型構造の上面に配置された前記接着部各々の縁が、前記メサ型構造の上面の縁よりも内側であることを特徴としている。
また、本発明の他の態様に係る装置は、上記態様の半導体発光装置を備えることを特徴としている。
A semiconductor light-emitting device according to one embodiment of the present invention includes a semiconductor substrate having a mesa structure in which an element substrate and an n-type semiconductor layer, a light-emitting layer, and a p-type semiconductor layer are stacked in this order from the element substrate side. A semiconductor light-emitting element that emits light in the deep ultraviolet region including a stacked portion, and a submount substrate that is electrically connected to the semiconductor light-emitting element through a plurality of adhesive portions. The total area of the plurality of adhesive portions arranged on the upper surface of the mesa structure is 10% to 50% of the light emitting area of the light emitting layer, and each of the adhesive portions arranged on the upper surface of the mesa structure Is characterized in that the edge is inside the edge of the top surface of the mesa structure.
In addition, an apparatus according to another aspect of the present invention is characterized by including the semiconductor light emitting device according to the above aspect.

本発明の一態様によれば、発光効率の低下を防止し、動作信頼性の高い半導体発光装置を得ることができ、すなわち長期信頼性に優れた半導体発光装置を実現することができる。   According to one embodiment of the present invention, a reduction in light emission efficiency can be prevented and a semiconductor light emitting device with high operation reliability can be obtained, that is, a semiconductor light emitting device with excellent long-term reliability can be realized.

本発明の一実施形態における半導体発光装置の一例を示す模式図である。It is a schematic diagram which shows an example of the semiconductor light-emitting device in one Embodiment of this invention. 本発明の一実施形態における半導体発光装置に含まれる半導体発光素子の一例を示す模式図である。It is a mimetic diagram showing an example of a semiconductor light emitting element contained in a semiconductor light emitting device in one embodiment of the present invention.

以下の詳細な説明では、本発明の実施形態の完全な理解を提供するように多くの特定の具体的な構成について記載されている。しかしながら、このような特定の具体的な構成に限定されることなく他の実施態様が実施できることは明らかであろう。また、以下の実施形態は、特許請求の範囲に係る発明を限定するものではなく、実施形態で説明されている特徴的な構成の組み合わせの全てを含むものである。   In the following detailed description, numerous specific specific configurations are described to provide a thorough understanding of embodiments of the invention. However, it will be apparent that other embodiments may be practiced without limitation to such specific specific configurations. Further, the following embodiments do not limit the invention according to the claims, but include all combinations of characteristic configurations described in the embodiments.

以下、図面を参照して本発明の実施形態を説明する。
本発明の一実施形態における半導体発光装置は、素子基板と、この素子基板側からn型半導体層、発光層及びp型半導体層がこの順に素子基板上に積層されてなるメサ型構造を有する半導体積層部とを備えた、深紫外領域の光を発光する半導体発光素子と、複数の接着部を介して半導体発光素子と電気的に接続されたサブマウント基板と、を備える。そして、平面視で、メサ型構造の上面に配置された複数の接着部の総面積が、発光層の発光面積の10%以上50%以下であり、且つメサ型構造の上面に配置された接着部各々の縁が、メサ型構造の上面の縁よりも内側となっている。
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
A semiconductor light-emitting device according to an embodiment of the present invention includes an element substrate and a semiconductor having a mesa structure in which an n-type semiconductor layer, a light-emitting layer, and a p-type semiconductor layer are stacked on the element substrate in this order from the element substrate side. A semiconductor light-emitting element that emits light in the deep ultraviolet region, and a submount substrate that is electrically connected to the semiconductor light-emitting element through a plurality of adhesive portions. The total area of the plurality of bonding portions arranged on the top surface of the mesa structure in plan view is 10% or more and 50% or less of the light emitting area of the light emitting layer, and the bonding arranged on the top surface of the mesa structure. The edge of each part is inside the edge of the upper surface of the mesa structure.

平面視で、メサ型構造の上面に配置された接着部の総面積が、発光層の発光面積の10%以上50%以下であり、且つメサ型構造の上面に配置された接着部の各々の縁が、半導体積層部のメサ型構造の上面の縁よりも内側となるように半導体積層部及び複数の接着部のレイアウトを設計することにより、発光効率の低下を防止すると共に、接着性の高い半導体発光装置を得ることができる。
次に、本発明の一実施形態の半導体発光装置及び各構成要件について説明する。なお各構成要件の特徴は、それぞれ独立して、または組み合わせて適用することが可能である。
In plan view, the total area of the bonding portions arranged on the top surface of the mesa structure is 10% to 50% of the light emitting area of the light emitting layer, and each of the bonding portions arranged on the top surface of the mesa structure By designing the layout of the semiconductor stacked portion and the plurality of bonding portions so that the edge is inside the edge of the upper surface of the mesa structure of the semiconductor stacked portion, the light emitting efficiency is prevented from being lowered and the adhesive property is high. A semiconductor light emitting device can be obtained.
Next, the semiconductor light-emitting device and each component of the embodiment of the present invention will be described. Note that the features of each component can be applied independently or in combination.

<半導体発光装置>
図1は、本発明の一実施形態における半導体発光装置100の一例を示す模式図であって、図1(a)は平面図、図1(b)は図1(a)のA−A′断面図である。なお、図1(a)の平面図では、図1(b)中のベース部21を省略している。
半導体発光装置100は、図1に示すように、半導体発光素子10とサブマウント基板20とを備える。
<Semiconductor light emitting device>
1A and 1B are schematic views showing an example of a semiconductor light emitting device 100 according to an embodiment of the present invention. FIG. 1A is a plan view, and FIG. 1B is an AA ′ line in FIG. It is sectional drawing. In addition, in the top view of Fig.1 (a), the base part 21 in FIG.1 (b) is abbreviate | omitted.
As shown in FIG. 1, the semiconductor light emitting device 100 includes a semiconductor light emitting element 10 and a submount substrate 20.

図2は、本発明の一実施形態における半導体発光素子10の一例を示す模式図である。図2において、図2(a)は平面図、図2(b)は、図2(a)のA−A′断面図である。
本発明の一実施形態における半導体発光素子10は、素子基板11と、素子基板11上に形成されたメサ型構造の半導体積層部12とを備える。
FIG. 2 is a schematic view showing an example of the semiconductor light emitting device 10 in one embodiment of the present invention. 2A is a plan view, and FIG. 2B is a cross-sectional view taken along the line AA ′ of FIG. 2A.
A semiconductor light emitting device 10 according to an embodiment of the present invention includes an element substrate 11 and a semiconductor laminated portion 12 having a mesa structure formed on the element substrate 11.

半導体積層部12は、n型半導体層121、発光層122、及びp型半導体層123が、この順に素子基板11側から積層されてなる。半導体積層部12は、素子基板11上に積層されたn型半導体層121、発光層122、及びp型半導体層123からなる積層構造を、図2(a)に示すように、平面視で一辺が開放された矩形状にn型半導体層121の一部を残してエッチングすることにより形成される。半導体積層部12のA−A′断面は、図2(b)に示すようにメサ形状となる。   The semiconductor stacked portion 12 is formed by stacking an n-type semiconductor layer 121, a light emitting layer 122, and a p-type semiconductor layer 123 in this order from the element substrate 11 side. As shown in FIG. 2A, the semiconductor laminated portion 12 has a laminated structure composed of an n-type semiconductor layer 121, a light emitting layer 122, and a p-type semiconductor layer 123 laminated on the element substrate 11. Is formed by etching while leaving a part of the n-type semiconductor layer 121 in a rectangular shape with an opening. The cross section AA ′ of the semiconductor laminated portion 12 has a mesa shape as shown in FIG.

半導体発光素子10は、さらに、n型半導体層121上に形成される第一電極部131と、p型半導体層123上に形成される第二電極部132とを含む電極部13を備える。
電極部13は、後述の、サブマウント基板20の接着部22と接する領域にパッド電極部をさらに備えていてもよい。
半導体積層部12のp型半導体層123上に形成される第二電極部132は、図2(a)に示すように、半導体積層部12の形状に沿って一辺が開放された矩形状に形成される。
The semiconductor light emitting device 10 further includes an electrode part 13 including a first electrode part 131 formed on the n-type semiconductor layer 121 and a second electrode part 132 formed on the p-type semiconductor layer 123.
The electrode unit 13 may further include a pad electrode unit in a region in contact with the bonding unit 22 of the submount substrate 20 described later.
The second electrode portion 132 formed on the p-type semiconductor layer 123 of the semiconductor stacked portion 12 is formed in a rectangular shape with one side open along the shape of the semiconductor stacked portion 12 as shown in FIG. Is done.

また、第一電極部131は、半導体積層部12の、一辺が開放された矩形の平行な2辺に相当する平行部12aと平行部12bとの間の、半導体積層部12作成時のエッチングにより一部が残されたn型半導体層121上に形成される。
一方、サブマウント基板20は、図1に示すように、半導体発光素子10の支持基板としてのベース部21と、接着部22とを備える。接着部22は、半導体積層部12の平行部12a、12b上の第二電極部132と、第一電極部131と対向する位置に複数配置され、接着部22と第一電極部131及び第二電極部132とが接合されることによって、サブマウント基板20と半導体発光素子10とが電気的に接合される。
In addition, the first electrode portion 131 is formed by etching at the time of forming the semiconductor multilayer portion 12 between the parallel portion 12a and the parallel portion 12b corresponding to two parallel sides of a rectangle with one side open of the semiconductor multilayer portion 12. It is formed on the remaining n-type semiconductor layer 121.
On the other hand, the submount substrate 20 includes a base portion 21 as a support substrate of the semiconductor light emitting element 10 and an adhesive portion 22 as shown in FIG. A plurality of adhesive portions 22 are arranged at positions facing the second electrode portion 132 and the first electrode portion 131 on the parallel portions 12a and 12b of the semiconductor stacked portion 12, and the adhesive portion 22, the first electrode portion 131, and the second electrode portion By joining the electrode part 132, the submount substrate 20 and the semiconductor light emitting element 10 are electrically joined.

<半導体発光素子>
(素子基板)
本発明の一実施形態の半導体発光素子10における素子基板11としては、サファイア基板、窒化アルミニウム基板(AlN基板)等が採用可能である。本発明の一実施形態では、信頼性向上のため転位密度が少ない基板等が採用される。素子基板11として、サファイア基板等、異種基板を用いる場合には、本発明の一実施形態では、ラテラルオーバー成長法やアンモニアパルス法等、よく知られた方法によってAlNバッファ層が作製され転位密度の低減が図られる。
<Semiconductor light emitting device>
(Element board)
As the element substrate 11 in the semiconductor light emitting element 10 of one embodiment of the present invention, a sapphire substrate, an aluminum nitride substrate (AlN substrate) or the like can be adopted. In one embodiment of the present invention, a substrate having a low dislocation density is employed to improve reliability. When a heterogeneous substrate such as a sapphire substrate is used as the element substrate 11, in one embodiment of the present invention, an AlN buffer layer is formed by a well-known method such as a lateral overgrowth method or an ammonia pulse method, and the dislocation density is increased. Reduction is achieved.

(半導体積層部)
本発明の一実施形態の半導体発光素子10におけるメサ型構造の半導体積層部12は、少なくとも、n型半導体層121、発光層122、及びp型半導体層123を含んでいればよく、これら以外の層を備えていてもよい。
例えば、発光層122とn型半導体層121との間、又は発光層122とp型半導体層123との間の、いずれか一方、又は両方の層間に、電子又は正孔をブロックするための機能層が備えられていてもよい。また、サブマウント基板20とのオーミック接合性を向上させる観点から、半導体積層部12は、高濃度に不純物がドーピングされたコンタクト層を備えていてもよい。
(Semiconductor stacking part)
The mesa structure semiconductor stacked portion 12 in the semiconductor light emitting device 10 according to the embodiment of the present invention only needs to include at least the n type semiconductor layer 121, the light emitting layer 122, and the p type semiconductor layer 123. A layer may be provided.
For example, a function for blocking electrons or holes between one or both of the layers between the light-emitting layer 122 and the n-type semiconductor layer 121 or between the light-emitting layer 122 and the p-type semiconductor layer 123. A layer may be provided. In addition, from the viewpoint of improving ohmic contact with the submount substrate 20, the semiconductor stacked portion 12 may include a contact layer doped with impurities at a high concentration.

また、半導体積層部12の形状は特に制限されないが、サブマウント基板20と容易に電気的に接続し、且つ発光した光を素子基板11側から外部に取り出す観点から、本発明の一実施形態では、半導体積層部12は、断面視で、一段又は多段のメサ型構造に形成される。メサ型構造であることにより、いわゆるフリップチップの形式でサブマウント基板20と半導体発光素子10とを電気的に接続することが可能である。断面視で、半導体積層部12の形状がメサ型構造である場合、平面視での半導体積層部12の形状としては、矩形状、円又は楕円状、多角形状、及びそれらの組み合わせからなる形状を採用可能である。   In addition, the shape of the semiconductor laminated portion 12 is not particularly limited, but from the viewpoint of easily electrically connecting to the submount substrate 20 and taking out emitted light from the element substrate 11 side, according to an embodiment of the present invention. The semiconductor stacked portion 12 is formed in a single-stage or multi-stage mesa structure in cross-sectional view. Due to the mesa structure, it is possible to electrically connect the submount substrate 20 and the semiconductor light emitting element 10 in a so-called flip chip format. When the shape of the semiconductor stacked portion 12 is a mesa structure in a cross-sectional view, the shape of the semiconductor stacked portion 12 in a plan view is a rectangular shape, a circular or elliptical shape, a polygonal shape, and a combination thereof. It can be adopted.

半導体積層部12は、例えば、MOCVD(Metal Organic Chemical Vapor Deposition:有機金属気相成長)法により形成することが可能である。半導体積層部12をメサ型構造にするためには、上述したMOCVD法等により半導体積層部12を構成する薄膜層を形成した後に、所望の領域をエッチングすることで実現可能である。
外部から発光層122に効率的に電力を印加する観点から、本発明の一実施形態における半導体積層部12はn型半導体層121と、p型半導体層123とのうちのいずれか一方又は両方に、電気的に接続される第一電極部131及び第二電極部132を備えている。
The semiconductor stacked portion 12 can be formed by, for example, MOCVD (Metal Organic Chemical Vapor Deposition) method. The semiconductor laminated portion 12 can be realized in a mesa structure by etching a desired region after forming the thin film layer constituting the semiconductor laminated portion 12 by the above-described MOCVD method or the like.
From the viewpoint of efficiently applying power to the light emitting layer 122 from the outside, the semiconductor stacked portion 12 in one embodiment of the present invention is applied to one or both of the n-type semiconductor layer 121 and the p-type semiconductor layer 123. The first electrode part 131 and the second electrode part 132 that are electrically connected are provided.

n型半導体層121上に形成される第一電極部131としては、本発明の一実施形態では、チタンTi、アルミウムAl、ニッケルni、及び金Au等のうちのいずれか複数を積層した積層体が用いられる。p型半導体層123上に形成される第二電極部132としては、本発明の一実施形態では、ニッケルNiと金Auとをp型半導体層123側からこの順に積層した積層体が用いられる。また、コンタクト特性向上の観点から、本発明の一実施形態では、半導体発光素子10は、第一電極部131又は第二電極部132となる電極部13形成用の材料を積層した後に窒素雰囲気中又は酸素雰囲気中で、500℃以上の環境下での高温アニールが行われる。
また、第一電極部131及び第二電極部132の上にさらに金Auを主成分とするパッド電極部を形成することも可能である。
As the first electrode portion 131 formed on the n-type semiconductor layer 121, in one embodiment of the present invention, a laminated body in which any one of titanium Ti, aluminum Al, nickel ni, gold Au, and the like is laminated. Is used. As the second electrode portion 132 formed on the p-type semiconductor layer 123, in one embodiment of the present invention, a stacked body in which nickel Ni and gold Au are stacked in this order from the p-type semiconductor layer 123 side is used. In addition, from the viewpoint of improving contact characteristics, in one embodiment of the present invention, the semiconductor light emitting device 10 is formed in a nitrogen atmosphere after laminating a material for forming the electrode part 13 to be the first electrode part 131 or the second electrode part 132. Alternatively, high temperature annealing is performed in an environment of 500 ° C. or higher in an oxygen atmosphere.
It is also possible to form a pad electrode portion mainly composed of gold Au on the first electrode portion 131 and the second electrode portion 132.

(n型半導体層、p型半導体層)
半導体積層部12に含まれる、n型半導体層121及びp型半導体層123は、本発明の一実施形態では、それぞれの導電型を示すInAlGa1−x−yN(0≦x+y≦1)から構成される。具体的には、n型半導体層121及びp型半導体層123は、GaN(x+y=0)、AlN(x=0、y=1)、InN(x=1、y=0)、InAlGa1−x−yN(0<x<1、0<y<1)、AlGa1−yN(x=0、0<y<1)、InGa1−xN(0<x<1、y=0)のいずれかから構成される。
素子基板11と発光層122との間に形成されるn型半導体層121、又は発光層122に積層されるp型半導体層123は、素子基板11の格子定数から発光層122の格子定数に近づくように、組成が連続的又は離散的に変化する構成になっていてもよい。
(N-type semiconductor layer, p-type semiconductor layer)
In one embodiment of the present invention, the n-type semiconductor layer 121 and the p-type semiconductor layer 123 included in the semiconductor stacked unit 12 are In x Al y Ga 1-xy N (0 ≦ x + y) indicating their respective conductivity types. ≦ 1). Specifically, the n-type semiconductor layer 121 and the p-type semiconductor layer 123 include GaN (x + y = 0), AlN (x = 0, y = 1), InN (x = 1, y = 0), In x Al y Ga 1-xy N (0 <x <1, 0 <y <1), Al y Ga 1-y N (x = 0, 0 <y <1), In x Ga 1-x N (0 <X <1, y = 0).
The n-type semiconductor layer 121 formed between the element substrate 11 and the light emitting layer 122 or the p-type semiconductor layer 123 stacked on the light emitting layer 122 approaches the lattice constant of the light emitting layer 122 from the lattice constant of the element substrate 11. As such, the composition may change continuously or discretely.

(発光層)
発光層122は、電力が印加された時に発光層122のバンドギャップに応じた光を発する。本発明の一実施形態の半導体発光装置100は、従来においては信頼性が特に問題となっていた中心発光波長が210nm以上320nm以下の紫外線を発する半導体発光素子10が用いられたとしても、十分な信頼性が確保されるため特に好ましく適用可能である。
発光層122の好ましい形態の例としては、多重量子井戸(Multi Quantum Well)構造が挙げられる。例えば、組成比が異なる(バンドギャップが異なる)AlGaN層を多数積層した多重量子井戸構造が採用可能である。
(Light emitting layer)
The light emitting layer 122 emits light corresponding to the band gap of the light emitting layer 122 when power is applied. The semiconductor light emitting device 100 according to an embodiment of the present invention is sufficient even if the semiconductor light emitting element 10 that emits ultraviolet rays having a central emission wavelength of 210 nm or more and 320 nm or less, in which reliability has been particularly a problem in the past, is used. Since reliability is ensured, it can be particularly preferably applied.
As an example of a preferable form of the light emitting layer 122, a multiple quantum well structure can be given. For example, a multiple quantum well structure in which a number of AlGaN layers having different composition ratios (different band gaps) are stacked can be employed.

(接着部)
接着部22は、ベース部21に形成された図示しない配線と電気的に接続するようにベース部21上に配置される。この接着部22は、半導体発光素子10とサブマウント基板20とを電気的に接続可能なものであれば特に制限されない。また単一の材料であってもよいし、複数の材料の混合又は積層体であってもよい。
(Adhesive part)
The bonding portion 22 is disposed on the base portion 21 so as to be electrically connected to a wiring (not shown) formed on the base portion 21. The bonding portion 22 is not particularly limited as long as it can electrically connect the semiconductor light emitting element 10 and the submount substrate 20. Moreover, a single material may be sufficient and the mixture or laminated body of several materials may be sufficient.

半導体発光素子10とサブマウント基板20とを任意に位置合わせを行いつつ強固に接着する観点から、本発明の一実施形態では、接着部22は圧力、熱、光等の外的要因により一時的に軟化し、その後硬化可能な性質を有する。
なお、図1では、接着部22は、サブマウント基板20側に設けられているが、これに限るものではない。
From the viewpoint of firmly bonding the semiconductor light emitting element 10 and the submount substrate 20 while arbitrarily aligning them, in one embodiment of the present invention, the bonding portion 22 is temporarily caused by external factors such as pressure, heat, and light. It has the property of softening and then curable.
In FIG. 1, the bonding portion 22 is provided on the submount substrate 20 side, but is not limited thereto.

接着部22として、例えば、サブマウント基板20側、すなわちベース部21に配置された金属部、具体的にはベース部21に形成された電極部や、この電極部上に形成されたパッド部やバンプ部、半田部を、接着部22として流用してもよい。また、半導体発光素子10側に配置された金属部、具体的には電極部131、132や、電極部131、132上にさらに形成された図示しないパッド部やバンプ部、半田部を、接着部22として流用してもよいし、それらを組み合わせて接着部22として流用してもよい。   As the bonding portion 22, for example, a metal portion disposed on the submount substrate 20 side, that is, the base portion 21, specifically, an electrode portion formed on the base portion 21, a pad portion formed on the electrode portion, A bump part and a solder part may be used as the bonding part 22. Further, a metal part arranged on the semiconductor light emitting element 10 side, specifically, electrode parts 131 and 132, pad parts or bump parts (not shown) further formed on the electrode parts 131 and 132, and a solder part are bonded to the bonding part. 22 may be diverted, or a combination thereof may be diverted as the adhesive portion 22.

(サブマウント基板)
サブマウント基板20は、半導体発光素子10と電気的に接続される。半導体発光装置100の放熱性向上の観点から、本発明の一実施形態では、ベース部21は、放熱性の高い材料から形成される。放熱性の高い材料としては、AlNセラミックが挙げられる。また、サブマウント基板20と半導体発光素子10とを簡易に電気的に接続する観点から、前述のように、本発明の一実施形態では、サブマウント基板20は、接着部22としてベース部21上に複数の金属部を備えている。金属部としては、金Auを含む球状又は柱状のバンプを適用することができる。
(Submount substrate)
The submount substrate 20 is electrically connected to the semiconductor light emitting element 10. From the viewpoint of improving heat dissipation of the semiconductor light emitting device 100, in one embodiment of the present invention, the base portion 21 is formed from a material having high heat dissipation. An example of a material having high heat dissipation is AlN ceramic. From the viewpoint of easily electrically connecting the submount substrate 20 and the semiconductor light emitting element 10, as described above, in one embodiment of the present invention, the submount substrate 20 is formed on the base portion 21 as the bonding portion 22. Has a plurality of metal parts. As the metal part, a spherical or columnar bump containing gold Au can be applied.

半導体発光素子10とサブマウント基板20とは、複数の接着部22を介して電気的に接続される。半導体発光素子10とサブマウント基板20とは、例えば金バンプからなる接着部22を介したフリップチップ接合で接続され、接合方法は一般によく知られた方法で実施される。例えば半導体発光素子10の第一電極部131、第二電極部132上に金ワイヤによるワイヤバンピング法で金バンプを形成する。一方サブマウント基板20側には、ベース部21上に、金メッキ或いは半田を接着部22として用意しておき、接着部22の位置合わせを行った後、フリップチップボンダーを用いて加圧しながら熱を加えて接着する。例えばベース部21上に約0.3μmの金メッキした後、φ25mmの金ワイヤで接着部22としての金バンプを作製し、この金バンプからなる接着部22を用いて、サブマウント基板20と半導体発光素子10とを接着する場合には、バンプあたり70gの加圧状態で約250℃の環境下で15秒間加熱することで良好な接着が得られる。この実例数値は一例であり、電極寸法やバンプ形成用金ワイヤ径等の各種の条件の違いにより最適値を選定すればよい。   The semiconductor light emitting element 10 and the submount substrate 20 are electrically connected via a plurality of adhesive portions 22. The semiconductor light emitting element 10 and the submount substrate 20 are connected to each other by flip-chip bonding via an adhesive portion 22 made of, for example, gold bumps, and the bonding method is generally performed by a well-known method. For example, gold bumps are formed on the first electrode portion 131 and the second electrode portion 132 of the semiconductor light emitting element 10 by a wire bumping method using a gold wire. On the other hand, on the side of the submount substrate 20, gold plating or solder is prepared as an adhesive part 22 on the base part 21, and after aligning the adhesive part 22, heat is applied while applying pressure using a flip chip bonder. In addition, adhere. For example, after gold plating of about 0.3 μm on the base portion 21, a gold bump is formed as the bonding portion 22 with a φ25 mm gold wire, and the submount substrate 20 and the semiconductor light emitting device are formed using the bonding portion 22 formed of the gold bump. When adhering to the element 10, good adhesion can be obtained by heating for 15 seconds in an environment of about 250 ° C. under a pressure of 70 g per bump. This actual numerical value is an example, and an optimal value may be selected depending on various conditions such as electrode dimensions and bump forming gold wire diameter.

また、半導体発光装置100において、接着部22は、平面視で半導体積層部12のメサ型構造の上面に配置された複数の接着部22の面積の総和、すなわち、半導体積層部12上の接着部22の総面積が、発光層122の発光面積の10%以上50%以下となるように配置される。ちなみに、図1では、平行部12a及び平行部12b上に配置された6つの接着部22の面積の総和が、接着部22の総面積となり、発光層122の発光面積の約30%となっている。   In the semiconductor light emitting device 100, the bonding portion 22 is the sum of the areas of the plurality of bonding portions 22 arranged on the upper surface of the mesa structure of the semiconductor stacked portion 12 in plan view, that is, the bonded portion on the semiconductor stacked portion 12. The total area 22 is arranged so as to be 10% or more and 50% or less of the light emitting area of the light emitting layer 122. Incidentally, in FIG. 1, the total area of the six bonding portions 22 arranged on the parallel portions 12 a and 12 b is the total area of the bonding portions 22, which is about 30% of the light emitting area of the light emitting layer 122. Yes.

また、平面視で半導体積層部12のメサ型構造の上面に配置された接着部22のそれぞれは、接着部22の縁が、メサ型構造の上面の縁よりも内側となるように配置される。つまり、接着部22の縁がメサ型構造の上面の縁よりも内側となるように接着部22を配置することによって、例えば、平行部12a上に配置される接着部22と、第一電極部131又は第一電極部131の上に配置される接着部22とが接触することを防止している。
さらに、半導体発光装置100において、接着部22の高さ、すなわち厚みは、例えば第一電極部131の上に配置される接着部22が、第二電極部132の上に配置される接着部や第二電極部132等、半導体発光素子10の意図しない部分と接触し、電気的ショート等の不良を起こさない範囲で適宜設定される。
In addition, each of the bonding portions 22 arranged on the upper surface of the mesa structure of the semiconductor stacked portion 12 in a plan view is arranged such that the edge of the bonding portion 22 is inside the edge of the upper surface of the mesa structure. . That is, by arranging the bonding portion 22 so that the edge of the bonding portion 22 is inside the edge of the upper surface of the mesa structure, for example, the bonding portion 22 disposed on the parallel portion 12a and the first electrode portion 131 or the adhesion part 22 arrange | positioned on the 1st electrode part 131 is prevented.
Furthermore, in the semiconductor light emitting device 100, the height of the bonding portion 22, that is, the thickness, is, for example, that the bonding portion 22 disposed on the first electrode portion 131 is bonded to the bonding portion 22 disposed on the second electrode portion 132. The thickness is appropriately set within a range where the second electrode portion 132 and the like are in contact with an unintended portion of the semiconductor light emitting element 10 and do not cause a failure such as an electrical short circuit.

このようにして、サブマウント基板20の接着部22と半導体発光素子10の電極部13とが電気的に接続された状態で、ベース部21内、又はベース部21に接続される電源(図示せず)から、ベース部21に形成された図示しない配線を介し、接着部22を経て、半導体発光素子10の第一電極部131、第二電極部132に電力が供給されることにより、半導体発光素子10に電力が供給されることによって、半導体発光素子10の発光層122で光が生成され、素子基板11側から外部に出力される。また、半導体発光素子10で生じた熱は、接着部22を介してベース部21側に伝導し、外部に放出される。   In this way, a power supply (not shown) is connected to the base portion 21 or to the base portion 21 in a state where the bonding portion 22 of the submount substrate 20 and the electrode portion 13 of the semiconductor light emitting element 10 are electrically connected. To the first electrode portion 131 and the second electrode portion 132 of the semiconductor light-emitting element 10 through the bonding portion 22 via the wiring (not shown) formed in the base portion 21. When power is supplied to the element 10, light is generated in the light emitting layer 122 of the semiconductor light emitting element 10 and is output to the outside from the element substrate 11 side. Further, heat generated in the semiconductor light emitting element 10 is conducted to the base portion 21 side through the bonding portion 22 and is released to the outside.

<装置>
本発明の一実施形態に係る装置は、本発明の一実施形態に係る半導体発光装置を備えるものである。
本発明の一実施形態に係る半導体発光装置は、各種の装置に適用可能である。
本発明の一実施形態に係る半導体発光装置は、紫外線ランプが用いられている既存の全ての装置に適用・置換可能である。特に、波長280nm以下の深紫外線を用いている装置に適用可能である。
本発明の一実施形態に係る半導体発光装置は、例えば、医療・ライフサイエンス分野、環境分野、産業・工業分野、生活・家電分野、農業分野、その他分野の装置に適用可能である。
<Device>
An apparatus according to an embodiment of the present invention includes a semiconductor light emitting device according to an embodiment of the present invention.
The semiconductor light emitting device according to one embodiment of the present invention can be applied to various devices.
The semiconductor light-emitting device according to an embodiment of the present invention can be applied to and replaced by all existing devices in which an ultraviolet lamp is used. In particular, the present invention can be applied to an apparatus using deep ultraviolet light having a wavelength of 280 nm or less.
The semiconductor light emitting device according to an embodiment of the present invention can be applied to, for example, devices in the medical / life science field, the environmental field, the industrial / industrial field, the life / home appliance field, the agricultural field, and other fields.

本発明の一実施形態に係る半導体発光装置は、薬品や化学物質の合成・分解装置、液体・気体・固体(容器、食品、医療機器等)殺菌装置、半導体等の洗浄装置、フィルム・ガラス・金属等の表面改質装置、半導体・フラットパネルディスプレイ(FPD)・プリント基板(PCB)・その他電子品製造用の露光装置、印刷・コーティング装置、接着・シール装置、フィルム・パターン・モックアップ等の転写・成形装置、紙幣・傷・血液・化学物質等の測定・検査装置に適用可能である。   A semiconductor light emitting device according to an embodiment of the present invention includes a chemical / chemical substance synthesis / decomposition device, a liquid / gas / solid (container, food, medical device, etc.) sterilizer, a semiconductor cleaning device, a film / glass / Surface modification equipment for metals, etc., exposure equipment for manufacturing semiconductors, flat panel displays (FPD), printed circuit boards (PCBs) and other electronic products, printing / coating equipment, adhesion / sealing equipment, films / patterns / mockups, etc. It can be applied to transfer / molding devices and measuring / inspecting devices for banknotes / scratches / blood / chemical substances.

液体殺菌装置の例としては、冷蔵庫内の自動製氷装置・製氷皿及び貯氷容器・製氷機用の給水タンク、冷凍庫、製氷機、加湿器、除湿器、ウォーターサーバの冷水タンク・温水タンク・流路配管、据置型浄水器、携帯型浄水器、給水器、給湯器、排水処理装置、ディスポーザ、便器の排水トラップ、洗濯機、透析用水殺菌モジュール、腹膜透析のコネクタ殺菌器、災害用貯水システム等が挙げられるがこの限りではない。   Examples of liquid sterilizers include automatic ice making equipment, ice trays, ice storage containers, water storage tanks for ice making machines, ice making machines, freezers, ice making machines, humidifiers, dehumidifiers, water server cold water tanks, hot water tanks, flow paths Pipes, stationary water purifiers, portable water purifiers, water heaters, water heaters, wastewater treatment devices, disposers, toilet drainage traps, washing machines, dialysis water sterilization modules, peritoneal dialysis connector sterilizers, disaster water storage systems, etc. This is not the case.

気体殺菌装置の例としては、空気清浄器、エアコンディショナー、天井扇、床面用や寝具用の掃除機、布団乾燥機、靴乾燥機、洗濯機、衣類乾燥機、室内殺菌灯、保管庫の換気システム、靴箱、タンス等が挙げられるがこの限りではない。
固体殺菌装置(表面殺菌装置を含む)の例としては、真空パック器、ベルトコンベヤ、医科用・歯科用・床屋用・美容院用のハンドツール殺菌装置、歯ブラシ、歯ブラシ入れ、箸箱、化粧ポーチ、排水溝のふた、便器の局部洗浄器、便器フタ等が挙げられるがこの限りではない。
Examples of gas sterilizers include air purifiers, air conditioners, ceiling fans, floor and bedding vacuum cleaners, futon dryers, shoe dryers, washing machines, clothes dryers, indoor sterilization lights, and storage cabinets. A ventilation system, a shoe box, a chiffon, etc. are mentioned, but not limited to this.
Examples of solid sterilizers (including surface sterilizers) include vacuum packers, belt conveyors, medical / dental / barber / beauty salon hand tool sterilizers, toothbrushes, toothbrush holders, chopstick boxes, cosmetic pouches, Examples include, but are not limited to, drainage lids, toilet bowl cleaners, toilet lids, and the like.

以下、本発明の一実施形態における半導体発光素子を、実施例及び比較例を挙げてより具体的に説明する。なお、本発明は、以下に説明する各実施例に限定されるものではない。
[実施例1]
本発明の一実施形態として、以下のような、半導体発光装置100を作製した。なお、ここでは、接着部22を半導体発光素子10側に設けた。
Hereinafter, the semiconductor light emitting device in one embodiment of the present invention will be described more specifically with reference to examples and comparative examples. In addition, this invention is not limited to each Example demonstrated below.
[Example 1]
As one embodiment of the present invention, the following semiconductor light emitting device 100 was fabricated. Here, the bonding portion 22 is provided on the semiconductor light emitting element 10 side.

素子基板11としてのAlN単結晶基板と、この素子基板11上に形成されたn型AlGaN層(n型半導体層121に対応)、多重量子井戸構造のAlGaN積層(発光層122に対応)、及びp型GaN層(p型半導体層123に対応)が素子基板11側から順に積層されたメサ型構造の半導体積層部12とを備える半導体発光装置100を作製した。また、n型AlGaN層(121)上には、20nmのチタンTi、150nmのアルミニウムAl、30nmのニッケルNi、及び50nmの金Auがこの順に積層された積層体からなるn型電極部(第一電極部131に対応)と、p型GaN層(123)上に形成された20nmのニッケルNi及び35nmの金Auとの積層体からなるp型電極部(第二電極部132に対応)とを設けた。さらに、これらn型電極部(131)及びp型電極部(132)上には、1000nmの金Auからなるパッド電極部を形成した。このパッド電極上に25mmφの金ワイヤをワイヤバンピングした金バンプ(接着部22に対応)を設けた。   An AlN single crystal substrate as the element substrate 11, an n-type AlGaN layer (corresponding to the n-type semiconductor layer 121) formed on the element substrate 11, an AlGaN stack having a multiple quantum well structure (corresponding to the light emitting layer 122), and A semiconductor light emitting device 100 including a mesa structure semiconductor laminated portion 12 in which a p-type GaN layer (corresponding to the p-type semiconductor layer 123) was laminated in order from the element substrate 11 side was produced. On the n-type AlGaN layer (121), an n-type electrode portion (first electrode) made of a laminate in which 20 nm titanium Ti, 150 nm aluminum Al, 30 nm nickel Ni, and 50 nm gold Au are laminated in this order. Electrode section 131) and a p-type electrode section (corresponding to the second electrode section 132) made of a laminate of 20 nm nickel Ni and 35 nm gold Au formed on the p-type GaN layer (123). Provided. Further, a pad electrode portion made of 1000 nm gold Au was formed on the n-type electrode portion (131) and the p-type electrode portion (132). On this pad electrode, a gold bump (corresponding to the bonding portion 22) obtained by wire bumping a gold wire of 25 mmφ was provided.

一方、サブマウント基板20側には、ベース部21上に約0.3μmの金メッキを作製した。
そして、各金バンプ(22)を70gで加圧しながら250℃で15秒間加熱することで、サブマウント基板20側の金メッキと半導体発光素子10側に形成した接着部22とを接着し、サブマウント基板20と半導体発光素子10とを接合した。
On the other hand, a gold plating of about 0.3 μm was produced on the base portion 21 on the submount substrate 20 side.
Then, each gold bump (22) is heated at 250 ° C. for 15 seconds while being pressurized with 70 g, thereby bonding the gold plating on the submount substrate 20 side and the bonding portion 22 formed on the semiconductor light emitting element 10 side to bond the submount. The substrate 20 and the semiconductor light emitting device 10 were joined.

作製された半導体発光装置100において、平面視における、発光層122の面積、すなわち半導体積層部12に電力を印加したときの発光面積と、接着部22の総面積とを比較した結果、半導体積層部12のメサ型構造の上面に配置された金バンプ(接着部22)の総面積は発光層122の発光面積の50%の割合を占めた。
得られた半導体発光装置100は、中心発光波長が270nmの紫外線を発するデバイスであった。
In the manufactured semiconductor light emitting device 100, as a result of comparing the area of the light emitting layer 122 in plan view, that is, the light emitting area when power is applied to the semiconductor stacked portion 12, and the total area of the bonding portion 22, The total area of the gold bumps (adhesive portion 22) disposed on the top surface of the twelve mesa structures accounted for 50% of the light emitting area of the light emitting layer 122.
The obtained semiconductor light emitting device 100 was a device that emits ultraviolet rays having a central emission wavelength of 270 nm.

上記のようにして得られた半導体発光装置100について、25℃の環境下で100mA連続通電にて信頼性試験を行った。この試験結果は、光出力劣化率が70%以下であった。
さらに同様の方法で得られた半導体発光装置100の素子基板11の側面に対して、Dage社製のボンドテスター「4000」で素子基板11の主面に平行な方向に毎秒20mmで外力を加えていったところ、1100gの外力を加えたところで半導体発光素子10がサブマウント基板20から剥離した。
About the semiconductor light-emitting device 100 obtained as mentioned above, the reliability test was done by 100 mA continuous electricity supply in 25 degreeC environment. As a result of this test, the light output deterioration rate was 70% or less.
Further, an external force is applied to the side surface of the element substrate 11 of the semiconductor light emitting device 100 obtained by the same method at a rate of 20 mm per second in a direction parallel to the main surface of the element substrate 11 by a Dage bond tester “4000”. As a result, the semiconductor light emitting device 10 was peeled off from the submount substrate 20 when an external force of 1100 g was applied.

[実施例2]
半導体発光素子10側に形成した接着部22としての金バンプの数を変え、半導体積層部12のメサ型構造の上面に配置される接着部22の数を変えることで、発光層122の発光面積に対する、接着部22の総面積の割合を15%に変えたこと以外は、実施例1と同じ方法で半導体発光装置100を作製した。
作製した半導体発光装置100を、実施例1と同様の方法で評価したところ、光出力劣化率が70%以下であり、560gの外力を加えたところで、半導体発光素子10がサブマウント基板20から剥離した。
[Example 2]
The light emitting area of the light emitting layer 122 is changed by changing the number of gold bumps as the bonding portions 22 formed on the semiconductor light emitting element 10 side and changing the number of bonding portions 22 arranged on the upper surface of the mesa structure of the semiconductor stacked portion 12. The semiconductor light emitting device 100 was manufactured by the same method as in Example 1 except that the ratio of the total area of the bonding portion 22 was changed to 15%.
The manufactured semiconductor light emitting device 100 was evaluated in the same manner as in Example 1. As a result, the light output deterioration rate was 70% or less, and when an external force of 560 g was applied, the semiconductor light emitting element 10 was peeled from the submount substrate 20. did.

[実施例3]
半導体発光素子10側に形成した接着部22としての金バンプの数を変え、半導体積層部12のメサ型構造の上面に配置される接着部22の数を変えることで、発光層122の発光面積に対する、接着部22の総面積の割合を10%に変えたこと以外は、実施例1と同じ方法で半導体発光装置100を作製した。
作製した半導体発光装置100を、実施例1と同様の方法で評価したところ、光出力劣化率が70%以下であり、440gの外力を加えたところで、半導体発光素子10がサブマウント基板20から剥離した。
[Example 3]
The light emitting area of the light emitting layer 122 is changed by changing the number of gold bumps as the bonding portions 22 formed on the semiconductor light emitting element 10 side and changing the number of bonding portions 22 arranged on the upper surface of the mesa structure of the semiconductor stacked portion 12. The semiconductor light emitting device 100 was manufactured by the same method as in Example 1 except that the ratio of the total area of the bonding portion 22 was changed to 10%.
The manufactured semiconductor light emitting device 100 was evaluated by the same method as in Example 1. As a result, the light output deterioration rate was 70% or less, and when the external force of 440 g was applied, the semiconductor light emitting element 10 was peeled from the submount substrate 20. did.

[比較例1]
半導体発光素子10側に形成した接着部22としての金バンプの数を変え、半導体積層部12のメサ型構造の上面に配置される接着部22の数を変えることで、発光層122の発光面積に対する、接着部22の総面積の割合を5%に変えたこと以外は、実施例1と同じ方法で半導体発光装置100を作製した。
作製した半導体発光装置100を、実施例1と同様の方法で評価したところ、光出力劣化率が50%以上であり、350gの外力を加えたところで、半導体発光素子10がサブマウント基板20から剥離した。
[Comparative Example 1]
The light emitting area of the light emitting layer 122 is changed by changing the number of gold bumps as the bonding portions 22 formed on the semiconductor light emitting element 10 side and changing the number of bonding portions 22 arranged on the upper surface of the mesa structure of the semiconductor stacked portion 12. The semiconductor light emitting device 100 was manufactured by the same method as in Example 1 except that the ratio of the total area of the bonding portion 22 to 5% was changed to 5%.
The manufactured semiconductor light emitting device 100 was evaluated by the same method as in Example 1. As a result, the light output deterioration rate was 50% or more, and when an external force of 350 g was applied, the semiconductor light emitting element 10 was peeled from the submount substrate 20. did.

[比較例2]
次に、第2の比較例について説明する。
第2の比較例では、接着部22としての金バンプ作製時の金ワイヤの直径を40mmφにしたこと以外は実施例1と同様の方法で半導体発光装置100を作製した。
作製した半導体発光装置100について通電試験をした結果、電気特性不良のため発光しなかった。半導体発光装置100を確認した結果、p型電極部(132)の縁から金バンプ(22)がはみ出て、n型電極部(131)に接触していることが原因であった。
[Comparative Example 2]
Next, a second comparative example will be described.
In the second comparative example, the semiconductor light emitting device 100 was manufactured in the same manner as in Example 1 except that the diameter of the gold wire at the time of manufacturing the gold bump as the bonding portion 22 was 40 mmφ.
As a result of conducting an energization test on the manufactured semiconductor light emitting device 100, no light was emitted due to poor electrical characteristics. As a result of checking the semiconductor light emitting device 100, the cause was that the gold bump (22) protruded from the edge of the p-type electrode portion (132) and was in contact with the n-type electrode portion (131).

以上の、実施例1〜3及び比較例1、2の評価結果から、半導体発光装置100において、平面視における、半導体積層部12のメサ構造の上面に配置される接着部22の総面積が、発光層122の発光面積の10%以上50%以下であり、且つ、半導体積層部12のメサ型構造の上面に配置された接着部22の各々の縁が、半導体積層部12のメサ型構造の上面の縁よりも内側となるように接着部22を配置することによって、信頼性の高い半導体発光装置を作製できることが確認された。
一方、接着部22の総面積を大きくするために、接着部22としての金バンプとなる金ワイヤの直径を一定以上大きくしてしまうと、接着部22としての金バンプが、半導体積層部12のメサ型構造の上面の縁からはみ出し、ショートによる電気特性不良率が高くなることが確認された。
From the evaluation results of Examples 1 to 3 and Comparative Examples 1 and 2 described above, in the semiconductor light emitting device 100, the total area of the bonding portion 22 arranged on the upper surface of the mesa structure of the semiconductor stacked portion 12 in plan view is The light emitting area of the light emitting layer 122 is not less than 10% and not more than 50%, and each edge of the bonding portion 22 arranged on the upper surface of the mesa structure of the semiconductor stacked portion 12 has the mesa structure of the semiconductor stacked portion 12. It was confirmed that a highly reliable semiconductor light emitting device can be manufactured by arranging the bonding portion 22 so as to be inside the edge of the upper surface.
On the other hand, in order to increase the total area of the bonding portion 22, if the diameter of the gold wire serving as the gold bump as the bonding portion 22 is increased to a certain level or more, the gold bump as the bonding portion 22 becomes the semiconductor laminated portion 12. It was confirmed that the rate of electrical property failure due to short-circuiting protruded from the top edge of the mesa structure.

(まとめ)
以上のように、本発明の一実施形態における半導体発光装置100は、従来の半導体発光装置と比較して、半導体発光素子10とサブマウント基板20側との間の密着力が強く、放熱性も向上することが確認できた。そのため、本発明の一実施形態における半導体発光装置100を、210nm以上320nm以下程度の深紫外線を発光する信頼性の高い発光装置として適用することができ、殺菌やバイオ分析等に好適に用いることができる。
(Summary)
As described above, the semiconductor light emitting device 100 according to the embodiment of the present invention has a strong adhesion between the semiconductor light emitting element 10 and the submount substrate 20 side and heat dissipation as compared with the conventional semiconductor light emitting device. It was confirmed that it improved. Therefore, the semiconductor light-emitting device 100 according to an embodiment of the present invention can be applied as a highly reliable light-emitting device that emits deep ultraviolet light of about 210 nm to 320 nm and is preferably used for sterilization, bioanalysis, and the like. it can.

なお、ここまで、本発明の実施形態について説明したが、本発明は上述した実施形態に限定されず、その技術的思想の範囲内において種々異なる形態にて実施されてよいことは言うまでもない。
また、本発明の範囲は、図示され記載された例示的な実施形態に限定されるものではなく、本発明が目的とするものと均等な効果をもたらす全ての実施形態をも含む。さらに、本発明の範囲は、各請求項により画される発明の特徴の組み合わせに限定されるものではなく、全ての開示されたそれぞれの特徴のうち特定の特徴のあらゆる所望する組み合わせによって画されうる。
Although the embodiments of the present invention have been described so far, it is needless to say that the present invention is not limited to the above-described embodiments, and may be implemented in various forms within the scope of the technical idea.
In addition, the scope of the present invention is not limited to the illustrated and described exemplary embodiments, and includes all embodiments that provide the same effects as those intended by the present invention. Further, the scope of the invention is not limited to the combinations of features of the invention defined by the claims, but may be defined by any desired combination of specific features among all the disclosed features. .

本発明は、フリップチップ型の半導体発光装置に利用可能であり、例えば、殺菌やバイオ分析等に好適に用いられる。   The present invention can be used for a flip-chip type semiconductor light emitting device, and is suitably used for, for example, sterilization and bioanalysis.

10 半導体発光素子
11 素子基板
12 半導体積層部
121 n型半導体層
122 発光層
123 p型半導体層
13 電極部
131 第一電極部
132 第二電極部
20 サブマウント基板
21 ベース部
22 接着部
100 半導体発光装置
DESCRIPTION OF SYMBOLS 10 Semiconductor light emitting element 11 Element substrate 12 Semiconductor laminated part 121 N type semiconductor layer 122 Light emitting layer 123 P type semiconductor layer 13 Electrode part 131 First electrode part 132 Second electrode part 20 Submount substrate 21 Base part 22 Adhesion part 100 Semiconductor light emission apparatus

Claims (5)

素子基板と、当該素子基板側からn型半導体層、発光層及びp型半導体層がこの順に前記素子基板上に積層されてなるメサ型構造を有する半導体積層部とを備えた、深紫外領域の光を発光する半導体発光素子と、
複数の接着部を介して前記半導体発光素子と電気的に接続されたサブマウント基板と、
を備え、
平面視で、前記メサ型構造の上面に配置された前記複数の接着部の総面積が、前記発光層の発光面積の10%以上50%以下であり、且つ前記メサ型構造の上面に配置された前記接着部各々の縁が、前記メサ型構造の上面の縁よりも内側である半導体発光装置。
An element substrate, and a semiconductor laminated portion having a mesa structure in which an n-type semiconductor layer, a light emitting layer, and a p-type semiconductor layer are laminated on the element substrate in this order from the element substrate side. A semiconductor light emitting device that emits light;
A submount substrate electrically connected to the semiconductor light emitting element through a plurality of adhesive portions;
With
In plan view, the total area of the plurality of bonding portions arranged on the upper surface of the mesa structure is 10% or more and 50% or less of the light emitting area of the light emitting layer, and is arranged on the upper surface of the mesa structure. In addition, the semiconductor light emitting device in which an edge of each of the bonding portions is inside an edge of an upper surface of the mesa structure.
前記半導体発光素子から発光される光の中心発光波長が210nm以上320nm以下である請求項1に記載の半導体発光装置。   2. The semiconductor light emitting device according to claim 1, wherein a central emission wavelength of light emitted from the semiconductor light emitting element is 210 nm or more and 320 nm or less. 前記素子基板がAlN単結晶基板又はサファイア基板を含む請求項1又は請求項2に記載の半導体発光装置。   The semiconductor light emitting device according to claim 1, wherein the element substrate includes an AlN single crystal substrate or a sapphire substrate. 前記半導体積層部が、InAlGa1−x−yN(0≦x+y≦1)層を含む請求項1から請求項3のいずれか一項に記載の半導体発光装置。 4. The semiconductor light emitting device according to claim 1, wherein the semiconductor stacked portion includes an In x Al y Ga 1-xy N (0 ≦ x + y ≦ 1) layer. 5. 請求項1から請求項4のいずれか1項に記載の半導体発光装置を備える装置。   The apparatus provided with the semiconductor light-emitting device of any one of Claims 1-4.
JP2015237732A 2015-03-24 2015-12-04 Semiconductor light-emitting device and apparatus including the same Pending JP2016181674A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2015060756 2015-03-24
JP2015060756 2015-03-24

Publications (1)

Publication Number Publication Date
JP2016181674A true JP2016181674A (en) 2016-10-13

Family

ID=57131813

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2015237732A Pending JP2016181674A (en) 2015-03-24 2015-12-04 Semiconductor light-emitting device and apparatus including the same

Country Status (1)

Country Link
JP (1) JP2016181674A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109560178A (en) * 2017-09-27 2019-04-02 旭化成株式会社 Semiconductor light-emitting apparatus and luminescence-utraviolet module
US10784407B2 (en) 2018-04-23 2020-09-22 Asahi Kasei Kabushiki Kaisha Nitride semiconductor light emitting element and nitride semiconductor light emitting device
JP7185105B1 (en) * 2021-07-16 2022-12-06 シチズン電子株式会社 light emitting device
WO2023286846A1 (en) * 2021-07-16 2023-01-19 シチズン電子株式会社 Light-emitting device

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001203386A (en) * 1999-12-22 2001-07-27 Lumileds Lighting Us Llc Group iii nitride ligh-emitting device with raised light generation capability
US20040061123A1 (en) * 2002-09-27 2004-04-01 Emcore Corporation Optimized contact design for flip-chip LED
JP2006041133A (en) * 2004-07-26 2006-02-09 Matsushita Electric Ind Co Ltd Light emitting device
JP2011258675A (en) * 2010-06-07 2011-12-22 Toshiba Corp Optical semiconductor device
JP2013530537A (en) * 2010-06-18 2013-07-25 センサー エレクトロニック テクノロジー インコーポレイテッド Deep ultraviolet light emitting diode
JP2013222925A (en) * 2012-04-19 2013-10-28 Asahi Kasei Corp Led substrate and method for producing the same
JP2013243241A (en) * 2012-05-21 2013-12-05 Nichia Chem Ind Ltd Semiconductor light-emitting element
JP2014154597A (en) * 2013-02-05 2014-08-25 Tokuyama Corp Nitride semiconductor light-emitting element
JP2014160748A (en) * 2013-02-20 2014-09-04 Stanley Electric Co Ltd Flip-chip semiconductor element, semiconductor device and manufacturing methods thereof
KR20140118042A (en) * 2013-03-28 2014-10-08 서울바이오시스 주식회사 Light emitting diode and lighting device employing the same

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001203386A (en) * 1999-12-22 2001-07-27 Lumileds Lighting Us Llc Group iii nitride ligh-emitting device with raised light generation capability
US20040061123A1 (en) * 2002-09-27 2004-04-01 Emcore Corporation Optimized contact design for flip-chip LED
JP2006041133A (en) * 2004-07-26 2006-02-09 Matsushita Electric Ind Co Ltd Light emitting device
JP2011258675A (en) * 2010-06-07 2011-12-22 Toshiba Corp Optical semiconductor device
JP2013530537A (en) * 2010-06-18 2013-07-25 センサー エレクトロニック テクノロジー インコーポレイテッド Deep ultraviolet light emitting diode
JP2013222925A (en) * 2012-04-19 2013-10-28 Asahi Kasei Corp Led substrate and method for producing the same
JP2013243241A (en) * 2012-05-21 2013-12-05 Nichia Chem Ind Ltd Semiconductor light-emitting element
JP2014154597A (en) * 2013-02-05 2014-08-25 Tokuyama Corp Nitride semiconductor light-emitting element
JP2014160748A (en) * 2013-02-20 2014-09-04 Stanley Electric Co Ltd Flip-chip semiconductor element, semiconductor device and manufacturing methods thereof
KR20140118042A (en) * 2013-03-28 2014-10-08 서울바이오시스 주식회사 Light emitting diode and lighting device employing the same

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109560178A (en) * 2017-09-27 2019-04-02 旭化成株式会社 Semiconductor light-emitting apparatus and luminescence-utraviolet module
JP2019062099A (en) * 2017-09-27 2019-04-18 旭化成株式会社 Semiconductor light emitting device and ultraviolet light emitting module
US10868218B2 (en) 2017-09-27 2020-12-15 Asahi Kasei Kabushiki Kaisha Semiconductor light emitting apparatus and ultraviolet light emitting module
US10784407B2 (en) 2018-04-23 2020-09-22 Asahi Kasei Kabushiki Kaisha Nitride semiconductor light emitting element and nitride semiconductor light emitting device
JP7185105B1 (en) * 2021-07-16 2022-12-06 シチズン電子株式会社 light emitting device
WO2023286846A1 (en) * 2021-07-16 2023-01-19 シチズン電子株式会社 Light-emitting device

Similar Documents

Publication Publication Date Title
JP6758044B2 (en) Light emitting element and lighting system
US8338837B2 (en) Light emitting device
JP7003058B2 (en) Light emitting element, light emitting element package and light emitting module
KR101303168B1 (en) Conneted body with semiconductor light emitting regions
JP6294031B2 (en) Light emitting element
TWI495084B (en) Light-emitting device
US10381509B2 (en) Light emitting device and light unit having same
JP2016181674A (en) Semiconductor light-emitting device and apparatus including the same
US10347789B2 (en) Light emitting device and light emitting device package having same
US10199530B2 (en) Ultraviolet light-emitting device and light unit comprising same
US9741903B2 (en) Light-emitting device and light emitting device package having the same
US10868218B2 (en) Semiconductor light emitting apparatus and ultraviolet light emitting module
CN205645804U (en) Emitting diode filament and have its emitting diode lamp
JP2022051304A (en) Ultraviolet light-emitting element
US10236417B2 (en) Light-emitting element
US11309456B2 (en) Nitride semiconductor light emitting device, ultraviolet light emitting module
KR102355604B1 (en) Light emitting device and light unit having thereof
JP2018125457A (en) Nitride semiconductor light-emitting device, and nitride semiconductor light-emitting module
US20230141035A1 (en) Ultraviolet (uv) light source and method of manufacturing the same
JP2016111364A (en) Light-emitting device and apparatus having the light-emitting device
JP2019192731A (en) Nitride semiconductor device and method for manufacturing nitride semiconductor device
JP2007042985A (en) Gallium-nitride-based compound semiconductor light-emitting device and packaging body thereof
JP2016171303A (en) Uv light-emitting device, device having the same, and method for manufacturing uv light-emitting device
JP2018195709A (en) Semiconductor device and uv light-emitting module
JP2021153123A (en) Ultraviolet light-emitting element and ultraviolet light-emitting device

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20181108

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20190828

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20190910

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20191031

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20200324

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20200929