JP2018195709A - Semiconductor device and uv light-emitting module - Google Patents

Abstract

To reduce the risk of short circuit of an electrode provided on a semiconductor chip and a wiring line of a package substrate, and to simplify manufacturing steps.SOLUTION: A semiconductor device comprises a semiconductor chip 10 having: a base body 11 having a first wiring line 2 formed on one face of a package substrate 1, and a second wiring line 3 isolated from the first wiring line 2; a first nitride semiconductor layer 5, a nitride semiconductor active layer 6 and a second nitride semiconductor layer 7 which are formed on a face of a semiconductor substrate 4 on the side of the base body 11 in turn; and a first electrode 8 provided in a part of a region on the first nitride semiconductor layer 5, where the nitride semiconductor active layer 6 is not formed; and a second electrode 9 formed on the second nitride semiconductor layer 7. At least a part of the first electrode 8 is joined to the first wiring line 2; at least a part of the second electrode 9 is joined to the second wiring line 3; and the first electrode 8 is provided in a location overlapping with a region except a region where the second wiring line 3 is formed when viewed from the side of the package substrate 1.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor device and an ultraviolet light emitting module.

  Semiconductor devices are used in various electronic devices and are applied to arithmetic processing devices, optical devices such as light emitting devices and light receiving devices, and the like. In particular, a semiconductor device including a semiconductor chip using a nitride semiconductor layer as a material controls a band gap by controlling the composition of the nitride semiconductor, and a light emitting device and a light receiving device ranging from a red region to a deep ultraviolet region, It is applied as a power device utilizing high breakdown voltage and high responsiveness, and a device that responds at high speed. Each device using these semiconductor devices is used for various purposes such as illumination, a light source for measuring instruments, a sterilizing light source, a solar cell, various sensors, and a transistor.

  A general form of a semiconductor device using a nitride semiconductor layer as a material for a semiconductor chip includes a form in which the semiconductor chip is mounted on a circuit board having a connection portion with an external metal wire. In a semiconductor device having a flip-chip structure, which is one of the embodiments, a semiconductor chip having a p-type electrode and an n-type electrode formed on one surface and a package substrate are formed on an electrode formation surface (connection surface) of the semiconductor chip and a package. It arrange | positions so that a board | substrate may face. The p-type electrode and n-type electrode of the semiconductor chip and the package substrate are connected by a connection medium formed of a conductive material such as a gold ball. When the semiconductor device is a light emitting device, light is emitted from both one surface (connection surface) and the other surface of the semiconductor chip. The p-type electrode and the n-type electrode are electrically joined to the corresponding positive electrode metal wire and negative electrode metal wire on the package substrate, respectively, and play a role of flowing current to the semiconductor chip by applying voltage from the outside. .

  In order to increase the energy conversion efficiency of the semiconductor device, the arrangement of the p-type electrode and the n-type electrode on the semiconductor chip is very important. When the semiconductor device is a light-emitting device, in order to increase its luminous efficiency, carrier injection efficiency for transporting electrons and holes from the outside to the active layer, internal quantum efficiency for converting electricity into light in the active layer, internal It is necessary to improve the light extraction efficiency for extracting the light generated in step 3 to the outside and the external quantum efficiency expressed by the product of these three efficiencies. In order to improve the external quantum efficiency, the arrangement of an n-type electrode for injecting electrons into the semiconductor layer and a p-type electrode for injecting holes into the semiconductor layer are very important.

When the current is locally concentrated, a phenomenon called “current droop” in which the electron injection efficiency or the internal quantum efficiency is lowered occurs, and the light emission efficiency is lowered. By arranging each electrode appropriately, uniform current density and uniform light emission density in the semiconductor light emitting device, particularly in the nitride semiconductor active layer, are realized, current droop is suppressed, and high external quantum efficiency is achieved. .
In order to pass a current from an external power source to the semiconductor chip, it is necessary to arrange and bond wirings in opposing regions on the package substrate in accordance with the arrangement of the p-type electrode and the n-type electrode of the semiconductor chip.
For example, Patent Document 1 discloses a structure in which a first electrode wiring and a second electrode wiring of a semiconductor chip and an electrode wiring of an opposing package substrate are arranged to face each other via a protective insulating film.

Japanese Patent No. 5985782

  The semiconductor device having the flip chip structure described in Patent Document 1 reduces the risk of a short circuit between the first electrode and the second electrode of the semiconductor chip and the wiring of the package substrate by using an insulating protective film. doing. However, in the semiconductor device described in Patent Document 1, the risk of short-circuiting between the wirings of the package substrate cannot be excluded due to dielectric breakdown of the insulating protective film. Further, the semiconductor device described in Patent Document 1 has a problem that the manufacturing process is complicated, and is not suitable for mass production. Therefore, in the conventional semiconductor device, it is difficult to reduce both the risk of short circuit between the electrode provided on the semiconductor chip and the wiring of the package substrate and the simplification of the manufacturing process.

  The present invention has been made in view of such a problem, and can reduce both the risk of short circuit between the electrode provided on the semiconductor chip and the wiring of the package substrate and the simplification of the manufacturing process. An object of the present invention is to provide a semiconductor device and an ultraviolet light emitting module.

  In order to achieve the above object, a semiconductor device according to an embodiment of the present invention includes a package substrate, a first wiring formed on one surface of the package substrate, and the first wiring on the one surface. A substrate having a second wiring formed insulated from the wiring; and a semiconductor substrate; a first nitride semiconductor layer of a first conductivity type formed on a surface of the semiconductor substrate on the substrate side; and A nitride semiconductor active layer formed on a portion of the first nitride semiconductor layer, a second conductivity type second nitride semiconductor layer formed on the nitride semiconductor active layer, and the first nitride A semiconductor chip having a first electrode provided in a part of a region on the semiconductor layer where the nitride semiconductor active layer is not formed, and a second electrode formed on the second nitride semiconductor layer; And at least a part of the first electrode includes the first wiring Bonded, at least a part of the second electrode is bonded to the second wiring, and the first electrode is not provided on a region facing the second wiring of the semiconductor chip. It is said.

  An ultraviolet light emitting module according to another embodiment of the present invention includes the semiconductor device according to the above embodiment.

  According to one embodiment of the present invention, it is possible to reduce both the risk of short circuit between the electrode provided on the semiconductor chip and the wiring of the package substrate and the simplification of the manufacturing process.

It is a top view showing an example of a semiconductor device concerning a first embodiment of the present invention. It is AA 'sectional drawing of FIG. It is explanatory drawing for demonstrating the effect of the semiconductor device which concerns on one Embodiment of this invention. It is a top view which shows an example of the semiconductor device which concerns on 2nd embodiment of this invention. It is AA 'sectional drawing of FIG. It is a top view which shows an example of the semiconductor device which concerns on 3rd embodiment of this invention. It is AA 'sectional drawing of FIG.

In the following detailed description, numerous specific specific configurations are described to provide a thorough understanding of embodiments of the invention. However, it is apparent that other embodiments can be implemented without being limited to such specific specific configurations. Further, the following embodiments do not limit the invention according to the claims, but include all combinations of characteristic configurations described in the embodiments.
Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the following description of the drawings, the same portions are denoted by the same reference numerals. However, the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones.

[First embodiment]
FIG. 1 is a plan view showing an example of a semiconductor device according to the first embodiment of the present invention. FIG. 2 is a cross-sectional view taken along the line AA ′ of FIG. In FIG. 1, a boundary line inside the device that is not partially exposed to the outside is also shown so that the overlapping of each layer becomes clear. 2 is an image diagram and does not necessarily represent the same distance and scale as the plan view of FIG.
As shown in FIGS. 1 and 2, the semiconductor device 100 according to the first embodiment includes a semiconductor chip 10 and a base 11.

(Semiconductor chip)
The semiconductor chip 10 includes a semiconductor substrate 4, a first nitride semiconductor layer 5 that is an n-type nitride semiconductor layer, a nitride semiconductor active layer 6, and a second nitride semiconductor that is a p-type nitride semiconductor layer, for example. It has the layer 7, the 1st electrode 8 which is an n-type electrode, for example, and the 2nd electrode 9 which is a p-type electrode, for example. The semiconductor chip 10 is assumed to be an ultraviolet light emitting diode.
The first nitride semiconductor layer 5 has a thick part and a thin part formed so as to surround the thick part, and is formed on one surface of the semiconductor substrate 4. ing. The first nitride semiconductor layer 5 is, for example, an n-type AlGaN layer.
The nitride semiconductor active layer 6 is formed on the thick part of the first nitride semiconductor layer 5. That is, the nitride semiconductor active layer 6 is formed on a part of the first nitride semiconductor layer 5.

The second nitride semiconductor layer 7 is formed on the nitride semiconductor active layer 6. Thereby, the thick part of the first nitride semiconductor layer 5, the nitride semiconductor active layer 6, and the second nitride semiconductor layer 7 are made to be smaller than the thin part of the first nitride semiconductor layer 5. A protruding mesa structure 10a is also formed. In FIG. 1, the end of the mesa structure 10 a is denoted by reference numeral 15.
The first electrode 8 is formed on the bottom of the mesa structure portion 10 a, that is, on the thin portion of the first nitride semiconductor layer 5. That is, the first electrode 8 is formed on a portion of the first nitride semiconductor layer 5 where the nitride semiconductor active layer 6 is not formed.
The second electrode 9 is formed on the top of the mesa structure portion 10 a, that is, on the second nitride semiconductor layer 7.

(Substrate)
The base 11 is insulated from the first wiring 2 on the surface of the package substrate 1, the first wiring 2 formed on one surface of the package substrate 1, and the first wiring 2 of the package substrate 1. And the second wiring 3 formed in this way.
The package substrate 1 is arranged so that one surface 1a faces the surface 4a of the semiconductor substrate 4 on which the mesa structure portion 10a is formed.
On the surface 1 a of the package substrate 1, the first wiring 2 is formed at a position facing the first electrode 8 of the semiconductor chip 10, and the second wiring 3 is formed at a position facing the second electrode 9 of the semiconductor chip 10. ing.

The first wiring 2 is joined to at least a part of the first electrode 8. The second wiring 3 is joined to at least a part of the second electrode 9. The first wiring 2 and the first electrode 8, and the second wiring 3 and the second electrode 9 may be in direct contact with each other, and are joined via a conductive medium 20 as shown in FIG. May be.
Here, the second wiring 3 is not provided at a position facing the first electrode 8. Therefore, for example, when metal foreign matter is mixed in the manufacturing process of the semiconductor device 100, the possibility that the wiring on the semiconductor chip 10 side and the electrode on the base 11 side are short-circuited through the metal foreign matter can be reduced.

Further, for example, metal foreign matter is mixed in the manufacturing process of the semiconductor device 100, and in FIG. 2, it is assumed that the metal foreign matter contacts both the second wiring 3 and the first nitride semiconductor layer 5 facing the second wiring 3. However, since the contact resistance between the metal foreign matter and the first nitride semiconductor layer 5 is large, there is a possibility that a short circuit will occur between the first nitride semiconductor layer 5 and the second wiring 3 via the metal foreign matter. Can be small.
The first wiring 2 is not provided at a position facing the second electrode 9. Therefore, for example, when a metal foreign object is mixed, it is possible to suppress the formation of a short-circuit path that conducts through the path formed by the first wiring 2, the metal foreign object, and the second electrode 9.

Since the second wiring 3 has the first portion 12 which is a part of the region not facing the semiconductor chip 10 of the package substrate 1, the wiring can be connected from the outside to the second wiring 3 by wire bonding or the like.
The second wiring 3 includes a second portion 13 that is a part of a region facing the second electrode 9 of the package substrate 1 and a third portion 14 that is a region between the first portion 12 and the second portion 13. Have. As a result, as shown in FIG. 1, even in a chip in which the second electrode 9 is formed near the center of the semiconductor chip 10, the second electrode 9 can be connected to the external wiring while suppressing the risk of short-circuiting due to contamination. The wiring 3 can be extended to the outside of the semiconductor chip 10 in plan view.

  In the semiconductor chip 10 arranged so that at least a part of the third portion 14 of the second wiring 3 faces the first nitride semiconductor layer 5 in the thickness direction of the semiconductor device 100, the second wiring 3 More preferably, the first electrode 8 is not formed in a region facing the three portions 14. That is, it is preferable that the second wiring 3 and the first electrode 8 do not overlap at the third portion 14 in plan view. By doing so, it is possible to reduce the possibility that a short circuit will occur between the second wiring 3 and the first electrode 8 on the semiconductor chip 10 side through foreign matter entering from the outside of the semiconductor chip 10 after assembly. .

  As shown in FIG. 2, in the semiconductor chip 10 having the mesa structure portion 10a, the second electrode 9 is formed on the top of the mesa structure portion 10a, and the second wiring 3 connected to the second electrode 9 is shown in FIG. In the structure extended to the outside of the semiconductor chip 10 in plan view, the first electrode 8, the second electrode 9, the first wiring 2 and the second wiring 3 are arranged in the positional relationship in the first embodiment of the present invention. As a result, a high short-circuit prevention effect between the wirings 2 and 3 of the package substrate 1 and the electrodes 8 and 9 of the semiconductor chip 10 can be obtained. That is, in the structure in which the first electrode 8 is disposed so as to surround the second electrode 9 in a plan view as shown in FIG. 1, in order to connect the second electrode 9 to the outside by wire bonding or the like, the plan view Therefore, it is necessary to extend the second wiring 3 to the outside of the semiconductor chip 10. For this reason, the second wiring 3 is connected to the first portion 12 connected to the outside and the second electrode 9 by wire bonding or the like. A third portion 14 that connects the portion 13 is provided. Since there is a gap between the third portion 14 and the semiconductor chip 10, there is a possibility that foreign matter is mixed. However, when extending the second wiring 3 to the outside of the semiconductor chip 10 in a plan view, the first electrode 8, the second electrode 9, the first electrode 8, and the third electrode 14 are not overlapped with the first electrode 8 in the plan view. By arranging the one wiring 2 and the second wiring 3, it is possible to suppress a short circuit from occurring between the third portion 14 and the electrode of the semiconductor chip 10 even if a metal foreign object is mixed.

(Details of components of semiconductor devices)
Each element which comprises the semiconductor device 100 which concerns on one Embodiment of this invention is explained in full detail below.
<Semiconductor chip>
In addition to the ultraviolet light emitting diode, the semiconductor chip 10 can be applied with a light emitting element such as a laser diode, a light receiving element such as a solar cell or an optical sensor, a power conversion element such as a thin film transistor, or the like.
When the semiconductor chip 10 is an ultraviolet light emitting diode, it is difficult to use a resin as an underfill or a sealing material because it causes ultraviolet degradation. Therefore, the possibility of a short circuit due to contamination is increased. The present invention is particularly effective when the semiconductor chip is an ultraviolet light emitting diode.

<Semiconductor substrate>
The semiconductor substrate 4 of the semiconductor chip 10 is not particularly limited as long as it has a surface on which a nitride semiconductor can be formed as an upper layer. Specifically, sapphire, Si, SiC, MgO, Ga ₂ O ₃ , Al ₂ O ₃ , ZnO, GaN, InN, AlN, or a mixed crystal thereof can be given. Further, impurities may be mixed in the semiconductor substrate 4.
In particular, from the viewpoint that the lattice constant difference with the nitride semiconductor formed on one surface of the semiconductor substrate 4 is small, and that threading dislocations can be reduced by growing in a lattice matching system, and that it has high thermal conductivity. The semiconductor substrate 4 is preferably aluminum nitride (AlN).
In addition, the semiconductor substrate here means a substrate used for the purpose of forming a semiconductor layer as an upper layer, and the semiconductor substrate 4 itself may be a semiconductor, a conductor, or an insulator. Is preferably an insulator.

<First nitride layer>
The first nitride semiconductor layer 5 is a first-type conductivity (n-type) nitride semiconductor layer, and even if it is directly formed on the semiconductor substrate 4, the first nitride semiconductor layer 5 is formed on the semiconductor substrate 4. Other layers may be formed, and the first nitride semiconductor layer 5 may be formed thereon. For example, a buffer layer may be formed on the semiconductor substrate 4, the first nitride semiconductor layer 5 may be formed thereon, and the nitride semiconductor active layer 6 may be formed. In the first embodiment, the first nitride semiconductor layer 5 is n-type, but may be p-type.

The first nitride semiconductor layer 5 is not particularly limited as long as it is a nitride semiconductor such as an n-type AlGaN layer. However, from the viewpoint of realizing high energy conversion efficiency, the first nitride semiconductor layer 5 should have conductivity using an appropriate dopant. It is desirable to be a mixed crystal using two or three of AlN, GaN, and InN that can be formed.
The first nitride semiconductor layer 5 is an n-type nitride semiconductor layer or a p-type nitride semiconductor layer. In addition to nitrogen (N), a group V element other than N such as P, As, Sb, C, H , F, O, Mg, Zn, Si, or other impurities may be mixed.

In particular, when the first nitride semiconductor layer 5 is Al _x In _y Ga _z N (0 <x ≦ 1, 0 ≦ y <1, 0 ≦ z <1, x + y + z = 1), this first nitride semiconductor There is a concern that the layer 5 changes in quality due to moisture in the atmosphere or heat generation of the semiconductor device 100 and partially peels to become a foreign substance and connect the first nitride semiconductor layer 5 and the substrate 11. Therefore, in the semiconductor device 100 according to the embodiment of the present invention, in particular, the first nitride semiconductor layer 5 has Al _x In _y Ga _z N (0 <x ≦ 1, 0 ≦ y <1, 0 ≦ z <1). , X + y + z = 1), the effect is high.

<Nitride semiconductor active layer>
Even if the nitride semiconductor active layer 6 is directly formed on the first nitride semiconductor layer 5, a layer other than the nitride semiconductor active layer 6 is formed on the first nitride semiconductor layer 5, and a nitride is formed thereon. A physical semiconductor active layer 6 may be formed. Specifically, the nitride semiconductor active layer 6 may be formed on the undoped AlGaN layer formed on the first nitride semiconductor layer 5.
The nitride semiconductor active layer 6 is not particularly limited as long as it is a nitride semiconductor, but is preferably a mixed crystal of AlN, GaN, and InN from the viewpoint of realizing high energy efficiency. In addition to N, the nitride semiconductor active layer 6 may be mixed with a V group element other than N, such as P, As, Sb, and impurities such as C, H, F, O, Mg, Si. In addition, a quantum well structure or a single layer structure may be used, but it is desirable to have at least one well structure from the viewpoint of realizing high luminous efficiency.

《Second nitride semiconductor layer》
The second nitride semiconductor layer 7 is a nitride semiconductor layer of a second type conductivity type (conductivity type different from that of the first nitride semiconductor layer 5), and may be formed directly on the nitride semiconductor active layer 6. A layer other than the second nitride semiconductor layer 7 may be formed on the nitride semiconductor active layer 6, and the second nitride semiconductor layer 7 may be formed thereon. For example, an undoped AlGaN layer may be formed on the nitride semiconductor active layer 6, and the second nitride semiconductor layer 7 may be formed thereon.
The second nitride semiconductor layer 7 is not particularly limited as long as it is a nitride semiconductor, but is preferably a mixed crystal of AlN, GaN, and InN from the viewpoint of realizing high energy conversion efficiency.
The second nitride semiconductor layer 7 is an n-type nitride semiconductor layer when the first nitride semiconductor layer 5 is a p-type nitride semiconductor layer, and the first nitride semiconductor layer 5 is an n-type nitride semiconductor layer. In this case, it is a p-type nitride semiconductor layer. In addition to N, the second nitride semiconductor layer 7 is mixed with V group elements other than N such as P, As, Sb, and impurities such as C, H, F, O, Mg, Zn, and Si. Also good.

<First electrode, second electrode>
The first electrode 8 and the second electrode 9 play a role of flowing current through the first nitride semiconductor layer 5 and the second nitride semiconductor layer 7, respectively. When the first nitride semiconductor layer 5 is an n-type nitride semiconductor layer and the second nitride semiconductor layer 7 is a p-type nitride semiconductor layer, the first electrode 8 is an n-type electrode, and the second electrode 9 is a p-type. Electrode. When the first nitride semiconductor layer 5 is a p-type nitride semiconductor layer and the second nitride semiconductor layer 7 is an n-type nitride semiconductor layer, the first electrode 8 is a p-type electrode and the second electrode 9 is an n-type. Electrode.
The material and shape of the p-type electrode are not particularly limited as long as holes can be injected into the contact layer. However, from the viewpoint of injecting holes into the p-type nitride semiconductor, Ni, Au, Pt, Ag, Rh, A metal having a high work function such as Pd, or an alloy thereof, or an oxide electrode such as ITO is desirable. The p-type electrode may be a single layer, a laminate, or an alloy. The electrode formed of an alloy can be formed, for example, by heat-treating a multilayer laminated structure at a high temperature.

The p-type electrode may be provided with a plurality of types of electrodes in plan view. For example, a reflective film using a metal having a high work function such as Ni, Au, Pt, Ag, Rh, or Pd or an alloy thereof, a metal such as Ag, Rh, or Al having a high reflectance, or a dielectric multilayer film In addition, a structure in which a fluororesin or the like is separated and arranged in a stripe or dot shape can be given.
As an n-type electrode, metals such as Al, Ti, Zr, Hf, V, Nb, Ta, Cr, Mo, W, Co, Rh, Ir, Ni, Pd, Pt, Cu, Ag, and Au, or these Mixed crystals or conductive oxides such as ITO and Ga ₂ O ₃ can be used, but not limited thereto. The p-type electrode may be a single layer, a laminate, or an alloy. The electrode formed of an alloy can be formed, for example, by heat-treating a multilayer laminated structure at a high temperature.

The n-type electrode may be provided with a plurality of types of electrodes in plan view. For example, metals having a small work function such as Ti, Al, and V or alloys thereof, metals such as Ag, Rh, and Al having high reflectivity, reflective films using dielectric multilayer films, fluororesins, etc. Examples include a structure in which stripes and dots are separately arranged.
If the first electrode 8 and the second electrode 9 have a structure that allows current to flow through the first nitride semiconductor layer 5 and the second nitride semiconductor layer 7, respectively, 9 and the first and second nitride semiconductor layers 5 and 7 may have different layers. For example, an extremely thin oxide film or nitride film may be provided between the first and second electrodes 8 and 9 and the first and second nitride semiconductor layers 5 and 7, and ITO or the like may be used as the current diffusion layer. May be included.
The first electrode 8 and the second electrode 9 may have a protective film on their surfaces. Examples of the protective film include inorganic insulating films such as SiO ₂ and SiN, organic insulating films such as resins, and the like.

<< Formation method of layer structure >>
A structure in which the first nitride semiconductor layer 5, the nitride semiconductor active layer 6, and the second nitride semiconductor layer 7 are stacked in this order on one surface of the semiconductor substrate 4 is formed by the following method, for example. Can do.
That is, after a first nitride semiconductor layer, a nitride semiconductor active layer, and a second nitride semiconductor layer are stacked in this order on one surface of the semiconductor substrate 4, the first nitride is obtained by a partial dry etching process. The second nitride semiconductor layer, the nitride semiconductor active layer, and a part of the first nitride semiconductor layer are removed, leaving a part in the thickness direction of the nitride semiconductor layer, and the first nitride semiconductor layer 5 and the nitride A mesa structure portion 10a in which the metal semiconductor active layer 6 and the second nitride semiconductor layer 7 are stacked is formed.

  The method for forming the nitride semiconductor layers to be the first and second nitride semiconductor layers 5 and 7 is not particularly limited. Physical vapor deposition methods such as sputtering and molecular beam epitaxy (MBE), chemical vapor deposition methods such as metal organic chemical vapor deposition (MCVD) and thermal CVD. Etc. From the viewpoint that the nitride semiconductor layer can be formed with less impurities and a well-controlled composition, the metal organic chemical vapor deposition method is optimal.

  Dry etching is a method of etching materials with reactive gases, ions, and radicals, including reactive ion etching (RIE), reactive ion beam etching (RIBE), and electron cyclotron. An apparatus such as resonance etching (ECR: Electron Cyclotron Resonance) or ion milling is used. Among these, it is preferable to use an ICP (inductive coupling type) -RIE apparatus that controls the plasma density by controlling the power of the excitation coil and controls the amount of ions drawn by controlling the power of the lower electrode.

In the dry etching process, plasma is generated between the substrate support and the electrode by applying high-frequency power between the electrode and the substrate support that also serves as an electrode using a high-frequency power source in an etching apparatus. Then, the nitride semiconductor layer is etched by decomposing and exciting the etching gas introduced into the chamber. Etching gas includes chlorine gas such as chlorine gas (Cl ₂ ), boron trichloride gas (BCl ₃ ), fluorine gas such as tetrafluoromethane gas (CF ₄ ), trifluoromethane gas (CHF ₃ ), or It is possible to use a mixed gas partially containing a halide gas, but this is not restrictive.

<< Method for forming first electrode and second electrode >>
The formation method of the first and second electrodes 8 and 9 is not particularly limited. In general, from the viewpoint that a high-purity metal material can be formed into a thin film, a thermal evaporation method using resistance heating or electron beam heating is used. In addition, a physical vapor deposition method such as a sputtering method is used. From the viewpoint that the electrode film thickness can be accurately controlled, the sputtering method is optimal.

<Substrate>
The substrate 11 includes a package substrate, a printed circuit board, a submount substrate that can be freely designed later, a support wafer made of Si or the like for holding a semiconductor chip, a main body portion such as an illumination device or a water sterilizer (ultraviolet light). The semiconductor chip 10 which is a light emitting diode can be directly connected by the first connection body and the second connection body).
Examples of the first wiring 2 and the second wiring 3 include, but are not limited to, metals such as Al, Cu, Ag, and Au, or alloys thereof. It is desirable to use Au that has high thermal conductivity, excellent corrosion resistance, and easy joining. The first wiring 2 and the second wiring 3 may be a single layer or a stacked layer. A multilayer wiring may be formed through an insulating layer.

<Structure in which second portion of second wiring and at least part of third portion are surrounded by first electrode in plan view>
If the second part 13 of the second wiring 3 and at least a part of the third part 14 are surrounded by the first electrode 8 of the semiconductor chip 10, this structure is included. Specifically, it is only necessary that the first electrode 8 is arranged on the outside of the second portion 13 and at least a part of the outside of the third portion 14 in plan view. That is, it is only necessary that the first electrode 8 be disposed outside the two sides of the second portion 13 and the third portion 14 in plan view. In order to efficiently arrange the first electrode 8 on the semiconductor chip 10, it is more preferable that the first electrode 8 is arranged on the outside in the three directions, and each first electrode 8 arranged in the three directions is the first. It is even better if they are connected on the nitride semiconductor layer 5.

In FIG. 1, there is only one third portion 14 that connects the first portion 12 and the second portion 13, but there may be a plurality of portions. For example, in FIG. 1, the third portion 14 is a single wire, but may be formed of two wires.
Although the third portion 14 is drawn in a straight line in FIG. 1, it may be a curved line.
In FIG. 1, the first electrode 8 is formed in a substantially similar shape to the second portion 13 and the third portion 14, but this is not restrictive. For example, the second portion 13 may be a circle in plan view, and the first electrode 8 may be a rectangle having an opening partly.

  As described above, in the semiconductor device 100 shown in FIGS. 1 and 2, the wirings 2 and 3 on the package substrate 1 side having different polarities and the electrodes 8 and 9 on the semiconductor chip 10 side have different polarities and electrodes. They are arranged so that they do not face each other. Therefore, it is possible to avoid a short circuit via a metal foreign object or the like mixed between the two, and as a result, a state equivalent to a short circuit between the first wiring 2 and the second wiring 3 of the base 11 can be avoided.

  For example, when the semiconductor chip 10 is driven and a current flows through the first nitride semiconductor layer 5, the first nitride semiconductor layer 5 generates heat due to the parasitic resistance of the semiconductor chip 10. Corrosion of the first nitride semiconductor layer 5 proceeds due to oxidation of the nitride in the first nitride semiconductor layer 5 by the heat and moisture in the atmosphere. Therefore, when the second wiring 3 and the first electrode 8 face each other as shown in FIG. 3, the vicinity of the interface between the first electrode 8 facing the second wiring 3 in the first nitride semiconductor layer 5 is When corroded, the first electrode 8 may be partially peeled from the first nitride semiconductor layer 5. In addition, when the first nitride semiconductor layer 5 is formed of a material that easily undergoes corrosion, for example, AlGaN with a high Al composition ratio, the first nitride semiconductor layer 5 is formed with GaN or the like with a low Al composition ratio. In comparison, the possibility that the first electrode 8 is partially peeled from the first nitride semiconductor layer 5 is increased. The peeled first electrode 8, that is, particles may connect the first nitride semiconductor layer 5 and the second wiring 3.

  As a result, a current flows through the path of the second wiring 3 -particle-first electrode 8 -conductive medium 20-first wiring 2, and as a result, the first wiring 2 and the second wiring 3 are short-circuited. There is a possibility that the situation will be equivalent to the case. 3A is a plan view of a conventional semiconductor device, FIG. 3B is a sectional view taken along the line AA 'in FIG. 3A, and FIG. 3C is a sectional view taken along the line BB' in FIG. It is. In FIG. 3A, a boundary line inside the device that is not partially exposed to the outside is also shown so that the overlapping of each layer becomes clear. The cross-sectional views shown in FIGS. 3B and 3C are image views, and do not necessarily represent the same distance and scale as the plan view of FIG.

  In the semiconductor device 100 according to this embodiment, the wirings 2 and 3 on the package substrate 1 side and the electrodes 8 and 9 on the semiconductor chip 10 side are arranged so that the wirings and electrodes having different polarities do not face each other. Therefore, even if the first nitride semiconductor layer 5 is corroded, no electrode is disposed on the first nitride semiconductor layer 5, so that a short circuit occurs between the second wiring 3 and the first wiring 2. It is possible to avoid the generation of particles that are partially peeled electrodes that are the cause. Further, even if the first nitride semiconductor layer 5 is peeled off due to corrosion, the wires and electrodes having different polarities do not face each other, so the peeled first nitride semiconductor layer 5 becomes a metal foreign matter. Therefore, it is possible to avoid short-circuiting between wirings and electrodes having different polarities. That is, it is possible to avoid a short circuit with the semiconductor chip 10 side through the metal foreign matter in the third portion 14 of the second wiring 3.

  Thus, since the possibility that a short circuit occurs can be reduced without providing an insulating protective film or the like for avoiding a short circuit occurring between the semiconductor chip 10 and the base 11, a complicated manufacturing process is required. It can manufacture by a comparatively simple process, without doing. Moreover, it is only necessary to arrange the wirings and electrodes having different polarities so as not to face each other, and the arrangement positions of the first electrode 8 and the second electrode 9 of the semiconductor chip 10 are not relatively restricted. The second electrode 9 can be disposed at a relatively optimal position, and it is possible to achieve both the reduction in short circuit risk and the optimal design of the electrode arrangement of the semiconductor chip 10.

[One-Mode Ultraviolet Light Emitting Module]
The ultraviolet light emitting module of one embodiment of the present invention includes the semiconductor device 100 of one embodiment of the present invention.
The ultraviolet light emitting module of one embodiment of the present invention can be applied to all existing apparatuses in which an ultraviolet lamp is used, and can be replaced. In particular, the present invention can be applied to an apparatus using deep ultraviolet light having a wavelength of 280 nm or less.
The semiconductor device 100 of one embodiment of the present invention and the ultraviolet light emitting module including the semiconductor device 100 are used in, for example, devices in the medical / life science field, the environmental field, the industrial / industrial field, the life / home appliance field, the agricultural field, and other fields. Applicable.

Semiconductor device 100 as a nitride semiconductor light emitting device includes chemical and chemical synthesis / decomposition equipment, liquid / gas / solid (containers, food, medical equipment, etc.) sterilization equipment, semiconductor cleaning equipment, film / glass / metal Surface modification equipment such as semiconductor, FPD, PCB, and other electronic equipment manufacturing exposure equipment, printing / coating equipment, adhesion / sealing equipment, film / pattern / mock-up transfer / molding equipment, banknotes / scratches / blood・ Applicable to measuring and inspection equipment for chemical substances.
Examples of liquid sterilizers include automatic ice making equipment, ice trays, ice storage containers, water storage tanks for ice making machines, ice making machines, freezers, ice making machines, humidifiers, dehumidifiers, water server cold water tanks, hot water tanks, flow paths Pipes, stationary water purifiers, portable water purifiers, water heaters, water heaters, wastewater treatment devices, disposers, toilet drainage traps, washing machines, dialysis water sterilization modules, peritoneal dialysis connector sterilizers, disaster water storage systems, etc. This is not the case.

  Examples of gas sterilizers include air purifiers, air conditioners, ceiling fans, floor and bedding vacuum cleaners, futon dryers, shoe dryers, washing machines, clothes dryers, indoor sterilization lights, and storage ventilation. Examples include, but are not limited to, systems, shoe boxes, and chests. Examples of solid sterilizers (including surface sterilizers) include vacuum packers, belt conveyors, medical / dental / barber / beauty salon hand tool sterilizers, toothbrushes, toothbrush holders, chopstick boxes, cosmetic pouches, Examples include, but are not limited to, drainage lids, toilet bowl cleaners, toilet lids, and the like.

[Second Embodiment]
FIG. 4 is a plan view showing an example of the semiconductor device 100 according to the second embodiment of the present invention. FIG. 5 is a cross-sectional view taken along the line AA ′ of FIG. In FIG. 4, a boundary line inside the device that is not partially exposed to the outside is also shown so that the overlapping of each layer becomes clear. 5 is an image diagram, and does not necessarily represent the same distance and scale as the plan view of FIG.
As shown in FIGS. 4 and 5, the semiconductor device 100 according to the second embodiment is different from the semiconductor device 100 according to the first embodiment in the first nitridation in the region of the semiconductor chip 10 facing the second wiring 3. Except that the portion where the physical semiconductor layer 5 is exposed does not exist and a part of the third portion 14 of the second wiring 3 faces the exposed portion 16 of the semiconductor substrate 4, the first embodiment is the same as the first embodiment. Has an equivalent structure. That is, in the thickness direction of the semiconductor device 100, the second wiring 3 and the portion where the first nitride semiconductor layer 5 is exposed do not face each other, and at least a part of the third portion 14 of the second wiring 3 is the semiconductor substrate 4. Opposite the exposed part.

By having this structure, even if, for example, metal foreign matter is mixed in the manufacturing process and the semiconductor substrate 4 and the second wiring 3 are in contact with each other via the metal foreign matter in the third portion 14 in FIG. Because of the insulating property, it is possible to avoid a short circuit between the first wiring 2 and the second wiring 3 in the base 11 via the semiconductor chip 10. Further, the region of the semiconductor chip 10 that faces the third portion 14 of the second wiring 3 is the semiconductor substrate 4, and the second wiring 3 does not face the first nitride semiconductor layer 5 in the first place. It is possible to reduce the generation of particles that are the first nitride semiconductor layer 5 that has been partially peeled off, causing a short circuit between the third portion 14 and the semiconductor chip 10 side. That is, the generation of the partially peeled electrode that causes a short circuit and the generation of the partially peeled first nitride semiconductor layer 5 can be suppressed, and as a result, the third portion 14 of the second wiring 3 can be suppressed. As a result, the possibility of a short circuit between the first wiring 2 and the second wiring 3 can be avoided.
In addition, since the first portion 12 is provided, the wiring can be connected from the outside to the second wiring 3 by wire bonding or the like.

[Third embodiment]
FIG. 6 is a plan view showing an example of the semiconductor device 100 according to the third embodiment of the present invention. FIG. 7 is a cross-sectional view taken along the line AA ′ of FIG. In FIG. 6, a boundary line inside the device that is not exposed to the outside is also shown so that the overlapping of each layer becomes clear. Further, the cross-sectional view of FIG. 7 is an image diagram and does not necessarily represent the same distance and scale as the plan view of FIG.
The semiconductor device 100 according to the third embodiment is the same as the semiconductor device 100 according to the first embodiment except that the first portion 12 is not included.
Accordingly, even in this case, for example, metal foreign matter is mixed in the manufacturing process, and even if the third portion 14 of the second wiring 3 and the first nitride semiconductor layer 5 are in contact with each other through the metal foreign matter in FIG. The possibility of causing a short circuit failure due to the large contact resistance between the foreign matter and the first nitride semiconductor layer 5 can be minimized. Further, since the first portion 12 is not provided, the outer shape of the semiconductor device 100 can be reduced accordingly.

  As mentioned above, although embodiment of this invention was described, the said embodiment has illustrated the apparatus and method for materializing the technical idea of this invention, and the technical idea of this invention is a component. It does not specify the material, shape, structure, arrangement, etc. The technical idea of the present invention can be variously modified within the technical scope defined by the claims described in the claims.

DESCRIPTION OF SYMBOLS 1 Package substrate 2 1st wiring 3 2nd wiring 4 Semiconductor substrate 5 1st nitride semiconductor layer 6 Nitride semiconductor active layer 7 2nd nitride semiconductor layer 8 1st electrode 9 2nd electrode 10 Semiconductor chip 11 Base | substrate 12 1st part 13 Second part 14 Third part

Claims (11)

A package substrate;
A first wiring formed on one surface of the package substrate;
A second wiring formed on the one surface so as to be insulated from the first wiring;
A substrate having a semiconductor substrate, and a semiconductor substrate;
A first nitride semiconductor layer of a first conductivity type formed on a surface of the semiconductor substrate on the base side;
A nitride semiconductor active layer formed on a part of the first nitride semiconductor layer;
A second nitride semiconductor layer of a second conductivity type formed on the nitride semiconductor active layer;
A first electrode provided in a part of the region where the nitride semiconductor active layer is not formed on the first nitride semiconductor layer;
A second electrode formed on the second nitride semiconductor layer;
A semiconductor chip having
With
At least a part of the first electrode is joined to the first wiring,
At least a part of the second electrode is joined to the second wiring,
A semiconductor device in which the first electrode is not provided on a region facing the second wiring of the semiconductor chip.   The semiconductor device according to claim 1, wherein the second electrode is not provided on a region facing the first wiring of the semiconductor chip.   3. The semiconductor device according to claim 1, wherein a region where the first nitride semiconductor layer is exposed is not provided in a region facing the second wiring of the semiconductor chip.   4. The semiconductor device according to claim 1, wherein the second wiring has a first portion formed in a part of a region of the package substrate that does not face the semiconductor chip. 5.   5. The semiconductor according to claim 4, wherein the second wiring includes a second portion formed in a region facing the second electrode of the package substrate, and a third portion connecting the first portion and the second portion. apparatus. The second wiring includes a first portion formed in a part of a region not facing the semiconductor chip of the package substrate, a second portion formed in a region facing the second electrode of the package substrate, A third portion connecting the first portion and the second portion,
The semiconductor device according to claim 1, wherein at least a part of the third portion is opposed to the first nitride semiconductor layer.   The semiconductor device according to claim 5, wherein at least a part of the third portion faces a region where the semiconductor substrate is exposed. The semiconductor chip has a mesa structure portion formed of a part of the first nitride semiconductor layer, the nitride semiconductor active layer, and the second nitride semiconductor layer,
The second electrode is formed on the top of the mesa structure,
The semiconductor device according to claim 5, wherein the first electrode is formed in a region surrounding the second part and at least a part of the third part in a plan view.   The semiconductor device according to claim 1, wherein the semiconductor chip is an ultraviolet light emitting diode. The first nitride semiconductor layer is Al _x In _y Ga _z N (0 <x ≦ 1, 0 ≦ y <1, 0 ≦ z <1, x + y + z = 1). The semiconductor device according to claim 1.   The ultraviolet light emitting module provided with the semiconductor device as described in any one of Claims 1-10.

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