JP2016128783A - センサシステムおよびデバイス - Google Patents
センサシステムおよびデバイス Download PDFInfo
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Abstract
FET型水素センサのセンス信号を低ノイズ化する。
【解決手段】
上記課題を解決するために、本発明のセンサシステムの一側面は基板上にFETにより参照デバイスとセンサデバイスを構成し、更に両者のウェル電位は電気的に分離する。
【選択図】 図5
Description
ここまでで、本願実施例により基板効果を取り除くことによる利点を述べた。次に、図9を用いて1/f雑音の低減効果を述べる。
FCV 燃料電池自動車
VDS ドレインソース電圧
VG 接地電位を基準としたゲート電位
VREF 参照FETデバイス出力
PASSI 検出対象遮断膜
OXIDE ゲート酸化膜
CATGATE 触媒金属ゲート
DREF 参照FETのドレイン端子
SREF 参照FETのソース端子
BREF 参照FETのウェル端子
IDS ドレインソース電流
WELL ウェル
SUB 半導体基板
PSUB P型半導体基板
VSEN センサFETデバイス出力
DIPOLE 水素双極子
DSEN センサFETのドレイン端子
SSEN センサFETのソース端子
BSEN センサFETのウェル端子
DCTCIRCUIT 検出回路
VTHSENSE VTH検出回路
VDSEN センサFET向けドレイン電位
VSSEN センサFET向けソース電位
VDSSEN センサFET向けドレインソース電圧
VGEN 基準電圧生成回路
VDSREF 参照FET向けドレインソース電圧
VDREF 参照FET向けドレイン電位
VSREF 参照FET向けソース電位
CAL 補正演算回路
VDD High側電源電位
VBS 基板電圧
VGS ゲートソース電圧
VTH しきい電圧
GATE 非触媒ゲート
IDSGEN ドレインソース電流生成回路
SBUF ソース電圧バッファ
DBUF ドレイン電圧バッファ
VDSGEN ドレインソース電圧生成回路
SW 切り替えスイッチ
SWCTRL 切り替えスイッチ制御線
APN PN接合のアノード端子
CPN PN接合のカソード端子
TEMPMETER 温度計
VDIODE PN接合向け制御電圧
IDIODEGEN PN接合向け制御電流生成回路
VF PN接合温度計出力
RH 抵抗温度計向けハイ端子
RL 抵抗温度計向けロウ端子
VRES 抵抗温度計向け制御電圧
IRESGEN 抵抗温度計向け制御電流生成回路
DPWELL ディープPウェル
DNWELL ディープNウェル
STI トレンチ型素子分離
Claims (15)
- P型半導体基板と、
前記P型半導体基板に形成された第一のNウェル内にP型FETで形成された検知対象物に対して感応性を持つセンサFETと、
前記P型半導体基板に形成された第二のNウェル内にP型FETで形成された検知対象に対して感応性を持たない参照FETと、
前記第一のNウェルと前記第二のNウェルが電気的に分離され、
ガス雰囲気中における前記センサFETと前記参照FETの閾電圧の差分を検出する検出回路とを有する、ことを特徴とするセンサシステム。 - 前記センサFETの閾電圧を計測する第一のソースフォロア回路と、
前記参照FETの閾電圧を計測する前記ソースフォロア回路とは独立して設けられた第二のソースフォロア回路とを有する、ことを特徴とする請求項1記載のセンサシステム。 - 前記センサFETの閾電圧と前記参照FETの閾電圧とを計測するソースフォロア回路を有し、
前記センサFETの閾電圧と前記参照FETの閾電圧とを計測するにあたっては、前記ソースフォロア回路と前記センサFET、もしくは、前記ソースフォロア回路と前記参照FETをスイッチングにより切り替えて接続する、ことを特徴とする請求項1記載のセンサシステム。 - 更に、前記P型半導体基板には温度測定のためのPN接合部を有する、ことを特徴とする請求項1記載のセンサシステム。
- 半導体基板と、前記半導体基板に形成された第一のウェル内にFETで形成された検知対象に対して感応性をもつセンサFETと、
前記半導体基板に形成された第二のウェル内にFETで形成された検知対象に感応性を持たない参照FETと、
前記第一のウェルと前記第二のウェルとは電気的に分離して設けられ、
前記センサFETのソースと前記第一のウェルとが短絡されており、
前記参照FETのソースと前記第二のウェルとが短絡されており、
ガス雰囲気中における前記センサFETと前記参照FETの閾電圧の差分を検出する検出回路とを有する
ことを特徴とするセンサシステム。 - 前記短絡されたセンサFETのウェル電位とソース電位に対して接続される、センサFET用ドレイン電流源と、
前記センサFETのソース電位を入力として、当該入力を前記検出回路に出力するセンサFET用ソース電圧バッファと、
前記センサFETのソースドレイン電圧を一定に維持する、センサFET用ソースドレイン電圧生成回路と、
前記短絡された参照FETのウェル電位とソース電位に対して接続される、参照FET用ドレイン電流源と、
前記参照FETのソース電位を入力として、当該入力を前記検出回路に出力する参照FET用ソース電圧バッファと、
前記参照FETのソースドレイン電圧を一定に維持する、参照FET用ソースドレイン電圧生成回路と、を有する、請求項5記載のセンサシステム。 - 同一の半導体基板に、
半導体領域と、
前記半導体領域に形成された第一のウェル内にFETで形成された、検知対象物に対して感応性を持つセンサFETと、
前記半導体領域に形成された第二のウェル内にFETで形成された、検知対象に対して感応性を持たない参照FETと
前記第一のウェルと前記第二のウェルの間の電気的導通を妨げる構成と、
前記センサFETの閾値電圧または閾値電圧の変化を示す信号を出力するセンサ信号出力端子と、
前記参照FETの閾電圧または閾値電圧の変化を示す信号を出力する参照信号出力端子と、
を有するセンサデバイス。 - 前記半導体領域が、第1導電型の半導体領域であり、
前記第一及び第二のウェルは、第2導電型のウェルであり、
前記第一及び第二の第2導電型ウェルの間を前記第1導電型の半導体領域で分離することにより、前記第一及び第二の第2導電型ウェルの間電気的導通を妨げる、請求項7記載のセンサデバイス。 - 前記第一及び第二のウェルの間に、トレンチ型素子分離構造を設けることにより、前記第一及び第二の第2導電型ウェルの間電気的導通を妨げる、請求項7記載のセンサデバイス。
- 前記半導体基板に、温度に対応した信号を発生する構造を設ける、請求項7記載のセンサデバイス。
- 前記温度に対応した信号を発生する構造として、PN接合を設ける、請求項10記載のセンサデバイス。
- 前記温度に対応した信号を発生する構造として、抵抗部材を設ける、請求項10記載のセンサデバイス。
- 前記センサFETのウェル電位とソース電位が短絡され、前記参照FETのウェル電位とソース電位が短絡されている、請求項7記載のセンサデバイス。
- 前記ウェル電位と短絡された前記センサFETのソース電位を前記センサ信号出力端子に出力し、前記ウェル電位と短絡された前記参照FETのソース電位を前記参照信号出力端子に出力する、請求項13記載のセンサデバイス。
- 前記半導体領域は、P型半導体領域であり、
前記第一及び第二のウェルは、N型半導体領域として形成され、
前記センサFET及び参照FETは、P型FETである、請求項7記載のセンサデバイス。
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US10830799B1 (en) * | 2019-07-12 | 2020-11-10 | Alpha And Omega Semiconductor (Cayman) Ltd. | Temperature and VGS compensation for current sensing using Rdson in MOSFETS |
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