JP2015228447A - Semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device in which a semiconductor chip mounted on a substrate and a substrate electrode on the substrate are connected by wire bonding and which can properly inhibit wire meandering and wire sweep even when a length of wire for connecting a chip electrode and the substrate electrode is increased.SOLUTION: A semiconductor device manufacturing method comprises the steps of: providing a relay electrode 50 at a place on one surface 11 of a substrate 10 and outside a semiconductor chip 20 and between a chip electrode 21 and a substrate electrode 30, in which a width W1 of the relay electrode 50 in a maximum dimension direction is smaller than a width W2 of the substrate electrode 30 and smaller than a width W3 of a tip 110 of a capillary 100; connecting an intermediate part of a wire 40 to the relay electrode 50 by a stitch bonding method without cutting a wire 40 after a primary bonding process; and finally, performing a secondary bonding process.

Description

  The present invention relates to a method for manufacturing a semiconductor device in which a semiconductor chip mounted on a substrate and a substrate electrode on the substrate are connected by wire bonding, and more particularly to a wire bonding method.

  Conventionally, as this type of semiconductor device, generally, a substrate, a semiconductor chip mounted on one surface of the substrate and having a chip electrode on the surface, a substrate electrode provided on the outer surface of the semiconductor chip on one surface of the substrate, and a chip An apparatus including a wire for connecting an electrode and a substrate electrode has been proposed.

  Here, the wire is formed by wire bonding, and one end is a chip connection point connected to the chip electrode, and the other end is a substrate connection point connected to the substrate electrode. The planar shape of the wire when viewed from one surface of the substrate is usually a straight line connecting the chip connection point and the substrate connection point, while the side surface shape of the wire is the connection point between the two points. It is supposed to form a loop shape that is convex on one surface of the substrate.

  In such a semiconductor device, when the wire length is increased, the planar shape of the wire becomes a meandering shape, and in the configuration in which the wire is sealed with the mold resin, a wire flow due to the mold resin is generated. There are concerns.

  On the other hand, in Patent Document 1, in such a semiconductor device, a relay electrode is further provided on the semiconductor chip, and a middle portion of the wire is connected to the relay electrode, thereby dividing one wire into two loops. What has been proposed.

JP-A-5-243317

  However, in the above-described conventional one, the length of each loop in one wire is shortened, but the wire is only divided into two loops within the range of the semiconductor chip. Therefore, when the distance between the chip electrode and the substrate electrode is large, the effect of dividing the wire length is small.

  In this case, it is conceivable that a relay electrode similar to the substrate electrode is provided outside the semiconductor chip on one surface of the substrate and between the chip electrode and the substrate electrode. The space on one side is limited.

  The present invention has been made in view of the above problems, and in a semiconductor device in which a semiconductor chip mounted on a substrate and a substrate electrode on the substrate are connected by wire bonding, the distance between the chip electrode and the substrate electrode. Even when the wire length is large, the object is to appropriately suppress the meandering of the wire and the wire flow.

  To achieve the above object, the invention described in claim 1 includes a substrate (10), a semiconductor chip (20) mounted on one surface (11) of the substrate and having a chip electrode (21) on the surface, and one surface of the substrate. And a substrate electrode (30) provided outside the semiconductor chip, and formed by wire bonding, one end being a chip connection point (41) connected to the chip electrode, and the other end being a substrate electrode A method for manufacturing a semiconductor device comprising a wire (40) for connecting a chip electrode and a substrate electrode by being a substrate connection point (42) connected to the substrate, and having the following steps It is.

  Prepare a substrate on which a semiconductor chip is mounted as a preparation member, one of which is a primary electrode in wire bonding and the other is a secondary electrode in wire bonding. Preparation process.

  -Using a wire bonding capillary (100) having an inner hole (120) opened at the tip (110), the wire inserted into the inner hole and led out from the inner hole at the tip, A primary bonding step in which the tip of the capillary is pressed against the primary electrode and joined.

  A secondary bonding step of drawing the wire from the inner hole of the capillary while drawing the wire to the secondary electrode by the capillary, pressing the wire against the secondary electrode by the tip of the capillary, and joining by stitch bonding. The manufacturing method of Claim 1 is provided with each said process, and also has the following each characteristics.

  In the preparation step, as the preparation member, one or more relay electrodes (50) are provided on the surface of the substrate outside the semiconductor chip and between the chip electrode and the substrate electrode, and the relay electrode The width (W1) in the maximum dimension direction of the substrate is smaller than the width (W2) of the substrate electrode in the wire extending direction and smaller than the width (W3) of the capillary tip in the wire drawing direction. Prepare.

  ・ After the primary bonding process, the middle part of the wire is connected to all of one or more relay electrodes by the stitch bonding method in which the wire is pressed at the tip of the capillary without cutting the wire. A wire is cut by performing a secondary bonding step on the wire, thereby connecting the wire between the chip connection point and the substrate connection point with a plurality of connection points (43) formed with one or more relay electrodes. It shall be one continuous shape with a loop. The invention of claim 1 is characterized by comprising the above points.

  According to this, at least one relay electrode is provided on one surface of the substrate outside the semiconductor chip, in the middle of the chip connection point that is both ends of the wire, the chip electrode to which the substrate connection point is respectively connected, and the substrate electrode. The intermediate portion of the wire is connected to the relay electrode. Thus, the wire is divided into a plurality of loops while maintaining one continuous state. Therefore, the wire length in each loop can be shortened, and the above-described meandering and wire flow of the wire can be prevented even when the entire wire length is large.

  In addition, the planar size of the relay electrode can be greatly reduced by making the width of the relay electrode in the maximum dimension direction smaller than the width of the substrate electrode and the width of the tip of the capillary. Therefore, it is possible to reduce the restriction of the space on the one surface of the substrate due to the relay electrode.

  Here, the width in the maximum dimension direction of the relay electrode is smaller than the width of the tip portion of the capillary, but when the middle portion of the wire is stitch-bonded to the relay electrode, the wire drawing direction in the tip portion of the capillary The wire may be pressed against the relay electrode only at the portion where the wire is positioned along the line.

  Therefore, in the present invention, even if the width in the maximum dimension direction of the relay electrode is smaller than the width of the tip portion of the capillary, wire connection to the relay electrode can be performed appropriately. Therefore, the planar size of the relay electrode can be made significantly smaller than the substrate electrode.

  As described above, according to the manufacturing method of the present invention, even when the distance between the chip electrode and the substrate electrode is large and the wire length is large, the meandering of the wire and the wire flow can be appropriately suppressed.

  In addition, the code | symbol in the bracket | parenthesis of each means described in the claim and this column is an example which shows a corresponding relationship with the specific means as described in embodiment mentioned later.

(A) is a schematic sectional drawing of the semiconductor device concerning 1st Embodiment of this invention, (b) is the upper-view schematic plan view of the semiconductor device shown by (a). FIG. 2 is a process diagram showing a cross-sectional view of the method for manufacturing the semiconductor device shown in FIG. FIG. 3 is a cross-sectional process diagram illustrating a method for manufacturing the semiconductor device following FIG. 2; It is an enlarged view of the capillary part in FIG.2 (b). It is an enlarged view of the capillary part in Fig.3 (a). It is process drawing which shows the principal part of the manufacturing method of the semiconductor device concerning 2nd Embodiment of this invention in cross section. (A) is a schematic sectional drawing of the semiconductor device concerning 3rd Embodiment of this invention, (b) is the upper-view schematic plan view of the semiconductor device shown by (a). It is a schematic sectional drawing of the semiconductor device concerning 4th Embodiment of this invention. It is a schematic plan view of the semiconductor device concerning 5th Embodiment of this invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other are given the same reference numerals in the drawings in order to simplify the description.

(First embodiment)
The semiconductor device S1 according to the first embodiment of the present invention will be described with reference to FIG. This semiconductor device S1 is mounted on a vehicle such as an automobile, for example, and is applied as a device for driving various electronic devices for the vehicle.

  The semiconductor device S1 of the present embodiment is broadly divided into a substrate 10, a semiconductor chip 20 mounted on one surface 11 of the substrate 10, and a substrate electrode 30 provided outside the semiconductor chip 20 on the one surface 11 of the substrate 10. And a wire 40 for connecting the semiconductor chip 20 and the substrate electrode 30 to each other.

  The substrate 10 has a plate shape, and one plate surface is the one surface 11. In FIG. 1A, a part on the one surface 11 side in the thickness direction of the substrate 10 is shown. As this board | substrate 10, the multilayer wiring board which consists of resin or a ceramic is mentioned, for example. Here, the substrate 10 is a wiring substrate made of a resin such as an epoxy resin.

  The semiconductor chip 20 is made of a semiconductor such as a silicon semiconductor and is formed by a typical semiconductor process. For example, the semiconductor chip 20 includes an IC chip, a transistor, and the like. The semiconductor chip 20 is fixed to the one surface 11 of the substrate 10 via a die mount material (not shown) such as an Ag paste or a conductive adhesive.

  A chip electrode 21 is provided on the surface of the semiconductor chip 20 opposite to the substrate 10. The chip electrode 21 functions as a wire pad to which the wire 40 is connected, and is not limited, but is made of a conductor such as aluminum.

  The substrate electrode 30 functions as a wire pad to which the wire 40 is connected, and is made of a normal pad material. Although not limited thereto, for example, the substrate electrode 30 is formed by stacking Cu, Ni, Au from the one surface 11 side of the substrate 10, a so-called Au / Ni / Cu laminated film, or Cu from the one surface 11 side of the substrate 10. , Ni, Pd, and Au are laminated, so-called Au / Pd / Ni / Cu laminated film or the like.

  In the substrate 10 of the present embodiment, a via hole 12 reaching the surface 11 of the substrate 10 is provided inside the substrate 10, and the substrate electrode 30 is provided on the surface 11 of the substrate 10 so as to cover the via hole 12. It has been. As a result, the substrate electrode 30 is electrically connected to the via hole 12 and integrated.

  Here, the via hole 12 may penetrate a part of the substrate 10 in the thickness direction, or may penetrate the whole substrate 10 in the thickness direction. The via hole 12 is made of a filled via using Cu or the like, and has a function of performing electrical connection between the front and back plate surfaces of the substrate 10 or heat dissipation.

  The chip electrode 21 of the semiconductor chip 20 and the substrate electrode 30 are electrically connected by a wire 40. Here, the wire 40 has one end as a chip connection point 41 connected to the chip electrode 21, and the other end as a substrate connection point 42 connected to the substrate electrode 30, whereby the chip electrode 21 and the substrate electrode 30. Are connected. The wire 40 is made of Au, Cu, Ag, or the like, and is formed by wire bonding.

  Here, as shown in FIG. 1B, the planar shape of the wire 40 when viewed from the top surface 11 of the substrate 10 connects the two points between the chip connection point 41 and the substrate connection point 42. It is supposed to form a straight line.

  In the present embodiment, the relay electrode 50 is provided on the surface 11 of the substrate 10 outside the semiconductor chip 20 and between the chip electrode 21 and the substrate electrode 30. Here, one relay electrode 50 is provided. The relay electrode 50 can be made of the same material as the substrate electrode 30 described above.

  The width W1 of the relay electrode 50 in the maximum dimension direction is smaller than the width W2 of the substrate electrode 30 in the direction in which the wire 40 extends, as shown in FIG. The width W1 in the maximum dimension direction of the relay electrode 50 is smaller than the width W3 in the lead-out direction of the wire 40 at the distal end portion 110 of the capillary 100, as shown in FIG.

  In FIG. 1, the relay electrode 50 is a plane circle, and the width W1 in the maximum dimension direction corresponds to the diameter. For example, when the relay electrode 50 is a plane square, the width W1 in the maximum dimension direction is a diagonal line. It corresponds to the length.

  Further, the width W2 of the substrate electrode 30 in the extending direction of the wire 40 is a width along the extending direction of the wire 40 when viewed from the one surface 11 of the substrate 10, as shown in FIG. Furthermore, the direction in which the wire 40 extends corresponds to a linear direction connecting the board connection point 42 and a relay connection point 43 described later adjacent thereto.

  Note that the width W2 of the substrate electrode 30 is larger than the width W3 of the leading end portion 110 of the capillary 100 in the drawing direction of the wire 40 shown in FIG. Thus, the relay electrode 50 has a significantly smaller planar size than the substrate electrode 30.

  And the intermediate part of the wire 40 is connected with respect to the relay electrode 50 by the stitch bonding method. Here, the connection point between the wire 40 and the relay electrode 50 is referred to as a relay connection point 43. As a result, the wire 40 has one continuous shape including a plurality of (two in this case) loops formed by the relay connection point 43 between the chip connection point 41 and the substrate connection point 42. Has been.

  Next, a method for manufacturing the semiconductor device S1 of this embodiment will be described with reference to FIGS. First, as shown in FIG. 2A, a preparation process is performed for preparing the substrate 10 on which the semiconductor chip 20 is mounted as a preparation member. This preparation member is formed by mounting the semiconductor chip 20 on the substrate 10 having the substrate electrode 30 and the relay electrode 50 integrated with the via hole 12.

  Here, one of the tip electrode 21 and the substrate electrode 30 in the preparation member is a primary electrode on the primary bonding side in wire bonding for forming the wire 40, and the other is on the secondary bonding side in which wire cutting is performed. The secondary electrode is used.

  In the present embodiment, the chip electrode 21 is a primary side electrode, and the substrate electrode 30 is a secondary side electrode. That is, in this case, in the formed wire 40, the chip connection point 41 is a primary joint in wire bonding, and the substrate connection point 42 is a secondary joint in wire bonding.

  Then, as shown in FIGS. 2A to 3B, wire bonding is performed using the stitch bonding capillary 100 to form the wire 40. Here, the capillary 100 is driven by a normal stitch bonding apparatus, and can perform bonding operations such as drawing, pressing, and application of ultrasonic vibration to the wire 40.

  Specifically, as shown in FIGS. 2 to 5, the capillary 100 has a cylindrical shape having an inner hole 120 that opens to the distal end portion 110. Here, the inner hole 120 is a hollow portion, and the distal end portion 110. Is a typical cylindrical shape with a circular shape. The wire 40 is inserted into the inner hole 120 and pulled out from the distal end portion 110.

  Here, FIG. 4 shows a width W3 of the distal end portion 110 of the capillary 100 in the drawing direction of the wire 40. This width W3 is the width of the distal end portion 110 along the direction in which the wire 40 is drawn from the inner hole 120. In the present embodiment, since the tip portion 110 is circular, the width W3 always corresponds to the diameter of the tip portion 110 even if the drawing direction of the wire 40 is different.

  Here, in the preparation member prepared in the preparation step, as described above, the width W1 in the maximum dimension direction of the relay electrode 50 extends the wire 40 in the substrate electrode 30 as shown in FIG. It is smaller than the width W2 in the direction. Further, as described above, as shown in FIG. 4, the width W1 in the maximum dimension direction of the relay electrode 50 is the width W3 in the lead-out direction of the wire 40 at the tip portion 110 of the capillary 100 (here, the diameter of the tip portion 110). Equivalent).

  As shown in FIG. 2A, first, a primary bonding process is performed on the prepared member prepared in this manner using the capillary 100 described above. Here, primary bonding is performed on the chip electrode 21 which is a primary side electrode.

  In this primary bonding step, the wire 40 inserted into the inner hole 120 of the capillary 100 and led out from the inner hole 120 at the distal end portion 110 is pressed against the chip electrode 21 by the distal end portion 110 of the capillary 100 and joined.

  Specifically, although not shown, an initial ball is formed by electric discharge machining at the tip of the wire 40 led out from the inner hole 120 at the tip portion 110 of the capillary 100, and this ball is pressed against the chip electrode 21 to cause ultrasonic vibration. By doing so, the joining is performed. Thereby, the chip connection point 41 in the wire 40 is formed.

  After this primary bonding step, a relay bonding step is performed. In this step, as shown in FIGS. 2A to 2B, the wire 40 is pulled out from the inner hole 120 of the capillary 100 to the relay electrode 50 without being cut by the capillary 100. .

  Then, as shown in FIGS. 2B and 4, the intermediate portion of the wire 40 is connected to the relay electrode 50 by a stitch bonding method in which the wire 40 is pressed by the tip portion 110 of the capillary 100. This is a relay bonding process, whereby a relay connection point 43 in the wire 40 is formed.

  Next, a secondary bonding process which is a final process for forming the wire 40 is performed. In this step, as shown in FIG. 2C to FIG. 3A, the wire 40 is pulled out from the inner hole 120 of the capillary 100 by the capillary 100 and the substrate electrode 30 as the secondary electrode is drawn. Route around.

  Then, as shown in FIGS. 3A and 5, the wire 40 is pressed against the substrate electrode 30 by the tip 110 of the capillary 100 and joined by stitch bonding. Thereby, the board | substrate connection point 42 in the wire 40 is formed, and wire cutting is performed by pressing the front-end | tip part 110 of the capillary 100 after that. Thus, the wire 40 of the present embodiment is completed.

  Thus, in the wire bonding process of this embodiment, the above-described primary bonding process, relay bonding process, and secondary bonding process are sequentially performed. As a result, the wire 40 forms a single continuous shape having a plurality of loops formed by providing the relay connection point 43 between the chip connection point 41 and the substrate connection point 42. It ’s done.

  By the way, according to the present embodiment, the chip connection point 41 and the substrate connection point 42 which are both ends of the wire 40 are respectively connected to the substrate 10 outside the semiconductor chip 20 between the chip electrode 21 and the substrate electrode 30. A relay electrode 50 is provided on the one surface 11, and an intermediate portion of the wire 40 is connected to the relay electrode 50.

  Thereby, the wire 40 is divided into a plurality of loops (here, two) by the relay connection point 43 while maintaining one continuous state. Therefore, the wire length in each loop can be shortened, and the meandering of the wire 40 and the flow of the wire 40 as described above can be prevented even when the overall wire length is large.

  Further, the width W1 in the maximum dimension direction of the relay electrode 50 is made smaller than the width W2 of the substrate electrode 30 and the width W3 of the tip portion 110 of the capillary 100, thereby greatly increasing the planar size of the relay electrode 50. Can be small. Therefore, the space restriction on the first surface 11 of the substrate 10 by the relay electrode 50 can be reduced.

  Here, the difference in stitch bonding between the relay bonding process and the secondary bonding process will be specifically described with reference to FIG. 4 and FIG.

  As shown in FIG. 5, in the substrate electrode 30 that performs the secondary bonding, the both ends of the inner hole 120 along the drawing direction of the wire 40 in the tip portion 110 of the capillary 100 are pressed against the substrate electrode 30. Make a cut. Therefore, the width W2 of the substrate electrode 30 needs to be larger than the width W3 of the tip portion 110 of the capillary 100.

  On the other hand, as shown in FIG. 4, in the relay electrode 50 that performs relay bonding, the wire is not cut, so that only the one side portion of the inner hole 120 along the lead-out direction of the wire 40 in the tip portion 110 of the capillary 100 is used. 40 may be pressed against the relay electrode 50.

  That is, when the intermediate portion of the wire 40 is stitch-bonded to the relay electrode 50, the wire 40 is connected to the relay electrode only at the portion of the distal end portion 110 of the capillary 100 where the wire 40 is positioned along the drawing direction of the wire 40. 50 may be pressed. Therefore, the width W1 in the maximum dimension direction of the relay electrode 50 may be smaller than the width W3 of the distal end portion 110 of the capillary 100 as long as the pressing area of the wire 40 is ensured.

  As described above, in this embodiment, even when the width W1 of the relay electrode 50 in the maximum dimension direction is smaller than the width W3 of the tip portion 110 of the capillary 100, the wire connection to the relay electrode 50 is appropriately performed. Yes. Therefore, the planar size of the relay electrode 50 can be made significantly smaller than the substrate electrode 30.

  Thus, according to the manufacturing method of this embodiment, the relay electrode 50 is provided on the one surface 11 of the substrate 10 even when the distance between the chip electrode 21 and the substrate electrode 30 is large and the length of the wire 40 is large. The meandering of the wire and the wire flow can be appropriately suppressed. Then, by making the planar size of the relay electrode 50 significantly small, the space restriction on the one surface 11 of the substrate 10 by the relay electrode 50 can be reduced as much as possible.

  A preferred embodiment in the present embodiment will be described next. In the above preparation process, the relay electrode 50 is arranged as the substrate 10 so that the distance between the adjacent connection points of the chip connection point 41, the relay connection point 43, and the substrate connection point 42 on the wire 40 is the same. It is desirable to prepare what has been prepared.

  That is, in the case of this embodiment, the length of the wire 40 between the chip connection point 41 and the substrate connection point 42 when viewed from the one surface 11 of the substrate 10 is divided into two equal parts by the relay connection point 43. It is desirable that the relay electrode 50 is disposed. Here, the fact that the distances between the connection points are the same is not limited to being completely the same, but includes errors within the range of the diameter of the wire 40 and the collapse width of each connection point.

  When the wire 40 is equally divided by such a relay connection point 43, the wire 40 is equally divided into a plurality of loops having the same wire length while maintaining one continuous state. There is an advantage that the wire length can be efficiently shortened.

  Further, in the present embodiment, as described above, in the substrate 10, the via hole 12 reaching the one surface 11 of the substrate 10 is provided inside the substrate 10, and the substrate electrode 30 is integrated with the via hole 12. It is said that

  Since the substrate electrode 30 integrated with the via hole 12 in this manner is a region in which the region to which the wire 40 is connected and the region covering the via hole 12 are continuous, the planar size tends to increase. Usually, a plurality of substrate electrodes 30 are provided around the semiconductor chip 20 on the one surface 11 of the substrate 10. In the plurality of substrate electrodes 30 in which the via holes 12 are integrated, the substrate electrodes It is necessary to take a large distance between 30.

  For this reason, when a plurality of substrate electrodes 30 in which the via holes 12 are integrated are arranged around the semiconductor chip 20 on the one surface 11 of the substrate 10, the distance between the semiconductor chip 20 and each substrate electrode 30. It is necessary to take large.

  This leads to an increase in the distance between the chip electrode 21 and the substrate electrode 30, that is, the wire length. Therefore, when adopting the substrate electrode 30 in which the via hole 12 is integrated, it is effective to adopt a configuration in which the wire length is divided by using the relay electrode 50 as in the present embodiment.

  In addition, since the relay electrode 50 and the substrate electrode 30 are connected by the same wire 40, the both electrodes may be electrically connected to each other by a wiring or the like provided on the substrate 10. However, providing such a wiring for connecting both electrodes may lead to complexity and complexity.

  In consideration of such a point, in the case of the substrate electrode 30 integrated with the via hole 12, it is desirable that the relay electrode 50 is electrically independent from the via hole 12. Further, the relay electrode 50 may be a dummy electrode that is electrically independent of the electric circuit configured by the substrate 10 including the substrate electrode 30. That is, the relay electrode 50 may be a dummy electrode that is electrically independent from components other than the relay electrode.

(Second Embodiment)
A method of manufacturing a semiconductor device according to the second embodiment of the present invention will be described with reference to FIG. 6 focusing on differences from the first embodiment. The manufacturing method of the present embodiment is the same as that of the first embodiment up to the preparation step, but the bonding order in the wire bonding step is different.

  In the manufacturing method of the first embodiment, among the chip electrode 21 and the substrate electrode 30 in the preparation member prepared in the preparation step, the chip electrode 21 is the primary side electrode and the substrate electrode 30 is the secondary side electrode.

  On the other hand, in this embodiment, among the chip electrode 21 and the substrate electrode 30 in the prepared member, the substrate electrode 30 is a primary electrode, and the chip electrode 21 is a secondary electrode. That is, in this embodiment, in the wire 40 after formation, the chip connection point 41 is a secondary joint in wire bonding, and the substrate connection point 42 is a primary joint in wire bonding. .

  In the wire bonding process of this embodiment, bumps 60 connected to the wires 40 are formed on the chip electrodes 21 as shown in FIG. 6A before the primary bonding process. The bump 60 is formed by ball bonding using the capillary 100 and is made of the same material as the wire 40.

  After this bump 60 is formed, in this embodiment, the substrate electrode 30 is used as the primary electrode and the chip electrode 21 is used as the secondary electrode, as in the first embodiment, and the primary bonding process, the relay bonding process, Next bonding process is performed sequentially. Thereby, as shown in FIG. 6B, the wire 40 is completed. Here, the chip connection point 41 is formed on the bump 60.

  As described above, in this embodiment, the wire bonding connection order is reversed between the chip electrode 21 and the substrate electrode 30 as compared to the first embodiment. Of course, the same effect as the embodiment is exhibited.

(Third embodiment)
A third embodiment of the present invention will be described with reference to FIG. 7 focusing on differences from the first embodiment. The manufacturing method of this embodiment is different from the first embodiment in that the number of relay electrodes 50 in the preparation member prepared in the preparation process is plural.

  In the first embodiment, one relay electrode 50 in the preparation member is provided between the chip electrode 21 and the substrate electrode 30 on the one surface 11 of the substrate 10. On the other hand, as in the present embodiment, a plurality of relay electrodes 50 may be provided between the chip electrode 21 and the substrate electrode 30, two in FIG.

  Here, for each of the plurality of relay electrodes 50, the width W1 in the maximum dimension direction is smaller than the width W2 of the substrate electrode 30 and smaller than the width W3 of the tip portion 110 of the capillary 100. is there.

  In this case, in the wire bonding process, the chip electrode 21 is used as the primary electrode and the substrate electrode 30 is used as the secondary electrode, and the primary bonding process, the relay bonding process, and the secondary bonding process are sequentially performed as in the first embodiment. . However, in this embodiment, the relay bonding process is repeated a plurality of times, and twice in the example of FIG. Thereby, as shown in FIG. 7, the wire 40 is completed.

  As described above, the present embodiment has a plurality of relay electrodes 50 as compared with the first embodiment, and the relay bonding process is performed a plurality of times along with this. Of course, the same effect as the first embodiment is exhibited. The number of relay electrodes 50 may be three or more in addition to the two as shown in FIG.

  Also in the present embodiment, as in the first embodiment, in the preparation process, as the substrate 10, the chip connection points 41, the relay connection points 43, and the substrate connection points 42 on the wires 40 are adjacent to each other. It is desirable to prepare a device in which the relay electrodes 50 are arranged so that the distance between them is the same.

  Here, in the example of FIG. 7, the length of the wire 40 between the chip connection point 41 and the substrate connection point 42 when viewed from the top surface 11 of the substrate 10 is divided into three equal parts by the two relay connection points 43. Thus, it is desirable that the two relay electrodes 50 be arranged. Furthermore, according to this preferred embodiment, the length of the wire 40 is divided into four equal parts if there are three relay electrodes 50, and (n + 1) equal parts if n (n is an integer of 1 or more). Equally divided.

  In the present embodiment, a plurality of relay electrodes 50 are used, and the relay bonding process is performed a plurality of times. Accordingly, the connection order as in the second embodiment is also adopted in this embodiment. Of course, it may be combined with the wire bonding method.

(Fourth embodiment)
A semiconductor device manufacturing method according to the fourth embodiment of the present invention will be described with reference to FIG. 8 focusing on the differences from the first embodiment. The manufacturing method of this embodiment is different from the wire bonding step in the manufacturing method of the first embodiment in that a part of the process is added.

  As shown in FIG. 8, in the wire bonding step of this embodiment, the wire 40 is formed using the chip electrode 21 as the primary electrode and the substrate electrode 30 as the secondary electrode. Here, in this embodiment, the bump 60 is formed on the relay electrode 50 before the primary bonding step. The bump 60 is formed by ball bonding using the capillary 100 and is made of the same material as the wire 40.

  After this bump 60 is formed, in this embodiment, the substrate electrode 30 is used as the primary electrode and the chip electrode 21 is used as the secondary electrode, as in the first embodiment, and the primary bonding process, the relay bonding process, Next bonding process is performed sequentially. Here, the relay bonding process is performed on the bump 60 on the relay electrode 50. Thereby, as shown in FIG. 8, the wire 40 is completed.

  As described above, the present embodiment is the same as the first embodiment because the bump 60 is formed on the relay electrode 50 in advance as compared with the first embodiment. Of course, will be demonstrated.

  In FIG. 8, the bump 60 is formed on the relay electrode 50 before the primary bonding step. However, the bump 60 may be formed on the substrate electrode 30 together with the relay electrode 50. Further, the bump 60 may be formed only on the substrate electrode 30 before the primary bonding step.

  In addition, since the present embodiment adds a step of forming bumps 60 on the relay electrode 50 or the substrate electrode 30 before the primary bonding step, not only the first embodiment but also the second embodiment. Needless to say, the third embodiment can be combined.

(Fifth embodiment)
A semiconductor device manufacturing method according to the fifth embodiment of the present invention will be described with reference to FIG. 9, focusing on the differences from the first embodiment. The manufacturing method of the present embodiment is different from the first embodiment in that the arrangement configuration of the substrate electrode 30 is partially changed.

  In the first embodiment, as shown in FIG. 1, the plurality of substrate electrodes 30 are arranged substantially linearly. On the other hand, as shown in FIG. 9, in the present embodiment, the plurality of substrate electrodes 30 are arranged in a staggered manner.

  Accordingly, as shown in FIG. 9, the wire 40 is divided into a wire having a long wire length that requires division by the relay electrode 50 and a wire having a short wire length that does not require the relay electrode 50. In addition, according to such a staggered arrangement, a large number of substrate electrodes 30 can be arranged efficiently in a space.

  Here, in FIG. 9, a part of the chip electrode 21 and the chip connection point 41 is omitted for the wire 40 not provided with the relay electrode 50.

(Other embodiments)
In each of the embodiments described above, the planar shape of the wire 40 when viewed from the top surface 11 of the substrate 10 is a straight line connecting the chip connection point 41 and the substrate connection point 42, and the relay connection point 43 was also located on this straight line. On the other hand, the planar shape of the wire 40 may be a shape bent with the relay connection point 43 in the wire 40 as a bending point. That is, one wire 40 may have different wire extending directions with the relay connection point 43 as a bending point.

  Although not shown in each of the above drawings, a mold resin for sealing one surface 11 of the substrate 10 together with the semiconductor chip 20, the substrate electrode 30, and the wire 40 may be provided on the one surface 11 of the substrate 10. Good. In this case, the problem of the wire flow described above occurs, but according to each of the embodiments described above, the wire flow can be prevented.

  Further, the substrate 10 is not limited to a multilayer substrate, and may be a single layer substrate, for example. Further, the substrate electrode 30 may not be integrated with the via hole 12. In other words, the substrate 10 may not have the via hole 12.

  Further, in each of the above embodiments, the capillary 100 is cylindrical, and the width W3 in the wire drawing direction at the tip portion 110 of the capillary 100 corresponds to the diameter of the tip portion 110. It may be oval or polygonal. Also in this case, it is needless to say that the width W3 in the wire drawing direction may be a width along the direction.

  Further, the present invention is not limited to the above-described embodiment, and can be appropriately changed within the scope described in the claims. The above embodiments are not irrelevant to each other, and can be combined as appropriate unless the combination is clearly impossible, and the above embodiments are not limited to the illustrated examples. Absent. In each of the above-described embodiments, it is needless to say that elements constituting the embodiment are not necessarily essential unless explicitly stated as essential and clearly considered essential in principle. Yes. Further, in each of the above embodiments, when numerical values such as the number, numerical value, quantity, range, etc. of the constituent elements of the embodiment are mentioned, it is clearly limited to a specific number when clearly indicated as essential and in principle. The number is not limited to the specific number except for the case. Further, in each of the above embodiments, when referring to the shape, positional relationship, etc. of the component, etc., the shape, unless otherwise specified and in principle limited to a specific shape, positional relationship, etc. It is not limited to the positional relationship or the like.

DESCRIPTION OF SYMBOLS 10 Substrate 11 One side of substrate 20 Semiconductor chip 21 Chip electrode 30 Substrate electrode 40 Wire 41 Chip connection point in wire 42 Substrate connection point in wire 43 Relay connection point in wire 50 Relay electrode 100 Capillary 110 Capillary tip 120 Capillary inner hole 120 W1 Width in the maximum dimension direction of the relay electrode W2 Width in the wire extending direction on the substrate electrode W3 Width in the wire drawing direction at the tip of the capillary

Claims (5)

A substrate (10);
A semiconductor chip (20) mounted on one surface (11) of the substrate and having a chip electrode (21) on the surface;
A substrate electrode (30) provided outside the semiconductor chip on one surface of the substrate;
It is formed by wire bonding, and one end is a chip connection point (41) connected to the chip electrode, and the other end is a substrate connection point (42) connected to the substrate electrode. A method of manufacturing a semiconductor device comprising: a wire (40) for connecting the chip electrode and the substrate electrode,
As the preparation member, the substrate on which the semiconductor chip is mounted, wherein one of the chip electrode and the substrate electrode is a primary electrode in the wire bonding, and the other is a secondary electrode in the wire bonding. A preparation process for preparing a thing,
Using the wire bonding capillary (100) having an inner hole (120) opening at the tip (110),
A primary bonding step in which the wire inserted into the inner hole and led out from the inner hole at the tip is pressed against the primary electrode by the tip of the capillary and joined;
While pulling out the wire from the inner hole of the capillary, the wire is routed to the secondary electrode by the capillary, and the wire is pressed against the secondary electrode by the tip of the capillary and joined by stitch bonding. A next bonding step,
In the preparation step, as the preparation member, one or more relay electrodes (50) are provided on one surface of the substrate outside the semiconductor chip and between the chip electrode and the substrate electrode. With
The width (W1) in the maximum dimension direction of the relay electrode is smaller than the width (W2) in the direction in which the wire extends in the substrate electrode, and the width (W3) in the wire drawing direction at the tip of the capillary. ) Prepare something smaller than
After the primary bonding step, an intermediate portion of the wire is applied to all of the one or more relay electrodes by a stitch bonding method in which the wire is pressed at the tip of the capillary without cutting the wire. By connecting the wire, and finally performing the secondary bonding step to perform wire cutting,
The wire has a continuous shape including a plurality of loops formed by connection points (43) to the one or more relay electrodes between the chip connection point and the substrate connection point. A method for manufacturing a semiconductor device.   In the preparing step, as the substrate, the chip connection point in the wire, the connection point with the relay electrode, and the distance between the adjacent connection points with respect to the substrate connection point are the same. 2. The method of manufacturing a semiconductor device according to claim 1, wherein a device in which at least one relay electrode is arranged is prepared. In the substrate, a via hole (12) reaching the one surface of the substrate is provided inside the substrate,
The method of manufacturing a semiconductor device according to claim 1, wherein the substrate electrode is integrated with the via hole.   4. The method of manufacturing a semiconductor device according to claim 3, wherein the one or more relay electrodes are electrically independent from the via hole.   5. The semiconductor device according to claim 1, wherein the one or more relay electrodes are dummy electrodes that are electrically independent of an electric circuit configured by the substrate. 6. Production method.

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