JP2006303086A - Semiconductor device - Google Patents

Semiconductor device Download PDF

Info

Publication number
JP2006303086A
JP2006303086A JP2005120993A JP2005120993A JP2006303086A JP 2006303086 A JP2006303086 A JP 2006303086A JP 2005120993 A JP2005120993 A JP 2005120993A JP 2005120993 A JP2005120993 A JP 2005120993A JP 2006303086 A JP2006303086 A JP 2006303086A
Authority
JP
Japan
Prior art keywords
wiring pattern
conductive member
external electrode
semiconductor device
pattern portion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2005120993A
Other languages
Japanese (ja)
Other versions
JP4622646B2 (en
Inventor
Jun Ishikawa
純 石川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toyota Industries Corp
Original Assignee
Toyota Industries Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toyota Industries Corp filed Critical Toyota Industries Corp
Priority to JP2005120993A priority Critical patent/JP4622646B2/en
Publication of JP2006303086A publication Critical patent/JP2006303086A/en
Application granted granted Critical
Publication of JP4622646B2 publication Critical patent/JP4622646B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

Abstract

<P>PROBLEM TO BE SOLVED: To provide a small semiconductor device of which energy loss is reduced. <P>SOLUTION: A ceramic insulating substrate 3 comprises an insulating board 6 of ceramics, and first and second conductive members 7 and 8 arranged on the upper and lower surfaces, respectively, of the insulating board 6. Since, in the first conductive member 7, a wiring pattern 9 to which the rear surface electrode of a semiconductor element 5 is jointed is integrally formed with a first external electrode 10, the wiring pattern 9 is not required to be connected to the first external electrode 10 using wire bonding. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

この発明は、半導体装置に係り、特にベース板の上に絶縁基板を介して半導体素子が配置される半導体装置に関する。   The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which a semiconductor element is disposed on a base plate via an insulating substrate.

例えば、特許文献１に開示されている半導体装置では、ベース基板の上に絶縁基板を介して半導体素子が配置されている。ここで絶縁基板は、セラミック板の上面及び下面にそれぞれ銅パターンが接合された構成を有しており、ベース基板上に絶縁基板の下面の銅パターンがはんだにより接合されると共に絶縁基板の上面の銅パターン上にはんだにより半導体素子の裏面電極が接合されている。   For example, in the semiconductor device disclosed in Patent Document 1, a semiconductor element is disposed on a base substrate via an insulating substrate. Here, the insulating substrate has a structure in which copper patterns are bonded to the upper surface and the lower surface of the ceramic plate, respectively, and the copper pattern on the lower surface of the insulating substrate is bonded to the base substrate by solder and the upper surface of the insulating substrate is The back electrode of the semiconductor element is joined to the copper pattern by solder.

特開２０００−４９２８１号公報JP 2000-49281 A

このような半導体装置では、例えば、絶縁基板から独立して配設された外部電極部と絶縁基板の上面の銅パターンとをワイヤボンディングにより互いに接続することにより、外部電極部を介して半導体素子の裏面電極を装置の外部に取り出すことができる。   In such a semiconductor device, for example, by connecting the external electrode part arranged independently from the insulating substrate and the copper pattern on the upper surface of the insulating substrate to each other by wire bonding, the semiconductor element is connected via the external electrode part. The back electrode can be taken out of the apparatus.

しかしながら、上述のように絶縁基板の上面の銅パターンと外部電極部とをワイヤボンディングにより接続する場合、ボンディング用のツールがこの半導体装置内の部分と干渉しないようにボンディング付近にクリアランスを設ける必要があり、そのため半導体装置が大型化してしまう。
また、ワイヤボンディングに用いられるワイヤは、電流が流れる断面積が小さいため電気抵抗が大きく、またインダクタンスも大きいため、電気的なエネルギー損失が大きいという問題があった。
この発明はこのような問題点を解消するためになされたもので、小型で且つエネルギー損失を低減することができる半導体装置を提供することを目的とする。 However, when the copper pattern on the upper surface of the insulating substrate and the external electrode part are connected by wire bonding as described above, it is necessary to provide a clearance in the vicinity of the bonding so that the bonding tool does not interfere with the part in the semiconductor device. For this reason, the semiconductor device is increased in size.
In addition, the wire used for wire bonding has a problem in that electrical energy loss is large because the cross-sectional area through which the current flows is small and the electrical resistance is large and the inductance is large.
The present invention has been made to solve such problems, and an object thereof is to provide a semiconductor device that is small in size and can reduce energy loss.

この発明に係る半導体装置は、ベース板の上に絶縁基板を介して半導体素子が配置された半導体装置において、絶縁基板が、平板状の絶縁板と、絶縁板の第１の主面上に直接接合される配線パターン部及び配線パターン部よりも厚く形成されると共に配線パターン部から延長して外方に引き出される第１外部電極部を有する第１導電部材と、絶縁板の第２の主面上に直接接合される配線パターン部を形成する第２導電部材とを備えるものである。   The semiconductor device according to the present invention is a semiconductor device in which a semiconductor element is disposed on a base plate via an insulating substrate, and the insulating substrate is directly on the flat insulating plate and the first main surface of the insulating plate. A first conductive member having a first external electrode portion that is formed thicker than the wiring pattern portion to be joined and that is thicker than the wiring pattern portion and extends outwardly from the wiring pattern portion, and a second main surface of the insulating plate And a second conductive member that forms a wiring pattern portion that is directly bonded thereon.

第１導電部材は、その配線パターン部と第１外部電極部との間に段差を有し、第１導電部材の配線パターン部に対して第１外部電極部を垂直に折り曲げて立設させることにより第１外部電極部を上方に引き出すことができる。
また、ベース板の上に第２導電部材の配線パターン部を接合し、第１導電部材の配線パターン部の上に半導体素子を接合することができる。
また、一端部が半導体素子上面の対応する電極部に接合されると共に他端部が外方に引き出される第２外部電極部をさらに備えることができる。
なお、絶縁板はセラミックまたは樹脂から形成することができる。 The first conductive member has a step between the wiring pattern portion and the first external electrode portion, and the first external electrode portion is vertically bent with respect to the wiring pattern portion of the first conductive member. Thus, the first external electrode portion can be drawn upward.
Further, the wiring pattern portion of the second conductive member can be bonded onto the base plate, and the semiconductor element can be bonded onto the wiring pattern portion of the first conductive member.
In addition, it may further include a second external electrode portion in which one end portion is joined to a corresponding electrode portion on the upper surface of the semiconductor element and the other end portion is drawn outward.
The insulating plate can be formed from ceramic or resin.

この発明によれば、小型で且つエネルギー損失を低減することができる半導体装置を実現することができる。   According to the present invention, a semiconductor device that is small in size and can reduce energy loss can be realized.

以下、この発明の実施の形態を添付図面に基づいて説明する。
実施の形態１．
図１に、この発明の実施の形態１に係る半導体装置の構成を示す。この半導体装置は、パワーモジュール等として用いられるものであり、ＣｕまたはＡｌ等からなる放熱性のベース板１を有している。このベース板１上に、はんだ２を介してセラミック絶縁基板３が配置されており、さらに、セラミック絶縁基板３上に、はんだ４を介してパワーチップ等の半導体素子５が搭載されている。 Embodiments of the present invention will be described below with reference to the accompanying drawings.
Embodiment 1 FIG.
FIG. 1 shows a configuration of a semiconductor device according to the first embodiment of the present invention. This semiconductor device is used as a power module or the like, and has a heat radiating base plate 1 made of Cu or Al. A ceramic insulating substrate 3 is disposed on the base plate 1 via solder 2, and a semiconductor element 5 such as a power chip is mounted on the ceramic insulating substrate 3 via solder 4.

セラミック絶縁基板３は、セラミックからなる平板状の絶縁板６と、絶縁板６の第１の主面としての上面に配置される第１導電部材７と、絶縁板６の第２の主面としての下面に配置される第２導電部材８とを有するものである。第１導電部材７は、配線パターン部９とこの配線パターン部９の一端部から上方に延長して配線パターン部９に対して垂直に立設される第１外部電極部１０とを有しており、その配線パターン部９が絶縁板６の上面に直接接合されている。また、第２導電部材８からなる配線パターン部が絶縁板６の下面に直接接合されている。この第２導電部材８の配線パターン部がはんだ２を介してベース板１の上面に接合されると共に、第１導電部材７の配線パターン部９の上面に半導体素子５の裏面電極がはんだ４を介して接合されている。   The ceramic insulating substrate 3 includes a flat insulating plate 6 made of ceramic, a first conductive member 7 disposed on an upper surface as a first main surface of the insulating plate 6, and a second main surface of the insulating plate 6. The second conductive member 8 is disposed on the lower surface of the first conductive member 8. The first conductive member 7 includes a wiring pattern portion 9 and a first external electrode portion 10 that extends upward from one end portion of the wiring pattern portion 9 and stands vertically with respect to the wiring pattern portion 9. The wiring pattern portion 9 is directly bonded to the upper surface of the insulating plate 6. Further, the wiring pattern portion made of the second conductive member 8 is directly bonded to the lower surface of the insulating plate 6. The wiring pattern portion of the second conductive member 8 is joined to the upper surface of the base plate 1 via the solder 2, and the back electrode of the semiconductor element 5 is soldered to the upper surface of the wiring pattern portion 9 of the first conductive member 7. Are joined through.

なお、例えば、絶縁板６は０．６ｍｍ程度の厚さを有し、第１導電部材７の配線パターン部９及び第２導電部材８の配線パターン部はそれぞれ０．３ｍｍ程度の厚さを有している。また、このとき、第１導電部材７の第１外部電極部１０は１ｍｍ程度の厚さを有し、第１外部電極部１０の厚さが配線パターン部９の厚さよりも大きい値を有するように構成されている。   For example, the insulating plate 6 has a thickness of about 0.6 mm, and the wiring pattern portion 9 of the first conductive member 7 and the wiring pattern portion of the second conductive member 8 each have a thickness of about 0.3 mm. is doing. At this time, the first external electrode portion 10 of the first conductive member 7 has a thickness of about 1 mm, and the thickness of the first external electrode portion 10 is larger than the thickness of the wiring pattern portion 9. It is configured.

また、ベース板１の周縁部に樹脂等からなるケース１１が固定され、ベース板１の上に配置された半導体素子５等がこのケース１１の内部に収容されると共にセラミック絶縁基板３の第１導電部材７の第１外部電極部１０がケース１１の外部にまで引き出されている。また、断面Ｌ字状の第２外部電極部１２が樹脂部材１３を介して第１導電部材７に対向するように配置されてケース１１の内部から外部へ引き出されており、ケース１１内に位置する第２外部電極部１２の部分と半導体素子５上面の対応する電極部とがボンディングワイヤ１４により互いに接続されている。さらに、Ｌ字状の制御端子部１５がケース１１内にインサート成形されてケース１１の内部から外部へ引き出されており、ケース１１内に位置する制御端子部１５の部分と半導体素子５上面の対応する電極部とがボンディングワイヤ１６により互いに接続されている。   In addition, a case 11 made of resin or the like is fixed to the peripheral portion of the base plate 1, and the semiconductor element 5 or the like disposed on the base plate 1 is accommodated inside the case 11 and the first of the ceramic insulating substrate 3. The first external electrode portion 10 of the conductive member 7 is drawn to the outside of the case 11. Further, the second external electrode portion 12 having an L-shaped cross section is disposed so as to face the first conductive member 7 with the resin member 13 interposed therebetween, and is drawn out from the inside of the case 11 to be positioned in the case 11. A portion of the second external electrode portion 12 to be connected to a corresponding electrode portion on the upper surface of the semiconductor element 5 is connected to each other by a bonding wire 14. Further, an L-shaped control terminal portion 15 is insert-molded in the case 11 and pulled out from the inside of the case 11. Correspondence between the portion of the control terminal portion 15 located in the case 11 and the upper surface of the semiconductor element 5 Are connected to each other by bonding wires 16.

なお、例えば半導体素子５上面にソース（またはエミッタ）電極部及びゲート電極部がそれぞれ設けられると共に半導体素子５の裏面電極としてドレイン（またはコレクタ）電極部が設けられ、第２外部電極部１２をボンディングワイヤ１４によりソース（またはエミッタ）電極部に接続し、制御端子部１５をボンディングワイヤ１６によりゲート電極部に接続することにより、第２外部電極部１２、制御端子部１５及び第１導電部材７の第１外部電極部１０をそれぞれこの半導体装置のソース（またはエミッタ）電極、ゲート電極及びドレイン（またはコレクタ）電極として用いることができる。   For example, a source (or emitter) electrode portion and a gate electrode portion are provided on the upper surface of the semiconductor element 5, and a drain (or collector) electrode portion is provided as a back electrode of the semiconductor element 5, and the second external electrode portion 12 is bonded. By connecting to the source (or emitter) electrode portion by the wire 14 and connecting the control terminal portion 15 to the gate electrode portion by the bonding wire 16, the second external electrode portion 12, the control terminal portion 15, and the first conductive member 7 are connected. The first external electrode portion 10 can be used as a source (or emitter) electrode, a gate electrode, and a drain (or collector) electrode of the semiconductor device, respectively.

また、図２及び３を参照して、セラミック絶縁基板３の製造方法を説明する。まず、図２に示されるように、セラミックからなる絶縁板６の上面に第１導電部材７の配線パターン部９を直接接合してセラミック絶縁基板３の上面側のパターンを形成する。ここで、第１導電部材７は、配線パターン部９と第１外部電極部１０との間に段差１７を有しており、段差１７及び第１外部電極部１０が絶縁板６の上面から外部にはみ出している。また、第２導電部材８からなる配線パターン部を絶縁板６の下面に直接接合してセラミック絶縁基板３の下面側のパターンを形成する。
なお、第１導電部材７の配線パターン部９と絶縁板６は、両者の活性面を出して共有結合させる、あるいはロー付けする等の方法により互いに接合することができる。同様の方法により、第２導電部材８の配線パターン部と絶縁板６も互いに接合することができる。
次に、図２に破線矢印で示されるように、第１導電部材７の第１外部電極部１０を段差１７付近を中心にして配線パターン部９に対して折り曲げることにより、図３に示されるように、第１外部電極部１０を配線パターン部９に対して垂直に立設させる。
このようにして、セラミック絶縁基板３を製造することができる。 A method for manufacturing the ceramic insulating substrate 3 will be described with reference to FIGS. First, as shown in FIG. 2, the wiring pattern portion 9 of the first conductive member 7 is directly bonded to the upper surface of the insulating plate 6 made of ceramic to form a pattern on the upper surface side of the ceramic insulating substrate 3. Here, the first conductive member 7 has a step 17 between the wiring pattern portion 9 and the first external electrode portion 10, and the step 17 and the first external electrode portion 10 are externally connected from the upper surface of the insulating plate 6. It sticks out. Further, the wiring pattern portion made of the second conductive member 8 is directly joined to the lower surface of the insulating plate 6 to form a pattern on the lower surface side of the ceramic insulating substrate 3.
Note that the wiring pattern portion 9 and the insulating plate 6 of the first conductive member 7 can be joined to each other by a method such that the active surfaces of both are exposed and covalently bonded or brazed. By the same method, the wiring pattern portion of the second conductive member 8 and the insulating plate 6 can also be joined to each other.
Next, as shown by a broken line arrow in FIG. 2, the first external electrode portion 10 of the first conductive member 7 is bent with respect to the wiring pattern portion 9 around the step 17 as shown in FIG. As described above, the first external electrode portion 10 is erected vertically with respect to the wiring pattern portion 9.
In this way, the ceramic insulating substrate 3 can be manufactured.

次に、この実施の形態１に係る半導体装置の作用を説明する。セラミック絶縁基板３の第１導電部材７は、半導体素子５の裏面電極が接合される配線パターン部９と、第１外部電極部１０とが一体に形成された構造を有するため、ワイヤボンディングにより配線パターン部９と第１外部電極部１０とを接続する必要がなくなる。したがって、ボンディング用のツールの干渉を防止するためのクリアランスの確保が不要となり、小型の半導体装置を実現することができると共に、装置の小型化により部品費が低減され、製造コストを低減することもできる。
また、配線パターン部９と第１外部電極部１０とがボンディングワイヤを用いずに直接に接続されているため、電気的なエネルギー損失を低減することができる。 Next, the operation of the semiconductor device according to the first embodiment will be described. Since the first conductive member 7 of the ceramic insulating substrate 3 has a structure in which the wiring pattern portion 9 to which the back electrode of the semiconductor element 5 is bonded and the first external electrode portion 10 are integrally formed, wiring is performed by wire bonding. It is not necessary to connect the pattern portion 9 and the first external electrode portion 10. Therefore, it is not necessary to secure a clearance for preventing the interference of the bonding tool, so that a small semiconductor device can be realized, and the component cost can be reduced by reducing the size of the device, thereby reducing the manufacturing cost. it can.
Further, since the wiring pattern portion 9 and the first external electrode portion 10 are directly connected without using a bonding wire, electrical energy loss can be reduced.

また、セラミック絶縁基板３の配線パターン部９と第１外部電極部１０とをワイヤボンディングにより接続する工程を省略できるため、この半導体装置の組み立てを容易に行うことができる。
また、セラミック絶縁基板３を用いているため、この装置全体の部品点数を低減することができる。
さらに、第１導電部材７の第１外部電極部１０は配線パターン部９よりも厚く形成されて電極として十分な強度を有するため、第１外部電極部１０をケース１１の上方に引き出して外部の機器を接続して用いることができる。 In addition, since the step of connecting the wiring pattern portion 9 and the first external electrode portion 10 of the ceramic insulating substrate 3 by wire bonding can be omitted, the semiconductor device can be easily assembled.
Further, since the ceramic insulating substrate 3 is used, the number of parts of the entire apparatus can be reduced.
Furthermore, since the first external electrode portion 10 of the first conductive member 7 is formed thicker than the wiring pattern portion 9 and has sufficient strength as an electrode, the first external electrode portion 10 is pulled out above the case 11 and externally connected. It can be used by connecting equipment.

実施の形態２．
次に図４を参照して、この発明の実施の形態２に係る半導体装置について説明する。この実施の形態２は、上述の実施の形態１の半導体装置において、ボンディングワイヤ１４を用いずに、ケース１１内に位置する第２外部電極部１２の部分を延長してその延長部分２１の先端部２１ａを半導体素子５上面の対応する電極部に直接に接続したものである。
第２外部電極部１２の延長部分２１は、半導体素子５との間の応力を緩和するために薄く形成されると共に応力を分散するためにアーチ状に形成されている。また、この延長部分２１の先端部２１ａは、半導体素子５上面の対応する電極部に超音波接合により直接接合されている。 Embodiment 2. FIG.
Next, a semiconductor device according to the second embodiment of the present invention will be described with reference to FIG. In the second embodiment, in the semiconductor device of the first embodiment described above, the portion of the second external electrode portion 12 located in the case 11 is extended without using the bonding wire 14, and the tip of the extended portion 21 is extended. The part 21 a is directly connected to the corresponding electrode part on the upper surface of the semiconductor element 5.
The extension portion 21 of the second external electrode portion 12 is formed thin in order to relieve stress between the semiconductor element 5 and is formed in an arch shape in order to disperse the stress. Further, the distal end portion 21 a of the extended portion 21 is directly bonded to the corresponding electrode portion on the upper surface of the semiconductor element 5 by ultrasonic bonding.

このような構成にすれば、第２外部電極部１２と半導体素子５上面の対応する電極部とをワイヤボンディングすることなく接続することができるため、この半導体装置がさらに小型化されると共に電気的なエネルギー損失がより低減され、また、装置の組み立てがより容易になる。
なお、第２外部電極部１２の延長部分２１の先端部２１ａと半導体素子５上面の対応する電極部とを超音波接合する代わりに、はんだ付けすることもできる。 With this configuration, the second external electrode portion 12 and the corresponding electrode portion on the upper surface of the semiconductor element 5 can be connected without wire bonding, so that the semiconductor device can be further miniaturized and electrically Energy loss is further reduced and the assembly of the device is easier.
In addition, it can also solder, instead of ultrasonically joining the front-end | tip part 21a of the extension part 21 of the 2nd external electrode part 12, and the corresponding electrode part of the semiconductor element 5 upper surface.

なお、上述の実施の形態１及び２において、半導体素子５上面にソース（またはエミッタ）電極を設け、半導体素子５の裏面電極としてドレイン（またはコレクタ）電極部を設ける代わりに、半導体素子５の裏面電極としてソース（またはエミッタ）電極を設け、半導体素子５上面にドレイン（またはコレクタ）電極部を設けて第２外部電極部１２を接続することにより、第２外部電極部１２及び第１導電部材７の第１外部電極部１０をそれぞれこの半導体装置のドレイン（またはコレクタ）電極及びソース（またはエミッタ）電極として用いることもできる。   In the first and second embodiments described above, instead of providing the source (or emitter) electrode on the upper surface of the semiconductor element 5 and providing the drain (or collector) electrode portion as the back electrode of the semiconductor element 5, the back surface of the semiconductor element 5. A source (or emitter) electrode is provided as an electrode, a drain (or collector) electrode part is provided on the upper surface of the semiconductor element 5 and the second external electrode part 12 is connected, whereby the second external electrode part 12 and the first conductive member 7 are connected. The first external electrode portion 10 can be used as a drain (or collector) electrode and a source (or emitter) electrode of the semiconductor device, respectively.

また、実施の形態１及び２において、セラミック絶縁基板３の第１導電部材７及び第２導電部材８はそれぞれＣｕまたはＡｌから形成することができる。このとき第１及び第２導電部材７及び８の双方をＣｕまたはＡｌから形成してもよいし、一方をＣｕから他方をＡｌから形成してもよい。   In the first and second embodiments, the first conductive member 7 and the second conductive member 8 of the ceramic insulating substrate 3 can be formed of Cu or Al, respectively. At this time, both the first and second conductive members 7 and 8 may be formed from Cu or Al, or one may be formed from Cu and the other from Al.

なお、絶縁板６の下面を第１の主面として第１導電部材７の配線パターン部９を直接接合し、絶縁板６の上面を第２の主面として第２導電部材８を直接接合することにより形成されたセラミック絶縁基板を用いることもできる。
また、絶縁板６は、樹脂から形成することもできる。 The wiring pattern portion 9 of the first conductive member 7 is directly bonded with the lower surface of the insulating plate 6 as the first main surface, and the second conductive member 8 is directly bonded with the upper surface of the insulating plate 6 as the second main surface. A ceramic insulating substrate formed by this method can also be used.
Moreover, the insulating plate 6 can also be formed from resin.

この発明の実施の形態１に係る半導体装置を示す断面図である。1 is a cross-sectional view showing a semiconductor device according to Embodiment 1 of the present invention. 実施の形態１におけるセラミック絶縁基板の製造の様子を示す図である。FIG. 5 is a diagram showing a state of manufacturing the ceramic insulating substrate in the first embodiment. 実施の形態１におけるセラミック絶縁基板の製造の様子を示す図である。FIG. 5 is a diagram showing a state of manufacturing the ceramic insulating substrate in the first embodiment. この発明の実施の形態２に係る半導体装置を示す断面図である。It is sectional drawing which shows the semiconductor device which concerns on Embodiment 2 of this invention.

符号の説明Explanation of symbols

１ ベース板、２，４ はんだ、３ セラミック絶縁基板、５ 半導体素子、６ 絶縁板、７ 第１導電部材、８ 第２導電部材、９ 配線パターン部、１０ 第１外部電極部、１１ ケース、１２ 第２外部電極部、１３ 樹脂部材、１４，１６ ボンディングワイヤ、１５ 制御端子部、１７ 段差、２１ 延長部分、２１ａ 先端部。   DESCRIPTION OF SYMBOLS 1 Base board, 2, 4 Solder, 3 Ceramic insulation board | substrate, 5 Semiconductor element, 6 Insulation board, 7 1st electroconductive member, 8 2nd electroconductive member, 9 Wiring pattern part, 10 1st external electrode part, 11 Case, 12 2nd external electrode part, 13 resin member, 14, 16 bonding wire, 15 control terminal part, 17 level | step difference, 21 extension part, 21a front-end | tip part.

Claims (5)

ベース板の上に絶縁基板を介して半導体素子が配置された半導体装置において、
前記絶縁基板は、
平板状の絶縁板と、
前記絶縁板の第１の主面上に直接接合される配線パターン部及び前記配線パターン部よりも厚く形成されると共に前記配線パターン部から延長して外方に引き出される第１外部電極部を有する第１導電部材と、
前記絶縁板の第２の主面上に直接接合される配線パターン部を形成する第２導電部材と
を備えることを特徴とする半導体装置。 In a semiconductor device in which a semiconductor element is disposed on a base plate via an insulating substrate,
The insulating substrate is
A flat insulating plate;
A wiring pattern portion that is directly bonded onto the first main surface of the insulating plate, and a first external electrode portion that is formed thicker than the wiring pattern portion and that extends from the wiring pattern portion and is drawn outward. A first conductive member;
A semiconductor device comprising: a second conductive member that forms a wiring pattern portion that is directly bonded onto the second main surface of the insulating plate. 前記第１導電部材はその配線パターン部と第１外部電極部との間に段差を有し、前記第１導電部材の配線パターン部に対して第１外部電極部を垂直に折り曲げて立設させることにより第１外部電極部が上方に引き出される請求項１に記載の半導体装置。   The first conductive member has a step between the wiring pattern portion and the first external electrode portion, and the first external electrode portion is bent vertically with respect to the wiring pattern portion of the first conductive member. The semiconductor device according to claim 1, wherein the first external electrode portion is drawn upward. ベース板の上に前記第２導電部材の配線パターン部が接合され、前記第１導電部材の配線パターン部の上に半導体素子が接合される請求項１または２に記載の半導体装置。   The semiconductor device according to claim 1, wherein a wiring pattern portion of the second conductive member is bonded onto a base plate, and a semiconductor element is bonded onto the wiring pattern portion of the first conductive member. 一端部が半導体素子上面の対応する電極部に接合されると共に他端部が外方に引き出される第２外部電極部をさらに備えることを特徴とする請求項１〜３のいずれか一項に記載の半導体装置。   4. The device according to claim 1, further comprising: a second external electrode portion having one end joined to a corresponding electrode on the upper surface of the semiconductor element and the other end drawn outward. Semiconductor device. 前記絶縁板は、セラミックまたは樹脂からなる請求項１〜４のいずれか一項に記載の半導体装置。   The semiconductor device according to claim 1, wherein the insulating plate is made of ceramic or resin.
JP2005120993A 2005-04-19 2005-04-19 Semiconductor device Expired - Fee Related JP4622646B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2005120993A JP4622646B2 (en) 2005-04-19 2005-04-19 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005120993A JP4622646B2 (en) 2005-04-19 2005-04-19 Semiconductor device

Publications (2)

Publication Number Publication Date
JP2006303086A true JP2006303086A (en) 2006-11-02
JP4622646B2 JP4622646B2 (en) 2011-02-02

Family

ID=37471041

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005120993A Expired - Fee Related JP4622646B2 (en) 2005-04-19 2005-04-19 Semiconductor device

Country Status (1)

Country Link
JP (1) JP4622646B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE112011104406T5 (en) 2010-12-16 2013-09-19 Mitsubishi Electric Corporation Semiconductor device
US9293390B2 (en) 2013-01-11 2016-03-22 Mitsubishi Electric Corporation Heat radiation structure for semiconductor device

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5717154U (en) * 1980-07-04 1982-01-28
JPS57154162U (en) * 1981-03-23 1982-09-28
JPS6217152U (en) * 1985-07-17 1987-02-02
JP2002043496A (en) * 2000-07-21 2002-02-08 Hitachi Ltd Semiconductor device
JP2004022968A (en) * 2002-06-19 2004-01-22 Mitsubishi Electric Corp Semiconductor device and method of manufacturing the same
JP2005057212A (en) * 2003-08-07 2005-03-03 Toyota Motor Corp Immersion type two-surface heat-radiation power module

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5717154U (en) * 1980-07-04 1982-01-28
JPS57154162U (en) * 1981-03-23 1982-09-28
JPS6217152U (en) * 1985-07-17 1987-02-02
JP2002043496A (en) * 2000-07-21 2002-02-08 Hitachi Ltd Semiconductor device
JP2004022968A (en) * 2002-06-19 2004-01-22 Mitsubishi Electric Corp Semiconductor device and method of manufacturing the same
JP2005057212A (en) * 2003-08-07 2005-03-03 Toyota Motor Corp Immersion type two-surface heat-radiation power module

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE112011104406T5 (en) 2010-12-16 2013-09-19 Mitsubishi Electric Corporation Semiconductor device
US9287201B2 (en) 2010-12-16 2016-03-15 Mitsubishi Electric Corporation Semiconductor device
US9293390B2 (en) 2013-01-11 2016-03-22 Mitsubishi Electric Corporation Heat radiation structure for semiconductor device

Also Published As

Publication number Publication date
JP4622646B2 (en) 2011-02-02

Similar Documents

Publication Publication Date Title
JP4459883B2 (en) Semiconductor device
EP1868244B1 (en) Semiconductor device
JP4815245B2 (en) Power semiconductor module having terminal elements arranged in a brazing manner
JP5176507B2 (en) Semiconductor device
JP2012089681A (en) Power semiconductor device
JP2002076252A (en) Semiconductor device
US8860220B2 (en) Semiconductor device and method for manufacturing the same
US8134838B2 (en) Semiconductor module and method
JP2005142189A (en) Semiconductor device
JP2006245618A (en) Semiconductor device with built-in passive element
JP2010287726A (en) Semiconductor device
JP2002009217A (en) Resin-sealed semiconductor device
JP4622646B2 (en) Semiconductor device
JP2005174955A (en) Semiconductor module
KR101698431B1 (en) Semiconductor power module pakage and methods of fabricating the same
JP3163214U (en) Semiconductor device
JP2004349300A (en) Semiconductor device and its manufacturing method
JP2004343146A (en) Thermoelectric module
JP2006196597A (en) Electronic apparatus and manufacturing method thereof
JP5048627B2 (en) Lead frame and semiconductor device
JP4150508B2 (en) Power semiconductor device
JP2006313821A (en) Semiconductor device
JP2001127226A (en) Semiconductor device
JP2004119670A (en) Semiconductor device using power element
KR101974920B1 (en) Bonded structural body between PCBs

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20070801

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20080331

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20100511

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20100702

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20101005

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20101018

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20131112

Year of fee payment: 3

LAPS Cancellation because of no payment of annual fees