KR101698431B1 - Semiconductor power module pakage and methods of fabricating the same - Google Patents

Abstract

The present invention relates to a semiconductor power module package including a lead formed to be coupled with an external circuit board and a method of manufacturing the semiconductor power module package.
A semiconductor power module package according to an aspect of the present invention includes at least one semiconductor chip on a substrate; A sealing member sealing the semiconductor chip; And a plurality of leads electrically connected to the semiconductor chip and exposed from the sealing member, wherein at least one of the leads has a terminal portion formed as a press fit terminal.
According to the present invention, it is possible to provide a semiconductor power module package having excellent bonding force with an external circuit board while minimizing the package size.

Description

Technical Field [0001] The present invention relates to a semiconductor power module package and a manufacturing method thereof.

The present invention relates to a semiconductor power module package and a method of manufacturing the semiconductor power module package, and more particularly, to a semiconductor power module package including a half including a lead formed to be coupled with an external circuit board and a method of manufacturing the semiconductor power module package .

In the semiconductor power module package, a semiconductor chip is attached on the lead frame, and the semiconductor chip is sealed using a sealing member. As the semiconductor chip is highly integrated, the number of bonding pads for connecting the semiconductor chip to the outside increases, and the number of leads of the lead frame also increases. The leads of these semiconductor power module packages were connected to an external circuit board by soldering or wire bonding.

Such a semiconductor power module package requires a separate area for soldering or wire bonding in order to connect the external circuit board to the lead frame, thereby increasing the size of the package. Soldered or wire-bonded leads are also susceptible to physical vibration or shock.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor power module package having an excellent bonding force with an external circuit board while minimizing the package size.

It is another object of the present invention to provide a method of manufacturing a semiconductor power module package having an excellent bonding force with an external circuit board while minimizing the package size.

According to an aspect of the present invention, there is provided a semiconductor power module package.

The semiconductor power module package comprising: at least one semiconductor chip on a substrate; A sealing member sealing the semiconductor chip; And a plurality of leads electrically connected to the semiconductor chip and exposed from the sealing member, wherein at least one of the leads has a terminal portion formed as a press fit terminal.

According to another aspect of the present invention, there is provided a semiconductor power module package, wherein the semiconductor power module package further includes an external circuit board coupled to the press-fit connection terminal, And the press-fit connecting terminal may be inserted into the through-hole to be coupled to the external circuit board. The press-fit connection terminal may include deformation portions that sandwich the connection hole, and the deformation portions may be deformed by being fitted into the through holes. The width between the deformed portions that sandwich the connection hole before being deformed by being fitted in the through hole is preferably smaller than the diameter of the through hole. The deformation portions may be fitted into the through holes and deformed and closely contacted.

According to another aspect of the present invention, in a semiconductor power module package, the press-fit connection terminal may include a conductive material having elasticity. Preferably, the press-fit connecting terminal may be configured to include a copper alloy. For example, the press-fitting connecting terminal may be composed of a material selected from the group consisting of CuSn5 and CuSn5.

According to another aspect of the present invention, there is provided a semiconductor power module package, wherein the lead having the terminal portion formed of the press-fit connecting terminal is bent and elongated from the sealing member, And the sealing member are formed spaced apart from each other by a first distance and the first distance is set such that the stress applied to the sealing member when the press-fit connecting terminal is fitted in the through-hole is smaller than the allowable design stress of the sealing member And so on.

According to another aspect of the present invention, there is provided a semiconductor power module package including a plurality of leads including power leads and signal leads, The leads may be composed of the indentation connecting terminals in which the respective ends are coupled with the external circuit board. Each of the power leads may be coupled to an application terminal by welding. The power leads may comprise a copper alloy having an electrical conductivity of 75% IACS (International Annealed Copper Standard) or higher.

The power leads may be electrically connected to the substrate by soldering or wire bonding, and the signal leads may be electrically connected to the substrate by soldering or wire bonding.

The substrate may be a substrate selected from the group consisting of a Direct Bonding Copper (DBC) substrate, a printed circuit board (PCB), a flexible printed circuit board (FPCB), and an insulated metal substrate (IMS).

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor power module package.

The method of manufacturing a semiconductor power module package includes: mounting one or more semiconductor chips on a substrate; Preparing a leadframe including a plurality of leads; Electrically connecting the lead frame and the semiconductor chip; And sealing the semiconductor chip, wherein at least one of the leads may be configured as a press-fit connection terminal so that the distal end thereof is engaged with the external circuit board.

Preparing the lead frame comprises: preparing a signal lead frame including a first inner lead, a first bent portion, and a first outer lead; Preparing a lead frame for power including a first inner lead, a second inner lead, a second bent portion, and a second outer lead; And combining the signal lead frame and the power lead frame, and the first outer lead may have a distal end formed of the press-fit connecting terminal.

Bending the first bent portion such that the first outer lead extends from the first inner lead and is bent after the step of sealing the semiconductor chip; And bending the second bent portion such that the second outer lead extends from the second inner lead and is bent.

Wherein the first outer lead and the sealing member bend the first bent portion such that the first outer lead and the sealing member are spaced apart from each other by a first distance and the first distance is smaller than the first distance when the sealing- The stress applied to the member can be set to be smaller than the design allowable stress of the sealing member.

According to the semiconductor power module package and the manufacturing method thereof according to the present invention, a separate area for soldering or wire bonding is not required for connecting the external circuit board to the lead frame, so that the size of the package can be minimized. Also, it has excellent bonding force with an external circuit board, and is relatively stable from physical vibration and impact.

1 to 8 are plan views sequentially illustrating a method of manufacturing a semiconductor power module package according to an embodiment of the present invention;
Figure 9 is a side view illustrating the exposed side of the first outer lead 120 in the semiconductor power module package of Figure 8;
10 is a side view illustrating the exposed side of the second outer lead 230 in the semiconductor power module package of FIG. 8; FIG.
11 is a side view illustrating a configuration in which the first bent portion 150 and the second outer lead 230 are bent in the semiconductor power module package 800 of FIG. 8;
12 is a side cross-sectional view illustrating a configuration in which the first bent portion 150 and the second outer lead 230 are bent in the semiconductor power module package 800 of FIG. 8;
13 is a cross-sectional view illustrating a cross-section of a semiconductor power module package 900 in which a first outer lead 120 is coupled to an outer circuit board 910;
14 is an enlarged cross-sectional view showing a configuration before the first external lead 120 is coupled to the external circuit board 910;
15 is an enlarged cross-sectional view illustrating a configuration in which the first external lead 120 is coupled to the external circuit board 910;
Figs. 16 and 17 are top cross-sectional views viewed from above of the semiconductor power module package in which the external circuit board disclosed in Fig. 15 and the deformations of the first external lead are combined; Fig.
18 is a cross-sectional view illustrating a section of a semiconductor power module package with a heat sink;
19 is a cross-sectional view showing various examples of the distance between the first outer lead 120 and the sealing member 710; And
Fig. 20 is a graph illustrating the stresses applied to the sealing member in the case of Fig. 19, respectively. Fig.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The embodiments of the present invention are described in order to more fully explain the present invention to those skilled in the art, and the following embodiments may be modified into various other forms, The present invention is not limited to the embodiment. Rather, these embodiments are provided so that this disclosure will be more thorough and complete, and will fully convey the concept of the invention to those skilled in the art. In the drawings, the thickness and size of each layer are exaggerated for convenience and clarity of explanation.

When referring to one element such as a film, a region, or a substrate, etc. throughout the specification being "on", or "connected to" another element, Quot ;, "connected ", or " connected ", or intervening elements may be present. On the other hand, when one element is referred to as being "directly on" or "directly connected" to another element, it is interpreted that there are no other elements intervening therebetween. Like numbers refer to like elements. As used herein, the term "and / or" includes any and all combinations of one or more of the listed items.

Although the terms first, second, etc. are used herein to describe various elements, components, regions, layers and / or portions, these members, components, regions, layers and / It is obvious that no. These terms are only used to distinguish one member, component, region, layer or section from another region, layer or section. Thus, a first member, component, region, layer or section described below may refer to a second member, component, region, layer or section without departing from the teachings of the present invention.

Also, relative terms such as "top" or "above" and "under" or "below" can be used herein to describe the relationship of certain elements to other elements as illustrated in the Figures. Relative terms are intended to include different orientations of the device in addition to those depicted in the Figures. For example, in the figures the elements are turned over so that the elements depicted as being on the top surface of the other elements are oriented on the bottom surface of the other elements. Thus, the example "top" may include both "under" and "top" directions depending on the particular orientation of the figure. If the elements are oriented in different directions (rotated 90 degrees with respect to the other direction), the relative descriptions used herein can be interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a,""an," and "the" include singular forms unless the context clearly dictates otherwise. Also, " comprise "and / or" comprising "when used herein should be interpreted as specifying the presence of stated shapes, numbers, steps, operations, elements, elements, and / And does not preclude the presence or addition of one or more other features, integers, operations, elements, elements, and / or groups.

1 to 8 are plan views sequentially illustrating a method of manufacturing a semiconductor power module package according to an embodiment of the present invention. The coordinate axes shown in Figs. 1 to 8 indicate that the paper surface is the XY plane, the rightward direction on the paper surface is the X direction, the upward direction on the paper is the Y direction, and the direction in which the paper surface extends forward is the Z direction .

1 is a plan view illustrating a signal lead frame according to an embodiment of the present invention.

Referring to FIG. 1, the signal lead frame 100 includes a plurality of first inner leads 110, a first bent portion 150, and a first outer lead 120. The distal end of the first outer lead 120 may be configured as a press fit terminal. The signal lead frame 100 has a connection part 130 for connecting a plurality of first external leads 120 to each other. On the other hand, first regions 140 for coupling with power lead frames may be disposed on the left and right sides of the signal lead frame 100, respectively.

The signal lead frame 100 may include a conductive material having elasticity. For example, the signal leadframe 100 may comprise a copper alloy having a high yield strength and a high yield strain. Specifically, the signal lead frame 100 may be composed of a material selected from the group consisting of CuSn5, CuSn5, and K75 having a yield strength of about 500 MPa.

2 is a plan view illustrating a power lead frame according to an embodiment of the present invention.

Referring to FIG. 2, the power lead frame 200 includes a plurality of second inner leads 210, a second bent portion 220, and a second outer lead 230. A connecting portion for connecting the plurality of second outer leads 230 is formed at the lower end of the power lead frame 200. On the other hand, a second region 240 for coupling with the signal lead frame 100 may be disposed on the left and right sides of the power lead frame 200, respectively.

The lead frame 200 for power may be configured to include a copper alloy whose electrical conductivity is 75% IACS (International Annealed Copper Standard) or more. The International Annealed Copper Standard (IACS), a unit of electrical conductivity, refers to the percentage of 5.8108 x 10 ⁷ S / m, which is the electrical conductivity of the annealed copper wires (pure copper wire) at 20 ° C. Copper alloys having an electrical conductivity of 75% IACS (International Annealed Copper Standard) or higher are, for example, TAMAC2, TAMAC4, OFC and the like.

3 is a plan view illustrating a lead frame 300 in which a signal lead frame 100 and a power lead frame 200 are combined.

Referring to FIG. 3, the first region 140 of the signal lead frame 100 shown in FIG. 1 and the second region 240 of the power lead frame 200 shown in FIG. 2 are overlapped with each other, (300). For example, the signal lead frame 100 and the power lead frame 200 can be joined by riveting the first region 140 and the second region 240. [

4 is a plan view illustrating a substrate 400 on which a semiconductor chip is mounted.

The substrate on which the semiconductor chip according to the present invention is mounted may be a DBC (Direct Bonding Copper) substrate, a printed circuit board (PCB), a flexible printed circuit board (FPCB), or an insulating metal substrate (IMS).

Referring to FIG. 4, the substrate on which the semiconductor chip 450 is mounted may be a DBC (Direct Bonding Copper) substrate, for example. Referring to FIG. 12, the DBC substrate 410 includes a ceramic insulating film 412, an upper conductive film pattern 411 disposed on the upper surface of the ceramic insulating film 412, And a lower conductive film pattern 413 disposed on the lower surface of the ceramic insulating film 412.

The ceramic insulating film 412 may include an Al ₂ O ₃ film, an AlN film, a SiO ₂ film, a SiN film, or a BeO film. The upper conductive film pattern 411 and the lower conductive film pattern 413 may include a Cu film pattern. For example, the upper conductive film pattern 411 and the lower conductive film pattern 413 may include a plated Cu film pattern selected from the group consisting of Ni, Au, and Ag, or may include a bare Cu film pattern . ≪ / RTI > The upper conductive film pattern 411 may be formed of a plurality of conductive film patterns electrically separated from each other. At least one semiconductor chip 450 is mounted on the upper conductive film pattern 411, for example, by a process of solder printing.

5 is a plan view illustrating a configuration in which a substrate on which a semiconductor chip is mounted and a lead frame are arranged.

Referring to FIG. 12 together with FIG. 5, a top view of the substrate 410 is shown in FIG. 12, which illustrates a cross section of a configuration in which the lead frames 220, 230, 120 and 150, the substrate 410 and the semiconductor chip 450 are disposed. The lead frame 200 for power may be coupled. Specifically, the second inner leads 210 of the power lead frame 200 may be coupled to the upper conductive film pattern 411 of the substrate 410, and may be coupled and electrically connected by soldering. However, it is apparent from the technical idea of the present invention that the substrate 410 and the power lead frame 200 may be electrically connected by various methods other than soldering, and may be electrically connected, for example, by wire bonding.

The signal lead frame 100 may also be connected to the substrate 410. Specifically, the first inner lead 110 of the signal lead frame 100 may be coupled to the upper conductive film pattern 411 of the substrate 410, and may be electrically connected by a bonding wire. However, it is apparent from the technical idea of the present invention that the substrate 410 and the signal lead frame 100 may be electrically connected by various methods other than wire bonding, and may be electrically connected by, for example, soldering.

6 is a plan view illustrating a configuration for electrically connecting a lead frame and a semiconductor chip.

12 is a cross-sectional view of a configuration for electrically connecting the lead frames 220, 230, 120 and 150, the substrate 410 and the semiconductor chip 450 in FIG. 12. Referring to FIG. 6 together with FIG. 12, 450 and the first inner lead 110 of the signal lead frame 100 can be electrically connected by the bonding wire 650. [ In addition, the semiconductor chip 450 and the upper conductive film pattern 411 of the substrate 410 may be electrically connected by the bonding wire 650. The bonding wire 650 may include a first bonding wire 610 having a narrow width and a second bonding wire 620 having a wide width depending on the electrical use to which the bonding wire 650 is connected. For example, the first bonding wire 610 may have a width of 6 mm, and the second bonding wire 620 may have a width of 12 mm.

7 is a plan view showing a sealing member sealing the semiconductor chip. 12, the sealing member 710 seals the semiconductor chip 450, and the sealing member 710 seals the semiconductor chip 450. The sealing member 710 includes a sealing member 710 sealing the semiconductor chip 450, The first inner lead 410, the second inner lead 210, and / or the first inner lead 110.

Specifically, the sealing member 710 is preferably formed to expose the lower surface of the lower conductive film pattern 413 of the substrate 410 to the outside. This structure is intended to allow heat to be radiated through the lower surface of the lower conductive film pattern 413. In order to further accelerate the heat emission, a heat sink 413, which contacts the lower surface of the exposed lower conductive film pattern 413, May be disposed.

Also, the sealing member 710 is preferably formed to expose at least a part of the first bent portion 150 and / or the second bent portion 220. That is, the first bent portion 150 is bent so that the first outer lead 120 extends from the first inner lead 110 and bent, and the second outer lead 230 is extended from the second inner lead 210 It is preferable that at least a part of the first bent portion 150 and / or the second bent portion 220 is exposed by the sealing member 710 because the second bent portion 220 is bent so as to bend.

8 is a plan view illustrating a top surface of a semiconductor power module package that has been subjected to a trimming and bending operation of a lead frame, and FIG. 9 is a side view of the semiconductor power module package of FIG. And FIG. 10 is a side view illustrating the exposed side of the second outer lead 230 in the semiconductor power module package of FIG.

The coordinate axes shown in Fig. 9 indicate that the paper surface is the YZ plane, the left direction on the paper surface is the Y direction, the upward direction on the paper is the Z direction, and the direction in which the paper surface extends forward from the paper surface is the X direction. The coordinate axes shown in Fig. 10 indicate that the paper surface is the ZX plane, the rightward direction on the paper surface is the X direction, the upward direction on the paper is the Z direction, and the direction in which the paper surface advances from the paper surface is the -Y direction .

6 to 9, the signal lead frame 100 is bent at the first bent portion 150 such that the first outer lead 120 extends from the first inner lead 110 and is bent. The power lead frame 200 is bent at the second bent portion 220 so that the second outer lead 230 extends from the second inner lead 210 and is bent.

Meanwhile, in the signal lead frame 100, a connecting portion (130 in FIG. 1) connecting the plurality of first outer leads 120 is trimmed and removed in order to individually form the plurality of first outer leads 120. Similarly, in order to separately form the plurality of second outer leads 230 in the power lead frame 200, a connection portion (250 in FIG. 2) connecting the plurality of second outer leads 230 is trimmed and removed .

In the method of manufacturing a semiconductor power module package according to the present invention, a trimming step may be performed after the bending step of the lead frame, but a bending step may be performed after the trimming step of the lead frame.

9 and 10 show that the sealing member 710 is composed of the upper sealing member 711 and the lower sealing member 712. [

FIG. 11 is a side view illustrating a configuration in which the first bent portion 150 and the second outer lead 230 are bent in the semiconductor power module package 800 of FIG. 8. FIG. 12 is a cross- 800 are folded at the first bent portion 150 and the second outer lead 230. As shown in FIG. The coordinate axes shown in Figs. 11 and 12 indicate that the paper surface is the YZ plane, the rightward direction on the paper surface is the Y direction, the upward direction on the paper is the Z direction, and the direction in which the paper surface extends forward is the X direction .

11 and 12, illustratively, the second outer lead 230 of the power lead frame 200 may face the upper direction (Z direction) of the semiconductor power module package, and the signal lead frame 100 May be oriented in the downward direction (-Z direction) of the semiconductor power module package. However, the combination of the orientations of the first outer lead 120 and / or the second outer lead 230 may vary. For example, the first outer lead 120 may be oriented in the Z direction and the second outer lead 230 may be oriented in the -Z direction. Also, the first outer lead 120 and the second outer lead 230 may all face the same direction.

The first bending part 150 may be bent such that the first outer lead 120 and the sealing member 710, particularly the bottom sealing member 712, are spaced apart from each other by a first distance W1. The first distance W1 is set such that the stress applied to the sealing member 710 when the first external lead 120 is fitted to the external circuit board 910 of Fig. 13 is greater than the allowable design stress of the sealing member 710 Is set to be small.

13 is a sectional view illustrating a section of a semiconductor power module package 900 in which a first outer lead 120 is coupled to an outer circuit board 910. FIG. FIG. 15 is an enlarged cross-sectional view illustrating a configuration in which the first external lead 120 is coupled to the external circuit board 910. As shown in FIG.

The coordinate axes shown in Figs. 14 and 15 indicate that the paper surface is in the XZ plane, the leftward direction on the paper is the X direction, the upward direction on the paper is the Z direction, and the direction in which the paper advances from the paper surface is the Y direction .

13, the first external lead 120 of the signal lead frame 100 may be connected to the external circuit board 910 in a press fit manner, and the second external lead 120 of the signal lead frame 100 may be connected to the external circuit board 910, The external leads 230 may be connected to an application terminal (not shown) by a welding method.

14 and 15, the first outer lead 120 may be configured as a press fit terminal. Specifically, the first outer lead 120 may include a body portion 121, deformation portions 122 between the connection holes C, and a penetration portion 123.

The external circuit board 910 includes a substrate body 911 and a through hole H penetrating the substrate body 911 in a height direction (Z direction). A conductive side wall portion 912 made of a conductive material is formed on a sidewall of the substrate body portion 911 in which the through hole H is formed.

Preferably, the width W2 between the deformed portions 122, which sandwich the connection hole C, is larger than the diameter W3 of the through hole H. [ Therefore, in order for the deformed portions 122 to be inserted and inserted into the through holes H, the first outer leads 120, particularly the deformed portions 122, are preferably made of a material having elasticity, and the deformed portions 122 Can be deformed to fit in the through hole H and the size of the connection hole C can be made smaller than that before the insertion of the deformed portions 122. [ The deformation may include elastic deformation and / or plastic deformation.

Figs. 16 and 17 are top cross-sectional views of the semiconductor power module package viewed from above, showing a configuration in which the external circuit board disclosed in Fig. 15 and the deformations of the first external lead are combined. The coordinate axes shown in Figs. 16 and 17 indicate that the paper surface is in the XY plane, the left direction on the paper is the X direction, the downward direction on the paper is the Y direction, and the direction in which the paper surface extends forward is the Z direction .

16, the deformation portions 122 of the first outer lead 120 are fitted and deformed in the through-holes H formed by the conductive side wall portions 912. As shown in FIG. However, the deformed portions 122 of the deformed first outer lead 120 do not contact each other.

17, the deformed portions 122 of the first outer lead 120 are fitted and deformed in the through hole H formed by the conductive side wall portion 912, and the deformed portions of the deformed first outer lead 120 The deformed portions 122 are brought into close contact with each other. When the deformed portions 122 are closely contacted, it is possible that the width of each of the deformed portions 122 is large, so that the connection hole C is relatively small or the diameter of the through hole H is relatively small.

18 is a cross-sectional view illustrating a section of a semiconductor power module package with a heat sink.

18, the lower surface of the lower conductive film pattern 413 is exposed by the sealing member 710. The lower surface of the lower conductive film pattern 413 is in contact with the heat sink 1010, Can be performed.

19 is a cross-sectional view showing various examples of the distance between the first outer lead 120 and the sealing member 710, and FIG. 20 is a graph showing stresses applied to the sealing member in the cases of FIG. 19 to be. The coordinate axes shown in FIG. 19 indicate that the paper surface is a YZ plane, the leftward direction on the paper surface is the Y direction, the upward direction on the paper is the Z direction, and the direction in which the paper surface extends forward is the -X direction.

19 and 20, the first outer lead 120 is bent at the first bent portion 150 of the signal lead frame 100 so that the first outer lead 120 is separated from the sealing member, particularly, the lower sealing member 712 by a predetermined distance Respectively. In this case, the predetermined distance is set so that the stress applied to the sealing member when the first outer lead 120 constituted by the press-fit connection terminal is fitted into the through hole of the external circuit board is smaller than the design allowable stress of the sealing member .

For example, in the case of Experiment A, the first outer lead 120 is bent at the first bent portion 150 of the signal lead frame 100 so that the sealing member, particularly the lower sealing member 712, In the case of Experiment B, the first outer lead 120 is bent at the first bent portion 150 of the signal lead frame 100 so that the first outer lead 120 is separated from the sealing member, particularly, the lower sealing member 712, And 2.6 mm (W5).

20, in the case of Experiments A and B, a force for inserting the first outer lead 120, which is a press-fit connecting terminal, into the through hole of the outer circuit board (in FIG. 20, The value of the stress applied to the sealing member (the value of the ordinate in FIG. 20, unit: Mpa) increases as the value of the stress increases.

For example, if the design permissible stress of the sealing member is 154 MPa, the force for inserting the first outer lead 120 constituted by the press-fit connecting terminal into the through hole of the outer circuit board is preferably less than about 120 N . More preferably, when the design allowable stress of the sealing member is 154 MPa, the first outer lead 120 constituted by the press-fit connection terminal is inserted into the through hole of the outer circuit board so as to reflect the safety factor of 20% The force may be less than about 100N.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but many variations and modifications may be made by those skilled in the art .

100: Signal lead frame
200: Lead frame for power
110: first inner lead
150: first bent portion
120: 1st outer lead
210: second inner lead
220: second bend
230: Second outer lead

Claims (20)

One or more semiconductor chips on a substrate;
A sealing member sealing the semiconductor chip;
A plurality of leads electrically connected to the semiconductor chip and partially exposed from the sealing member; And
And an external circuit board coupled to the press-fit connecting terminal,
Wherein the external circuit board has a through hole penetrating the external circuit board in the height direction,
At least one of the leads has a terminal portion formed as a press fit terminal, the press-fit connecting terminal is fitted into the through hole and is coupled to the external circuit board,
Wherein the press-fit connecting terminal includes deformation portions which sandwich the connection hole, the deformation portions being deformed by being fitted in the through holes,
And a width between the deformed portions which sandwich the through hole and before the deformed portion is inserted into the through hole is larger than the diameter of the through hole. One or more semiconductor chips on a substrate;
A sealing member sealing the semiconductor chip;
A plurality of leads electrically connected to the semiconductor chip and partially exposed from the sealing member; And
And an external circuit board coupled to the press-fit connecting terminal,
At least one of said leads has a distal end configured as a press fit terminal,
Wherein the external circuit board has a through hole passing through the external circuit board in the height direction, the press-in connecting terminal is inserted into the through hole and is coupled to the external circuit board,
The lead having the terminal portion formed of the press-fit connecting terminal is elongated and bent from the sealing member, and the bent lead and the sealing member are spaced apart from each other by a first distance, Is set to be smaller than a design allowable stress of the sealing member when the sealing member is fitted into the through-hole. delete delete The method according to claim 1,
And the deformation portions are fitted into the through holes and deformed and brought into close contact with each other. The method according to claim 1,
Wherein the press-fit connection terminal comprises a conductive material having elasticity. The method according to claim 1,
Wherein the press-fit connection terminal comprises a copper alloy. The method according to claim 1,
Wherein the press-fit connection terminal is made of a material selected from the group consisting of CuSn5 and CuSn5. The method according to claim 1,
The lead whose distal end is constituted by the press-fit connecting terminal is elongated and bent from the sealing member,
The bent lead and the sealing member are spaced apart from each other by a first distance, and
Wherein the first distance is set so that a stress applied to the sealing member when the press-fit connecting terminal is fitted in the through-hole is smaller than a design allowable stress of the sealing member. The method according to claim 1,
The plurality of leads are configured to include power leads and signal leads,
Wherein the signal leads are each comprised of a press-fit connection terminal, the distal end of each of which is coupled to an external circuit board. 11. The method of claim 10,
Wherein the power leads are each coupled to an application terminal by welding. 11. The method of claim 10,
Wherein the power leads comprise a copper alloy having an electrical conductivity of 75% IACS (International Annealed Copper Standard) or greater. 11. The method of claim 10,
Wherein the power leads are electrically connected to the substrate by soldering or wire bonding. 11. The method of claim 10,
Wherein the signal leads are electrically connected to the substrate by soldering or wire bonding. The method according to claim 1,
Wherein the substrate is a substrate selected from the group consisting of a Direct Bonding Copper (DBC) substrate, a printed circuit board (PCB), a flexible printed circuit board (FPCB), and an insulated metal substrate (IMS). The method according to claim 1,
Further comprising a heat sink in contact with a lower portion of the substrate. Mounting one or more semiconductor chips on a substrate;
Preparing a leadframe including a plurality of leads;
Electrically connecting the lead frame and the semiconductor chip; And
And forming a sealing member for sealing the semiconductor chip,
At least one of the leads is formed as a press-fit connection terminal so that the distal end thereof is engaged with the external circuit board,
Wherein the at least one lead and the sealing member bend the at least one lead exposed to the outside of the sealing member such that the at least one lead and the sealing member are spaced apart from each other by a first distance,
Wherein the first distance is set so that a stress applied to the sealing member when the press-fit connecting terminal is fitted into the through hole formed in the external circuit board is smaller than a design allowable stress of the sealing member. A method of manufacturing a package. 18. The method of claim 17,
The step of preparing the lead frame
Preparing a signal lead frame including a first inner lead, a first bent portion, and a first outer lead;
Preparing a lead frame for power including a first inner lead, a second inner lead, a second bent portion, and a second outer lead; And
And combining the signal lead frame and the power lead frame, and
Wherein the first external lead has a terminal portion formed by the press-fit connection terminal. 19. The method of claim 18,
After the step of forming the sealing member,
Bending the first bent portion such that the first outer lead extends from the first inner lead and is bent; And
And bending the second bent portion such that the second outer lead extends from the second inner lead and is bent. ≪ Desc / Clms Page number 19 > 20. The method of claim 19,
The first outer lead and the sealing member bend the first bent portion such that the first outer lead and the sealing member are spaced apart from each other by the first distance,
Wherein the first distance is set so that a stress applied to the sealing member when the press-fit connecting terminal is fitted into the through hole formed in the external circuit board is smaller than a design allowable stress of the sealing member. A method of manufacturing a package.

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