JP2015208765A - 無鉛はんだ材、電力用半導体装置、および電力用半導体装置の製造方法 - Google Patents
無鉛はんだ材、電力用半導体装置、および電力用半導体装置の製造方法 Download PDFInfo
- Publication number
- JP2015208765A JP2015208765A JP2014092241A JP2014092241A JP2015208765A JP 2015208765 A JP2015208765 A JP 2015208765A JP 2014092241 A JP2014092241 A JP 2014092241A JP 2014092241 A JP2014092241 A JP 2014092241A JP 2015208765 A JP2015208765 A JP 2015208765A
- Authority
- JP
- Japan
- Prior art keywords
- power semiconductor
- lead
- particles
- free solder
- diameter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2014092241A JP2015208765A (ja) | 2014-04-28 | 2014-04-28 | 無鉛はんだ材、電力用半導体装置、および電力用半導体装置の製造方法 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2014092241A JP2015208765A (ja) | 2014-04-28 | 2014-04-28 | 無鉛はんだ材、電力用半導体装置、および電力用半導体装置の製造方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2015208765A true JP2015208765A (ja) | 2015-11-24 |
| JP2015208765A5 JP2015208765A5 (enExample) | 2017-03-09 |
Family
ID=54611433
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2014092241A Pending JP2015208765A (ja) | 2014-04-28 | 2014-04-28 | 無鉛はんだ材、電力用半導体装置、および電力用半導体装置の製造方法 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2015208765A (enExample) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116316047A (zh) * | 2023-05-17 | 2023-06-23 | 苏州长光华芯光电技术股份有限公司 | 一种高可靠性半导体封装结构及其制备方法 |
| WO2025254166A1 (ja) * | 2024-06-05 | 2025-12-11 | 三菱マテリアル株式会社 | はんだペースト、はんだ接合体、および、はんだ接合体の製造方法 |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59215294A (ja) * | 1983-05-24 | 1984-12-05 | Toshiba Corp | 半田接合材料とその材料を使用した接合方法 |
| JPS62179889A (ja) * | 1986-01-31 | 1987-08-07 | Senjiyu Kinzoku Kogyo Kk | クリ−ムはんだ |
| JPH0639583A (ja) * | 1992-07-27 | 1994-02-15 | Toshiba Lighting & Technol Corp | 半田ペースト及び回路基板 |
| JP2002254194A (ja) * | 2000-06-12 | 2002-09-10 | Hitachi Ltd | 電子機器およびはんだ |
| JP2005167257A (ja) * | 2000-12-25 | 2005-06-23 | Tdk Corp | はんだ付け方法 |
| JP2009125753A (ja) * | 2007-11-20 | 2009-06-11 | Toyota Central R&D Labs Inc | はんだ材料及びその製造方法、接合体及びその製造方法、並びにパワー半導体モジュール及びその製造方法 |
| WO2013017885A2 (en) * | 2011-08-02 | 2013-02-07 | Fry's Metals, Inc. | Solder compositions |
-
2014
- 2014-04-28 JP JP2014092241A patent/JP2015208765A/ja active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59215294A (ja) * | 1983-05-24 | 1984-12-05 | Toshiba Corp | 半田接合材料とその材料を使用した接合方法 |
| JPS62179889A (ja) * | 1986-01-31 | 1987-08-07 | Senjiyu Kinzoku Kogyo Kk | クリ−ムはんだ |
| JPH0639583A (ja) * | 1992-07-27 | 1994-02-15 | Toshiba Lighting & Technol Corp | 半田ペースト及び回路基板 |
| JP2002254194A (ja) * | 2000-06-12 | 2002-09-10 | Hitachi Ltd | 電子機器およびはんだ |
| JP2005167257A (ja) * | 2000-12-25 | 2005-06-23 | Tdk Corp | はんだ付け方法 |
| JP2009125753A (ja) * | 2007-11-20 | 2009-06-11 | Toyota Central R&D Labs Inc | はんだ材料及びその製造方法、接合体及びその製造方法、並びにパワー半導体モジュール及びその製造方法 |
| WO2013017885A2 (en) * | 2011-08-02 | 2013-02-07 | Fry's Metals, Inc. | Solder compositions |
| JP2014527466A (ja) * | 2011-08-02 | 2014-10-16 | アルファ・メタルズ・インコーポレイテッドAlpha Metals,Inc. | はんだ組成物 |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116316047A (zh) * | 2023-05-17 | 2023-06-23 | 苏州长光华芯光电技术股份有限公司 | 一种高可靠性半导体封装结构及其制备方法 |
| CN116316047B (zh) * | 2023-05-17 | 2023-08-15 | 苏州长光华芯光电技术股份有限公司 | 一种高可靠性半导体封装结构及其制备方法 |
| WO2025254166A1 (ja) * | 2024-06-05 | 2025-12-11 | 三菱マテリアル株式会社 | はんだペースト、はんだ接合体、および、はんだ接合体の製造方法 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP6895131B2 (ja) | 半導体装置用はんだ材 | |
| CN1076998C (zh) | 软钎料及使用该软钎料的电子器件 | |
| KR101773733B1 (ko) | 파워 디바이스용의 땜납 합금과 고전류 밀도의 땜납 조인트 | |
| US9847310B2 (en) | Flip chip bonding alloys | |
| JP2014135411A (ja) | 半導体装置および半導体装置の製造方法 | |
| JP7215206B2 (ja) | 半導体装置の製造方法 | |
| JP3827322B2 (ja) | 鉛フリーはんだ合金 | |
| JP2011138968A (ja) | 面実装部品のはんだ付け方法および面実装部品 | |
| CN105006471A (zh) | 一种igbt模块及焊接方法 | |
| TW201334907A (zh) | 錫銅系無鉛焊錫合金 | |
| WO2014024271A1 (ja) | 高温鉛フリーはんだ合金 | |
| JP6641524B1 (ja) | 半導体装置の製造方法 | |
| KR102259122B1 (ko) | 접합 구조체의 제조 방법 | |
| JP2005340268A (ja) | トランジスタパッケージ | |
| JP2015208765A (ja) | 無鉛はんだ材、電力用半導体装置、および電力用半導体装置の製造方法 | |
| US20190013308A1 (en) | Die bonding to a board | |
| US7413110B2 (en) | Method for reducing stress between substrates of differing materials | |
| JP6083451B2 (ja) | 面実装部品のはんだ付け方法および面実装部品 | |
| CN108284286B (zh) | 用于芯片焊接的钎焊合金 | |
| JP2012061508A (ja) | 接合材料 | |
| JP5941036B2 (ja) | 面実装部品のはんだ付け方法および面実装部品 | |
| JP2012049182A (ja) | 半導体装置の製造方法 | |
| JP6036905B2 (ja) | 面実装部品のはんだ付け方法および面実装部品 | |
| WO2009093335A1 (ja) | 熱容量制御材料及び部品実装方法 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20170203 |
|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20170203 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20180124 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20180306 |
|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20181002 |