JP2011138968A - 面実装部品のはんだ付け方法および面実装部品 - Google Patents
面実装部品のはんだ付け方法および面実装部品 Download PDFInfo
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- JP2011138968A JP2011138968A JP2009298932A JP2009298932A JP2011138968A JP 2011138968 A JP2011138968 A JP 2011138968A JP 2009298932 A JP2009298932 A JP 2009298932A JP 2009298932 A JP2009298932 A JP 2009298932A JP 2011138968 A JP2011138968 A JP 2011138968A
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- H01L23/495—Lead-frames or other flat leads
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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Abstract
【解決手段】ダイパット用はんだ材料30として、Cuの含有量が所定値以下のSnを主成分とする(Sn−Sb)系の高融点はんだ材料を使用して形成された面実装部品を、回路基板の基板端子部に塗布された実装用はんだ材料70として、(Sn−Ag−Cu−Bi)系はんだ材料を用いてはんだ付けする。ダイボンド用はんだ材料30の固相線温度は243℃であり、実装用はんだ材料70の液相線温度は215〜220℃程度であるので、リフロー炉の加熱温度(240℃以下)によってもダイボンド用はんだ材料30は溶解しない。
【選択図】 図1
Description
しかしながら、これらをダイボンド用はんだ材料として用いて熱膨張係数が大きく異なる部材を接合した場合でも、はんだ接合部にかかる歪みが過大となり、熱サイクル性能に顕著な改善効果が見られないという問題があった。
以下に示す実施例では、回路素子としてウエハから切り出された半導体素子(ICチップ)を面実装する場合について説明する。したがって回路基板としてはプリント基板が使用されている。
Snを主成分とする(Sn−Sb)系はんだ材料である。
(表1)には、(Sn−Sb)系はんだ材料として、Cuを含有するものと、そうでない2種類のはんだ材料を示す。(Sn−10Sb)系はんだ材料は、0.1質量%以下の不純物を含む。また、(Sn−10Sb)系はんだ材料それ自身の固相線温度は245℃であり、液相線温度は268℃である。
(表2)では、ダイボンド用はんだ材料30として(Sn−10Sb)系のはんだ材料を使用し、実装用はんだ材料70として(Sn−Ag−Cu−Bi)系のはんだ材料を使用した場合である。
(表3)の例は、実装用はんだ材料70として(表2)に示した成分の他にInを添加した(Sn−Ag−Cu−Bi−In)系のはんだ材料を使用した場合である。
(1)実装用はんだ材料70としては、(表2)以下に示す組成比となされた
(Sn−Ag−Cu−Bi)系のはんだ材料若しくはこれにInを添加した(表3)以下に示す組成比となされた(Sn−Ag−Cu−Bi−In)系のはんだ材料が好適である。
(2)ダイボンド用はんだ材料30としては、(Sn−10Sb)系のはんだ材料であって、0.1質量%以下の不純物に含まれるCuの含有量が0.01質量%以下に抑えたはんだ材料が好適である。特にCuの含有量が0.005質量%以下、好ましくは0.001質量%以下であることが好ましい。
(3)なお、上述した(Sn−Sb)系はんだ材料をダイボンド用はんだ材料30として使用するとき、これにPを添加することもできる。上述した(Sn−Sb)系はんだ材料にさらに、Pを微量に添加すると、濡れ性と共にボイドの改善に繋がる。
(4)上述した(3)の(Sn−Sb)系はんだ材料に、さらに(Ni,Fe,Co)の一種以上の成分を添加することもできる。Pの代わりに(Ni,Fe,Co)の一種以上の成分を添加してもよい。
14,24・・・Niメッキ層
16,26・・・Auメッキ層
20・・・リードフレーム
22・・・ダイパット電極部(アイランド部)
34・・・リード部
34a・・・内部端子部
34b・・・外部端子部
30・・・ダイボンド用はんだ材料
38・・・放熱板
40・・・電極ワイヤ
50・・・面実装部品
60・・・プリント基板
62・・・基板端子部(ランド)
70・・・実装用はんだ材料
Claims (9)
- Niメッキ層が形成された電極面を有する回路素子が、Niメッキ層が形成されたリードフレームのダイパット電極面に、Cuの含有量が所定値以下のSnを主成分とする(Sn−Sb)系はんだ材料を用いて、はんだ付けされた面実装部品を、回路基板の基板端子部に塗布された(Sn−Ag−Cu−Bi)系はんだ材料を実装用はんだ材料として用いてはんだ付けする
ことを特徴とする面実装部品のはんだ付け方法。 - 上記(Sn−Sb)系はんだ材料中のSbは10〜13質量%、好ましくは10〜11質量%で、上記Cuは0.01質量%以下、好ましくは0.005質量%以下である
ことを特徴とする請求項1記載の面実装部品のはんだ付け方法。 - 上記(Sn−Sb)系はんだ材料に、さらにP又はおよび1種以上のNi,Co,Feからなる機械的強度改善成分が添加された
ことを特徴とする請求項1または請求項2記載の面実装部品のはんだ付け方法。 - 添加される上記Pは0.0001〜0.01質量%であり、上記Ni,Co,Feは0.01〜0.1質量%である
ことを特徴とする請求項3記載の面実装部品のはんだ付け方法。 - 上記面実装部品に使用されるリードフレームのリード部は、Snメッキ層又はSn−Biメッキ層で被覆されてなる
ことを特徴とする請求項1記載の面実装部品のはんだ付け方法。 - 上記実装用はんだ材料として、Agが3〜3.5質量%、Cuが0.5〜1.0質量%、Biが3〜7質量%好ましくは3〜5質量%、残部がSnである(Sn−Ag−Cu−Bi)系はんだ材料が使用される
ことを特徴とする請求項1記載の面実装部品のはんだ付け方法。 - 上記実装用はんだ材料として、さらにInが添加された
ことを特徴とする請求項1および6記載の面実装部品のはんだ付け方法。 - 上記Biは2〜5質量%であって、上記Inは3〜5質量%である
ことを特徴とする請求項7記載の面実装部品のはんだ付け方法。 - 回路素子が載置されるダイパット電極部と回路基板に接合されるリード部からなり、上記アイランド部にはNiメッキ層が形成されたリードフレームと、
上記ダイパット電極部に対して、Cuの含有量が所定値以下のSnを主成分とする(Sn−Sb)系はんだ材料を介して接合される、Niメッキ層をその接合面とする回路素子と、
上記リード部が、(Sn−Ag−Cu−Bi)系はんだ材料、若しくは(Sn−Ag−Cu−Bi−In)系はんだ材料を介して、基板端子部を構成するランド部に接合される回路基板とからなる
ことを特徴とする面実装部品。
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US13/519,217 US10354944B2 (en) | 2009-12-28 | 2010-12-22 | Method for soldering surface-mount component and surface-mount component |
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EP10841068.9A EP2521429B1 (en) | 2009-12-28 | 2010-12-22 | Method for soldering surface-mount component and surface-mount component |
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