JP2015138898A - Lead frame, semiconductor device and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a lead frame, a semiconductor device and an electronic apparatus, which can ensure sufficient solder thickness without hindering a stress relaxation function by a lead terminal.SOLUTION: A lead frame comprises: a lead terminal 21 which is solder bonded to a land 4 and subjected to solder plating 27 for improving solder wettability, in which an intermediate part of the lead terminal 21 in a longer direction of the high wettability region subjected to the solder plating 27 is covered annularly with a low wettability member 28 having wettability lower than that of the other region.

Description

  The present invention relates to a lead frame including a plurality of leads to be soldered, a semiconductor device, and an electronic device.

  A semiconductor device such as a SOP (Small Outline Package) or a QFP (Quad Flat Package) is mounted on a circuit board by soldering each lead terminal of the lead frame to a land on the circuit board. As described above, when solder is used for electrical connection between the semiconductor device and the circuit board, thermal fatigue due to the difference in thermal expansion coefficient between the semiconductor device and the circuit board may accumulate, and the solder may crack. . Therefore, surface treatment such as plating is applied to each lead terminal to improve the solder wettability of the lead terminal. This makes it easier for the solder to wet the lead terminal, and increases the joint area between the lead terminal and the solder. Bonding strength is improved.

  As a technique relating to such solder bonding, a lead frame of a semiconductor package disclosed in Patent Document 1 below is known. The lead frame is provided with a frame-like member that supports the vicinity of the upper end at each end in the lead-out direction of the outer lead, and the boundary between the outer lead and the frame-like member is a line along the side surface of the outer lead. Is disconnected. For this reason, a cut surface without plating with the base of the outer lead exposed is formed in the vicinity of the upper end portion of the side surface of the outer lead, and the lower portion excluding the cut surface is in a plated state. As a result, the solder does not come into contact with the cut surface having poor wettability and wets along the side surface below, so that the bonding area between the solder and the outer lead is increased to increase the bonding strength.

JP 2007-214185 A

  Incidentally, in order to improve the solder life, it is necessary to increase the distance between the land and the end portion of the lead terminal facing the land (hereinafter also referred to as the solder thickness). This is because by securing a sufficient solder thickness, the shear stress caused by the difference in thermal expansion coefficient can be absorbed by the solder.

  However, if the solder wettability of the surface of each lead terminal is increased as described above, the solder may overwhelm the lead terminal, and in this case, it is interposed between the land and the end of the lead terminal. Since the amount of solder to be reduced is reduced, the solder thickness may not be sufficiently secured.

  In addition, if most of each lead terminal is covered with wet solder, the lead terminal rigidity may increase unnecessarily. When the rigidity is increased in this way, the stress relaxation function required for the lead terminal is lowered, and there is a problem that cracks due to thermal stress or the like are likely to occur in the solder.

  SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a lead frame, a semiconductor device, and a semiconductor device capable of ensuring a sufficient solder thickness without impairing the stress relaxation function of the lead terminals. It is to provide an electronic device.

In order to achieve the above object, the invention described in claim 1 includes a plurality of lead terminals (21) led out from a sealing member (13) in which a semiconductor element (11) is sealed. In the lead frame (20) in which the end (24) of the lead terminal is soldered to the land (4) of the circuit board (3), the lead terminal has a surface treatment (27) for improving solder wettability. The intermediate portion of the lead terminal in the longitudinal direction of the high wettability region that has been subjected to the surface treatment is annularly covered with a low wettability member (28) having lower solder wettability than the other regions. It is characterized by.
In addition, the code | symbol in the parenthesis of a claim and the said means shows a corresponding relationship with the specific means as described in embodiment mentioned later.

  According to the first aspect of the present invention, the lead terminals soldered to the lands of the circuit board are subjected to a surface treatment for improving the solder wettability, and the length of the lead terminal in the high wettability region subjected to the surface treatment. The direction intermediate portion is annularly covered with a low wettability member having lower solder wettability than other regions.

  As a result, the solder that has wetted the high wettability region from the end portion of the lead terminal reaches the low wettability member disposed at the intermediate portion in the longitudinal direction, and the wettability is suppressed. That is, while the low wettability member suppresses the solder wet-up, the solder wet-up amount and the wet-up position can be controlled according to the position of the low wettability member. Therefore, a sufficient solder thickness can be ensured without impairing the stress relaxation function by the lead terminal.

It is sectional drawing which shows schematic structure of the electronic device which concerns on 1st Embodiment. FIG. 2 is a top view showing the semiconductor device of FIG. 1. It is sectional drawing by the cut surface equivalent to the XX line of FIG. FIG. 4 is an enlarged cross-sectional view showing the vicinity of the lead terminal in FIG. 3 in an enlarged manner. FIG. 6 is an enlarged cross-sectional view showing an enlarged lead frame according to a first modification of the first embodiment. It is a top view which shows the semiconductor device which concerns on the 2nd modification of 1st Embodiment. It is an expanded sectional view showing an important section of a lead frame concerning a 2nd embodiment.

[First Embodiment]
Hereinafter, a first embodiment embodying a lead frame, a semiconductor device, and an electronic device according to the present invention will be described with reference to the drawings.
The electronic device 1 shown in FIG. 1 is employed in an environment where the temperature change is large, and is configured as an electronic control unit (Electronic Control Unit) that controls in-vehicle equipment such as an engine mounted on the vehicle, for example. . The electronic device 1 is configured by housing a printed circuit board (circuit board) 3, another board, and the like in a housing 2.

  A semiconductor device 10, an external connector 3 b, and the like are mounted on the mounting surface 3 a of the printed circuit board 3. The semiconductor device 10 is solder-bonded via lands 4 and solder 5 arranged at predetermined positions on the mounting surface 3a.

Next, the configuration of the semiconductor device 10 will be described with reference to FIGS. FIG. 2 is a top view showing the semiconductor device 10 of FIG. 3 is a cross-sectional view taken along the line XX in FIG.
As shown in FIGS. 2 and 3, the semiconductor device 10 is a QFP type semiconductor package, and mainly includes a semiconductor element 11, a heat sink 12, and a lead frame 20, and includes the semiconductor element 11, the heat sink 12, and the lead frame 20. A part is configured to be sealed by a sealing member 13 formed by molding an epoxy resin or the like.

  The semiconductor element 11 is made of a silicon substrate or the like, and is an IC chip or the like on which elements such as transistors are formed using semiconductor process technology. The heat sink 12 is configured as a rectangular plate-like heat radiating member made of a material having excellent heat radiating properties such as metals such as Cu, Fe, Mo, 42 alloy, and Kovar. The back surface of the semiconductor element 11 is fixed to the one surface side of the heat sink 12 via the adhesive 14, and the other surface side 12 a of the heat sink 12 is exposed from the sealing member 13, thereby improving the heat dissipation of the semiconductor element 11. Yes.

  Next, the shape of the lead frame 20 which is a characteristic part of the present invention will be described in detail with reference to the drawings. FIG. 4 is an enlarged cross-sectional view showing the vicinity of the lead terminal 21 of FIG. In FIG. 4, for convenience, the thicknesses of the base plating 26, the solder plating 27, the low wettability member 28, and the like are exaggerated.

  The lead frame 20 is formed to have a plurality of lead terminals 21 by patterning a thin metal plate such as copper or 42 alloy (42% Ni—Fe alloy) by etching or die pressing. Each lead terminal 21 is arranged such that the outer lead side is led out from the four sides of the sealing member 13 (see FIGS. 2 and 3).

  As shown in FIG. 4, the lead terminal 21 includes a first terminal part 22, a second terminal part 23, and a third terminal part 24, and the first terminal part 22 and the third terminal part 24 are the second terminal part. The one end side and the other end side of 23 are connected via a bent portion 25a and a bent portion 25b. That is, the first terminal portion 22 and the second terminal portion 23 are connected so as to be bent via the bent portion 25a, and the second terminal portion 23 and the third terminal portion 24 are bent via the bent portion 25b. To be connected.

  The first terminal portion 22 is electrically connected to the semiconductor element 11 via the bonding wire 15 or the like at the inner lead portion sealed by the sealing member 13 (see FIG. 3). The third terminal portion 24 is disposed as an end portion of the lead terminal 21 so as to face the land 4, and is electrically connected to the land 4 via the solder 5.

  Each lead terminal 21 is coated with a base film for plating (hereinafter also referred to as base plating 26) on the entire surface thereof, and as a surface treatment for improving solder wettability, zinc (Zn), tin (Sn), etc. Each of these materials is plated (hereinafter also referred to as solder plating 27). Thus, the area | region where the solder plating 27 was given functions as a high wettability area | region where solder wettability was improved.

  Of the high wettability region to which the solder plating 27 is applied, the intermediate portion in the longitudinal direction of the second terminal portion 23 is annularly covered with a low wettability member 28 having lower solder wettability than other regions. The low wettability member 28 is made of a non-conductive material, and is formed of, for example, a solder resist made of an epoxy resin. The low wettability member 28 may be formed on the second terminal portion 23 after the inner lead portion of the first terminal portion 22 is sealed by the sealing member 13, or the low wettability member 28 may be formed by the sealing member 13. It may be formed on the second terminal portion 23 of the lead frame 20 at the component level in the previous process to be sealed.

Next, the solder joint using the solder 5 between each lead terminal 21 and the land 4 of the semiconductor device 10 configured as described above will be described in detail.
The semiconductor device 10 in which the low wettability member 28 is formed on the second terminal portion 23 of each lead terminal 21 is prepared. Then, the semiconductor device 10 is placed on the mounting surface 3 a of the printed board 3 so that the third terminal portion 24 of each lead terminal 21 is placed on each land 4 of the printed board 3 through the paste-like solder 5.

  Subsequently, the semiconductor device 10 placed on the printed circuit board 3 is transferred to a reflow process, and the solder 5 is reflowed in a furnace. At this time, when the solder 5 interposed between the third terminal portion 24 and the land 4 melts, the second terminal portion 23 gets wet and reaches the low wettability member 28. Furthermore, wetting up to the first terminal portion 22 side is suppressed. As a result, as shown in FIG. 4, the wettability is prevented by the low wettability member 28, and the solder fillet is well formed in a state where a sufficient thickness of the solder thickness t is secured. Solder joint using the solder 5 with the land 4 is completed.

  In the lead terminal 21 in which the first terminal portion 22 and the second terminal portion 23 are bent and connected, when the solder 5 that wets the second terminal portion 23 reaches the bent portion 25a, the bent portion 25a is formed by the hardened solder 5. It becomes difficult to elastically deform, and the stress relaxation function by the lead frame 20 tends to decrease.

  In the present embodiment, as described above, since the low wettability member 28 is formed on the second terminal portion 23, the wettability of the solder 5 in the second terminal portion 23 is suppressed by the low wettability member 28, and The solder 5 does not wet up to the bent portion 25a.

  As described above, in the lead frame 20 according to the present embodiment, the lead terminals 21 soldered to the lands 4 are subjected to the solder plating 27 for improving the solder wettability, and the solder plating 27 is applied to the lead frame 21. Of the wettability region, the longitudinal intermediate portion of the lead terminal 21 is annularly covered with a low wettability member 28 having lower solder wettability than other regions.

  As a result, the solder 5 that has wetted the high wettability region from the third terminal portion 24 reaches the low wettability member 28 disposed at the intermediate portion in the longitudinal direction of the second terminal portion 23. Will be. That is, while the wettability of the solder 5 is suppressed by the low wettability member 28, the wettage amount and the wetness position of the solder 5 can be controlled according to the position of the low wettability member 28. Therefore, a sufficient solder thickness t can be ensured without impairing the stress relaxation function by the lead terminal 21.

  Then, by configuring the semiconductor device 10 to include the lead frame 20 configured as described above, the semiconductor element 11, and the sealing member 13, a sufficient solder thickness without impairing the stress relaxation function by the lead terminal 21. It is possible to realize the semiconductor device 10 having the effect of ensuring the length t. The electronic device 1 is configured to include the semiconductor device 10 configured as described above and the printed circuit board 3 having the lands 4 to which the end portions of the lead terminals 21 are soldered via the solder 5. Thus, it is possible to realize the electronic device 1 that has an effect of ensuring a sufficient solder thickness t without impairing the stress relaxation function of the lead terminal 21.

  In particular, since the intermediate portion in the longitudinal direction of the second terminal portion 23 is annularly covered with the low wettability member 28, the wetting of the solder 5 inside the second terminal portion 23 (left side in FIG. 4) is suppressed. In addition, it is possible to suppress the wetting of the solder 5 on the outside (right side in FIG. 4) or the like. Thereby, since the solder 5 does not wet up to the bending part 25a, the fall of the stress relaxation function by the lead frame 20 can be suppressed reliably.

FIG. 5 is an enlarged cross-sectional view showing a lead frame according to a first modification of the first embodiment. FIG. 6 is a top view showing a semiconductor device according to a second modification of the first embodiment.
As a first modified example of the first embodiment, the low wettability member 28 is not limited to be formed so as to cover the intermediate portion in the longitudinal direction of the second terminal portion 23 in an annular manner, and covers a plurality of different surfaces. It may be formed. For example, the low wettability members 28a and 28b illustrated in FIG. 5 are formed on the inner side (left side in FIG. 5) of the second terminal portion 23 and the opposite land side of the third terminal portion 24 (upper side in FIG. 5). ). Even in this case, the wet-up of the solder 5 can be suppressed by the low wettability members 28a and 28b.

  As a second modification of the first embodiment, since the low wettability member 28 is non-conductive, as illustrated in FIG. 6, another low wettability member 28 that covers the adjacent lead terminals 21 is illustrated. It may be formed so that it may be connected with. Thereby, after the inner lead part of the 1st terminal part 22 is sealed by the sealing member 13, the surface for collectively forming the low wettability member 28 with respect to the longitudinal direction intermediate part of each 2nd terminal part 23 By performing the treatment or the like, each low wettability member 28 can be easily formed.

  In the present embodiment and the modification, the low wettability members 28, 28a, and 28b are not limited to being formed of a solder resist made of an epoxy resin, and may be formed of, for example, another resin material. It may be formed of metal oxide, fluorine or silicon. Further, the low wettability members 28, 28a, and 28b may be formed by, for example, metal plating that does not form an alloy with solder as long as the low wettability members 28, 28a, and 28b are configured not to contact other low wettability members 28 that cover adjacent lead terminals. .

[Second Embodiment]
Next, a lead frame, a semiconductor device, and an electronic device according to a second embodiment of the invention will be described with reference to FIG. FIG. 7 is an enlarged cross-sectional view showing a main part of the lead frame 30 according to the second embodiment.
The second embodiment is mainly different from the first embodiment in that a lead frame 30 is employed instead of the lead frame 20 described above. For this reason, substantially the same components as those in the first embodiment are denoted by the same reference numerals and description thereof is omitted.

  As shown in FIG. 7, the lead terminal 31 of the lead frame 30 of the semiconductor device 10 according to the present embodiment eliminates the low wettability member 28 from the lead frame 20 described above, and the solder plating 27 is the first. It is configured to be formed only on the land side inside the two terminal portion 23 (left side in FIG. 7) and on the land side (lower side in FIG. 7) of the third terminal portion 24.

  The solder plating 27 is formed, for example, by performing a plating process by masking an area different from the area where the solder plating 27 is applied, of each lead terminal 31 having the base plating 26 applied to the entire surface.

  For this reason, the region where the solder plating 27 is applied functions as a high wettability region, and the region where the base plating 26 is exposed without being subjected to the solder plating 27 functions as a low wettability region. That is, each lead terminal 31 is formed so that the solder wettability on the semiconductor element side is lower than that on the land side by performing a surface treatment for improving the solder wettability on the land side.

  With this configuration, when the solder 5 interposed between the third terminal portion 24 and the land 4 is melted, the highly wettable region to which the solder plating 27 is applied in the second terminal portion 23 is wetted. Although it rises, the wet-up is suppressed by the low wettability region where the base plating 26 is exposed.

  As a result, the wettability of the solder 5 is suppressed by the high wettability region to which the solder plating 27 is applied, while the wetting amount and the wettability of the solder 5 are determined according to the position of the low wettability region where the base plating 26 is exposed. The position to be raised can be controlled. Therefore, a sufficient solder thickness t can be ensured without impairing the stress relaxation function by the lead terminal 31.

  By configuring the semiconductor device 10 so as to include the lead frame 30 configured as described above, the semiconductor element 11, and the sealing member 13, a sufficient solder thickness without impairing the stress relaxation function by the lead terminal 31. It is possible to realize the semiconductor device 10 having the effect of ensuring the length t. The electronic device 1 is configured to include the semiconductor device 10 configured as described above and the printed circuit board 3 having the lands 4 to which the end portions of the lead terminals 31 are soldered via the solder 5. Thus, it is possible to realize the electronic device 1 that has an effect of ensuring a sufficient solder thickness t without impairing the stress relaxation function of the lead terminal 31.

  In particular, the second terminal portion 23 is formed so that solder wettability is lower on the land side than on the land side by applying solder plating 27 as a surface treatment for improving solder wettability on the land side. Yes. For this reason, since the solder 5 does not wet up to the bending part 25a, the fall of the stress relaxation function by the lead frame 30 can be suppressed reliably.

  In addition, since the area where the solder plating 27 is applied becomes narrower than the conventional structure applied to the entire lead terminal, the necessary plating amount is reduced, so that the metal protrusions such as needles are formed from the solder plating 27. The generation of whiskers in which the portion grows can be suitably suppressed.

  The solder plating 27 is not limited to being formed only on the land side inside the second terminal portion 23 (left side in FIG. 7) and on the land side (lower side in FIG. 7) of the third terminal portion 24. The second terminal portion 23 may be formed only below the intermediate portion in the longitudinal direction. Even in this case, while the wettability of the solder 5 is suppressed by the high wettability region to which the solder plating 27 is applied, the solder 5 is wetted according to the position of the low wettability region where the base plating 26 is exposed. You can control the amount and position of wetting.

In addition, this invention is not limited to said each embodiment, For example, you may actualize as follows.
(1) The solder plating 27 is not limited to being formed by a surface treatment using a material such as zinc (Zn) or tin (Sn). For example, the surface such as plating using a material such as tin, gold, silver, palladium, nickel, etc. It may be formed by processing. Further, the high wettability region is not limited to being formed by applying the solder plating 27, but may be formed by increasing the solder wettability by other surface treatment or the like.

(2) The semiconductor device 10 may be configured not to employ the heat sink 12 according to the amount of heat generated by the semiconductor element 11.

(3) The characteristic configuration of the present invention is not limited to being applied to a QFP lead frame. For example, the lead terminals are taken out from two side surfaces of the sealing member 13 in a gull wing shape (substantially L shape) or a straight shape. From a sealing member in which a semiconductor element is sealed, such as a lead frame of a semiconductor package (for example, SOP) or a lead frame of a semiconductor package in which lead terminals are taken out from four side surfaces of the sealing member 13 in a gull wing shape or a straight shape. The present invention can be applied to a lead frame having a plurality of lead terminals to be derived.

DESCRIPTION OF SYMBOLS 1 ... Electronic device 3 ... Printed circuit board (circuit board) 4 ... Land 5 ... Solder 10 ... Semiconductor device 11 ... Semiconductor element 13 ... Sealing member 20, 30 ... Lead frame 21, 31 ... Lead terminal 22 ... 1st terminal part 23 ... 2nd terminal part 24 ... 3rd terminal part 25a, 25b ... Bending part 27 ... Solder plating 28 ... Low wettability member

Claims (7)

A plurality of lead terminals (21) led out from a sealing member (13) in which a semiconductor element (11) is sealed;
In the lead frame (20) in which the end (24) of the lead terminal is soldered to the land (4) of the circuit board (3),
The lead terminal is subjected to a surface treatment (27) for improving solder wettability,
Of the high wettability region subjected to the surface treatment, an intermediate portion in the longitudinal direction of the lead terminal is annularly covered with a low wettability member (28) having lower solder wettability than other regions. Lead frame. The lead terminal is formed such that the first terminal portion (22) on the semiconductor element side and the second terminal portion (23) on the land side are bent and connected,
2. The lead frame according to claim 1, wherein an intermediate portion in the longitudinal direction of the second terminal portion is annularly covered with the low wettability member.   3. The lead according to claim 1, wherein the low wettability member is made of a non-conductive material and is formed so as to be connected to another low wettability member covering an adjacent lead terminal. flame. A plurality of lead terminals (31) led out from a sealing member (13) in which a semiconductor element (11) is sealed;
In the lead frame (30) in which the end (24) of the lead terminal is soldered to the land (4) of the circuit board (3),
The lead terminal is formed so that a solder treatment on the semiconductor element side is lower than that on the land side by performing a surface treatment (27) for improving the solder wettability on the land side. flame. The lead terminal is formed such that the first terminal portion (22) on the semiconductor element side and the second terminal portion (23) on the land side are bent and connected,
The second terminal portion is formed so that the solderability on the land side is lower than that on the land side by performing a surface treatment for improving solder wettability on the land side. The lead frame according to claim 4. A lead frame according to any one of claims 1 to 5;
A semiconductor element (11) electrically connected to the lead frame;
A sealing member (13) for sealing the semiconductor element and a part of the lead frame;
A semiconductor device (10) comprising: A semiconductor device according to claim 6;
A circuit board (3) having lands (4) to which the end portions (24) of the lead terminals are respectively soldered via solder (5);
An electronic device (1) comprising:

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