JP2015106691A5 - - Google Patents
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- JP2015106691A5 JP2015106691A5 JP2013249382A JP2013249382A JP2015106691A5 JP 2015106691 A5 JP2015106691 A5 JP 2015106691A5 JP 2013249382 A JP2013249382 A JP 2013249382A JP 2013249382 A JP2013249382 A JP 2013249382A JP 2015106691 A5 JP2015106691 A5 JP 2015106691A5
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- JP
- Japan
- Prior art keywords
- potential level
- register
- signal
- output node
- setting unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 239000004065 semiconductor Substances 0.000 claims 1
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Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2013249382A JP6225674B2 (ja) | 2013-12-02 | 2013-12-02 | 半導体装置および通信インタフェース回路 |
| US14/550,725 US9240788B2 (en) | 2013-12-02 | 2014-11-21 | Semiconductor device and communication interface circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2013249382A JP6225674B2 (ja) | 2013-12-02 | 2013-12-02 | 半導体装置および通信インタフェース回路 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2015106691A JP2015106691A (ja) | 2015-06-08 |
| JP2015106691A5 true JP2015106691A5 (cg-RX-API-DMAC7.html) | 2016-07-21 |
| JP6225674B2 JP6225674B2 (ja) | 2017-11-08 |
Family
ID=53266174
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2013249382A Active JP6225674B2 (ja) | 2013-12-02 | 2013-12-02 | 半導体装置および通信インタフェース回路 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US9240788B2 (cg-RX-API-DMAC7.html) |
| JP (1) | JP6225674B2 (cg-RX-API-DMAC7.html) |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5151623A (en) | 1985-03-29 | 1992-09-29 | Advanced Micro Devices, Inc. | Programmable logic device with multiple, flexible asynchronous programmable logic blocks interconnected by a high speed switch matrix |
| JPS61262026A (ja) * | 1985-05-15 | 1986-11-20 | 三菱電機株式会社 | 無停電電源装置の短絡保護方式 |
| DE19739246A1 (de) * | 1997-09-08 | 1999-03-11 | Siemens Ag | Schaltungsanordnung und Verfahren zum Überlastschutz für ein Schaltelement |
| JP2003249562A (ja) * | 2002-02-25 | 2003-09-05 | Seiko Epson Corp | 特性調整回路及びそれを用いた半導体装置 |
| KR101165027B1 (ko) * | 2004-06-30 | 2012-07-13 | 삼성전자주식회사 | 반도체 메모리 장치에서의 리던던시 프로그램 회로 |
| US7562272B2 (en) * | 2005-10-06 | 2009-07-14 | International Business Machines Corporation | Apparatus and method for using eFuses to store PLL configuration data |
| KR100821585B1 (ko) * | 2007-03-12 | 2008-04-15 | 주식회사 하이닉스반도체 | 반도체 메모리 장치의 온 다이 터미네이션 회로 |
| JP5422259B2 (ja) * | 2009-05-18 | 2014-02-19 | 新日本無線株式会社 | トリミング回路 |
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2013
- 2013-12-02 JP JP2013249382A patent/JP6225674B2/ja active Active
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2014
- 2014-11-21 US US14/550,725 patent/US9240788B2/en active Active