JP2015005124A - Device for electronic apparatus, and electronic apparatus mounting the device therein - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the capacity of memory accumulating log information on the access from control means to a register.SOLUTION: There is provided a device for an electronic apparatus that has a module accessed from control means, and includes an access detection unit that detects the access from the control means to the module, and a log creation unit that creates log information on the detected access. When the detected access is temporally continuous access to spatially continuous addresses, the log creation unit includes, in the log information on the detected access, the time and address of the initial access of the continuous access and the difference in time and difference in address between the initial access to the final access of the continuous access.

Description

  The present invention relates to a device for electronic equipment and an electronic equipment equipped with the device.

  In recent years, a semiconductor device having a CPU I / F and having a module accessible by the CPU is used in various electronic apparatuses. An example of the electronic apparatus is an image forming apparatus such as a copying machine.

  In the analysis when a failure occurs in such an electronic device, a general method conventionally performed is to trace the access contents of the CPU using a debugging device such as ICE (In Circuit Emulator) or It is a method of investigating the cause by making settings.

  However, with this method, it takes time to prepare for bringing in and connecting a debugging device for analysis. In addition, in this method, since a debug device cannot be connected to the CPU I / F in the case of a device with a built-in CPU, it has been impossible to take a method of analysis using the debug device.

  As a method that can solve such problems, CPU access to registers is monitored, detected access log information is created, and the created logs are saved in internal memory and output to the outside There is known a method of facilitating debugging by providing hardware capable of performing the above in the device (for example, see Patent Document 1).

  In Patent Document 1, access from a CPU to a register is monitored and log information is acquired. At that time, Patent Document 1 aims to acquire log information without wasteful use of processing and resources due to acquisition of unnecessary access log information. Therefore, Patent Document 1 discloses that the necessity and necessity of log information are determined based on the type of access from the CPU to the register, and only necessary log information is acquired.

  However, as described above, in the method of monitoring the access to the register and creating the log information, the address (for example, 32 bits) and data (for example, 16 bits) information is directly logged for all accesses to be acquired. Save as information. For this reason, when the analysis time is long or the range of access to be acquired is wide, the amount of log information becomes enormous, the memory capacity required for storage increases, and the cost increases. It was.

  In view of the above problems, an object of one aspect is to suppress the capacity of a memory that stores log information for access to a register from a control unit.

In order to solve the above problem, according to one aspect,
A device for electronic equipment having a module accessed from a control means,
An access detector for detecting access to the module from the control means;
A log creation unit for creating log information relating to the detected access,
The log creating unit
When the detected access is a temporally continuous access to a spatially continuous address, the log information related to the detected access includes the time and address of the top access of the continuous access and the continuous Including the time difference and the address difference from the top access to the last access
A device for electronic equipment is provided.

  According to one aspect, it is possible to suppress the capacity of the memory that stores log information for access from the control means to the register.

1 is an overall configuration diagram of a device for an electronic apparatus according to an embodiment. The internal block diagram of the debug control part which concerns on one Embodiment. The example of a format of the log information which concerns on one Embodiment. The figure which showed the data access amount and log data amount concerning one Embodiment. The sequence diagram concerning one embodiment (when reading log information from CPU). The sequence diagram concerning one embodiment (when reading log information from terminal PC). The sequence diagram concerning one embodiment (when there is a log acquisition start / end instruction).

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of the invention will be described with reference to the accompanying drawings. In addition, in this specification and drawing, about the substantially same structure, the duplicate description is abbreviate | omitted by attaching | subjecting the same code | symbol.

[Devices for electronic devices]
First, a device for an electronic apparatus according to an embodiment of the present invention will be described with reference to FIG. FIG. 1 is an overall configuration diagram of a device for an electronic apparatus according to an embodiment.

  The electronic device 601 is formed on the target substrate 600. The target substrate 600 is a component that constitutes a circuit unit of an electronic device. On the target substrate 600, a CPU 620 and a device 601 for electronic equipment that receives access from the CPU 620 are mounted. In the configuration example of FIG. 1, the CPU 620 is external to the device 601, and a built-in memory 609 that stores log information for access from the CPU 620 acquired in the device 601 is built in the device 601. Yes. Note that the CPU 620 may be built in the device 601. The internal memory 609 may be external to the device 601. The CPU 620 is an example of a control unit.

  The electronic device in which the device 601 is mounted may be an image forming apparatus such as a copier, for example. In this case, the device 601 may be a device having a CPU I / F, such as an ASIC (Application Specific Integrated Circuit) for printer control. As illustrated in FIG. 1, the device 601 includes a CPU I / F 603, functional modules 607a, 607b, and 607c, a built-in memory 609, a serial I / F 611, and a debug control unit 613. The CPU I / F 603 includes an interrupt controller 605.

  The CPU I / F 603 is connected to the CPU 620 via the CPU bus. The CPU I / F 603 is connected to the function module A 607a, the function module B 607b, and the function module C 607c (hereinafter collectively referred to as the function module 607) via the register I / F in the device 601.

  The function module A 607a, the function module B 607b, and the function module C 607c correspond to modules having a desired function built in the device 601, and each have a register accessible from the CPU 620. Access from the CPU 620 to the functional module 607 is performed via an internal bus (register I / F). In FIG. 1, three modules of the function module A 607a, the function module B 607b, and the function module C 607c are exemplified, but any number of function modules may be used.

  The built-in memory 609 is a storage device used for storing log information of access from the CPU 620 to the register of the functional module 607. The log information stored in the built-in memory 609 can be acquired by direct access from the CPU 620 or by access from a terminal PC 630 described later.

  The serial I / F 611 functions as an I / F for accessing the built-in memory 609 from the terminal PC 630. The terminal PC 630 is an example of an external device capable of serial communication. The serial I / F 611 is an example of a serial communication unit for outputting log information stored in the built-in memory 609 to an external device. The terminal PC 630 and the serial I / F 611 are connected serially.

  The terminal PC 630 is a display PC (Personal Computer) capable of serial operation. The terminal PC 630 is a management terminal capable of accessing the internal memory 609 via the serial I / F 611 and acquiring access log information stored in the internal memory 609.

  The debug control unit 613 is a module that monitors access from the CPU 620 to the functional module 607, creates log information of the detected access, and outputs the log information to the built-in memory 609. The debug control unit 613 can notify the CPU 620 of an interrupt via the interrupt controller 605 according to the monitoring status.

[Configuration of debug controller]
Next, the internal configuration of the debug control unit 613 according to an embodiment will be described with reference to FIG. FIG. 2 is an internal configuration diagram of the debug control unit according to the embodiment. The debug control unit 613 includes an access detection unit 641, a timer 643, a log creation unit 645, and a control register 647.

  The access detection unit 641 monitors the access from the CPU 620 to the register of the functional module 607 using the register I / F. The access detection unit 641 generates log information of the detected access and outputs it to the built-in memory 609.

The access detection unit 641 normally records the log information shown below for all accesses to the registers of the functional module 607.
・ Time stamp ・ Address ・ Access type (read / write)
Data On the other hand, when the access detection unit 641 detects access of the same access type (read / write) to a spatially continuous address a plurality of times in succession, the following information is recorded in the access log. Record as information.
-Time stamp of top access-Address of top access-Access type (read / write)
・ Data for all accesses ・ Timestamp difference between last access and head access ・ Address difference between last access and head access The above “same access type (read / read to multiple spatially continuous addresses) “Access to spatially continuous addresses” among “when a write access is detected” indicates that the access destination addresses of two or more consecutive accesses from the CPU 620 to the register of the functional module 607 are continuous (for example, 2 The first address is the address of the first address + 1).

  In addition, “access to temporally continuous addresses” in the above “when the access of the same access type (read / write) is detected multiple times in succession to spatially continuous addresses” is The above-mentioned “two or more consecutive accesses from the CPU 620 to the register of the function module 607”. In this case, it does not matter whether the second access time is continuous in a certain unit, such as the first access time + 1 ms (or + 1s).

  The timer 643 measures the time for access using a counter. The timer 643 can variably set a time count period for access from the CPU 620 to the functional module. The unit of the count cycle can be set in the register. The count value by the timer 643 is notified from the timer 643 to the access detection unit 641 in real time as a time stamp. As described above, a time stamp having an appropriate resolution can be added to the log information in accordance with the time range analyzed by the timer 643. As a result, more detailed analysis can be performed using the log information.

  The log creation unit 645 creates log information related to the access detected by the access detection unit 641. When the detected access is a temporally continuous access to a spatially continuous address, the log creating unit 645 adds the time and address of the first access of the continuous access to the log information regarding the detected access. , The time difference from the first access to the last access and the address difference are included. The log creation unit 645 may include time information (for example, a time stamp) for access notified to the access detection unit 641 in the log information. By including time information such as a time stamp in the log information, more detailed analysis can be performed using the log information.

  The control register 647 includes various registers shown below.

(1) Log acquisition mode (log_mode)
The control register 647 sets the control register for the log acquisition mode to “0” or “1”.
0: Normal mode 1: Differential mode When the log acquisition mode is set to the normal mode “0”, a time stamp and an address are recorded as log information for all accesses to the registers of the function module 607.

  When the log acquisition mode is set to the difference mode “1”, the temporally continuous access to the spatially continuous addresses is the time stamp difference between the last access and the time stamp between the last access and the top access. Only the address difference between the last access and the head access is recorded as log information.

(2) Log acquisition timing control (log_timing)
The control register 647 switches the control register for log acquisition timing to “0” or “1”.

  When the log acquisition timing control register is set to “0”, log acquisition is started as soon as the power is turned on, and the acquisition is continued until the power is turned off.

  When the log acquisition timing control register is set to “1”, the following log acquisition start instruction and log acquisition end instruction are validated.

(3) Log acquisition start instruction (log_start)
Valid only when the log_timing control register is set to "1". In other words, when the control register 647 sets the log acquisition start instruction log_start to “1” while the log_timing control register is set to “1”, acquisition of log information is started.

(4) Log acquisition end instruction (log_end)
Valid only when the log_timing control register is set to "1". That is, when the control register 647 sets the log acquisition end instruction log_end to “1” while the log_timing control register is set to “1”, the log acquisition acquisition ends.

[Timer count cycle]
Further, the control register 647 can variably set the count cycle (also referred to as timer cycle) of the timer 643 as described below, for example. The timer 643 increments the value of the time stamp every time when the time corresponding to the set count cycle elapses. For example, if the timer 643 is 16 bits (bit) and the set value of the following count cycle is “4”, the count cycle of the timer 643 is 1 ms, and when the timer 643 completes a cycle, a time stamp of 65.535 s is added. It will be.
0: Timer period 100ns
1: Timer period 1μs
2: Timer period 10 μs
3: Timer period 100 μs
4: Timer period 1 ms
[Example of access log information format]
Next, a format example of access log information according to an embodiment will be described with reference to FIG. FIG. 3A shows a format example of the log information 100 for normal access. FIG. 3B is a format example of access log information 200 for continuous access. An example in which log information 100 and 200 of access for 8 times is acquired is shown.

  In the format example of the access log information 100 in FIG. 3A, time [15: 0] indicates a time stamp (time stamp) 101, addr [31: 1] indicates an address 102, and rw indicates an access type ( Read / write) 103, and data [15: 0] indicates data 104.

  In the format example of the access log information 200 in FIG. 3B, time_st [15: 0] indicates the time stamp (time counter) 201 of the head access, and addr_st [31: 1] indicates the address 202 of the head access. . Also, rw indicates the access type (read / write) 203, and data [15: 0] indicates the data 204. Also, time_length [7: 0] indicates the difference 205 between the time stamps of the last access and the head access, and addr_length [7: 0] indicates the difference 206 between the addresses of the last access and the head access.

(Normal time)
In the access log information 100 in FIG. 3A, the time stamp 101 (time [15: 0]) is 16 bits (2 bytes), and the address 102 and rw103 (addr [31: 1] / rw) are 32 bits ( 4 bytes) and data 104 (data [15: 0]) are 16 bits (2 bytes).

Therefore, the data amount of the log information 100 for normal access is expressed by the following equation.
Size of access log information 100 per access = 2 bytes (time) + 4 bytes (addr / rw) + 2 bytes (data) = 8 bytes Access log information 100 data amount when access count n = 8 bytes (log size per access) x number of accesses
(During continuous access)
In the access log information 200 of FIG. 3B, the time stamp 201 (time_st [15: 0]) of the head access is 16 bits (2 bytes), the address 202 of the head access and rw203 (addr_st [31: 1] / rw) is 32 bits (4 bytes), and data 204 (data [15: 0]) is 16 bits (2 bytes). Also, the time difference 205 (time_length [7: 0]) between the last access and the head access is 8 bits (1 byte), and the address difference 206 between the last access and the head access (addr_length [7: 0]) is 8 bits. (1 byte).

Therefore, the data amount of the access log information 200 at the time of continuous access is expressed by the following equation.
Data amount of access log information 200 when access count is n = 2 bytes (time_st) +4 bytes (addr_st) + [2 bytes (data) × access count n] +1 byte (time_length) +1 byte (addr_length)
[Number of consecutive accesses and amount of log information]
Next, the number of temporally continuous accesses to spatially continuous addresses, the data amount of the log information 200 (during continuous access in FIG. 3B), and the normal log information in FIG. A description will be given in comparison with 100 data amounts. The horizontal axis in FIG. 4 indicates the number of consecutive accesses, and the vertical axis indicates the data amount (bytes) of the log information.

  According to this, as the number of continuous accesses increases, the data amount of the log information 200 at the time of continuous access becomes smaller than the data amount of the log information 100 at the normal time, and the effect of reducing the data amount of the log information is reduced. large. For example, when the number of continuous accesses is 4, the data amount of the log information 200 at the time of continuous access is half of the data amount of the log information 100 at the normal time. On the other hand, when the number of continuous accesses is 10, the data amount of the log information 200 at the time of continuous access is about 1/3 of the data amount of the log information 100 at the normal time. It can be seen that the reduction effect is large.

[Sequence (when reading log information from the CPU)]
Next, an example of a log information reading sequence according to an embodiment will be described with reference to the sequence shown in FIG. FIG. 5 is a sequence diagram when the log information is read from the CPU 620 and the debug control unit 613 is operated when analyzing the device 601 for electronic equipment using the log information.

  In the log information reading sequence according to the present embodiment, the CPU 620 first sets each control register 647 of the debug control unit 613 in advance (step S10). In the present embodiment, the CPU 620 sets log_timing = 0 in advance in the control register 647.

  When the electronic device in which the device 601 is mounted is operated, the CPU 620 generates an access (register access) to the register of the functional module 607 of the device 601 (steps S12 and S14). The access detection unit 641 detects access to the register of the functional module 607. The log creation unit 645 creates log information of the access detected by the access detection unit 641 and stores it in the built-in memory 609 (step S16). After the operation is completed, the CPU 620 reads and acquires log information from the built-in memory 609 by performing a command operation (step S18).

  The log information reading sequence when the log information is read from the CPU 620 has been described above. According to this, the log information stored in the built-in memory 609 can be read by software.

[Sequence (when reading log information from terminal PC)]
Next, another example of the log information reading sequence according to the embodiment will be described with reference to the sequence shown in FIG. FIG. 6 is a sequence diagram when the log information is read from the terminal PC 630 and the debug control unit 613 is operated when the electronic device 601 is analyzed using the log information.

  In the log information reading sequence according to the present embodiment, the CPU 620 first sets each control register 647 of the debug control unit 613 in advance (step S20). In the present embodiment, the CPU 620 sets log_timing = 0 in advance in the control register 647.

  When the electronic device in which the device 601 is mounted is operated, the CPU 620 generates access (register access) to the register of the functional module 607 of the device 601 (steps S22 and S24). The access detection unit 641 detects access to the register of the functional module 607. The log creation unit 645 creates log information of the access detected by the access detection unit 641 and stores it in the built-in memory 609 (step S26). After the operation is completed, the terminal PC 630 performs a command operation for reading log information (step S28). The terminal PC 630 reads and acquires log information from the built-in memory 609 (step S29).

  The log information reading sequence when reading log information from the terminal PC 630 has been described above. According to this, by connecting an external device capable of serial communication, for example, a device such as a PC, to the device 601, the external device can directly acquire log information.

[Sequence (when there is a log acquisition start / end instruction)]
Next, another example of the log information reading sequence according to the embodiment will be described with reference to the sequence shown in FIG. FIG. 7 shows a sequence when the log information is read from the CPU 620 in response to the start instruction and the end instruction for log acquisition, and the debug control unit 613 is operated when the electronic device 601 is analyzed using the log information. FIG.

  In the log information reading sequence according to the present embodiment, the CPU 620 first sets each control register 647 of the debug control unit 613 in advance (step S30). In this embodiment, the CPU 620 presets log_timing = 1 in the control register 647.

  When the electronic device in which the device 601 is mounted is operated, the CPU 620 generates an access (register access) to the register of the functional module 607 of the device 601 (steps S32, S36, and S38). Before the CPU 620 issues a log acquisition start instruction (that is, before “log_start” is set to 1), even if the CPU 620 accesses the register of the functional module 607, the log information is acquired. Absent. For example, since the access that occurred in step S32 is performed before a log acquisition start instruction is given, log information about the access is not acquired. That is, log information is not acquired during the period T1 before the start of log acquisition from the CPU 620 (log_start = 1).

  On the other hand, when the CPU 620 issues an instruction to start log acquisition (step S34) and an access to the register of the function module 607 occurs thereafter, the access detection unit 641 detects the access. For example, when the accesses in steps S36 and S38 are detected, the log creating unit 645 creates log information for the detected accesses and stores them in the built-in memory 609 (step S40).

  Thereafter, the CPU 620 issues a log acquisition end instruction (log_start = 0) (step S42). When the access detection unit 641 detects access to the register during a period T2 from the log acquisition start instruction (log_start = 1) from the CPU 620 to the log acquisition end instruction (log_start = 0), the log creation unit 645 Log information for the detected access is created and stored in the built-in memory 609.

  After the CPU 620 issues a log acquisition end instruction, even if access to the register occurs (step S44), log information is not acquired. For example, log information is not acquired in a period T3 after a log acquisition end instruction (log_start = 0) is issued.

  After the operation is completed, the CPU 620 reads the log information from the built-in memory 609 by performing a command operation, and acquires the log information (step S46).

  The sequence of reading log information when there is a log acquisition start instruction and end instruction from the CPU 620 has been described above. According to this, the period for acquiring log information can be arbitrarily set by software. Therefore, log information for only a necessary period can be acquired, and the built-in memory 609 can be used efficiently.

  As described above, when log information is acquired for access from the CPU 620 to the electronic device 601 according to the present embodiment, when spatially continuous access occurs to spatially continuous addresses. Does not record the time and address as log information for all accesses, but only the time and address of the head access, the time difference from the head access to the last access, and the address difference from the head access to the last access Is recorded as log information. As a result, the capacity of the built-in memory 609 that accumulates log information can be kept small.

  As mentioned above, although the device for electronic devices and the electronic device carrying the device were demonstrated by the said embodiment, this invention is not limited to the said Example, Various deformation | transformation and improvement are within the scope of the present invention. Is possible.

600 Target substrate 601 Device 603 CPU I / F
605 Interrupt controller 607, 607a, 607b, 607c Function module 609 Built-in memory 611 Serial I / F
613 Debug control unit 620 CPU
641 Access detection unit 643 Timer 645 Log creation unit 647 Control register

JP 2008-287319 A

Claims (7)

A device for electronic equipment having a module accessed from a control means,
An access detector for detecting access to the module from the control means;
A log creation unit for creating log information relating to the detected access,
The log creating unit
When the detected access is a temporally continuous access to a spatially continuous address, the log information related to the detected access includes the time and address of the top access of the continuous access and the continuous Including the time difference and the address difference from the top access to the last access
A device for electronic equipment characterized by the above. A timer for measuring the time for the access;
The log creating unit
The log information includes time information for the access timed by the timer.
The device for electronic equipment according to claim 1. The timer can variably set the time counting period for the access,
The device for an electronic device according to claim 2, wherein the device is an electronic device. A built-in memory for storing the created log information;
The log information stored in the built-in memory is transmitted to the control unit in response to an instruction from the control unit.
The device for electronic equipment as described in any one of Claims 1-3 characterized by the above-mentioned. A serial communication unit for outputting log information stored in the built-in memory to an external device;
The device for an electronic device according to claim 4. The log creation unit starts creating log information related to the detected access in response to a log acquisition start instruction from the control unit, and relates to the detected access in response to a log acquisition end instruction from the control unit Finish creating log information,
The device for electronic devices as described in any one of Claims 1-5 characterized by the above-mentioned.   The electronic device carrying the device as described in any one of Claims 1-6.

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