JPH06174802A - Cpu mounted integrated circuit and debugger - Google Patents

Abstract

PURPOSE:To improve a debugger in workability by monitoring data accessed by a CPU from the outside without increasing the number of circuits built in a CPU mounted integrated circuit and drawing out an inside bus to the outside. CONSTITUTION:A CPU 10 in a CPU mounted integrated circuit accesses a ROM and a RAM inside through an inside bus and at the same time accesses a ROM and a RAM provided in an outside debugger through an outside addressing part 22, an access data conversion part 24 and a serial interface 26 in a debugging mode. A RAM and a ROM used in the debugging mode are provided outside to improve the degree of integration. The number of input and output pins is not increased because of serial communication with the debugger.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CPU (central processing) for executing a program written in a memory such as a ROM (read only memory) mounted together.
unit), or a debugger for the CPU-mounted integrated circuit, in particular, without significantly increasing the number of circuits incorporated in the CPU-mounted integrated circuit, A CPU-equipped integrated circuit with improved workability for debugging, such as monitoring data accessed by a CPU inside the CPU-equipped integrated circuit without drawing its internal bus outside the circuit, and debugging of the CPU-mounted integrated circuit Related to the debugger used for work.

[0002]

2. Description of the Related Art Integrating an electronic device into an integrated circuit has many advantages such as miniaturization of the entire device, improvement of reliability and reduction of power consumption. In addition, there are various designing methods for forming an integrated circuit. For example, various design methods are known for reducing the design man-hours and design costs associated with the design of integrated circuits. For example, there is a technique in which at least a part of the design process or the manufacturing process is shared and prepared in advance, and the other processes are customized.

An integrated circuit based on such a technique is called a semi-custom type integrated circuit, and includes a standard cell type integrated circuit, a gate array type integrated circuit, and the like.
The standard cell type integrated circuit is an integrated circuit based on a design method in which registered cells (functional blocks) are arranged and interconnected according to a circuit incorporated in the integrated circuit. The gate array type integrated circuit is an integrated circuit of a type in which a group of cells arranged in a matrix which is processed before the wiring process is made common and the subsequent wiring process is performed according to a circuit incorporated in the integrated circuit. .

According to such a semi-custom type integrated circuit, TAT (turn around time) at the time of design and production
And cost can be reduced, and an integrated circuit designed to suit the customer can be provided.

In recent years, in such a semi-custom type integrated circuit, a CPU, a RAM (random access memory) or a ROM (read) accessed by the CPU are read.
There is one that provides memory such as only memory) and various peripherals in a macro library. According to the semi-custom type integrated circuit in which such a macro library is prepared, an integrated circuit (hereinafter referred to as a CPU-incorporated custom integrated circuit) in which a microcomputer system having a customized configuration including a CPU is incorporated into one. ) Can also be provided. Along with such a CPU-installed custom integrated circuit, a conventional C
Including a so-called one-chip microcomputer equipped with PU,
Hereinafter, these are collectively referred to as a CPU-mounted integrated circuit.

In such a CPU-mounted integrated circuit,
Debugging programs written in memory such as ROM and non-volatile RAM mounted with CPU is
This is done by using a debugger unit provided in the CPU mounted integrated circuit. Alternatively, such debugging is performed when the CPU mounted on the CPU-mounted integrated circuit is in the ROM.
The internal bus used for accessing the RAM, the RAM, etc. is pulled out of the integrated circuit equipped with the CPU, and the internal bus is monitored by a predetermined debugger.

FIG. 20 is a block diagram of a conventional CPU-mounted integrated circuit.

The integrated circuit incorporating the CPU shown in FIG. 20 includes a CPU 10a, a ROM 12a, and a RAM 14
A debugger section 20 is provided together with a. The debugger unit 20 includes a ROM 12b, a RAM 14b, an event detection unit 16a, and a monitor unit 18a. Also, the C
A so-called one-chip microcomputer is realized by the PU 10a, the ROM 12a, the RAM 14a, and other peripheral devices (not shown).

The CPU 10a executes the program written in the ROM 12a,
It realizes a predetermined function. In the ROM 12a, a program executed by the CPU 10a is written and various data used when the program is executed is also written. The RAM 14a is the CPU 10a.
The data used when executing the program is stored. In addition, the RAM 14a is also written with data required by the system when the CPU 10a executes the program. For example, a return address when branching to a subroutine, data to be stacked, and the like are also stored.

On the other hand, in the debugger section 20, for example, a CRT (cathod) connected to the monitor section 18a.
By using a terminal device including an e-ray tube) and a keyboard, the operating state of the CPU 10a and the RAM 14a
Monitors the data written in and rewrite settings. Such monitor and rewriting setting functions are
This is performed by the CPU 10a executing a predetermined debug monitor program written in the OM 12b. The RAM 14b is used when the CPU 10a is executed. The RAM 14b is used not only for writing the data of the debug monitor program itself, but also for writing systematic data when the debug monitor program is executed.

Further, in the above-mentioned debugger section 20, the event detecting section 16a uses a monitor address register and a monitor data register provided therein,
The internal bus is constantly monitored. The event detector 16
a compares the address data of the internal bus, especially the address bus A, with the address data written in the monitor address register, and determines whether or not they match. Further, the event detection unit 16a compares the data of the internal bus, particularly the data bus, with the data written in the monitor data register, and determines whether they match. The event detection unit 16a suspends the operation of the CPU 10a according to a preset event condition based on the match determination regarding the address bus and the match determination regarding the data bus.

That is, by using the monitor section 18a to set the monitor address register and the monitor data register of the event detecting section 16a as desired,
The event detection condition of the event detection unit 16a is set in advance, and when the internal bus has a certain event condition, the CPU 1
The operation of 0a can be stopped. For example, when the internal bus becomes a predetermined event condition, the CPU 1
0a can be stopped and the data of the RAM 14a at this time can be monitored, or the operating state of the CPU 10a, for example, the state of the internal register thereof can be monitored.

Therefore, according to the conventional integrated circuit with CPU as shown in FIG. 20, the CPU 10a is stopped under a desired event condition, such as when debugging the user program written in the ROM 12a, It is possible to effectively perform the debugging work such as monitoring the data in the RAM 14a.

[0014]

However, in the above-mentioned conventional CPU-mounted integrated circuit shown in FIG.
The debugger section 20 had to be provided inside.

As described above, the debugger section 20 includes, for example, the ROM 12b and the RAM 14b, requires many elements, and occupies a large area of the integrated circuit chip. Therefore, by providing such a debugger unit 20, there is a problem that the degree of integration of the CPU-integrated integrated circuit is reduced, and the manufacturing cost and the like are increased.

Generally, the above-mentioned integrated circuit with a CPU is incorporated in a mass-produced product such as a home air conditioner or a multi-function telephone, and the reduction of its cost is a major issue. If the degree of integration of the integrated circuit equipped with a CPU that is to be incorporated into such a mass-produced product is lowered, the above-mentioned problem of increased cost will occur.

On the other hand, the debugger unit 20 is connected to the CPU
It may be possible to attach the integrated circuit externally. However, in this case, the internal bus must be drawn to the outside of the CPU mounted integrated circuit.

For example, the above-mentioned CP shown in FIG.
In the U-mounted integrated circuit, a total of 24 signal lines of 16 address buses in total and 8 data buses in total must be led out of the CPU-mounted integrated circuit. As described above, if many signal lines are drawn out, the number of input / output pins provided in the package of the CPU-mounted integrated circuit increases.
Also, with such an increase in the number of pins, the size of the package also increases, which causes not only the problem of cost increase but also the problem of increase of mounting space.

The present invention has been made in order to solve the above-mentioned conventional problems, and does not significantly increase the number of circuits to be incorporated in a CPU-integrated circuit, and is also external to the CPU-integrated circuit. A CPU capable of improving debug workability, for example, by making it possible to monitor the data accessed by the CPU inside the CPU-equipped integrated circuit from the outside without pulling out the internal bus.
An object of the present invention is to provide an on-board integrated circuit and a debugger used for the CPU-on-board integrated circuit.

[0020]

A CPU according to the first invention of the present application
The on-board integrated circuit is a CPU that includes a CPU that executes a program written in the on-board memory.
In the on-board integrated circuit, the serial interface used to connect the debugger and the address of the memory address space in the debugger accessed by the CPU are stored in the CPU.
Is designated via the serial interface, an access data converter for passing data of the memory in the debugger accessed by the CPU via the serial interface, and an preset address The object is achieved by including a debug interrupt control unit that, when established, generates a debug interrupt to the debugger and stops the execution of the CPU.

On the other hand, the debugger of the second invention of the present application is a debug target C having a CPU for executing the program written in the memory mounted together.
A serial interface that is used by connecting to a PU-integrated circuit, a target memory that is accessed by the CPU and that has a predetermined memory address space, and the CPU that uses the target memory while addressing via the serial interface. Target addressing unit that addresses the target memory when accessing the target memory, and the target memory when the CPU accesses the target memory while addressing via the serial interface. The first object that can achieve the above-mentioned object by including an access data conversion unit that transfers data in the memory via the serial interface and a data monitor unit that stores the data stored in the target memory. Invention C It is obtained by providing a debugger is used to connect to a U mounting integrated circuits.

[0022]

When the CPU-equipped integrated circuit is debugged as described above, it is necessary to monitor the operation of the CPU-mounted integrated circuit from the outside by some method.

In the first invention and the second invention, a RAM or a ROM which is required to be monitored during debugging and which is accessed by the CPU in the CPU-integrated circuit is provided outside the CPU-integrated circuit, particularly outside the CPU-integrated circuit. I am trying. That is, for example, the so-called debugger side, which is used for debugging operation or the like, is provided. Further, access to the ROM and the RAM provided outside the CPU mounted integrated circuit from the CPU inside the CPU mounted integrated circuit is performed by serial communication.

Thus, the ROM or RAM accessed by the CPU can be easily monitored because the ROM and RAM are outside the CPU integrated circuit.

Further, the CPU in the integrated circuit incorporating the CPU of the first aspect of the invention and the CP in the debugger of the second aspect of the invention.
Since the ROM and the RAM accessed by the CPU of the U-mounted integrated circuit are connected by serial communication, there is no problem that the number of input / output pins increases and the package becomes large as in the conventional case. .

FIG. 1 is a block diagram showing the gist of the integrated circuit incorporating a CPU according to the first aspect of the present invention.

As shown in FIG. 1, the CPU-equipped integrated circuit of the first invention has a CPU 10 inside.
An external address designating section 22, an access data converting section 24, a serial interface 26, and a debug interrupt control section 16.

The CPU 10 shown in FIG. 1 is similar to the above-mentioned CPU 10a shown in FIG. 20 in that the address bus A and the data bus D of its internal bus allow the ROM or RAM not shown, or a predetermined memory. Connected to peripheral devices. These ROM and RA
Each of M is the same as that shown in FIG.

The CPU 10 of the first aspect of the invention can be switched between the normal mode and the debug mode.
In the normal mode, the CPU 10 operates using its internal bus, similar to the conventional CPU-mounted integrated circuit shown in FIG.

On the other hand, in the debug mode, the CPU
10 accesses the ROM, RAM, etc. in the debugger of the second invention through the external address designating section 22, the access data converting section 24, and the serial interface 26. When accessing in such a debug mode, the CPU-mounted integrated circuit of the first invention and the debugger of the second invention are connected by serial communication.

The external address designating section 22 uses the CP
It is used when the CPU 10 designates an address of a memory address space external to the CPU-integrated integrated circuit accessed by the U10, for example, an address of the memory address space in the debugger of the second invention by the serial communication as described above. . The external address designation unit 22 is, for example, the CPU.
The address specified by a total of m signal lines of the internal bus output by 10 is converted into a hexadecimal number having a predetermined number of digits.

Further, the access data conversion unit 24 converts the data of the memory external to the CPU mounted integrated circuit accessed by the CPU 10, for example, the data in the memory in the debugger of the second invention into the serial communication as described above. Used when handing over. The access data conversion unit 24
For example, the data of a total of n signal lines (data lines) of the internal bus input and output by the CPU 10 and the data represented by a hexadecimal number of a predetermined number of digits are mutually converted.

The serial interface 26 is parallel / serial-converted or serial / parallel-converted at the time of access to the outside of the integrated circuit incorporating the CPU, for example, serial communication connection at the time of access to the debugger of the second invention. I do. Further, the serial interface 26 also functions as a protocol controller in such serial communication. That is, the serial interface 26, together with the external address designating section 22 and the access data converting section 24, controls the protocol of serial communication relating to commands and passing data when the CPU 10 accesses.

For example, the serial interface 26
Generates a predetermined protocol when transmitting to the debugger of the second invention. On the other hand, when receiving from the debugger, the serial interface 26 decodes the received protocol.

In addition to such a configuration, the debug interrupt control section 16 is
The debugger according to the second aspect of the present invention generates a debug interrupt to the debugger and stops the execution of the CPU 10 when necessary. The debug interrupt control unit 1
The setting of the event as described in 6 is performed by the debugger via the serial interface 26. The setting is performed by, for example, the debug interrupt control unit 16
Is writing data to the monitor address register and the monitor data register provided therein.

The debug interrupt control unit 16 is, for example,
The data written in such a monitor address register is compared with the state of the address bus A of the internal bus, and the data written in such a monitor data register and the data bus D of the internal bus are compared. The above-mentioned event is established when they match. The debug interrupt to the debugger when such an event is established may be performed through the serial interface 26, or as shown in FIG. 1, an interrupt signal is directly output to the debugger. May be.

In the integrated circuit equipped with CPU of the first invention,
It is also conceivable to provide such a debug interrupt control unit 16 on the outside of the CPU integrated circuit, such as the debugger side of the second invention. However, in view of various debug work situations, the inventors have made the debug interrupt control unit 1
No. 6 finds that it is more effective to equip the CPU mounted integrated circuit side of the first invention. this is,
This is because, when the debug interrupt control unit 16 is provided on the debugger side, it is more difficult to quickly stop the execution of the CPU when the above-described event is established. .

As described above, according to the first invention, it is possible to access the external memory address space such as the ROM or the RAM in the debugger of the second invention while addressing it. Therefore, it is possible to relatively easily monitor the external memory such as the ROM and the RAM in the debugger, and the debugging workability can be improved. Also in this case, the external address designating section 22, the access data converting section 24, and the serial interface 26 have a smaller number of elements than the debugger section 20 shown in FIG.
Fewer problems such as lower integration. Further, in the first aspect of the present invention, it is not necessary to draw out the internal bus to the outside, and problems such as cost increase can be avoided.

The CP on which the integrated circuit with CPU of the first invention accesses during the debug mode.
The memory in the debugger external to the U-mounted integrated circuit does not necessarily have to be provided in the debugger, and the present invention does not limit this point. For example, the memory may be arranged outside the integrated circuit equipped with a CPU according to the first aspect of the present invention and can be accessed by a predetermined debugger. In this case, the same effect can be obtained. Can be obtained.

Further, the CPU-integrated circuit according to the first aspect of the present invention is not limited to the one in which all the internal memory is replaced with the external memory as described above in the debug mode. That is, at least the external memory as described above may be used.

FIG. 2 is a block diagram showing the gist of the debugger of the second invention.

The debugger of the second invention shown in FIG. 2 is the CPU of the first invention described above with reference to FIG.
Used by connecting to on-board integrated circuits. The debugger of the second invention shown in FIG. 2 mainly includes a serial interface 32, a target memory addressing unit 34, an access data conversion unit 35, a target memory 36, and a monitor unit 37. There is.

The serial interface 32 is used when connecting by serial communication to the CPU mounted integrated circuit of the first invention described above with reference to FIG. The serial interface 32 performs serial / parallel conversion or parallel / serial conversion when connected by serial communication in this way. Further, the serial interface 32 also functions as a protocol controller during such serial communication. Specifically, the serial interface 32 decodes the received protocol when receiving from the CPU-mounted integrated circuit.
On the other hand, when transmitting to the integrated circuit equipped with CPU, a protocol to be transmitted is generated.

The target memory 36 includes the first memory
It is a memory accessed by the CPU 10 included in the CPU-mounted integrated circuit of the invention. The target memory 36
Is, for example, a memory such as a ROM or a RAM.
The PU 10 is accessed during the debug mode as described above.

The target memory addressing section 34 is used when the CPU 10 accesses the target memory while addressing via the serial communication as described above. The target memory addressing unit 34 uses the CP for serial communication.
According to the decoding of the serial interface 32 of the protocol received from the U-mounted integrated circuit, the target memory 36 is addressed by the decoded address data. The target memory addressing unit 34 is, for example, the serial interface 3
Predetermined number of digits obtained by deciphering the protocol in 2
According to the hexadecimal address data, the target memory 36 is addressed by a predetermined number of signal lines, for example, a total of m signal line address lines.

The access data converter 35 is used when the CPU 10 accesses the target memory 36 while addressing it through the serial communication as described above.

The access data conversion unit 35, when addressing the target memory addressing unit 34 while writing predetermined data to the target memory 36, selects the serial interface 32 of the received protocol. The access data (write data) resulting from the decoding is converted into a form writable in the target memory 36. For example, the written hexadecimal access data of a predetermined number of digits is converted into data of n data lines input / output to / from the target memory 36.

On the other hand, the access data conversion section 35 reads out the read data when the predetermined data in the target memory 36 is read out while the target memory addressing section 34 is addressing. The interface 32 converts into a form that can be generated into a predetermined protocol. For example, in such a read access, the data of the total n data lines output from the target memory 36 is converted into hexadecimal data having a predetermined digit number.

The monitor section 37 is for monitoring the data written in the target memory 36 and for setting rewriting. As aforementioned,
Even if the target memory 36 is provided in the debugger of the second aspect of the invention, in the debug mode as described above, a memory such as a ROM or a RAM inside the CPU-integrated circuit of the first aspect of the invention. It is being accessed as etc. Therefore, by monitoring the target memory 36 during the debug mode, the C
It is possible to monitor the ROM and RAM in the PU integrated circuit.

As described above, according to the debugger of the second invention, it is possible to perform the debugging work efficiently by connecting to the CPU-equipped integrated circuit of the first invention described above with reference to FIG. For example, at the time of such a debugging operation, the ROM and the RAM of the CPU-equipped integrated circuit side in the normal mode of the CPU 10 are controlled by the monitor and the data setting of the target memory 36 provided in the debugger side of the second invention. The same thing as the monitor and data writing can be performed.

[0051]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 3 is a block diagram of a CPU-mounted integrated circuit to which the present invention is applied.

As shown in FIG. 3, the CP of this embodiment
The U-mounted integrated circuit mainly includes a CPU 10 and a ROM 1.
2, a RAM 14, a peripheral 15, an event detection unit 16, a monitor unit 18, an external address designation unit 22,
The access data converter 24 and the serial interface 26a are included.

The ROM 12 and the RAM 14 shown in FIG. 3 are the same as those shown in FIG. 20, and the peripheral 15 is the same as that shown in FIG.
Is the same as that described above using.

Further, the monitor 18 shown in FIG.
Is for monitoring the ROM 12, the RAM 14, and the peripheral 15 and writing data as in the monitor unit 18a shown in FIG. However, the monitor 18 shown in FIG. 3 performs such monitoring and data writing from the debugger side to which the second invention is applied through the serial interface 26a.

Further, the CPU 10 shown in FIG.
The external address designating section 22 and the access data converting section 24 are the same as those described above with reference to FIG. Also, the event detection unit 16a of FIG.
Corresponds to the debug interrupt controller 16 of FIG. The serial interface 26a of FIG. 3 has the functions of the monitor 18 described above in addition to the functions of the serial interface 26 described with reference to FIG.

Inside the CPU-mounted integrated circuit of the present embodiment shown in FIG. 3, the CPU 10 and the ROM 12 are provided.
The RAM 14, the peripheral 15, the event detector 16a, and the monitor 18 are connected by an internal bus. The internal bus is composed of an address bus having a total of 16 signal lines and a data bus having a total of 8 signal lines.

FIG. 4 is a ROM used in this embodiment.
3 is a memory map diagram of FIG.

In FIG. 4, reference numeral M1 is a memory map of the ROM 12 provided in the CPU-integrated integrated circuit of this embodiment. On the other hand, the code M2 is C in this embodiment.
FIG. 6 is a memory map diagram of a ROM provided inside a debugger to which the second invention is applied, which is connected to a PU-integrated circuit. The ROM in the debugger is actually a rewritable RAM so that the stored program can be easily changed. As a result, the debugging work efficiency is improved.

As indicated by the symbol M1 in FIG. 4, the memory address space of the ROM 12 is represented by a hexadecimal number.
It is changed from "0000" to "03FF". Further, as indicated by the symbol M2, the memory address space of the ROM in the debugger is a hexadecimal number from "0000" to "07FF". In this way, the ROM1
The memory address space of the debugger is twice as wide as the memory address space of 2.

FIG. 5 is a memory map diagram of the RAM of this embodiment.

Reference numeral M3 in FIG. 5 indicates the CP of this embodiment.
A memory map of the RAM 14 provided inside the U-mounted integrated circuit is shown. On the other hand, reference numeral M4 shows a memory map diagram of the RAM in the debugger to which the second invention is applied, which is connected to the CPU-mounted integrated circuit of the present embodiment. As indicated by the symbol M3 in FIG. 5, the memory address space of the RAM 14 inside the CPU-incorporated integrated circuit of this embodiment is "1000" to "10FF" in hexadecimal. On the other hand, as indicated by a symbol M4, the memory address space of the RAM on the debugger side is in hexadecimal numbers from "1000" to "13FF". That is, the area of the memory address space of the RAM on the debugger side is four times as large as the area of the memory address space of the RAM 14 inside the integrated circuit with CPU of this embodiment.

The first invention is also applied to this embodiment, and the CPU 10 has a first normal mode, a second normal mode, and a debug mode.

In the first normal mode (hereinafter, the first normal mode is also simply referred to as a normal mode), the memory address space of the CPU 10 is as follows.

(1) From "0000" to "03FF": Access the ROM 12 on the CPU mounted integrated circuit side. (2) From "1000" to "10FF": Access the RAM 14 on the CPU mounted integrated circuit side.

In the second normal mode, the CP
The memory address space of U10 is as follows.

(1) From "0000" to "03FF": Access the ROM 12 on the integrated circuit side with CPU (2) From "0400" to "07FF": Access ROM on the debugger side (3) From "1000" Up to “10FF”: Access the RAM 14 on the integrated circuit side with CPU (4) From “1100” to “13FF”: Access RAM on the debugger side

On the other hand, when the CPU 10 is in the debug mode as described above, the memory address space of the CPU 10 is as follows.

(1) From "0000" to "07FF": Access the ROM on the debugger side (2) From "1000" to "13FF": Access the RAM on the debugger side

The following ROM is stored in the ROM on the debugger side.

(1) Memory address space from "0000" to "03FF": A memory address space corresponding to that stored in the ROM 12 on the CPU mounted integrated circuit side is stored. However, it is not always the same as that stored in the ROM 12. It is also possible to make some changes if necessary.

(2) Memory address space from "0400" to "07FF": Mainly stores a debug monitor program and the like. The debug monitor program is executed by the CPU 10 in association with the monitor unit 18.

The memory address space of the RAM on the debugger side is used as follows.

(1) Memory address space from "1000" to "10FF": Used in the same manner as the RAM 14 on the CPU mounted integrated circuit side. However,
It is not always the same. It may be changed if necessary. This memory address space is mainly used corresponding to the user program stored in the ROM 12.

(2) Memory address space from "1100" to "13FF": Mainly used as a work data storage area of the debug monitor program. That is, it is mainly used for the debug monitor program written from "0400" to "07FF" in the ROM.

As described with reference to FIGS. 4 and 5, a ROM for storing the above-mentioned debug monitor program executed by the CPU 10 with respect to the monitor section 18 and the like, and a work data storage area used by the debug monitor program. Is not provided on the side of the CPU-mounted integrated circuit of this embodiment, so that the degree of integration of the CPU-mounted integrated circuit will not be unnecessarily increased. Further, during the debug mode as described above, since the memory address space of the ROM 12 and the memory address space of the RAM 14 are transferred to the debugger side, it is possible to easily monitor and change the data. That is, by monitoring the ROM or RAM on the debugger side or changing the data, the same thing as monitoring or changing the data of the ROM 12 or the RAM 14 in the normal mode can be performed. In particular, since the ROM on the debugger side is actually a RAM, it is possible to easily change the user program that accompanies the debugging work.

6 to 16 are protocol diagrams of a protocol used in serial communication between the CPU-mounted integrated circuit of this embodiment and the debugger.

6 to 16, "HD"
Is the header of each protocol. The header is different for all protocol types. The type of the protocol and the processing content are identified by the identification of the header HD. Further, "AD" indicates an address designated for the process or command such as reading or writing designated by the header HD. or,
"D" and "D1" to "Dn" indicate data transmitted by each protocol. Also, "T"
Is a so-called terminator indicating the end of the protocol, and includes data related to error control.

First, FIG. 6 is used by connecting to the target to which the second invention is applied from the CPU-mounted integrated circuit (hereinafter referred to as the target) of the present embodiment to which the first invention is applied. A protocol used when reading data at a desired address in a memory address space in a debugger (hereinafter, simply referred to as a debugger) is shown.
At the time of such a memory read, the upper protocol of FIG. 6 is first transmitted from the target to the debugger to convey the occurrence of the memory read and the target address. After this, the protocol shown in the lower part of FIG. 6 is transmitted from the debugger to the target. Read data is transmitted to the target by the protocol.

Next, FIG. 7 shows a protocol used when a desired memory is read from the memory address space in the debugger from the target. The memory reading is particularly used when reading an address next to the address of the previous memory reading. Therefore,
The protocol transmitted from the target to the debugger shown in the upper part of FIG. 7 does not include “address AD” indicating the address of the data to be read. This is because the header HD specifies that the data at the address next to the previously accessed address is read. The lower protocol of FIG. 7 is a protocol for transmitting the read data from the debugger to the target.

Next, referring to FIG. 8, from the target,
This is a protocol for reading consecutive addresses of the debugger. The protocol in the upper part of FIG. 8 is transmitted from the target to the debugger when a memory read request is made. In the header HD of the protocol,
Memory reading of this continuous address is designated. Further, the start address of this continuous address is designated by the address AD. Further, "N" designates the number of data (the number of bytes) to be continuously read. Also, this figure 8
The protocol below is for responding to memory read requests,
It is a protocol for transmitting the data read from the debugger to the target. The protocol includes a total of n pieces of data requested to be read.

FIG. 9 shows a protocol for writing a memory from the target to the debugger. The upper protocol of FIG. 9 is a protocol for transmitting the write address and the write data from the target to the debugger when writing to the memory. On the other hand, in the lower part of FIG. 9, there is a protocol transmitted from the debugger to the target in order to convey that the memory writing is completed.

FIG. 10 shows a protocol for writing a memory from the target to the debugger. Particularly, in the memory write by the protocol shown in FIG. 10, the protocol used when the memory write is performed to the address next to the previously accessed address is shown. Therefore, in the protocol of the memory write request sent from the target to the debugger shown in the upper part of FIG. 10, the data indicating the desired address to be written is not included. This is because the header HD of that protocol specifies that data should be written to the address next to the previously accessed address. The lower protocol of FIG. 10 is a protocol transmitted from the debugger to the target for notifying that the memory writing has been completed.

FIG. 11 shows a protocol used for memory writing when writing a large amount of data from the target to the debugger at consecutive addresses. In the upper part of FIG. 11, there is shown a protocol transmitted from the target to the debugger when such memory writing is performed. In this protocol, a start address of consecutive addresses for writing a plurality of data, the number of consecutively written data (the number of bytes),
The contents of each data to be written continuously are included. On the other hand, the lower part of FIG. 11 shows a protocol transmitted from the debugger to the target for transmitting the completion of such continuous memory writing.

The protocol shown in FIG. 12 is a protocol for monitoring a desired address of the target from the debugger. First, in the upper protocol of FIG. 12, the protocol transmitted from the debugger to the target in order to monitor the content of the data written in the memory is shown. The protocol includes the start address of the memory to be monitored,
The number of data to be monitored (the number of bytes) is included. On the other hand, the lower part of FIG. 12 shows a protocol for transmitting data from the target to the debugger in response to a request from the memory monitor. This protocol includes the data requested for monitoring.

The protocol shown in FIG. 13 is a protocol for writing data from the debugger to a desired address of the target, that is, for setting memory. First, the upper protocol of FIG. 13 is a protocol transmitted from the debugger to the target. The protocol includes the start address of the target, which is set in the memory from the debugger, the number of data (the number of bytes) set in the memory, and each data set in the memory. Further, the lower protocol of FIG. 13 is a protocol used for transmitting from the target to the debugger that the memory setting is actually completed.

The protocol shown in FIG. 14 is a protocol used when setting the operation mode of the target from the debugger. For example, with the setting of the first normal mode and the second normal mode as described above of the CPU of the target, and the debug mode as described above,
Further, it is used when stopping or starting the execution of the CPU or setting the one-step execution. This Figure 1
In the upper protocol of 4, the header HD indicates that the operation mode is set and the setting content. The protocol is sent from the debugger to the target. The lower part of FIG. 14 shows a protocol used when the target notifies the debugger that the operation mode setting is completed.

FIG. 15 shows a protocol used when the event setting of the event detecting unit 16a of the target is performed from the debugger. In particular, the protocol shown in FIG. 15 is used for event setting of an address. That is, it is a protocol for writing a desired address value in the above-mentioned monitor address register provided in the event detecting unit 16a. First, the upper protocol of FIG. 15 is transmitted from the debugger to the target and transmits the address value to be written in the monitor address register. On the other hand, this FIG.
The protocol below is sent from the target to the debugger to convey the completion of event setting of such an address.

FIG. 16 shows a protocol used when the event setting of the event detecting unit 16a of the target is performed from the debugger. In particular, the protocol shown in FIG. 16 is a protocol for setting the data of the monitor data register of the event detecting unit 16a. The upper protocol of FIG. 16 is transmitted from the debugger to the target, and includes data to be written in the monitor data register.
On the other hand, the protocol shown below in FIG.
It is a protocol transmitted from the target to the debugger.

Hereinafter, C of the present embodiment will be described using the specific example of the user program to be debugged and the communication sequence diagram.
The debugging work of the PU-integrated circuit will be described.

FIG. 17 is a specific example of a user program written in the ROM of the integrated circuit with CPU according to this embodiment.

In FIG. 17, the user program is written in the ROM 12 and also in the corresponding memory address of the ROM of the debugger as described above with reference to FIG. This FIG.
The user program shown in (1) adds the data stored in the address 1000 and the address 1002 shown in hexadecimal, and then adds this addition result to the address 1004.
It is to write in. In addition, the result of incrementing this addition result (increasing by 1) is the address 10
It is to write to 06. Further, the result of such increment is further incremented and written to the address 1008.

Of the programs shown in FIG. 17,
Steps 101, 102, 104, 106 and 108 are
The instruction consists of a total of 3 bytes. Therefore, the instructions in these steps require three addresses. Further, "LD" is an instruction to transfer data from one designated location to another designated location. “ADD” is to add the value of the designated first register and the value of the designated second register and store the addition result in the first register. “INC” is an instruction to increment the value of the designated register.

FIG. 18 is a communication sequence diagram when one step is executed in the debug mode in this embodiment.

In FIG. 18, according to the protocol shown in FIG. 14, the operation mode of the CPU 10 is set to the debug mode and the one-step execution mode, and the user program is debugged while executing it every step. At this time, the protocol exchange performed by serial communication between the debugger and the target is shown.

In FIG. 18 and FIG. 19 which will be described next, reference numerals S100, S102 and the like are steps indicating sequential protocol transmissions.

First, in step S100 of FIG. 18, the user who performs debugging performs an operation of stopping the operation of the CPU 10. According to this operation, the debugger transmits a protocol for stopping the operation of the CPU 10 to the target. The protocol is
It is the protocol shown above in FIG. When the target receives the protocol, the target actually stops the operation of the CPU 10. The CPU1
When 0 actually stops, the target transmits the completion of this stop to the debugger by a predetermined protocol by the protocol shown in the lower part of FIG. The protocol is shown in the lower part of FIG.
(Completion of acceptance and completion of execution) ”is transmitted.

When the "ACK" protocol is received,
With the debugger, the user can set the one-step execution of the CPU 10. In step S104, when the user sets this one-step execution setting, the protocol according to the setting is transmitted from the debugger to the target. The protocol is the protocol shown above in FIG. When the target receives the protocol, the target actually changes the execution state of the CPU 10 to the execution of each step. In this way, upon execution of each step, the target returns the protocol of "ACK" shown in the lower part of FIG. 14 to the debugger.

When the debugger receives the "ACK" protocol, the user can execute the operation step by step. When the user performs the operation of executing one step in step S108, the debugger transmits the accompanying protocol to the target. The protocol is the one shown in the upper part of FIG. When the target receives the protocol, the CPU
10 actually executes the user program only one step. For example, the user program as shown in FIG. 17 is executed only one step. When the execution of such one step is completed, the target returns the protocol shown in the lower part of FIG. 14 to the debugger.

Upon receipt of the protocol for completion of execution of one step, the user can perform operations such as target monitoring and data setting in step S112. For example, it is possible to confirm the contents of the RAM written in the CPU 10 after the execution of one step in steps 108 and 110. Also, the setting contents of the peripheral 15 can be confirmed. The data written in the RAM is monitored by the RAM in the debugger.
Can be done by reading

On the other hand, the data written in the peripheral 15 and the setting contents are monitored from the debugger side on the target side by a predetermined protocol. Therefore, when the target side such as the peripheral 15 is monitored in this way, the protocol shown in the upper part of FIG. 12 is transmitted to the target in step S112 while following the predetermined operation of the user. To be done. When the protocol is received, the target performs actual monitoring according to the received protocol in step S114.

In such a monitor on the target side, first, the protocol transmitted from the debugger to the target is received by the serial interface 26a in FIG. The number of addresses and data to be monitored in the received protocol are transmitted from the serial interface 26a to the monitor unit 18. The monitor unit 18 performs the monitoring requested by the address bus A and the data bus D of the internal bus. The monitor result is transmitted from the monitor unit 18 to the serial interface 26a.

According to the transmitted contents, in step S114, the serial interface 26a transmits the protocol shown in the lower part of FIG. 12 to the debugger. In this protocol, n data contents are transmitted from the start address requested by the monitor. Upon receipt of such a protocol from the serial interface 26a, the debugger will display this content in, for example, a CRT (ca
It is displayed to the user with a thode ray tube).

In FIG. 18, steps S116 and S118 perform the same operations as steps S112 and S114, respectively.

As described above with reference to FIG. 18, 1
According to the step execution and the desired monitor operation, the user program can be debugged while sequentially confirming the operation state of the target.

For example, while the user program as shown in FIG. 17 is executed step by step from step 101, the register A and the register B in the CPU 10 are
It is also possible to monitor the contents of. Further, in such a user program, whether or not the address accessed by the CPU 10 is correct, and whether the content of the accessed data is the same as expected or not can be easily determined by executing each step. It is possible to confirm.

FIG. 19 is a communication sequence diagram when debugging is performed by setting a stop event in this embodiment.

In FIG. 19, the user performs a predetermined stop event setting from the debugger side, and a state of debugging while monitoring the operating state of the CPU 10 etc. stopped by the set stop event setting is shown. It is shown.

In step S140 of FIG. 19, first, the user operates to stop the execution of the CPU 10.
Based on the operation, the debugger sends the protocol shown in the upper part of FIG. 14 to the target. Upon receiving the protocol, the target actually stops the execution of the CPU 10. CPU 1
When the execution of 0 is actually stopped, the next step S142
At, the target sends the protocol of "ACK" shown in the lower part of FIG. 14 to the debugger.

When the "ACK" protocol is received,
In step S144, the user can set the desired stop event. This stop event setting is based on the CP
This is the setting of conditions for stopping U10. For example, the CP
The condition is such that the CPU 10 is stopped at the time when the predetermined data is written in the predetermined address of the address space accessed by the U10. Such setting is actually to write data to the monitor address register in the event detection unit 16a or write data to the monitor data register, and these are performed by serial communication. .

When the user sets a desired stop event in step S144, the protocol shown in the upper part of FIG. 15 and the protocol shown in the upper part of FIG. 16 are transmitted from the debugger according to the stop event setting. Sent to the target. Upon receiving such a protocol, the target actually writes the received address value and data to the monitor address register and the monitor data register in the detection unit 16a in step S146. Upon completion of such writing, in step S146, "AC" shown in the lower part of FIG.
K ”protocol and“ A ”shown at the bottom of FIG.
The "CK" protocol is sent back to the debugger.

When such an "ACK" protocol is received, the user can restart the execution of the CPU 10 in the debugger and actually debug.

In step S148, the user uses the CPU
When an operation for starting execution of 10 is performed, a protocol based on the operation is transmitted from the debugger to the target. The protocol is the protocol shown in the upper part of FIG. When the target receives the protocol, execution of the CPU 10 is actually started.
When the execution is actually started, the target sends back the protocol of “ACK” shown in the lower part of FIG. 14 to the debugger. Also, in this way, the CPU 10
When the execution of (1) is started, a user program as shown in FIG. 17 is sequentially executed.

During execution of such a user program,
Execution of the CPU 10 is stopped when the above-described condition for setting the stop event, which is performed in step S144 or step S146, is satisfied. This Figure 1
In step 9, the condition is satisfied in step S152, and the execution of the CPU 10 is stopped. When the CPU 10 stops in step S152, the stop of the execution of the CPU 10 is transmitted to the debugger by the "ACK" protocol shown in the lower part of FIG.

When the "ACK" protocol is received, the user can operate the target monitor or the like in the debugger.

As described above with reference to FIG. 19, in the present embodiment, the desired stop event is set and the C
It is possible to stop the PU 10 and monitor the state of the target at this point, and it is possible to debug the user program more efficiently.

For example, when the user program as shown in FIG. 17 is executed from step 101, the predetermined stop event setting performed in step S144, step S146, etc. can be performed to perform debugging efficiently. . For example, in the user program shown in FIG. 17, the address "100" read and accessed in step 101 or step 102
It is uncertain what data is written in 0 ”or address“ 1002 ”, and depending on the content, if the user program or a user program executed thereafter malfunctions, it causes a malfunction. With regard to the data that occurs, it is possible to set the stop event as described above, so that it is possible to easily confirm what kind of program step is executed and the data that causes the malfunction is set. .

As described above, according to this embodiment, the data accessed by the CPU 10 can be easily monitored and the data can be changed, and the debugging workability can be improved. it can.

Further, in this embodiment, as shown in FIG. 3, the external address designating section 22, the access data converting section 24, and the serial interface 26a.
However, the RAM accessed during the debug mode is provided on the debugger side. Therefore, considering the increase in the storage capacity of the RAM provided on the debugger side, the external address designating unit 22 and the access data converting unit 24 are used.
The number of circuits incorporated in the CPU-mounted integrated circuit of this embodiment due to the serial interface 26a and the like is relatively small. Therefore, according to this embodiment, the C
It does not unnecessarily increase the integration degree of the PU-integrated circuit. Moreover, in this embodiment, since the debugger and the target are connected by serial communication, the number of input / output pins on the package of the target used for debugging can be further reduced.

[0120]

As described above, according to the present invention, C
Data to be accessed by the CPU inside the CPU-incorporated integrated circuit can be stored without significantly increasing the number of circuits to be incorporated in the PU-integrated integrated circuit and without pulling out the internal bus outside the CPU-integrated integrated circuit. Further, it is possible to obtain an excellent effect that the debug workability can be improved, such that monitoring can be performed from the outside.

[Brief description of drawings]

FIG. 1 is a block diagram showing the gist of a first invention of the present application.

FIG. 2 is a block diagram showing the gist of a second invention of the present application.

FIG. 3 is a block diagram of a CPU-mounted integrated circuit of an embodiment to which the first invention and the second invention are applied.

FIG. 4 is a memory map diagram of a ROM according to the embodiment.

FIG. 5 is a memory map diagram of the RAM according to the embodiment.

FIG. 6 is a protocol diagram of a protocol used when reading a memory (with address designation) from a target in the above embodiment.

FIG. 7 is a protocol diagram of a protocol used when reading a memory from a target (next address) in the embodiment.

FIG. 8 is a protocol diagram of a protocol used when reading a memory (sequential address) from a target in the above embodiment.

FIG. 9 is a protocol diagram of a protocol used when writing a memory (with address designation) from a target in the above embodiment.

FIG. 10 is a protocol diagram of a protocol used when writing a memory (next address) from a target in the embodiment.

FIG. 11 is a protocol diagram of a protocol used at the time of memory writing (sequential address) from the target in the embodiment.

FIG. 12 is a protocol diagram of a protocol used when the memory is monitored from the debugger in the above embodiment.

FIG. 13 is a protocol diagram of a protocol used when setting a memory from the debugger in the embodiment.

FIG. 14 is a protocol diagram of a protocol used when setting an operation mode from the debugger in the above embodiment.

FIG. 15 is a protocol diagram of a protocol used when setting an event (address) from the debugger in the embodiment.

FIG. 16 is a protocol diagram of a protocol used when setting an event (data) from the debugger in the embodiment.

FIG. 17 is a diagram showing an example of a user program written in the ROM of the embodiment.

FIG. 18 is a communication sequence diagram during debugging by one-step execution in the above embodiment.

FIG. 19 is a communication sequence diagram during debugging by setting a stop event in the above embodiment.

FIG. 20 is a block diagram showing a configuration of a conventional CPU-mounted integrated circuit.

[Explanation of symbols]

10, 10a ... CPU 12, 12a, 12b ... ROM 14, 14a, 14b ... RAM 16 ... Debug interrupt control section 16a ... Event detection section 18, 18a ... Monitor section (target side) 20 ... Debugger section 22 ... External address designation section 24 ... Access data conversion unit 26, 26a ... Serial interface (target side) 32 ... Serial interface (debugger side) 34 ... Target memory addressing unit 35 ... Access data conversion unit 36 ... Target memory 37 ... Monitor unit (debugger side) M1 to M4 ... Memory address space P1 to P11 ... Protocol HD ... Header AD ... Address D ... Data N ... Data (number, etc.) T ... Terminator

Continuation of the front page (51) Int.Cl. ⁵ Identification number Office reference number FI Technical display location G06F 15/78 510 K 7323-5L H01L 27/04 T 8427-4M

Claims (2)

[Claims] 1. A CPU-equipped integrated circuit having a CPU for executing a program written in a memory mounted together, a serial interface used for connection of a debugger, and a memory address in the debugger accessed by the CPU. An external address designating unit for designating a space address by the CPU via the serial interface; and an access data converting unit for delivering data of the memory in the debugger accessed by the CPU via the serial interface. A CPU-integrated integrated circuit, comprising: a debug interrupt control unit for generating a debug interrupt to the debugger and stopping the execution of the CPU when a preset event is established. 2. A serial interface used by connecting to a CPU-equipped integrated circuit as a debug target having a CPU for executing a program written in a memory mounted together, and a predetermined memory accessed by the CPU. A target memory having an address space; a target addressing unit for addressing the target memory when the CPU accesses the target memory while addressing via the serial interface; An access data conversion unit that transfers data in the target memory via the serial interface when the CPU accesses the target memory while addressing via the serial interface; And a data monitor unit for the data stored in the storage memory.