KR100526547B1 - Method for managing nand flash memory in terminal including dual dhip - Google Patents

Abstract

The present invention provides a method for managing errors that may occur during memory access in using a NAND flash memory. According to an aspect of the present invention, there is provided a terminal including a first controller and a second controller, and a memory for storing data required by the first controller and a NAND flash memory for storing data required by the second controller. Storing the main area ECC and the spare area ECC stored in the spare area in a memory used by the first control unit; and the main area ECC and spare area stored in the spare area of the NAND flash memory by the second control unit when the terminal is booted. Comparing the ECC of the main area and the spare area which have previously stored the ECC in the memory of the first control unit, and if the 1-bit error occurs in the ECC of the NAND flash memory after performing the comparison process, the ECC is stored in the memory of the first control unit in advance. The process of modifying the ECC of the NAND flash memory based on the ECC of one main area and the spare area. The features.

Description

TECHNICAL FOR MANAGING NAND FLASH MEMORY IN TERMINAL INCLUDING DUAL DHIP

The present invention relates to a memory management method, and more particularly, to a method for managing a NAND flash memory in a terminal having a dual chip.

Recently, the field of mobile communication has been rapidly developed, and accordingly, various functions can be performed in the mobile communication terminal. In particular, with the rapid development of multimedia-related functions, a single chip for operating a mobile communication terminal has caused a lot of data processing. Therefore, the mobile communication terminal may be equipped with a dual chip including a modem chip for performing a function of a general terminal and a multimedia related chip for performing a function related to multimedia, thereby enabling multimedia related functions to operate more efficiently. have. As described above, the current mobile communication terminal can use a camera and an LCD (Liquid Crystal Display) by using a multimedia dedicated chip for performing a multimedia function. In addition, it is possible to efficiently control the distribution of the load on each chip by performing a role such as transmitting multimedia-related files while performing multimedia-related functions through a chip dedicated to the modem. In a mobile communication terminal using a multimedia dedicated chip and a modem chip, each chip operates separately except for communication using a communication means such as FIFO (Fist In First Out) or Dual Poted RAM (DPRAM). In this case, the DPRAM is a RAM having two ports, and has two address buses to enable communication between two central processing units (CPUs). It is designed for CPUs used for tightly coupled multiprocessing. The role of DPRAM is to deliver the multimedia-related information to the multimedia-only chip when the modem chip wirelessly receives the multimedia-related information, and to deliver the information produced by the multimedia-only chip to the mobile communication terminal of the other party talking over the air. It transfers to the modem chip.

A general mobile communication terminal uses a flash memory as a storage means for storing codes, fonts, contents, etc. necessary for various terminal operations. NOR and NAND flash are mainly used as such flash memories. In the past, NOR flash was widely used as a flash memory, but nowadays, a storage means is shifting to NAND flash which can store a lot of data and is inexpensive in terms of price. As described above, NAND flash is about 1/4 the price of NOR flash, and currently has a large storage space of 1G Bit. The internal structure of the NAND flash is divided into a main area and a spare area. A main area is used to store commonly used codes, and a spare area is used to store ECC codes, which are error correction information about the main area. The spare area also stores error correction information of itself, that is, the spare area. The reason for storing the error correction information in the NAND flash is that it has a great advantage of low price and large capacity, while bit error of 1 bit or more than 2 bit may occur during reading or writing the flash. In addition, the memory cell may be broken during the initial process, and when the memory cell is broken during the process, the spare area may be marked as a block that cannot be used in the process. When used, this information is read and used except for this block. Increasingly, NAND flash having such characteristics is applied to mobile communication terminals, and the use of MCP (Micro Control Processor) including NOR or NAND flash and synchronous dynamic random access memory (SDRAM) in a single package is increasing. . The trend of using the MCP (Micro Control Processor) is increasing to meet the requirements of the mobile communication terminal which is becoming smaller and lighter.

Referring to FIG. 1, which is a diagram showing the structure of such a NAND flash region, as shown in FIG. 1, the NAND flash is a 256-word (512-byte) main area and an 8-word (16-byte) spare area. It is divided into (Spare area). As described above, a structure composed of a main area and a spare area is called a page in a NAND flash, and data is written or read in units of pages shown in FIG. 1 in a NAND flash. If a 1-bit error occurs in the main area (512 bytes) while using such a NAND flash, this bit error can be corrected and used. For this purpose, error correction information (ECC) generation and correction methods are provided. Used. However, if an error occurs more than 2 bits, it is recognized as a block that cannot be corrected, that is, an unusable block (hereinafter referred to as a 'Bad block') and used in the spare area after displaying it in the spare area. I never do that. When writing data to the NAND flash, check the write operation completion status register, and if it indicates that this register has failed, correct it if 1-bit error occurs after reading and comparing the data already written. . In addition, when an error of 2 bits or more occurs, it is displayed in the spare area as a bad block and is not used from the next time. The ECC for the main area generated at this time is stored in a spare area. The following sequence is used to read a NAND flash. First, read the ECC of the main area previously stored in the spare area. Generate ECC for the current main area and compare it with the read ECC value to check how many bit errors have occurred. Thereafter, when an error occurs in the spare area, the error is corrected in the spare area if it is a 1-bit error. In addition, such error correction is not made for all 16 bytes of the spare area, and usually only for 3 bytes storing important data. Therefore, the remaining bytes cannot be dealt with in the case of any error occurrence.

As described above, error correction is not possible for all bit error occurrences in the spare area of the NAND flash memory area used in a terminal having a dual chip, thus causing a management problem.

Accordingly, an object of the present invention is to provide a method for managing errors that may occur during memory access in using a NAND flash memory.

Another object of the present invention is to provide a method for enabling error correction for all bit error occurrences in all spare areas of a NAND flash memory.

The present invention for achieving the above object is provided with a first control unit and a second control unit, a terminal having a memory for storing the data required by the first control unit and a NAND flash memory for storing the data required by the second control unit The method of claim 1, wherein the main area ECC and the spare area ECC stored in the spare area of the NAND flash memory are stored in a memory used by the first control part, and when the terminal is booted, the second control part of the NAND flash memory is stored. Comparing the main area ECC and the spare area ECC stored in the spare area with the ECC of the main area and the spare area pre-stored in the memory of the first controller; and performing the comparison process, after performing the comparison process, the NAND flash memory If a 1-bit error occurs in the ECC of the pre-stored in the memory of the first controller And modifying the ECC of the NAND flash memory based on the ECC of the main area and the spare area.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In describing the present invention, if it is determined that the detailed description of the related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

The present invention relates to a spare area management method in which the ECC of the NAND flash is stored when the NAND flash is used as a storage means in the dual chip. Among the dual chips, a modem chip (hereinafter referred to as a modem controller) may use NOR flash memory or NAND flash memory, and a multimedia related chip (hereinafter referred to as an application controller) uses NAND flash memory. Assume

Then, when one control unit uses the NAND flash memory with reference to FIG. 2, the ECC for the main / spar area is stored in the memory of the other control unit, and the ECC stored in the other memory during booting is the ECC of the NAND flash memory. This section describes how to correct a bit error after comparing with.

2 is a block diagram illustrating a terminal having a dual chip and a memory corresponding to each chip according to an exemplary embodiment of the present invention.

First, the controller 200 controls the overall operation of the mobile communication terminal using the duup chip. The controller 200 includes a modem controller 210 and an application controller 220. The application control unit 200 controls a camera and an LCD (liquid crystal display) as a multimedia dedicated chip for performing a function related to multimedia. In addition, the application control unit 200 transmits data to the modem control unit 210 to transmit the multimedia-related files while performing a multimedia-related function. At this time, the application control unit 220 and the modem control unit 210 communicates using a communication means such as FIFO (Fist In First out) or DPRAM (Dual Poted RAM). Here, DPRAM (Dual Poted RAM) is a RAM having two ports, and has two address buses to enable communication between two central processing units (CPUs). It is designed for CPUs used for tightly coupled multiprocessing. The role of the DPRAM is that when the modem control unit 210 receives multimedia-related data wirelessly, the modem control unit 210 transmits the multimedia data to the application control unit 220, and the application control unit 220 receives the mobile communication terminal of the other party who is receiving the call. Control to send In this way, the data transmission and reception related operations are controlled by the modem controller 210 and multimedia related data processing is controlled by the application controller 220 to efficiently distribute loads applied to the respective controllers.

The application control unit 220 stores data generated while performing multimedia-related functions in the NAND flash memory 242 which is cheaper and larger in capacity than the NOR flash memory. However, the NAND flash memory 242 has the advantage of having a cheap and large storage space, while the probability of error that is not present in the NOR flash memory is large, and the location and time at which such an error occurs are random and may occur depending on temperature. There are drawbacks to this. The occurrence of such an error will be described in more detail with reference to FIG. 1. EDD (M_ECC) for the main area and ECC (S_ECC) for the spare area are stored in the spare area, respectively. If an error occurs in the two areas, the error can be corrected when the error is 1 bit in all areas. However, if the error is more than 2 bits, it cannot be corrected. Instead, if an error occurs more than 2 bits, treat the block as bad block and do not use it afterwards. However, the ECC (S_ECC) for the spare area does not correspond to all 16 bytes of the spare area, but only for the leftmost 3 bytes (word 0, word 1, word 2) of the spare area. Therefore, the remaining bytes (word 3, word 4, word 5, word 6, word 7) can not cope with any error occurrence case.

In the present invention, the ECC of the NAND flash memory 242 is stored in advance in the modem memory 232, which is another memory, and the ECC stored in the NAND flash memory and the ECC stored in the modem memory, in order to prevent the error of the spare area. By comparison, it can be corrected if a bit error occurs. That is, when the application control unit 220 is booted, the modem memory of the modem control unit 210 when the predetermined portion of the NAND flash memory 242 in which the code is stored in the booting sequence is read and transferred to the second SDRAM 244. The ECC group previously stored at 232 is compared with the ECC group stored in the spare area of the NAND flash memory 242 and checked. At this time, if a 1-bit error occurs, it is possible to guarantee a part of a spare area that has not been conventionally guaranteed.

First, the ECC for the main area and the spare area generated in the NAND flash memory 242 used by the application control unit 220 is stored in the modem memory 232 of the modem control unit 200. In this case, when the modem memory 232 is a NOR flash memory, ECCs for the main area and the spare area generated in the NAND flash memory 242 are stored in the NOR flash memory 232. In addition, when the modem memory 232 is a NAND flash memory, ECCs for the main area and the spare area generated in the NAND flash memory 242 are stored in the NAND flash memory 232.

Next, a storage process for storing the ECC group of the NAND flash memory 242 in the modem memory 232 as described above will be described with reference to FIGS. 3 to 5.

The NAND flash memory 242 is composed of a plurality of pages as much as the storage space of the NAND flash memory. One page is composed of a main area (512 bytes) and a spare area (16 bytes) as shown in FIG. Hereinafter, the ECC information of the main area for all pages of the NAND flash memory 242 is called a main area ECC group, and the ECC information of the spare area is called a spare area ECC group.

3 is a diagram illustrating a method of storing an ECC group of the NAND flash memory 242 in the modem memory 232 according to an embodiment of the present invention. The entire main area ECC information 300 and the spare area ECC information 302 for each page of the NAND flash memory 242 as described above are stored in the ECC group area 300 of the main area of the modem memory 232. Also, it is stored in the ECC group area 302 of the spare area. At this time, the format of the ECC group 300 of the main area of the NAND flash memory 242 and the ECC group 302 of the spare area stored in the modem memory 232 will be described with reference to FIGS. 4A and 4B. 4A is a diagram illustrating the format of the ECC group 300 of the main area of the NAND flash memory 242 transferred from the NAND flash memory 242 to the modem memory 232. 4B is a diagram showing the format of the ECC group 302 in the spare area of the NAND flash memory 242 transferred from the NAND flash memory 242 to the modem memory 232.

The ECC group stored in the spare area of the NAND flash memory 242 is divided into the ECC group of the main area and the ECC group of the spare area as shown in FIG. 3 in the modem memory 232 in the format shown in FIGS. 4A and 4B. This is to cope with when the ECC of the main area and the ECC of the spare area are distinguished and only one of them is compared in the comparison step. Storing the block number and page number together for each ECC is to avoid comparing the pages of unused blocks when booting later if necessary. A header for indicating that the ECC group is used, and the number of blocks for indicating how many blocks are used are stored. The block number, page number, and ECC are stored. Since 32 page numbers are generally mapped automatically for one block number, the same block number is not written for the remaining page numbers.

In the spare area of the NAND flash memory 242, an area to be actually protected from 13 bytes (104 bits) in which data codes other than ECC information are stored is 34 bits per page (512 bytes). This is because the ECC for the main area is 24 bits and the ECC for the spare area has 10 bits. Currently, the total size of NAND flash memory of a mobile communication terminal which is generally used is up to 64 MBytes. Therefore, when the NAND flash memory 242 is a memory having a size of 64 MBytes (512 Mbits), the size of the main area ECC group is 384 KByte, and the size of the spare area ECC group is 160 KByte. The sum of both main and spare ECC codes is 544 Kbytes. It is not unreasonable to store this size of data in other memory.

In general, when a mobile communication terminal including the NAND flash memory 242 is booted, a boot code is first transmitted from the NAND flash memory 242 to the second SDRAM 244, and the second SDRAM 244 is used. The boot code transferred to reads the application code back to a predetermined area of the second SDRAM 244. Then, the PC (Program Counter) is placed at the beginning of the read area. After that, the application runs. Therefore, when the ECC group is compared with respect to the entire area of the NAND flash memory 242 at boot time, the boot time may be slightly increased. Therefore, when saving an ECC group, save only the area that will be used for future booting.

In order to prevent an error in the spare area as described above, the ECC of the NAND flash memory 242 is previously stored in the modem memory 232, which is another memory, and the code is stored in the boot sequence when the application control unit 220 is booted. The predetermined portion is read and stored in the second SDRAM 244. In this case, the application control unit 220 compares the ECC groups stored in the NAND flash memory 242 with the ECC groups previously stored in the modem memory and corrects an error when it occurs. That is, when booting, ECCs stored in the modem memory 232 are transferred to the second SDRAM 244 of the NAND flash memory 242 and compared with the ECC group stored in the spare area. If a bit error occurs, it is corrected. Next, a management process for correcting an error when an error occurs in an area where the ECC is stored in the spare area of the NAND flash memory will be described with reference to FIG. 5.

FIG. 5 is a diagram illustrating a process for managing an area in which an ECC is stored in a spare area of a NAND flash memory during booting according to an exemplary embodiment of the present invention.

First, as shown in FIG. 3, the ECC group of the main area and the spare area stored in the spare area of the NAND flash memory 242 is previously stored in the modem memory 232. After booting, the ECC group stored in the modem memory 232 of the modem controller 210 is transferred back to the second SDRAM 244 of the application controller. Referring to FIG. 5, a flow of signals transmitted between the application controller 220 and the modem controller 210 is illustrated. When booting first, in step 500, the application control unit 220 transmits a signal to start the ECC transmission to the modem control unit 210. Upon receiving this, the modem controller 210 transmits a signal in response to the signal in step 500. Thereafter, the application controller 220 transmits a signal to the modem controller 210 to transmit an ECC group for the main region, and the modem controller 210 transmits a signal to the ECC group 300 of the main region stored in the modem memory 232. ) Is transmitted to the application control unit 210 in step 506. Then, in step 508, the application control unit 220 transmits a signal to the modem control unit 210 to transmit the ECC group for the spare area, and the modem control unit 210 transmits a signal to the spare area stored in the modem memory 232. The ECC group 302 is transmitted to the application controller 210 in step 510. When the transmission of the ECC group of the main area and the ECC group of the spare area is completed, the application control unit 220 transmits a signal indicating that all ECCs have been transmitted to the modem control unit 210 in step 512. In step 514, the response signal is transmitted to the application controller 220.

As described above, in the present invention, when the first control unit uses the NAND flash memory in the terminal having a dual chip, the second control unit at boot time is stored in advance in the memory of the second control unit in the ECC information of the main / spar area. If there is a bit error compared to ECC information stored in the memory, it can be corrected.

As described above, the present invention stores the same ECC as the ECC information of the NAND flash memory in another memory in advance, compares the ECC information of the NAND flash memory with the ECC stored in advance at boot time, and stores in advance when a 1-bit error occurs. Modifications can be made based on existing ECC information. This has the advantage of guaranteeing a portion of the spare area of the NAND flash memory that did not guarantee the conventional bit error.

1 is a diagram illustrating a structure of a general NAND flash memory region;

2 is a block diagram showing a terminal having a dual chip according to an embodiment of the present invention,

3 is a view for explaining a method of storing an Error Correcting Code (ECC) of a NAND flash memory in another memory according to an embodiment of the present invention;

4A and 4B illustrate an ECC group format for storing an ECC group from a NAND flash memory to another memory according to an embodiment of the present invention;

FIG. 5 is a diagram illustrating a process for managing an area where an ECC is stored in a spare area of a NAND flash memory during booting according to an exemplary embodiment of the present invention. FIG.

Claims (5)

A terminal having a first control unit and a second control unit, and having a memory for storing data necessary for the first control unit and a NAND flash memory for storing data necessary for the second control unit, Storing a main area ECC (Error Correcting Code) and a spare area ECC stored in the spare area of the NAND flash memory in a memory used by the first controller; When the terminal is booted, the second control unit stores the main area ECC and the spare area ECC stored in the spare area of the NAND flash memory in the memory of the first control unit and the ECC of the spare area, respectively. Comparison process, Modifying an ECC of the NAND flash memory based on ECCs of the main area and the spare area previously stored in the memory of the first controller when a 1-bit error occurs in the ECC of the NAND flash memory after performing the comparing process; NAND flash memory management method characterized in that consisting of. The NAND flash memory management method of claim 1, wherein the memory of the first controller is a NAND flash memory or a NOR flash memory. The method of claim 1, wherein the storing of the ECC for the main area and the spare area generated in the NAND flash memory in a memory of the first controller includes: The ECCs stored in the spare area of the NAND flash memory are stored in the memory of the first controller by dividing the ECC group of the main area and the ECC group of the spare area. The method of claim 3, wherein the ECC group of the main region, And a header for indicating that the ECC group, a number of blocks for indicating how many blocks are used, a number and a page number of the block, and ECC information. The method of claim 3, wherein the ECC group of the spare area, And a header for indicating that the ECC group, a number of blocks for indicating how many blocks are used, a number and a page number of the block, and ECC information.