CN115243047A

CN115243047A - Video compression method, device, equipment and medium

Info

Publication number: CN115243047A
Application number: CN202210868405.1A
Authority: CN
Inventors: 张贞雷; 李拓; 满宏涛; 刘同强; 周玉龙; 邹晓峰; 王贤坤
Original assignee: Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Center Co Ltd
Current assignee: Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Center Co Ltd
Priority date: 2022-07-22
Filing date: 2022-07-22
Publication date: 2022-10-25

Abstract

The present invention relates to the field of video processing technologies, and in particular, to a video compression method, apparatus, device, and medium. The method comprises the following steps: converting RGB format video data received from a host into YUV format data by using a color space conversion module; judging whether the FIFO array module is normal or not; in response to the abnormality of the FIFO array module, the YUV format data is written into an external DDR by using a color space conversion module; reading YUV format data from external DDR by using a central processing unit, converting the YUV format data into BLOCK format data, and writing the BLOCK format data into the external DDR; the method comprises the steps of reading BLOCK format data from an external DDR by using a video compression module, compressing the BLOCK format data to obtain first video compression data, and writing the first video compression data into the external DDR. The scheme of the invention does not depend on the FIFO array module to buffer data any more, thereby improving the stability of video compression.

Description

Video compression method, device, equipment and medium

Technical Field

The present invention relates to the field of video processing technologies, and in particular, to a video compression method, apparatus, device, and medium.

Background

The transmission flow of the video compression system in the baseboard management control chip is as follows: firstly, the VGA transmits video information of a HOST HOST to a video compression control module for video compression, after the compression is completed, data is written into a DDR, an EMAC (network card) drive reads the compressed data, and the video data is transmitted to a remote place through a network for remote display. Referring to fig. 1A and fig. 1B, the logic of the compression processing executed inside the bmc is as follows: the original video information at the host end is in RGB format, and is converted into YUV format (according to a matrix conversion formula) through RGB2YUV format conversion, and then converted into BLOCK format data through a YUV2BLOCK module to be input to CMP (video compression IP).

In the prior art, the conversion of YUV format data into BLOCK format data mainly depends on a FIFO array module on a baseboard management control chip, and according to the BLOCK format conversion requirement, 16Y _ FIFOs, 8U _ FIFOs, and 8V _ FIFOs are needed, and according to project practice experience, when the maximum resolution is 1920 × 1200, the situation that the FIFOs are not full can be met only by requiring the depth of the FIFOs to be 16384 and the width to be 8 bits. Since the video data at the host end is generated continuously, if the FIFO is full at this time, the data will be lost. Therefore, the traditional method for compressing video by relying on the FIFO array module has the following disadvantages: the method is characterized in that extremely large on-chip resources are occupied, meanwhile, the number of FIFO/RAMs is large (32), the depth of each FIFO/RAM is deep (16384, the FIFO/RAMs are generally formed by splicing 16 1024 RAMs, so that 16 × 32=512 RAMs with the depth of 1024 are needed in total), the large number of centralized RAMs cause great risks in comprehensive constraint, layout and wiring, packaging and manufacturing and the like at the rear end of a chip, and the stability of the video compression function of a substrate management control chip after tape-out is poor.

Disclosure of Invention

In view of the foregoing, it is desirable to provide a video compression method, apparatus, device and medium.

According to a first aspect of the present invention, there is provided a video compression method, the method comprising:

converting RGB format video data received from a host into YUV format data by using a color space conversion module arranged on a substrate management control chip;

judging whether an FIFO array module arranged on a substrate management control chip is normal or not;

in response to the abnormality of the FIFO array module, the YUV format data is written into a DDR (double data rate) arranged outside a substrate management control chip by using the color space conversion module;

reading the YUV format data from DDR arranged outside the baseboard management control chip by using a central processing unit arranged on the baseboard management control chip, converting the YUV format data into BLOCK format data, and writing the BLOCK format data into the DDR arranged outside the baseboard management control chip;

and reading the BLOCK format data from the DDR arranged outside the baseboard management control chip by using a video compression module arranged on the board management control chip, compressing to obtain first video compression data, and writing the first video compression data into the DDR arranged outside the baseboard management control chip.

In some embodiments, the method further comprises:

in response to the FIFO array module being normal, the YUV format data is written into the FIFO array module by using the color space conversion module;

reading data from the FIFO array module by using a read-write control module arranged on a substrate management control chip according to a BLOCK format and sending the data to the video compression module;

and compressing the data read from the FIFO array module by using the video compression module to obtain second video compression data, and writing the second video compression data into a DDR (double data rate) arranged outside a substrate management control chip.

In some embodiments, the method further comprises:

responding to a video acquisition request sent by a remote device to a network card arranged on a substrate management control chip through a network, and reading the first video compressed data or the second video compressed data from a DDR arranged outside the substrate management control chip by using the network card arranged on the substrate management control chip;

and sending the first video compression data or the second video compression data to a remote device through a network by utilizing a network card arranged on a substrate management control chip.

In some embodiments, the determining whether the FIFO array module disposed on the bmc chip is normal includes:

judging whether each bit of the second video compressed data is abnormal or not, and judging whether the color of an image obtained after the second video compressed data is decompressed is different or not and whether the image has horizontal stripes or not;

in response to the exception of at least one of the second video compression data, confirming that the FIFO array module is abnormal;

in response to the difference of image colors obtained after the second video compressed data is decompressed, determining that the FIFO array module is abnormal;

confirming that the FIFO array module is abnormal in response to the existence of horizontal stripes in the image obtained after the second video compressed data is decompressed;

and confirming that the FIFO array module is normal in response to the fact that all bits of the second video compressed data are not abnormal, the image color obtained after the second video compressed data is decompressed is not different, and the image obtained after the second video compressed data is decompressed is not provided with horizontal stripes.

In some embodiments, any one of YUV420 write logic, YUV422 write logic and YUV444 write logic is adopted for writing YUV format data into the DDR external to the bmc chip and into the FIFO array module, and any one of YUV420 read logic, YUV422 read logic and YUV444 read logic is adopted for reading data from the DDR external to the bmc chip by the central processor and for reading data from the FIFO array module by the read-write control module.

In some embodiments, the color space conversion module communicates with the host via a PCIe protocol, and both the color space conversion module and the video compression module communicate with a DDR external to the bmc chip via an AXI interface protocol.

According to a second aspect of the present invention, there is provided a video compression apparatus, the apparatus comprising:

the first conversion module is configured to convert RGB format video data received from a host into YUV format data by using a color space conversion module arranged on a substrate management control chip;

the judging module is configured for judging whether the FIFO array module arranged on the substrate management control chip is normal or not;

the first writing module is configured to respond to the FIFO array module exception, and write the YUV format data into a DDR (double data rate) arranged outside a substrate management control chip by using the color space conversion module;

the second conversion module is configured to read the YUV format data from the DDR arranged outside the baseboard management control chip and convert the YUV format data into BLOCK format data by using a central processing unit arranged on the baseboard management control chip, and write the BLOCK format data into the DDR arranged outside the baseboard management control chip;

the first compression module is configured to read the BLOCK format data from the DDR arranged outside the baseboard management control chip and compress the BLOCK format data to obtain first video compression data by using the video compression module arranged on the board management control chip, and write the first video compression data into the DDR arranged outside the baseboard management control chip.

In some embodiments, the apparatus further comprises:

the second writing module is configured to write the YUV format data into the FIFO array module by using the color space conversion module in response to the FIFO array module being normal;

the third conversion module is configured to read data from the FIFO array module according to the BLOCK format by using a read-write control module arranged on the baseboard management control chip and send the data to the video compression module;

and the second compression module is configured to compress the data read from the FIFO array module by using the video compression module to obtain second video compression data, and write the second video compression data into a DDR (double data rate) arranged outside the substrate management control chip.

According to a third aspect of the present invention, there is also provided a computer apparatus comprising:

at least one processor; and

a memory, in which a computer program is stored, the computer program being executable on a processor, the processor executing the video compression method as described above.

According to a fourth aspect of the present invention, there is also provided a computer-readable storage medium storing a computer program which, when executed by a processor, performs the aforementioned video compression method.

The video compression method improves the video compression processing mode of the traditional substrate management control chip, adopts DDR (double data rate) buffer YUV format data arranged outside the substrate management control chip when an FIFO (first in first out) array module is abnormal, unloads a conversion task from the YUV format data to a BLOCK format to a central processing unit on the substrate management control chip for execution, and does not completely rely on the FIFO array module to buffer the YUV format data, thereby avoiding the situations of chip rear end design, time sequence constraint, layout wiring and chip video compression function abnormity caused by the large FIFO number of the FIFO array module, improving the stability of the video compression function in the substrate management control chip, and enriching the video compression mode by adopting the substrate management control chip.

In addition, the invention also provides a video compression device, a computer device and a computer readable storage medium, which can also realize the technical effects and are not repeated herein.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by using the drawings without creative efforts.

FIG. 1A is a block diagram of a conventional BMC compressed video;

FIG. 1B is a schematic diagram of the sequence of BLOCKs in compression control;

fig. 2 is a flow chart of a video compression method according to an embodiment of the present invention;

fig. 3 is a schematic diagram of an architecture of a bmc chip for converting YUV format data into BLOCK format data in a redundant manner according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of a video compression apparatus according to another embodiment of the present invention;

fig. 5 is an internal structural view of a computer device in another embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.

It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two entities with the same name but different names or different parameters, and it should be noted that "first" and "second" are only used for convenience of expression and should not be construed as a limitation to the embodiments of the present invention, and no description is given in the following embodiments.

In one embodiment, referring to fig. 2, the present invention provides a video compression method 100, specifically, the method includes the following steps:

step 101, converting RGB format video data received from a host into YUV format data by using a color space conversion module arranged on a substrate management control chip;

step 102, judging whether an FIFO array module arranged on a substrate management control chip is normal or not;

103, in response to the abnormality of the FIFO array module, writing the YUV format data into a DDR (double data rate) arranged outside a substrate management control chip by using the color space conversion module;

104, reading the YUV format data from DDR (double data rate) arranged outside a baseboard management control chip by using a central processing unit arranged on the baseboard management control chip, converting the YUV format data into BLOCK format data, and writing the BLOCK format data into the DDR arranged outside the baseboard management control chip;

and 105, reading the BLOCK format data from the DDR arranged outside the baseboard management control chip by using a video compression module arranged on the board management control chip, compressing the BLOCK format data to obtain first video compression data, and writing the first video compression data into the DDR arranged outside the baseboard management control chip.

The video compression method improves the video compression processing mode of the traditional substrate management control chip, adopts DDR arranged outside the substrate management control chip to cache YUV format data when the FIFO array module is abnormal, unloads a conversion task from the YUV format data to a BLOCK format to a central processing unit on the substrate management control chip to execute, and does not completely rely on the FIFO array module to cache the YUV format data, thereby avoiding the situations of chip rear end design, time sequence constraint, chip video compression function abnormity caused by the large FIFO number of FIFO array modules, layout wiring and packaging manufacture, improving the stability of the video compression function in the substrate management control chip, and enriching the video compression mode by adopting the substrate management control chip.

In some embodiments, the method further comprises:

reading data from the FIFO array module according to a BLOCK format by using a read-write control module arranged on a substrate management control chip and sending the data to the video compression module;

In some embodiments, the method further comprises:

in response to the presence of an exception to at least one of the second video compressed data, acknowledging that the FIFO array module is anomalous;

In a YUV420 mode in YUV write logic, all Y data and U/V data in even rows and even columns are retained, and the specific processing mode refers to the following:

writing Y data of 0/16/32/48 \8230lineinto Y _ FIFO _0;

writing the Y data of the 1/17/33/49 \8230lineinto Y _ FIFO _1;

writing Y data of 2/18/34/50 \8230linesinto Y _ FIFO _2;

……

writing Y data of a 15/31/47/63 \8230lineinto a Y _ FIFO _15;

writing the U data of the even column of the 0/16/32/48 \8230';

writing the U data of the even column of the 2/18/34/50 \8230';

……

the data of the even column U of the 14/30/46/62 \8230linesis written into the U _ FIFO _7;

writing the U data of the even column of the 0/16/32/48 \8230';

writing the U data of the even column of the 2/18/34/50 \8230rowsinto V _ FIFO _1;

……

the even column U data for row 14/30/46/62 \8230, row is written into V _ FIFO _7.

In the YUV write logic, the principle in the YUV422 mode is to retain all Y data and U/V data in an even column, and the specific processing mode refers to the following:

writing Y data of 0/16/32/48 \8230lineinto Y _ FIFO \;

writing the Y data of the 1/17/33/49 \8230lineinto Y _ FIFO _1;

writing Y data of 2/18/34/50 \8230linesinto Y _ FIFO _2;

……

writing the Y data of the 15 th/31 th/47 th/63 \8230codeline into Y _ FIFO _15;

writing the U data of the even column of the 0/16/32/48 \8230';

writing the U data of the even column of the 1/17/33/49 \8230';

writing the U data of the even column of the 2/18/34/50 \8230';

……

writing the U data of the 15/31/47/63 \8230 # even-numbered row columns into the U _ FIFO _15;

writing the even column V data of 0/16/32/48 \8230inV _ FIFO _0;

writing the even column V data of the 1/17/33/49 \8230';

writing the even column V data of 2/18/34/50 \8230linesinto V _ FIFO _2;

……

the V data of the 15/31/47/63 \8230throw even column is written into V _ FIFO _15.

In YUV write logic, the principle in the YUV444 mode is to retain all rows and columns of Y/U/V data, and the specific processing mode refers to the following:

writing Y data of 0/8/16/24 \8230linesinto Y _ FIFO _0;

writing the Y data of the 1/9/17/25 \8230lineinto Y _ FIFO _1;

writing Y data of 2/10/18/26 \8230linesinto Y _ FIFO _2;

……

writing the Y data of the 7 th/15 th/23 th/31 \8230lineinto Y _ FIFO _7;

writing U data of 0/8/16/24 \8230lineinto U _ FIFO _0;

writing U data of 1/9/17/25 \8230lineinto U _ FIFO _1;

the U data of the 2/10/18/26 \8230; line is written into U _ FIFO _2;

……

writing U data of 7/15/23/31 \8230linesinto U _ FIFO _7;

writing the V data of 0/8/16/24 \8230';

writing the V data of the 1/9/17/25 \8230';

v data of 2/10/18/26 \8230lineis written into V _ FIFO _2;

……

v data for line 7/15/23/31 \8230iswritten into V _ FIFO _7.

In YUV420 mode, FIFO _ CTRL does not care about the read address sent by CMP, but only about the read enable sent by CMP, and reads Y _ FIFO _0 16 times, Y _ FIFO _1 16 times, 8230, Y _ FIFO _15, U _ FIFO _0, U _ FIFO _1, U _ FIFO _7, V _ FIFO _0, V _ FIFO _1, V _ FIFO _7, 8 times, and then cycle in turn 16 times.

In YUV422 mode, FIFO _ CTRL does not care about the read address sent by CMP, but only about the read enable sent by CMP, and reads Y _ FIFO _0 16 times, Y _ FIFO _1 \823016times, U _ FIFO _0 8 times, U _ FIFO _1, 823016 times, U _ FIFO _15, U _ FIFO _0 8 times, U _ FIFO _1, 82308 times, U _ FIFO _15, V _ FIFO _0 8 times, V _ FIFO _1, 82308 times, V _ FIFO _ 82308215 8 times, and V _ FIFO _15 8 times in sequence.

In YUV444 mode, FIFO _ CTRL does not care about the read address from CMP, but only about the read enable from CMP, and reads Y _ FIFO _0, Y _ FIFO _1, 82308 times, Y _ FIFO _7, U _ FIFO _0, U _ FIFO _1, U _ FIFO _7, V _ FIFO _0, V _ FIFO _1, V _ FIFO _7 8 times, and Y _ FIFO _7 8 times in sequence.

In another embodiment, please refer to fig. 3, in order to facilitate understanding of the scheme of the present invention, the embodiment of the present invention adopts two redundancy methods to convert YUC format data into BLOCK format data, and performs optimization based on the architecture of the compressed video of the conventional bmc chip, by setting a Bypass register, a user can select to enable/disable the Bypass function of the YUC 2BLOCK module, when the YUC 2BLOCK hardware module function is disabled, write the YUC data after RGB2 YUC to the off-chip DDR, then run the new software (mainly array processing) function implemented on the CPU of the bmc chip, the program reads the YUC data, and then after the calculation, write the BLOCK data to the DDR, and read the BLOCK data by the CMP module. Therefore, the defect of abnormal chip video compression function caused by numerous FIFOs of YUV2BLOCK modules, such as chip rear end design, time sequence constraint, layout and wiring, packaging and manufacturing is overcome, the stability of the video compression function in the substrate management control chip is improved, and particularly, another video compression method is improved, and the processing process is as follows:

firstly, processing video information of the HOST end by an RGB2YUV module to finish the conversion of a color space, so that the video data is converted from an RGB format to a YUV format, and the specific implementation mode is to use a color space conversion matrix.

And step two, under the condition that a user opens the enabling of the YUV2BLOCK hardware module (namely the video compression function of the chip is normal at the moment), the trend of data is in the direction of a dotted arrow in fig. 3, the data flows from the RGB2YUV module to the YUV2BLOCK module, the BLOCK conversion of the YUV data is completed in the module, the function of the module is to disregard a read address sent by the CMP, the YUV data is written into the FIFO array by directly using FIFO _ CTRL read-write control logic, then the YUV data is read according to the BLOCK sequence, and then the YUV data is sent to the CMP module for compression. The specific writing and reading order differs according to the compression mode (YUV 444/YUV422/YUV 420).

And step three, the user can shield the YUV2BLOCK hardware module function (a special Bypass register can be configured). (the specific scenario is that the video compression function of the chip is abnormal due to the fact that the number of FIFOs is large, which causes the video compression function of the chip to be abnormal due to chip rear end design, timing constraint, layout and wiring, and packaging and manufacturing), the data flow after the RGB2YUV module is the data flow from the solid line 1 to the solid line 4 in FIG. 3, and the specific processing procedure is as follows

(1) Firstly, an RGB2YUV module is perfected, an AXI interface is added, after an AXI _ INTF module and an RGB2YUV sub-module receive the configuration of a Bypass register, the data flow direction of a dotted arrow is cut off, and YUV data are converted into data in an AXI format through an AXI _ INTF module and written into a DDR module.

(2) The CPU runs newly added software (the software is used for realizing the YUV2BLOCK function), the software reads YUV data from the DDR, and then the software is used for processing, the software processing has the advantages of simple processing, mainly the operation of an array, and the disadvantage that the processing speed is slower than that of hardware.

(3) After the software processing is finished, writing the BLOCK data to the DDR;

(4) The CMP module is added with AXI _ INTF, and the INTF (interface) is used for reading data after YUV2BLOCK is completed by software and compressing the data.

And fourthly, writing the compressed video data to the DDR again, and sending the compressed video data read by the network driver to a remote end through the EMAC for displaying.

According to the video compression method, the user can select to enable/close the bypass function of the YUV2BLOCK module by setting the register, when the YUV2BLOCK module function is closed, data after RGB2YUV are written to an off-chip DDR, then a YUV2BLOCK program which is realized by a software function is allowed on a CPU (central processing unit) of a substrate management control chip, the program reads YUV data from the DDR, and then writes to the DDR after calculation is completed, and the program is read by a CMP (chemical mechanical polishing) module, so that the conversion stability from YUV to BLOCK in the video compression process is remarkably improved, and the general situation of compression errors is reduced.

In some embodiments, referring to fig. 4, the present invention further provides a video compression apparatus 200, including:

a first conversion module 201 configured to convert RGB format video data received from a host computer into YUV format data using a color space conversion module provided on a baseboard management control chip;

the judging module 202 is configured to judge whether the FIFO array module arranged on the baseboard management control chip is normal;

the first writing module 203 is configured to, in response to the abnormality of the FIFO array module, write the YUV format data into a DDR external to the bmc chip using the color space conversion module;

the second conversion module 204 is configured to read the YUV format data from the DDR arranged outside the bmc chip and convert the YUV format data into BLOCK format data by using a central processing unit arranged on the bmc chip, and write the BLOCK format data into the DDR arranged outside the bmc chip;

the first compression module 205 is configured to read and compress the BLOCK format data from the DDR arranged outside the bmc by using the video compression module arranged on the board bmc, so as to obtain first video compression data, and write the first video compression data into the DDR arranged outside the bmc.

The video compression device improves the video compression processing mode of the traditional substrate management control chip, when the FIFO array module is abnormal, the YUV format data is cached by adopting a DDR (double data rate) arranged outside the substrate management control chip, the YUV format data is unloaded to a central processing unit on the substrate management control chip for execution by a BLOCK format conversion task, the YUV format data is not completely cached by the FIFO array module, and therefore the situations of chip video compression function abnormity caused by the numerous FIFO number of the FIFO array module, time sequence constraint, layout and wiring and packaging manufacture are avoided, the stability of the video compression function in the substrate management control chip is improved, and the video compression mode by adopting the substrate management control chip is enriched.

In some embodiments, the apparatus further comprises:

the second writing module is configured to, in response to the FIFO array module being normal, write the YUV format data into the FIFO array module using the color space conversion module;

the third conversion module is configured to read data from the FIFO array module according to a BLOCK format by using a read-write control module arranged on the baseboard management control chip and send the data to the video compression module;

In some embodiments, the apparatus further comprises a module configured to:

In some embodiments, the determining module 202 is further configured to:

In some embodiments, the color space conversion module communicates with the host via a PCIe protocol, and the color space conversion module and the video compression module both communicate with the DDR external to the baseboard management control chip via an AXI interface protocol.

It should be noted that, for specific limitations of the video compression apparatus, reference may be made to the above limitations on the video compression method, and details are not described herein again. The various modules in the video compression apparatus described above may be implemented in whole or in part by software, hardware, and combinations thereof. The modules can be embedded in a hardware form or independent of a processor in the computer device, and can also be stored in a memory in the computer device in a software form, so that the processor can call and execute operations corresponding to the modules.

According to another aspect of the present invention, a computer device is provided, the computer device may be a server, and the internal structure thereof is shown in fig. 5. The computer device includes a processor, a memory, a network interface, and a database connected by a system bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device comprises a nonvolatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operating system and the computer program to run on the non-volatile storage medium. The database of the computer device is used for storing data. The network interface of the computer device is used for communicating with an external terminal through a network connection. The computer program when executed by a processor implements the video compression method described above, in particular the method comprises the steps of:

In some embodiments, the method further comprises:

and confirming that the FIFO array module is normal in response to the fact that each bit of the second video compressed data is not abnormal, the image color obtained after the second video compressed data is decompressed is not different, and the image obtained after the second video compressed data is decompressed is not provided with transverse stripes.

According to a further aspect of the present invention, there is provided a computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements the video compression method described above, in particular comprising performing the steps of:

in response to the FIFO array module exception, the YUV format data is written into a DDR arranged outside a substrate management control chip by using the color space conversion module;

reading the YUV format data from DDR arranged outside the baseboard management control chip and converting the YUV format data into BLOCK format data by using a central processing unit arranged on the baseboard management control chip, and writing the BLOCK format data into the DDR arranged outside the baseboard management control chip;

In some embodiments, the method further comprises:

and compressing the data read from the FIFO array module by using the video compression module to obtain second video compression data, and writing the second video compression data into a DDR arranged outside the substrate management control chip.

In some embodiments, the method further comprises:

and sending the first video compressed data or the second video compressed data to a remote device through a network by utilizing a network card arranged on a baseboard management control chip.

confirming that the FIFO array module is abnormal if the image obtained after decompressing the second video compressed data has horizontal stripes;

It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware instructions of a computer program, which can be stored in a non-volatile computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium used in the embodiments provided herein may include non-volatile and/or volatile memory, among others. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically Programmable ROM (EPROM), electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double Data Rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous Link DRAM (SLDRAM), rambus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

All possible combinations of the technical features in the above embodiments may not be described for the sake of brevity, but should be considered as being within the scope of the present disclosure as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is specific and detailed, but not to be understood as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims

1. A method of video compression, the method comprising:

and reading the BLOCK format data from the DDR arranged outside the baseboard management control chip by using a video compression module arranged on the board management control chip, compressing the BLOCK format data to obtain first video compression data, and writing the first video compression data into the DDR arranged outside the baseboard management control chip.

2. The video compression method of claim 1, wherein the method further comprises:

3. The video compression method according to claim 1 or 2, wherein the method further comprises:

4. The video compression method of claim 2, wherein the determining whether the FIFO array module disposed on the bmc chip is normal comprises:

5. The video compression method of claim 2, wherein the writing of YUV format data to the DDR external to the bmc chip and to the FIFO array module employs any one of YUV420 write logic, YUV422 write logic, and YUV444 write logic, and the reading of data from the DDR external to the bmc chip by the cpu and the reading of data from the FIFO array module by the read/write control module employ any one of YUV420 read logic, YUV422 read logic, and YUV444 read logic.

6. The video compression method of claim 2, wherein the color space conversion module communicates with a host via a PCIe protocol, and the color space conversion module and the video compression module both communicate with a DDR external to the baseboard management control chip via an AXI interface protocol.

7. A video compression apparatus, characterized in that the apparatus comprises:

the first writing module is configured to respond to the abnormality of the FIFO array module, and write the YUV format data into a DDR (double data rate) arranged outside a substrate management control chip by using the color space conversion module;

the second conversion module is configured to read the YUV format data from the DDR arranged outside the baseboard management control chip and convert the YUV format data into BLOCK format data by using the central processing unit arranged on the baseboard management control chip, and write the BLOCK format data into the DDR arranged outside the baseboard management control chip;

the first compression module is configured to read the BLOCK format data from the DDR arranged outside the baseboard management control chip by using the video compression module arranged on the board management control chip, compress the BLOCK format data to obtain first video compression data, and write the first video compression data into the DDR arranged outside the baseboard management control chip.

8. The video compression apparatus of claim 7, wherein the apparatus further comprises:

9. A computer device, comprising:

at least one processor; and

a memory storing a computer program operable in the processor, the processor when executing the program performing the method of any of claims 1-6.

10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, is adapted to carry out the method of any one of claims 1 to 6.