CN116361111A

CN116361111A - Data acquisition method and device and electronic equipment

Info

Publication number: CN116361111A
Application number: CN202310269321.0A
Authority: CN
Inventors: 李广迅; 易凌鹰
Original assignee: Lenovo Beijing Information Technology Ltd
Current assignee: Lenovo Beijing Information Technology Ltd
Priority date: 2023-03-15
Filing date: 2023-03-15
Publication date: 2023-06-30

Abstract

The application discloses a data acquisition method, a data acquisition device and electronic equipment, wherein the method comprises the following steps: the FPGA obtains log data, wherein the log data are recorded data of various operations and signals monitored after the FPGA is electrified; the FPGA sends the log data to a baseboard management controller BMC; so that the BMC stores the received log data in a local file system. According to the scheme, the signals and the operation record data monitored by the FPGA after the FPGA is powered on can be associated with the storage of the BMC, the obtained log data are sent to the BMC in real time, so that the BMC stores the received log data in a storage area corresponding to the BMC, and therefore when a server system is in a problem, the bottom signals and the operations can be conveniently analyzed based on the log data of the FPGA stored in the BMC, and the problem is determined.

Description

Data acquisition method and device and electronic equipment

Technical Field

The present disclosure relates to data processing technologies, and in particular, to a data acquisition method, apparatus, and electronic device.

Background

In the existing server system, when an abnormal event occurs, the problem is mainly located by analyzing logs of a BMC (Baseboard ManagementController ) and a BIOS (basic input output system). However, there are some problems related to the state of the peripheral hardware, and multiple departments and colleagues are often required to cooperate in multiple directions, and each analysis is performed on the links; in addition, there are some problems caused by the rapid change signal, and the BMC cannot record in time, so that the problem of analysis is blocked.

Disclosure of Invention

In view of this, the present application provides the following technical solutions:

a data acquisition method is applied to a Field Programmable Gate Array (FPGA), and comprises the following steps:

obtaining log data, wherein the log data are recorded data of various operations and signals monitored after the FPGA is electrified;

and sending the log data to a Baseboard Management Controller (BMC) so that the BMC stores the log data.

Optionally, the obtaining log data includes:

the state change of the signal interface is monitored through high-speed clock sampling, and log data related to the state of the signal is obtained.

Optionally, the obtaining log data includes:

the log data related to the operation is obtained based on the request instruction sent by other components and the response operation of the FPGA.

Optionally, the method further comprises:

and receiving time data sent by the BMC and correcting the local time based on the event data.

Optionally, the log data includes various signals monitored by the FPGA, a generation time of the corresponding signals, a control operation of the FPGA, and a record of other component access registers, where the various signals monitored by the FPGA include at least one of the following: reset signals of the processor, the bus device and/or the hard disk device, error trigger signals of the processor and/or the memory module, and state detection signals of the power manager.

A data acquisition method is applied to a baseboard management controller BMC, and comprises the following steps:

obtaining log data from the FPGA, wherein the log data are recorded data of various operations and signals monitored after the FPGA is electrified;

and storing the log data in a local file system.

Optionally, the method further comprises:

establishing connection with a peripheral log analysis tool;

and exporting the log data to the peripheral log analysis tool.

The application also discloses a data acquisition device, is applied to field programmable gate array FPGA, includes:

the log collection module is used for obtaining log data, wherein the log data are recorded data of various operations and signals monitored after the FPGA is electrified;

and the data sending module is used for sending the log data to a Baseboard Management Controller (BMC) so that the BMC stores the log data.

A data acquisition device applied to a baseboard management controller BMC, comprising:

the log obtaining module is used for obtaining log data from the FPGA, wherein the log data are recorded data of various operations and signals monitored after the FPGA is electrified;

and the log storage module is used for storing the log data in a local file system.

Further, the application also discloses electronic equipment, which comprises a Field Programmable Gate Array (FPGA) and a Baseboard Management Controller (BMC), wherein:

the FPGA obtains log data, wherein the log data are recorded data of various operations and signals monitored after the FPGA is electrified;

the FPGA sends the log data to a baseboard management controller BMC;

and the BMC stores the received log data in a local file system.

As can be seen from the above technical solutions, the embodiments of the present application disclose a data acquisition method, a device, and an electronic device, where the method includes: the FPGA obtains log data, wherein the log data are recorded data of various operations and signals monitored after the FPGA is electrified; the FPGA sends the log data to a baseboard management controller BMC; so that the BMC stores the received log data in a local file system. According to the scheme, the signals and the operation record data monitored by the FPGA after the FPGA is powered on can be associated with the storage of the BMC, the obtained log data are sent to the BMC in real time, so that the BMC stores the received log data in a storage area corresponding to the BMC, and therefore when a server system is in a problem, the bottom signals and the operations can be conveniently analyzed based on the log data of the FPGA stored in the BMC, and the problem is determined.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present application, and that other drawings may be obtained according to the provided drawings without inventive effort to a person skilled in the art.

FIG. 1 is a flow chart of a data acquisition method disclosed in an embodiment of the present application;

FIG. 2 is a schematic diagram of an implementation architecture of a data acquisition method disclosed in an embodiment of the present application;

FIG. 3 is an exemplary diagram of encoded log data disclosed in an embodiment of the present application;

FIG. 4 is an exemplary diagram of log data after decoding by a decoding analysis tool according to an embodiment of the present disclosure;

FIG. 5 is an exemplary diagram of a search interface of a decoding analysis tool disclosed in an embodiment of the present application;

FIG. 6 is a flow chart of another method of data acquisition disclosed in an embodiment of the present application;

fig. 7 is a schematic structural diagram of a data acquisition device according to an embodiment of the present disclosure;

fig. 8 is a schematic structural diagram of another data acquisition device according to an embodiment of the present application.

Detailed Description

The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.

The embodiment of the application can be applied to electronic equipment, the product form of the electronic equipment is not limited, and the electronic equipment can comprise but is not limited to a smart phone, a tablet personal computer, a wearable device, a Personal Computer (PC), a netbook and the like, and can be selected according to application requirements.

Fig. 1 is a flowchart of a data acquisition method disclosed in an embodiment of the present application. The flow shown in fig. 1 is applied to an FPGA (field programmable gate array). Referring to fig. 1, the data acquisition method may include:

step 101: and obtaining log data, wherein the log data are recorded data of various operations and signals monitored after the FPGA is electrified.

The log data are some data collected in real time in the normal working process of the FPGA after power-on, and the data can comprise data related to various signals, data related to some operations and the like. For example, the log data may include various types of signals monitored by the FPGA, the time of generation of the corresponding signals, the control operations of the FPGA, and other records of component access registers, etc. The various signals monitored by the FPGA may include, but are not limited to, at least one of the following: reset signals of the processor, the bus device and/or the hard disk device, error trigger signals of the processor and/or the memory module, and state detection signals of the power manager.

In the implementation application, the FPGA bears a large number of peripheral monitoring and control tasks in the server, and the important information states which can be used for later fault analysis are collected and obtained by the FPGA to form the log data. The peripheral monitoring and control tasks of the FPGA may include, but are not limited to: power on time sequence control power failure detection, system reset control, front panel and back panel lighting control, hard disk drive sequence management, BMC (baseboard management controller), BIOS (basic input output system), back panel, transfer card and the like, and all communication records of other peripheral board cards and FPGA and the like. The FPGA can collect the log data while performing these peripheral monitoring and control tasks. The log data has wide signal types and operation content ranges, and the range from the start time sequence of the system to various trigger signals, the state of the card and the like is in the recording range of the FPGA log data.

In particular, how the FPGA obtains log data will be described in detail in the following examples, and will not be described in detail here.

Step 102: and sending the log data to a Baseboard Management Controller (BMC) so that the BMC stores the log data.

Because the FPGA has no capability of storing log data, the FPGA can send the log data to the BMC through a serial port after obtaining the log data. The BMC has an independent storage area that can store several pieces of log data to the local file system.

The log data is not generated at uninterrupted times, but rather is generated based on the signals or controlled operations that the FPGA is responsible for monitoring. That is, only when a change of the working state of a certain signal or a certain signal is detected, or when a received instruction of other devices accessing a register or certain operation is executed, log data is generated in real time, and the generated log data is sent to the BMC in real time.

It should be noted that, after the BMC receives the log data, it does not perform any processing on the log data, but directly stores the log data, and its role in the scheme of the present application may be to store the log data of the FPGA instead. In this way, no additional BMC resources are consumed.

According to the data acquisition method, signals and operation record data monitored by the FPGA after power-on can be associated with the storage of the BMC, the obtained log data are sent to the BMC in real time, so that the BMC stores the received log data in a storage area corresponding to the BMC, and therefore when a server system is in a problem, the analysis of some bottom signals and operations can be conveniently carried out based on the log data of the FPGA stored in the BMC, and the problem is determined.

In the above embodiment, the obtaining log data may include: the state change of the signal interface is monitored through high-speed clock sampling, and log data related to the state of the signal is obtained.

In practical application, the FPGA monitors a plurality of signals, the signals are provided with independent interfaces in the FPGA, the FPGA respectively performs high-speed clock sampling on each signal interface, determines the working state of the signal corresponding to the interface based on the sampling result, and monitors the dynamic change process of the signals. For example, monitoring the level at the first signal interface, and when the level at the interface is below 0.1V, deeming that the first signal has not been received; when the level at the interface suddenly rises to a large extent and the value reaches more than 1V, the first signal is considered to appear at the interface, and the FPGA can record the first signal and record the time for generating the first signal.

The operation-related data in the log data is obtained in a different manner from the aforementioned signal-related data. Thus, the obtaining log data may further include: the log data related to the operation is obtained based on the request instruction sent by other components and the response operation of the FPGA.

Other components herein may be BMC, BIOS, etc. During the operation of the server system, the BMC and the BIOS access registers of the FPGA, the FPGA can record the access operations, and the processing results of the access operations are recorded based on response control for the access operations, so that log data related to the operations is obtained. For example, the FPGA receives a request for the BIOS to access a register at a first time point, and the FPGA allows the BIOS to read the register content in response to the request for access; the FPGA may record the request to access the registers of the BIOS at the first point in time, and may also record the duration of time that the BIOS reads the registers.

In the embodiment of the application, the FPGA collects log data through the hardware, so that the accuracy of millisecond level can be achieved by recording all events in the FPGA, the granularity of the recordable event is finer, and any state change cannot be missed. For events within a unified millisecond, the FPGA can distinguish the order of occurrence, thereby also ensuring the accuracy of the log data finally obtained. Thus, when the requirement of analyzing the log data of the FPGA is met, the result with high accuracy can be analyzed based on the log data with high accuracy.

The above description is related to the obtaining modes of different types of data in the FPGA log data, so that the implementation mode of obtaining the log data can be well understood by those skilled in the art.

In other embodiments, the data acquisition method may further include, in addition to the foregoing content of acquiring the log data and sending the log data to the BMC: and receiving time data sent by the BMC and correcting the local time based on the event data.

Specifically, the FPGA may receive time data sent by the BMC and perform synchronization processing based on the time, so as to ensure uniformity of time between the BMC and the FPGA. In the application, the FPGA and the BMC are time-synchronized, so that the search and the positioning in the time dimension can be conveniently performed during the subsequent correlation analysis.

In a specific implementation, the BMC can write the current time of the BMC into the FPGA at regular time, and the FPGA records the time into log data, so that the subsequent analysis and the log searching are very convenient. Of course, the time synchronization process may be periodic, or may be actively triggered at some event node, for example, the time synchronization of the FPGA and the BMC may be performed after each power-up of the server system.

In addition, after the FPGA obtains the log data, the log data can be encoded before being sent to the BMC due to the consideration of data security, and finally the encoded log data is sent to the BMC through a serial port.

The specific encoding method is not limited, and for example, the log data may be encoded in bits or in characters. In the mode of encoding according to the bits, a very large amount of information can be recorded by a very small amount of data, so that the log data can be conveniently transmitted and stored. In the implementation, the log data of the FOGA is coded based on bits, and only 28 bytes are occupied by one log after the time stamping; if calculated as one log per second, 2.419 mbytes are required to record a log of one day. The amount of the log is determined according to the frequency of the event state change. Thus, if the FPGA performs self-encoding on the log data according to the bits, the data volume is small, and the encoded log data are output through the serial port in real time, so that the log data can be stored for a long time.

The memory space allocated by the BMC for storing the log data of the FPGA is limited, so in this embodiment of the present application, the data amount of the log data may be compressed by encoding the log data, so that more log data or longer time periods of log data can be stored in the limited memory space as much as possible.

In practical application, a special decoding analysis tool can be designed to derive the log data of the FPGA from the file system of the BMC and analyze and process the log data without on-line decoding of the BMC; therefore, redundant system resources are not occupied, the analysis process is not dependent on BMC, and the situation that the FPGA log data cannot be analyzed due to BMC faults is avoided.

The special decoding analysis tool is used for processing the log data of the FPGA, so that the safety of the log data can be effectively ensured, and even if the log data is exported by other illegal equipment, the original log data cannot be accurately analyzed and obtained because the encoding mode of the log data is not clear.

Fig. 2 is a schematic diagram of an implementation architecture of a data acquisition method according to an embodiment of the present application. The following description can be understood in conjunction with the description shown in fig. 2.

In a specific implementation, an FPGA and a BMC on a system main board complete monitoring of signals related to the FPGA and store log files, and a PC end log analysis tool analyzes the exported log to check the problem.

The signal monitoring module inside the FPGA realizes real-time monitoring of important signals, including a CPU, PCIE (peripheral component interconnect express), a high-speed serial computer expansion bus standard) device, various reset signals of NVME (non-volatile Memory host controller interface specification) hard disk, error trigger signals of various CPUs and DIMMs (Dual-Inline-Memory-Modules), status detection signals of PSU (power supply) and the like, and the FPGA can detect signal changes with 20ns precision. And simultaneously, the read-write behaviors of the BMC and the BIOS operation register are recorded, and the recorded information is sent out through the debugging serial port. The debugging serial port of the FPGA is connected with the BMC, and the BMC stores the serial port log of the FPGA in a local file system for later analysis and positioning. Thus, the important information log of the FPGA can be stored in a log file through the BMC.

When the problem needs to be analyzed, the FPGA serial port log can be exported from the BMC and then imported into a special FPGA log analysis tool for analyzing and checking the problem one by one. The system realizes a set of log analysis software tool, and can import the log exported from the BMC into a decoding analysis tool for signal-by-signal analysis based on a time axis. The log is used to see the relative time point of error and the state of other signals at that time. Fig. 3 is an exemplary diagram of encoded log data disclosed in the embodiments of the present application, and fig. 4 is an exemplary diagram of log data decoded by the decoding analysis tool disclosed in the embodiments of the present application, where the foregoing description may be understood in conjunction with fig. 3 and fig. 4.

In some fault cases, the decoding analysis tool can automatically identify fault data existing in the log data, such as power faults, based on some preset processing logic, and the system can directly identify the log data representing the power faults. In other fault situations, some problems need to be manually analyzed, such as time sequence association problems, so that staff can participate in checking log data to locate fault sources. Therefore, in order to facilitate analysis, the decoding and analyzing tool can be designed to have a retrieval function, so that the data of a certain signal in the log data can be independently retrieved for independent analysis, and great convenience is provided for related staff. FIG. 5 is an exemplary diagram of a search interface for a decoding analysis tool disclosed in an embodiment of the present application, which can be understood in conjunction with FIG. 5.

Fig. 6 is a flowchart of another data acquisition method disclosed in an embodiment of the present application. The flow shown in fig. 6 is applied to the baseboard management controller BMC. As shown in connection with fig. 6, the data acquisition method may include:

step 601: and obtaining log data from the FPGA, wherein the log data are recorded data of various operations and signals monitored after the FPGA is electrified.

In combination with the content of the previous embodiment, the BMC receives log data of the FPGA through a serial port of the FPGA. The log data can be data which is generated by the FPGA in real time and sent out through a serial port.

The log data may include, but is not limited to, various signals monitored by the FPGA, generation time of corresponding signals, control operation of the FPGA, and recording of other component access registers, where the various signals monitored by the FPGA include at least one of: reset signals of the processor, the bus device and/or the hard disk device, error trigger signals of the processor and/or the memory module, and state detection signals of the power manager.

The log data may be data subjected to FPGA encoding processing. The method for coding the log data is not limited in a fixed manner, and can be determined based on the system configuration and the requirements of the actual application scene.

Step 602: and storing the log data in a local file system.

After receiving the log data of the FPGA, the BMC does not process the log data and directly stores the log data in a local file system so as to support the export of other devices when log analysis requirements exist later.

In this embodiment, the BMC only "helps" the log data of the FPGA memory, and does not perform any substantial data processing, so that no additional processing resources are occupied.

In other implementations, the data obtaining method may further include, in addition to obtaining the log data from the FPGA and storing the log data in the local file system, the method further includes: establishing connection with a peripheral log analysis tool; and exporting the log data to the peripheral log analysis tool.

When a server system fails, the failure analysis is needed, so that the log data of the FPGA can be exported from the file system of the BMC through a special log analysis tool, and then the log data of the FPGA is analyzed to determine the problem.

For the foregoing method embodiments, for simplicity of explanation, the methodologies are shown as a series of acts, but one of ordinary skill in the art will appreciate that the present application is not limited by the order of acts described, as some acts may, in accordance with the present application, occur in other orders or concurrently. Further, those skilled in the art will also appreciate that the embodiments described in the specification are all preferred embodiments, and that the acts and modules referred to are not necessarily required in the present application.

The method is described in detail in the embodiments disclosed in the application, and the method can be implemented by using various devices, so that the application also discloses a device, and a specific embodiment is given in the following detailed description.

Fig. 7 is a schematic structural diagram of a data acquisition device according to an embodiment of the present application. The apparatus shown in fig. 7 is applied to a field programmable gate array FPGA. Referring to fig. 7, the data acquisition device 70 may include:

the log collection module 701 is configured to obtain log data, where the log data is recorded data of various operations and signals monitored after the FPGA is powered on.

The data sending module 702 is configured to send the log data to a baseboard management controller BMC, so that the BMC stores the log data.

The data acquisition device can correlate the signals and operation record data monitored by the FPGA after the FPGA is powered on with the storage of the BMC, and send the obtained log data to the BMC in real time, so that the BMC stores the received log data in a storage area corresponding to the BMC, and when a server system has a problem, the analysis of some bottom signals and operations can be conveniently carried out based on the log data of the FPGA stored in the BMC, and the problem is determined.

In one implementation, the log collection module is specifically configured to: the state change of the signal interface is monitored through high-speed clock sampling, and log data related to the state of the signal is obtained.

In one implementation, the log collection module is specifically configured to: the log data related to the operation is obtained based on the request instruction sent by other components and the response operation of the FPGA.

In one implementation, the data acquisition device may further include: and the time synchronization module is used for receiving the time data sent by the BMC and correcting the local time based on the event data.

In one implementation, the log data includes various signals monitored by the FPGA, a generation time of the corresponding signals, a control operation of the FPGA, and a record of other components accessing the register, where the various signals monitored by the FPGA include at least one of: reset signals of the processor, the bus device and/or the hard disk device, error trigger signals of the processor and/or the memory module, and state detection signals of the power manager.

Fig. 8 is a schematic structural diagram of another data acquisition device according to an embodiment of the present application. The apparatus shown in fig. 8 is applied to a baseboard management controller BMC. Referring to fig. 8, the data acquisition device 80 may include:

the log obtaining module 801 is configured to obtain log data from the FPGA, where the log data is recorded data of various operations and signals monitored after the FPGA is powered on;

the log storage module 802 is configured to store the log data in a local file system.

In this embodiment, the function of the data acquisition device of the BMC is only to "help" log data of the FPGA memory, and no substantial data processing is performed, so that no extra processing resource is occupied, and when the subsequent fault analysis is required, log data of the FPGA stored in the file system can be provided in time, so that the fault cause can be determined in time.

In one implementation, the data acquisition device may further include: the export processing module is used for establishing connection with the peripheral log analysis tool; and exporting the log data to the peripheral log analysis tool.

The specific implementation of the data acquisition device and each module may be referred to the content description of the corresponding parts in the method embodiment, and the detailed description is not repeated here.

Any one of the data acquisition devices in the above embodiments includes a processor and a memory, where the log collection module, the data transmission module, the log obtaining module, the log storage module, the time synchronization module, the export processing module, and the like in the above embodiments are stored as program modules in the memory, and the processor executes the program modules stored in the memory to implement corresponding functions.

The processor comprises a kernel, and the kernel fetches the corresponding program module from the memory. The kernel can be provided with one or more kernels, and the processing of the return visit data is realized by adjusting kernel parameters.

The memory may include volatile memory, random Access Memory (RAM), and/or nonvolatile memory, such as Read Only Memory (ROM) or flash memory (flash RAM), among other forms in computer readable media, the memory including at least one memory chip.

In an exemplary embodiment, a computer readable storage medium is also provided, which can be directly loaded into an internal memory of a computer, and in which software code is contained, and the computer program can implement the steps shown in any embodiment of the data acquisition method after being loaded and executed by the computer.

In an exemplary embodiment, a computer program product is also provided, which can be directly loaded into an internal memory of a computer, and in which a software code is contained, and which, when loaded and executed by the computer, is capable of implementing the steps shown in any of the embodiments of the data acquisition method described above.

The application also discloses electronic equipment, including field programmable gate array FPGA and baseboard management controller BMC, wherein: the FPGA obtains log data, wherein the log data are recorded data of various operations and signals monitored after the FPGA is electrified; the FPGA sends the log data to a baseboard management controller BMC; and the BMC stores the received log data in a local file system.

According to the scheme, signals and operation record data monitored by the FPGA after the FPGA is powered on can be associated with the storage of the BMC, the obtained log data are sent to the BMC in real time, so that the BMC stores the received log data in a storage area corresponding to the BMC, and therefore when a server system is in a problem, the bottom signals and operations can be conveniently analyzed based on the log data of the FPGA stored in the BMC, and the problem is determined.

In the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section.

It is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. The software modules may be disposed in Random Access Memory (RAM), memory, read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A data acquisition method is applied to a Field Programmable Gate Array (FPGA), and comprises the following steps:

2. The data acquisition method according to claim 1, the obtaining log data, comprising:

3. The data acquisition method according to claim 1, the obtaining log data, comprising:

4. The data acquisition method of claim 1, further comprising:

5. The data acquisition method according to claim 1, wherein the log data includes various signals monitored by the FPGA, the generation time of the corresponding signals, the control operation of the FPGA, and the record of other component access registers, and the various signals monitored by the FPGA include at least one of the following: reset signals of the processor, the bus device and/or the hard disk device, error trigger signals of the processor and/or the memory module, and state detection signals of the power manager.

6. A data acquisition method is applied to a baseboard management controller BMC, and comprises the following steps:

and storing the log data in a local file system.

7. The data acquisition method of claim 6, further comprising:

establishing connection with a peripheral log analysis tool;

and exporting the log data to the peripheral log analysis tool.

8. A data acquisition device for a field programmable gate array FPGA, comprising:

9. A data acquisition device applied to a baseboard management controller BMC, comprising:

10. An electronic device comprising a field programmable gate array FPGA and a baseboard management controller BMC, wherein:

the FPGA sends the log data to a baseboard management controller BMC;

and the BMC stores the received log data in a local file system.